c4220324a05549b2008c1d47da02f142a310c2b2
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ramips_esw.c
1 #include <linux/ioport.h>
2
3 #include <rt305x_regs.h>
4 #include <rt305x_esw_platform.h>
5
6 #define RT305X_ESW_REG_FCT0 0x08
7 #define RT305X_ESW_REG_PFC1 0x14
8 #define RT305X_ESW_REG_PVIDC(_n) (0x48 + 4 * (_n))
9 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
10 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
11 #define RT305X_ESW_REG_FPA 0x84
12 #define RT305X_ESW_REG_SOCPC 0x8c
13 #define RT305X_ESW_REG_POC1 0x90
14 #define RT305X_ESW_REG_POC2 0x94
15 #define RT305X_ESW_REG_POC3 0x98
16 #define RT305X_ESW_REG_SGC 0x9c
17 #define RT305X_ESW_REG_PCR0 0xc0
18 #define RT305X_ESW_REG_PCR1 0xc4
19 #define RT305X_ESW_REG_FPA2 0xc8
20 #define RT305X_ESW_REG_FCT2 0xcc
21 #define RT305X_ESW_REG_SGC2 0xe4
22
23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
24 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
26
27 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
28
29 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
30
31 #define RT305X_ESW_VLANI_VID_M 0xfff
32 #define RT305X_ESW_VLANI_VID_S 12
33
34 #define RT305X_ESW_VMSC_MSC_M 0xff
35 #define RT305X_ESW_VMSC_MSC_S 8
36
37 #define RT305X_ESW_PORT0 0
38 #define RT305X_ESW_PORT1 1
39 #define RT305X_ESW_PORT2 2
40 #define RT305X_ESW_PORT3 3
41 #define RT305X_ESW_PORT4 4
42 #define RT305X_ESW_PORT5 5
43 #define RT305X_ESW_PORT6 6
44
45 struct rt305x_esw {
46 void __iomem *base;
47 struct rt305x_esw_platform_data *pdata;
48 spinlock_t reg_rw_lock;
49 };
50
51 static inline void
52 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
53 {
54 __raw_writel(val, esw->base + reg);
55 }
56
57 static inline u32
58 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
59 {
60 return __raw_readl(esw->base + reg);
61 }
62
63 static inline void
64 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
65 unsigned long val)
66 {
67 unsigned long t;
68
69 t = __raw_readl(esw->base + reg) & ~mask;
70 __raw_writel(t | val, esw->base + reg);
71 }
72
73 static void
74 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
75 unsigned long val)
76 {
77 unsigned long flags;
78
79 spin_lock_irqsave(&esw->reg_rw_lock, flags);
80 rt305x_esw_rmw_raw(esw, reg, mask, val);
81 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
82 }
83
84 static u32
85 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
86 u32 write_data)
87 {
88 unsigned long t_start = jiffies;
89 int ret = 0;
90
91 while (1) {
92 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
93 RT305X_ESW_PCR1_WT_DONE))
94 break;
95 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
96 ret = 1;
97 goto out;
98 }
99 }
100
101 write_data &= 0xffff;
102 rt305x_esw_wr(esw,
103 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
104 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
105 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
106 RT305X_ESW_REG_PCR0);
107
108 t_start = jiffies;
109 while (1) {
110 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
111 RT305X_ESW_PCR1_WT_DONE)
112 break;
113
114 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
115 ret = 1;
116 break;
117 }
118 }
119 out:
120 if (ret)
121 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
122 return ret;
123 }
124
125 static void
126 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
127 {
128 unsigned s;
129
130 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
131 rt305x_esw_rmw(esw,
132 RT305X_ESW_REG_VLANI(vlan / 2),
133 RT305X_ESW_VLANI_VID_M << s,
134 (vid & RT305X_ESW_VLANI_VID_M) << s);
135 }
136
137 static void
138 rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
139 {
140 unsigned s;
141
142 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
143 rt305x_esw_rmw(esw,
144 RT305X_ESW_REG_VMSC(vlan / 4),
145 RT305X_ESW_VMSC_MSC_M << s,
146 (msc & RT305X_ESW_VMSC_MSC_M) << s);
147 }
148
149 static void
150 rt305x_esw_hw_init(struct rt305x_esw *esw)
151 {
152 int i;
153
154 /* vodoo from original driver */
155 rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
156 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
157 rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
158 rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
159 rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
160 rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
161 rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
162 rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
163 rt305x_esw_wr(esw, 0x00001002, RT305X_ESW_REG_PVIDC(2));
164 rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
165 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
166
167 rt305x_mii_write(esw, 0, 31, 0x8000);
168 for (i = 0; i < 5; i++) {
169 /* TX10 waveform coefficient */
170 rt305x_mii_write(esw, i, 0, 0x3100);
171 /* TX10 waveform coefficient */
172 rt305x_mii_write(esw, i, 26, 0x1601);
173 /* TX100/TX10 AD/DA current bias */
174 rt305x_mii_write(esw, i, 29, 0x7058);
175 /* TX100 slew rate control */
176 rt305x_mii_write(esw, i, 30, 0x0018);
177 }
178
179 /* PHY IOT */
180 /* select global register */
181 rt305x_mii_write(esw, 0, 31, 0x0);
182 /* tune TP_IDL tail and head waveform */
183 rt305x_mii_write(esw, 0, 22, 0x052f);
184 /* set TX10 signal amplitude threshold to minimum */
185 rt305x_mii_write(esw, 0, 17, 0x0fe0);
186 /* set squelch amplitude to higher threshold */
187 rt305x_mii_write(esw, 0, 18, 0x40ba);
188 /* longer TP_IDL tail length */
189 rt305x_mii_write(esw, 0, 14, 0x65);
190 /* select local register */
191 rt305x_mii_write(esw, 0, 31, 0x8000);
192
193 /* set default vlan */
194 rt305x_esw_set_vlan_id(esw, 0, 1);
195 rt305x_esw_set_vlan_id(esw, 1, 2);
196 rt305x_esw_set_vmsc(esw, 0,
197 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
198 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
199 BIT(RT305X_ESW_PORT6)));
200 rt305x_esw_set_vmsc(esw, 1,
201 (BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)));
202 rt305x_esw_set_vmsc(esw, 2, 0);
203 rt305x_esw_set_vmsc(esw, 3, 0);
204 }
205
206 static int
207 rt305x_esw_probe(struct platform_device *pdev)
208 {
209 struct rt305x_esw_platform_data *pdata;
210 struct rt305x_esw *esw;
211 struct resource *res;
212 int err;
213
214 pdata = pdev->dev.platform_data;
215 if (!pdata)
216 return -EINVAL;
217
218 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 if (!res) {
220 dev_err(&pdev->dev, "no memory resource found\n");
221 return -ENOMEM;
222 }
223
224 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
225 if (!esw) {
226 dev_err(&pdev->dev, "no memory for private data\n");
227 return -ENOMEM;
228 }
229
230 esw->base = ioremap(res->start, resource_size(res));
231 if (!esw->base) {
232 dev_err(&pdev->dev, "ioremap failed\n");
233 err = -ENOMEM;
234 goto free_esw;
235 }
236
237 platform_set_drvdata(pdev, esw);
238
239 esw->pdata = pdata;
240 spin_lock_init(&esw->reg_rw_lock);
241 rt305x_esw_hw_init(esw);
242
243 return 0;
244
245 free_esw:
246 kfree(esw);
247 return err;
248 }
249
250 static int
251 rt305x_esw_remove(struct platform_device *pdev)
252 {
253 struct rt305x_esw *esw;
254
255 esw = platform_get_drvdata(pdev);
256 if (esw) {
257 platform_set_drvdata(pdev, NULL);
258 iounmap(esw->base);
259 kfree(esw);
260 }
261
262 return 0;
263 }
264
265 static struct platform_driver rt305x_esw_driver = {
266 .probe = rt305x_esw_probe,
267 .remove = rt305x_esw_remove,
268 .driver = {
269 .name = "rt305x-esw",
270 .owner = THIS_MODULE,
271 },
272 };
273
274 static int __init
275 rt305x_esw_init(void)
276 {
277 return platform_driver_register(&rt305x_esw_driver);
278 }
279
280 static void __exit
281 rt305x_esw_exit(void)
282 {
283 platform_driver_unregister(&rt305x_esw_driver);
284 }