ramips: ramips_esw: move hardware initialization into a separate function
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ramips_esw.c
1 #include <rt305x.h>
2 #include <rt305x_regs.h>
3
4 #define GPIO_PRUPOSE 0x60
5 #define GPIO_MDIO_BIT (1<<7)
6 #define RT305X_ESW_PHY_WRITE (1 << 13)
7 #define RT305X_ESW_PHY_TOUT (5 * HZ)
8 #define RT305X_ESW_PHY_CONTROL_0 0xC0
9 #define RT305X_ESW_PHY_CONTROL_1 0xC4
10
11 struct rt305x_esw {
12 void __iomem *base;
13 };
14
15 static struct rt305x_esw rt305x_esw;
16
17 static inline void
18 ramips_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
19 {
20 __raw_writel(val, esw->base + reg);
21 }
22
23 static inline u32
24 ramips_esw_rr(struct rt305x_esw *esw, unsigned reg)
25 {
26 return __raw_readl(esw->base + reg);
27 }
28
29 static void
30 ramips_enable_mdio(int s)
31 {
32 u32 gpio = rt305x_sysc_rr(GPIO_PRUPOSE);
33 if(s)
34 gpio &= ~GPIO_MDIO_BIT;
35 else
36 gpio |= GPIO_MDIO_BIT;
37 rt305x_sysc_wr(gpio, GPIO_PRUPOSE);
38 }
39
40 u32
41 mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
42 u32 write_data)
43 {
44 unsigned long volatile t_start = jiffies;
45 int ret = 0;
46
47 ramips_enable_mdio(1);
48 while(1)
49 {
50 if(!(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)))
51 break;
52 if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
53 {
54 ret = 1;
55 goto out;
56 }
57 }
58 ramips_esw_wr(esw, ((write_data & 0xFFFF) << 16) | (phy_register << 8) |
59 (phy_addr) | RT305X_ESW_PHY_WRITE, RT305X_ESW_PHY_CONTROL_0);
60 t_start = jiffies;
61 while(1)
62 {
63 if(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))
64 break;
65 if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
66 {
67 ret = 1;
68 break;
69 }
70 }
71 out:
72 ramips_enable_mdio(0);
73 if(ret)
74 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
75 return ret;
76 }
77
78 static void
79 rt305x_esw_hw_init(struct rt305x_esw *esw)
80 {
81 int i;
82
83 /* vodoo from original driver */
84 ramips_esw_wr(esw, 0xC8A07850, 0x08);
85 ramips_esw_wr(esw, 0x00000000, 0xe4);
86 ramips_esw_wr(esw, 0x00405555, 0x14);
87 ramips_esw_wr(esw, 0x00002001, 0x50);
88 ramips_esw_wr(esw, 0x00007f7f, 0x90);
89 ramips_esw_wr(esw, 0x00007f3f, 0x98);
90 ramips_esw_wr(esw, 0x00d6500c, 0xcc);
91 ramips_esw_wr(esw, 0x0008a301, 0x9c);
92 ramips_esw_wr(esw, 0x02404040, 0x8c);
93 ramips_esw_wr(esw, 0x00001002, 0x48);
94 ramips_esw_wr(esw, 0x3f502b28, 0xc8);
95 ramips_esw_wr(esw, 0x00000000, 0x84);
96
97 mii_mgr_write(esw, 0, 31, 0x8000);
98 for(i = 0; i < 5; i++)
99 {
100 mii_mgr_write(esw, i, 0, 0x3100); //TX10 waveform coefficient
101 mii_mgr_write(esw, i, 26, 0x1601); //TX10 waveform coefficient
102 mii_mgr_write(esw, i, 29, 0x7058); //TX100/TX10 AD/DA current bias
103 mii_mgr_write(esw, i, 30, 0x0018); //TX100 slew rate control
104 }
105 /* PHY IOT */
106 mii_mgr_write(esw, 0, 31, 0x0); //select global register
107 mii_mgr_write(esw, 0, 22, 0x052f); //tune TP_IDL tail and head waveform
108 mii_mgr_write(esw, 0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
109 mii_mgr_write(esw, 0, 18, 0x40ba); //set squelch amplitude to higher threshold
110 mii_mgr_write(esw, 0, 14, 0x65); //longer TP_IDL tail length
111 mii_mgr_write(esw, 0, 31, 0x8000); //select local register
112
113 /* Port 5 Disabled */
114 rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50)
115 rt305x_sysc_wr(0xfff, 0x674); //GPIO41-GPIO50 output mode
116 rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low
117
118 /* set default vlan */
119 ramips_esw_wr(esw, 0x2001, 0x50);
120 ramips_esw_wr(esw, 0x504f, 0x70);
121 }
122
123 static int
124 rt305x_esw_init(void)
125 {
126 struct rt305x_esw *esw;
127
128 esw = &rt305x_esw;
129 esw->base = ioremap_nocache(RT305X_SWITCH_BASE, PAGE_SIZE);
130 if(!esw->base)
131 return -ENOMEM;
132
133 rt305x_esw_hw_init(esw);
134 return 0;
135 }