target/linux/ramips/patches-3.10/0022-MIPS-add-driver-for-the-built-in-PCI-controller-of-the-RT3883-SoC.patch

   1 From patchwork Fri Aug 23 12:03:20 2013
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   5 Subject: [v3] MIPS: add driver for the built-in PCI controller of the RT3883
   6  SoC
   7 From: Gabor Juhos <juhosg@openwrt.org>
   8 X-Patchwork-Id: 5758
   9 Message-Id: <1377259400-21211-1-git-send-email-juhosg@openwrt.org>
  10 To: Ralf Baechle <ralf@linux-mips.org>
  11 Cc: linux-mips@linux-mips.org, Gabor Juhos <juhosg@openwrt.org>,
  12  devicetree@vger.kernel.org
  13 Date: Fri, 23 Aug 2013 14:03:20 +0200
  14
  15 The Ralink RT3883 SoCs have a built-in PCI Host Controller
  16 device. The patch adds a platform driver and device tree
  17 binding documentation for that.
  18
  19 The patch also enables the HW_HAS_PCI config option. This
  20 is required in order to be able to enable the PCI support.
  21
  22 Cc: devicetree@vger.kernel.org
  23 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  24 Acked-by: John Crispin <blogic@openwrt.org>
  25
  26 ---
  27 Changes since v2:
  28   - fix compiler warning:
  29
  30   CC      arch/mips/pci/pci-rt3883.o
  31   arch/mips/pci/pci-rt3883.c: In function 'rt3883_pci_probe':
  32   arch/mips/pci/pci-rt3883.c:458:4: warning: use of 'h' length modifier with 'a' type character [-Wformat]
  33
  34 Changes since v1:
  35   - change the 'status' property to optional in the binding doc
  36   - add board specific example to the binding doc
  37
  38 rt3883-pci: fix-build-warning
  39
  40 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  41 ---
  42  .../devicetree/bindings/pci/ralink,rt3883-pci.txt  |  190 ++++++
  43  arch/mips/pci/Makefile                             |    1 +
  44  arch/mips/pci/pci-rt3883.c                         |  636 ++++++++++++++++++++
  45  arch/mips/ralink/Kconfig                           |    1 +
  46  4 files changed, 828 insertions(+)
  47  create mode 100644 Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
  48  create mode 100644 arch/mips/pci/pci-rt3883.c
  49
  50 --- /dev/null
  51 +++ b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
  52 @@ -0,0 +1,190 @@
  53 +* Mediatek/Ralink RT3883 PCI controller
  54 +
  55 +1) Main node
  56 +
  57 +   Required properties:
  58 +
  59 +   - compatible: must be "ralink,rt3883-pci"
  60 +
  61 +   - reg: specifies the physical base address of the controller and
  62 +     the length of the memory mapped region.
  63 +
  64 +   - #address-cells: specifies the number of cells needed to encode an
  65 +     address. The value must be 1.
  66 +
  67 +   - #size-cells: specifies the number of cells used to represent the size
  68 +     of an address. The value must be 1.
  69 +
  70 +   - ranges: specifies the translation between child address space and parent
  71 +     address space
  72 +
  73 +  Optional properties:
  74 +
  75 +   - status: indicates the operational status of the device.
  76 +     Value must be either "disabled" or "okay".
  77 +
  78 +2) Child nodes
  79 +
  80 +   The main node must have two child nodes which describes the built-in
  81 +   interrupt controller and the PCI host bridge.
  82 +
  83 +   a) Interrupt controller:
  84 +
  85 +   Required properties:
  86 +
  87 +   - interrupt-controller: identifies the node as an interrupt controller
  88 +
  89 +   - #address-cells: specifies the number of cells needed to encode an
  90 +     address. The value must be 0. As such, 'interrupt-map' nodes do not
  91 +     have to specify a parent unit address.
  92 +
  93 +   - #interrupt-cells: specifies the number of cells needed to encode an
  94 +     interrupt source. The value must be 1.
  95 +
  96 +   - interrupt-parent: the phandle for the interrupt controller that
  97 +     services interrupts for this device.
  98 +
  99 +   - interrupts: specifies the interrupt source of the parent interrupt
 100 +     controller. The format of the interrupt specifier depends on the
 101 +     parent interrupt controller.
 102 +
 103 +   b) PCI host bridge:
 104 +
 105 +   Required properties:
 106 +
 107 +   - #address-cells: specifies the number of cells needed to encode an
 108 +     address. The value must be 0.
 109 +
 110 +   - #size-cells: specifies the number of cells used to represent the size
 111 +     of an address. The value must be 2.
 112 +
 113 +   - #interrupt-cells: specifies the number of cells needed to encode an
 114 +     interrupt source. The value must be 1.
 115 +
 116 +   - device_type: must be "pci"
 117 +
 118 +   - bus-range: PCI bus numbers covered
 119 +
 120 +   - ranges: specifies the ranges for the PCI memory and I/O regions
 121 +
 122 +   - interrupt-map-mask,
 123 +   - interrupt-map: standard PCI properties to define the mapping of the
 124 +     PCI interface to interrupt numbers.
 125 +
 126 +   The PCI host bridge node migh have additional sub-nodes representing
 127 +   the onboard PCI devices/PCI slots. Each such sub-node must have the
 128 +   following mandatory properties:
 129 +
 130 +     - reg: used only for interrupt mapping, so only the first four bytes
 131 +       are used to refer to the correct bus number and device number.
 132 +
 133 +     - device_type: must be "pci"
 134 +
 135 +   If a given sub-node represents a PCI bridge it must have following
 136 +   mandatory properties as well:
 137 +
 138 +     - #address-cells: must be set to <3>
 139 +
 140 +     - #size-cells: must set to <2>
 141 +
 142 +     - #interrupt-cells: must be set to <1>
 143 +
 144 +     - interrupt-map-mask,
 145 +     - interrupt-map: standard PCI properties to define the mapping of the
 146 +       PCI interface to interrupt numbers.
 147 +
 148 +   Besides the required properties the sub-nodes may have these optional
 149 +   properties:
 150 +
 151 +     - status: indicates the operational status of the sub-node.
 152 +       Value must be either "disabled" or "okay".
 153 +
 154 +3) Example:
 155 +
 156 +   a) SoC specific dtsi file:
 157 +
 158 +       pci@10140000 {
 159 +               compatible = "ralink,rt3883-pci";
 160 +               reg = <0x10140000 0x20000>;
 161 +               #address-cells = <1>;
 162 +               #size-cells = <1>;
 163 +               ranges; /* direct mapping */
 164 +
 165 +               status = "disabled";
 166 +
 167 +               pciintc: interrupt-controller {
 168 +                       interrupt-controller;
 169 +                       #address-cells = <0>;
 170 +                       #interrupt-cells = <1>;
 171 +
 172 +                       interrupt-parent = <&cpuintc>;
 173 +                       interrupts = <4>;
 174 +               };
 175 +
 176 +               host-bridge {
 177 +                       #address-cells = <3>;
 178 +                       #size-cells = <2>;
 179 +                       #interrupt-cells = <1>;
 180 +
 181 +                       device_type = "pci";
 182 +
 183 +                       bus-range = <0 255>;
 184 +                       ranges = <
 185 +                               0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
 186 +                               0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
 187 +                       >;
 188 +
 189 +                       interrupt-map-mask = <0xf800 0 0 7>;
 190 +                       interrupt-map = <
 191 +                               /* IDSEL 17 */
 192 +                               0x8800 0 0 1 &pciintc 18
 193 +                               0x8800 0 0 2 &pciintc 18
 194 +                               0x8800 0 0 3 &pciintc 18
 195 +                               0x8800 0 0 4 &pciintc 18
 196 +                               /* IDSEL 18 */
 197 +                               0x9000 0 0 1 &pciintc 19
 198 +                               0x9000 0 0 2 &pciintc 19
 199 +                               0x9000 0 0 3 &pciintc 19
 200 +                               0x9000 0 0 4 &pciintc 19
 201 +                       >;
 202 +
 203 +                       pci-bridge@1 {
 204 +                               reg = <0x0800 0 0 0 0>;
 205 +                               device_type = "pci";
 206 +                               #interrupt-cells = <1>;
 207 +                               #address-cells = <3>;
 208 +                               #size-cells = <2>;
 209 +
 210 +                               interrupt-map-mask = <0x0 0 0 0>;
 211 +                               interrupt-map = <0x0 0 0 0 &pciintc 20>;
 212 +
 213 +                               status = "disabled";
 214 +                       };
 215 +
 216 +                       pci-slot@17 {
 217 +                               reg = <0x8800 0 0 0 0>;
 218 +                               device_type = "pci";
 219 +
 220 +                               status = "disabled";
 221 +                       };
 222 +
 223 +                       pci-slot@18 {
 224 +                               reg = <0x9000 0 0 0 0>;
 225 +                               device_type = "pci";
 226 +
 227 +                               status = "disabled";
 228 +                       };
 229 +               };
 230 +       };
 231 +
 232 +   b) Board specific dts file:
 233 +
 234 +       pci@10140000 {
 235 +               status = "okay";
 236 +
 237 +               host-bridge {
 238 +                       pci-bridge@1 {
 239 +                               status = "okay";
 240 +                       };
 241 +               };
 242 +       };
 243 --- a/arch/mips/pci/Makefile
 244 +++ b/arch/mips/pci/Makefile
 245 @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
 246  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
 247  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
 248  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
 249 +obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
 250  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
 251  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
 252  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
 253 --- /dev/null
 254 +++ b/arch/mips/pci/pci-rt3883.c
 255 @@ -0,0 +1,636 @@
 256 +/*
 257 + *  Ralink RT3662/RT3883 SoC PCI support
 258 + *
 259 + *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
 260 + *
 261 + *  Parts of this file are based on Ralink's 2.6.21 BSP
 262 + *
 263 + *  This program is free software; you can redistribute it and/or modify it
 264 + *  under the terms of the GNU General Public License version 2 as published
 265 + *  by the Free Software Foundation.
 266 + */
 267 +
 268 +#include <linux/types.h>
 269 +#include <linux/pci.h>
 270 +#include <linux/io.h>
 271 +#include <linux/init.h>
 272 +#include <linux/delay.h>
 273 +#include <linux/interrupt.h>
 274 +#include <linux/module.h>
 275 +#include <linux/of.h>
 276 +#include <linux/of_irq.h>
 277 +#include <linux/of_pci.h>
 278 +#include <linux/platform_device.h>
 279 +
 280 +#include <asm/mach-ralink/rt3883.h>
 281 +#include <asm/mach-ralink/ralink_regs.h>
 282 +
 283 +#define RT3883_MEMORY_BASE             0x00000000
 284 +#define RT3883_MEMORY_SIZE             0x02000000
 285 +
 286 +#define RT3883_PCI_REG_PCICFG          0x00
 287 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
 288 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
 289 +#define   RT3883_PCICFG_PCIRST         BIT(1)
 290 +#define RT3883_PCI_REG_PCIRAW          0x04
 291 +#define RT3883_PCI_REG_PCIINT          0x08
 292 +#define RT3883_PCI_REG_PCIENA          0x0c
 293 +
 294 +#define RT3883_PCI_REG_CFGADDR         0x20
 295 +#define RT3883_PCI_REG_CFGDATA         0x24
 296 +#define RT3883_PCI_REG_MEMBASE         0x28
 297 +#define RT3883_PCI_REG_IOBASE          0x2c
 298 +#define RT3883_PCI_REG_ARBCTL          0x80
 299 +
 300 +#define RT3883_PCI_REG_BASE(_x)                (0x1000 + (_x) * 0x1000)
 301 +#define RT3883_PCI_REG_BAR0SETUP(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x10)
 302 +#define RT3883_PCI_REG_IMBASEBAR0(_x)  (RT3883_PCI_REG_BASE((_x)) + 0x18)
 303 +#define RT3883_PCI_REG_ID(_x)          (RT3883_PCI_REG_BASE((_x)) + 0x30)
 304 +#define RT3883_PCI_REG_CLASS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x34)
 305 +#define RT3883_PCI_REG_SUBID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x38)
 306 +#define RT3883_PCI_REG_STATUS(_x)      (RT3883_PCI_REG_BASE((_x)) + 0x50)
 307 +
 308 +#define RT3883_PCI_MODE_NONE   0
 309 +#define RT3883_PCI_MODE_PCI    BIT(0)
 310 +#define RT3883_PCI_MODE_PCIE   BIT(1)
 311 +#define RT3883_PCI_MODE_BOTH   (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
 312 +
 313 +#define RT3883_PCI_IRQ_COUNT   32
 314 +
 315 +#define RT3883_P2P_BR_DEVNUM   1
 316 +
 317 +struct rt3883_pci_controller {
 318 +       void __iomem *base;
 319 +       spinlock_t lock;
 320 +
 321 +       struct device_node *intc_of_node;
 322 +       struct irq_domain *irq_domain;
 323 +
 324 +       struct pci_controller pci_controller;
 325 +       struct resource io_res;
 326 +       struct resource mem_res;
 327 +
 328 +       bool pcie_ready;
 329 +};
 330 +
 331 +static inline struct rt3883_pci_controller *
 332 +pci_bus_to_rt3883_controller(struct pci_bus *bus)
 333 +{
 334 +       struct pci_controller *hose;
 335 +
 336 +       hose = (struct pci_controller *) bus->sysdata;
 337 +       return container_of(hose, struct rt3883_pci_controller, pci_controller);
 338 +}
 339 +
 340 +static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
 341 +                                unsigned reg)
 342 +{
 343 +       return ioread32(rpc->base + reg);
 344 +}
 345 +
 346 +static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
 347 +                                 u32 val, unsigned reg)
 348 +{
 349 +       iowrite32(val, rpc->base + reg);
 350 +}
 351 +
 352 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 353 +                                        unsigned int func, unsigned int where)
 354 +{
 355 +       return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
 356 +              0x80000000;
 357 +}
 358 +
 359 +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 360 +                              unsigned bus, unsigned slot,
 361 +                              unsigned func, unsigned reg)
 362 +{
 363 +       unsigned long flags;
 364 +       u32 address;
 365 +       u32 ret;
 366 +
 367 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 368 +
 369 +       spin_lock_irqsave(&rpc->lock, flags);
 370 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 371 +       ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 372 +       spin_unlock_irqrestore(&rpc->lock, flags);
 373 +
 374 +       return ret;
 375 +}
 376 +
 377 +static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 378 +                                unsigned bus, unsigned slot,
 379 +                                unsigned func, unsigned reg, u32 val)
 380 +{
 381 +       unsigned long flags;
 382 +       u32 address;
 383 +
 384 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 385 +
 386 +       spin_lock_irqsave(&rpc->lock, flags);
 387 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 388 +       rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
 389 +       spin_unlock_irqrestore(&rpc->lock, flags);
 390 +}
 391 +
 392 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 393 +{
 394 +       struct rt3883_pci_controller *rpc;
 395 +       u32 pending;
 396 +
 397 +       rpc = irq_get_handler_data(irq);
 398 +
 399 +       pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
 400 +                 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 401 +
 402 +       if (!pending) {
 403 +               spurious_interrupt();
 404 +               return;
 405 +       }
 406 +
 407 +       while (pending) {
 408 +               unsigned bit = __ffs(pending);
 409 +
 410 +               irq = irq_find_mapping(rpc->irq_domain, bit);
 411 +               generic_handle_irq(irq);
 412 +
 413 +               pending &= ~BIT(bit);
 414 +       }
 415 +}
 416 +
 417 +static void rt3883_pci_irq_unmask(struct irq_data *d)
 418 +{
 419 +       struct rt3883_pci_controller *rpc;
 420 +       u32 t;
 421 +
 422 +       rpc = irq_data_get_irq_chip_data(d);
 423 +
 424 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 425 +       rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 426 +       /* flush write */
 427 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 428 +}
 429 +
 430 +static void rt3883_pci_irq_mask(struct irq_data *d)
 431 +{
 432 +       struct rt3883_pci_controller *rpc;
 433 +       u32 t;
 434 +
 435 +       rpc = irq_data_get_irq_chip_data(d);
 436 +
 437 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 438 +       rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 439 +       /* flush write */
 440 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 441 +}
 442 +
 443 +static struct irq_chip rt3883_pci_irq_chip = {
 444 +       .name           = "RT3883 PCI",
 445 +       .irq_mask       = rt3883_pci_irq_mask,
 446 +       .irq_unmask     = rt3883_pci_irq_unmask,
 447 +       .irq_mask_ack   = rt3883_pci_irq_mask,
 448 +};
 449 +
 450 +static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
 451 +                             irq_hw_number_t hw)
 452 +{
 453 +       irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
 454 +       irq_set_chip_data(irq, d->host_data);
 455 +
 456 +       return 0;
 457 +}
 458 +
 459 +static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
 460 +       .map = rt3883_pci_irq_map,
 461 +       .xlate = irq_domain_xlate_onecell,
 462 +};
 463 +
 464 +static int rt3883_pci_irq_init(struct device *dev,
 465 +                              struct rt3883_pci_controller *rpc)
 466 +{
 467 +       int irq;
 468 +
 469 +       irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
 470 +       if (irq == 0) {
 471 +               dev_err(dev, "%s has no IRQ",
 472 +                       of_node_full_name(rpc->intc_of_node));
 473 +               return -EINVAL;
 474 +       }
 475 +
 476 +       /* disable all interrupts */
 477 +       rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 478 +
 479 +       rpc->irq_domain =
 480 +               irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
 481 +                                     &rt3883_pci_irq_domain_ops,
 482 +                                     rpc);
 483 +       if (!rpc->irq_domain) {
 484 +               dev_err(dev, "unable to add IRQ domain\n");
 485 +               return -ENODEV;
 486 +       }
 487 +
 488 +       irq_set_handler_data(irq, rpc);
 489 +       irq_set_chained_handler(irq, rt3883_pci_irq_handler);
 490 +
 491 +       return 0;
 492 +}
 493 +
 494 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 495 +                                 int where, int size, u32 *val)
 496 +{
 497 +       struct rt3883_pci_controller *rpc;
 498 +       unsigned long flags;
 499 +       u32 address;
 500 +       u32 data;
 501 +
 502 +       rpc = pci_bus_to_rt3883_controller(bus);
 503 +
 504 +       if (!rpc->pcie_ready && bus->number == 1)
 505 +               return PCIBIOS_DEVICE_NOT_FOUND;
 506 +
 507 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 508 +                                        PCI_FUNC(devfn), where);
 509 +
 510 +       spin_lock_irqsave(&rpc->lock, flags);
 511 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 512 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 513 +       spin_unlock_irqrestore(&rpc->lock, flags);
 514 +
 515 +       switch (size) {
 516 +       case 1:
 517 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 518 +               break;
 519 +       case 2:
 520 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 521 +               break;
 522 +       case 4:
 523 +               *val = data;
 524 +               break;
 525 +       }
 526 +
 527 +       return PCIBIOS_SUCCESSFUL;
 528 +}
 529 +
 530 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 531 +                                  int where, int size, u32 val)
 532 +{
 533 +       struct rt3883_pci_controller *rpc;
 534 +       unsigned long flags;
 535 +       u32 address;
 536 +       u32 data;
 537 +
 538 +       rpc = pci_bus_to_rt3883_controller(bus);
 539 +
 540 +       if (!rpc->pcie_ready && bus->number == 1)
 541 +               return PCIBIOS_DEVICE_NOT_FOUND;
 542 +
 543 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 544 +                                        PCI_FUNC(devfn), where);
 545 +
 546 +       spin_lock_irqsave(&rpc->lock, flags);
 547 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 548 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 549 +
 550 +       switch (size) {
 551 +       case 1:
 552 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 553 +                      (val << ((where & 3) << 3));
 554 +               break;
 555 +       case 2:
 556 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 557 +                      (val << ((where & 3) << 3));
 558 +               break;
 559 +       case 4:
 560 +               data = val;
 561 +               break;
 562 +       }
 563 +
 564 +       rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
 565 +       spin_unlock_irqrestore(&rpc->lock, flags);
 566 +
 567 +       return PCIBIOS_SUCCESSFUL;
 568 +}
 569 +
 570 +static struct pci_ops rt3883_pci_ops = {
 571 +       .read   = rt3883_pci_config_read,
 572 +       .write  = rt3883_pci_config_write,
 573 +};
 574 +
 575 +static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
 576 +{
 577 +       u32 syscfg1;
 578 +       u32 rstctrl;
 579 +       u32 clkcfg1;
 580 +       u32 t;
 581 +
 582 +       rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 583 +       syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 584 +       clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 585 +
 586 +       if (mode & RT3883_PCI_MODE_PCIE) {
 587 +               rstctrl |= RT3883_RSTCTRL_PCIE;
 588 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 589 +
 590 +               /* setup PCI PAD drive mode */
 591 +               syscfg1 &= ~(0x30);
 592 +               syscfg1 |= (2 << 4);
 593 +               rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 594 +
 595 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 596 +               t &= ~BIT(31);
 597 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 598 +
 599 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 600 +               t &= 0x80ffffff;
 601 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 602 +
 603 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 604 +               t |= 0xa << 24;
 605 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 606 +
 607 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 608 +               t |= BIT(31);
 609 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 610 +
 611 +               msleep(50);
 612 +
 613 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 614 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 615 +       }
 616 +
 617 +       syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
 618 +
 619 +       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
 620 +
 621 +       if (mode & RT3883_PCI_MODE_PCI) {
 622 +               clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 623 +               rstctrl &= ~RT3883_RSTCTRL_PCI;
 624 +       }
 625 +
 626 +       if (mode & RT3883_PCI_MODE_PCIE) {
 627 +               clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 628 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 629 +       }
 630 +
 631 +       rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 632 +       rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 633 +       rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 634 +
 635 +       msleep(500);
 636 +
 637 +       /*
 638 +        * setup the device number of the P2P bridge
 639 +        * and de-assert the reset line
 640 +        */
 641 +       t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
 642 +       rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
 643 +
 644 +       /* flush write */
 645 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
 646 +       msleep(500);
 647 +
 648 +       if (mode & RT3883_PCI_MODE_PCIE) {
 649 +               msleep(500);
 650 +
 651 +               t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
 652 +
 653 +               rpc->pcie_ready = t & BIT(0);
 654 +
 655 +               if (!rpc->pcie_ready) {
 656 +                       /* reset the PCIe block */
 657 +                       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 658 +                       t |= RT3883_RSTCTRL_PCIE;
 659 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 660 +                       t &= ~RT3883_RSTCTRL_PCIE;
 661 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 662 +
 663 +                       /* turn off PCIe clock */
 664 +                       t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 665 +                       t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
 666 +                       rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 667 +
 668 +                       t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 669 +                       t &= ~0xf000c080;
 670 +                       rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 671 +               }
 672 +       }
 673 +
 674 +       /* enable PCI arbiter */
 675 +       rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 676 +}
 677 +
 678 +static int rt3883_pci_probe(struct platform_device *pdev)
 679 +{
 680 +       struct rt3883_pci_controller *rpc;
 681 +       struct device *dev = &pdev->dev;
 682 +       struct device_node *np = dev->of_node;
 683 +       struct resource *res;
 684 +       struct device_node *child;
 685 +       u32 val;
 686 +       int err;
 687 +       int mode;
 688 +
 689 +       rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 690 +       if (!rpc)
 691 +               return -ENOMEM;
 692 +
 693 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 694 +       if (!res)
 695 +               return -EINVAL;
 696 +
 697 +       rpc->base = devm_ioremap_resource(dev, res);
 698 +       if (IS_ERR(rpc->base))
 699 +               return PTR_ERR(rpc->base);
 700 +
 701 +       /* find the interrupt controller child node */
 702 +       for_each_child_of_node(np, child) {
 703 +               if (of_get_property(child, "interrupt-controller", NULL) &&
 704 +                   of_node_get(child)) {
 705 +                       rpc->intc_of_node = child;
 706 +                       break;
 707 +               }
 708 +       }
 709 +
 710 +       if (!rpc->intc_of_node) {
 711 +               dev_err(dev, "%s has no %s child node",
 712 +                       of_node_full_name(rpc->intc_of_node),
 713 +                       "interrupt controller");
 714 +               return -EINVAL;
 715 +       }
 716 +
 717 +       /* find the PCI host bridge child node */
 718 +       for_each_child_of_node(np, child) {
 719 +               if (child->type &&
 720 +                   of_node_cmp(child->type, "pci") == 0 &&
 721 +                   of_node_get(child)) {
 722 +                       rpc->pci_controller.of_node = child;
 723 +                       break;
 724 +               }
 725 +       }
 726 +
 727 +       if (!rpc->pci_controller.of_node) {
 728 +               dev_err(dev, "%s has no %s child node",
 729 +                       of_node_full_name(rpc->intc_of_node),
 730 +                       "PCI host bridge");
 731 +               err = -EINVAL;
 732 +               goto err_put_intc_node;
 733 +       }
 734 +
 735 +       mode = RT3883_PCI_MODE_NONE;
 736 +       for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
 737 +               int devfn;
 738 +
 739 +               if (!child->type ||
 740 +                   of_node_cmp(child->type, "pci") != 0)
 741 +                       continue;
 742 +
 743 +               devfn = of_pci_get_devfn(child);
 744 +               if (devfn < 0)
 745 +                       continue;
 746 +
 747 +               switch (PCI_SLOT(devfn)) {
 748 +               case 1:
 749 +                       mode |= RT3883_PCI_MODE_PCIE;
 750 +                       break;
 751 +
 752 +               case 17:
 753 +               case 18:
 754 +                       mode |= RT3883_PCI_MODE_PCI;
 755 +                       break;
 756 +               }
 757 +       }
 758 +
 759 +       if (mode == RT3883_PCI_MODE_NONE) {
 760 +               dev_err(dev, "unable to determine PCI mode\n");
 761 +               err = -EINVAL;
 762 +               goto err_put_hb_node;
 763 +       }
 764 +
 765 +       dev_info(dev, "mode:%s%s\n",
 766 +                (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
 767 +                (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
 768 +
 769 +       rt3883_pci_preinit(rpc, mode);
 770 +
 771 +       rpc->pci_controller.pci_ops = &rt3883_pci_ops;
 772 +       rpc->pci_controller.io_resource = &rpc->io_res;
 773 +       rpc->pci_controller.mem_resource = &rpc->mem_res;
 774 +
 775 +       /* Load PCI I/O and memory resources from DT */
 776 +       pci_load_of_ranges(&rpc->pci_controller,
 777 +                          rpc->pci_controller.of_node);
 778 +
 779 +       rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
 780 +       rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
 781 +
 782 +       ioport_resource.start = rpc->io_res.start;
 783 +       ioport_resource.end = rpc->io_res.end;
 784 +
 785 +       /* PCI */
 786 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
 787 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
 788 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
 789 +       rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
 790 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
 791 +
 792 +       /* PCIe */
 793 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
 794 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
 795 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
 796 +       rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
 797 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
 798 +
 799 +       err = rt3883_pci_irq_init(dev, rpc);
 800 +       if (err)
 801 +               goto err_put_hb_node;
 802 +
 803 +       /* PCIe */
 804 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
 805 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 806 +       rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
 807 +
 808 +       /* PCI */
 809 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
 810 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 811 +       rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
 812 +
 813 +       if (mode == RT3883_PCI_MODE_PCIE) {
 814 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
 815 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
 816 +
 817 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 818 +                                      PCI_BASE_ADDRESS_0,
 819 +                                      RT3883_MEMORY_BASE);
 820 +               /* flush write */
 821 +               rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 822 +                                     PCI_BASE_ADDRESS_0);
 823 +       } else {
 824 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 825 +                                      PCI_IO_BASE, 0x00000101);
 826 +       }
 827 +
 828 +       register_pci_controller(&rpc->pci_controller);
 829 +
 830 +       return 0;
 831 +
 832 +err_put_hb_node:
 833 +       of_node_put(rpc->pci_controller.of_node);
 834 +err_put_intc_node:
 835 +       of_node_put(rpc->intc_of_node);
 836 +       return err;
 837 +}
 838 +
 839 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 840 +{
 841 +       struct of_irq dev_irq;
 842 +       int err;
 843 +       int irq;
 844 +
 845 +       err = of_irq_map_pci(dev, &dev_irq);
 846 +       if (err) {
 847 +               pr_err("pci %s: unable to get irq map, err=%d\n",
 848 +                      pci_name((struct pci_dev *) dev), err);
 849 +               return 0;
 850 +       }
 851 +
 852 +       irq = irq_create_of_mapping(dev_irq.controller,
 853 +                                   dev_irq.specifier,
 854 +                                   dev_irq.size);
 855 +
 856 +       if (irq == 0)
 857 +               pr_crit("pci %s: no irq found for pin %u\n",
 858 +                       pci_name((struct pci_dev *) dev), pin);
 859 +       else
 860 +               pr_info("pci %s: using irq %d for pin %u\n",
 861 +                       pci_name((struct pci_dev *) dev), irq, pin);
 862 +
 863 +       return irq;
 864 +}
 865 +
 866 +int pcibios_plat_dev_init(struct pci_dev *dev)
 867 +{
 868 +       return 0;
 869 +}
 870 +
 871 +static const struct of_device_id rt3883_pci_ids[] = {
 872 +       { .compatible = "ralink,rt3883-pci" },
 873 +       {},
 874 +};
 875 +MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
 876 +
 877 +static struct platform_driver rt3883_pci_driver = {
 878 +       .probe = rt3883_pci_probe,
 879 +       .driver = {
 880 +               .name = "rt3883-pci",
 881 +               .owner = THIS_MODULE,
 882 +               .of_match_table = of_match_ptr(rt3883_pci_ids),
 883 +       },
 884 +};
 885 +
 886 +static int __init rt3883_pci_init(void)
 887 +{
 888 +       return platform_driver_register(&rt3883_pci_driver);
 889 +}
 890 +
 891 +postcore_initcall(rt3883_pci_init);
 892 --- a/arch/mips/ralink/Kconfig
 893 +++ b/arch/mips/ralink/Kconfig
 894 @@ -26,6 +26,7 @@ choice
 895                 bool "RT3883"
 896                 select USB_ARCH_HAS_OHCI
 897                 select USB_ARCH_HAS_EHCI
 898 +               select HW_HAS_PCI
 899
 900         config SOC_MT7620
 901                 bool "MT7620"