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[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.10 / 0122-pinmux.patch
1 From d59fe652e3674e98caa688b4ddc9308007267adc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 19 Aug 2013 13:49:52 +0200
4 Subject: [PATCH] pinctrl: ralink; add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/ralink/common.h | 21 +--
10 arch/mips/ralink/dts/mt7620a.dtsi | 7 +
11 drivers/pinctrl/Kconfig | 5 +
12 drivers/pinctrl/Makefile | 1 +
13 drivers/pinctrl/pinctrl-rt2880.c | 368 +++++++++++++++++++++++++++++++++++++
14 6 files changed, 385 insertions(+), 19 deletions(-)
15 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
16
17 Index: linux-3.10.9/arch/mips/Kconfig
18 ===================================================================
19 --- linux-3.10.9.orig/arch/mips/Kconfig 2013-08-28 16:34:42.449951676 +0200
20 +++ linux-3.10.9/arch/mips/Kconfig 2013-08-28 16:34:43.361951711 +0200
21 @@ -446,6 +446,8 @@
22 select HAVE_MACH_CLKDEV
23 select CLKDEV_LOOKUP
24 select ARCH_REQUIRE_GPIOLIB
25 + select PINCTRL
26 + select PINCTRL_RT2880
27
28 config SGI_IP22
29 bool "SGI IP22 (Indy/Indigo2)"
30 Index: linux-3.10.9/drivers/pinctrl/Kconfig
31 ===================================================================
32 --- linux-3.10.9.orig/drivers/pinctrl/Kconfig 2013-08-21 00:40:47.000000000 +0200
33 +++ linux-3.10.9/drivers/pinctrl/Kconfig 2013-08-28 16:34:43.361951711 +0200
34 @@ -114,6 +114,11 @@
35 select PINMUX
36 select PINCONF
37
38 +config PINCTRL_RT2880
39 + bool
40 + depends on RALINK
41 + select PINMUX
42 +
43 config PINCTRL_FALCON
44 bool
45 depends on SOC_FALCON
46 Index: linux-3.10.9/drivers/pinctrl/Makefile
47 ===================================================================
48 --- linux-3.10.9.orig/drivers/pinctrl/Makefile 2013-08-21 00:40:47.000000000 +0200
49 +++ linux-3.10.9/drivers/pinctrl/Makefile 2013-08-28 16:34:43.361951711 +0200
50 @@ -45,6 +45,7 @@
51 obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
52 obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
53 obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
54 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
55
56 obj-$(CONFIG_PLAT_ORION) += mvebu/
57 obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
58 Index: linux-3.10.9/drivers/pinctrl/pinctrl-rt2880.c
59 ===================================================================
60 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
61 +++ linux-3.10.9/drivers/pinctrl/pinctrl-rt2880.c 2013-08-28 16:34:43.361951711 +0200
62 @@ -0,0 +1,456 @@
63 +/*
64 + * linux/drivers/pinctrl/pinctrl-rt2880.c
65 + *
66 + * This program is free software; you can redistribute it and/or modify
67 + * it under the terms of the GNU General Public License version 2 as
68 + * publishhed by the Free Software Foundation.
69 + *
70 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
71 + */
72 +
73 +#include <linux/module.h>
74 +#include <linux/device.h>
75 +#include <linux/io.h>
76 +#include <linux/platform_device.h>
77 +#include <linux/slab.h>
78 +#include <linux/of.h>
79 +#include <linux/pinctrl/pinctrl.h>
80 +#include <linux/pinctrl/pinconf.h>
81 +#include <linux/pinctrl/pinmux.h>
82 +#include <linux/pinctrl/consumer.h>
83 +#include <linux/pinctrl/machine.h>
84 +
85 +#include <asm/mach-ralink/ralink_regs.h>
86 +#include <asm/mach-ralink/pinmux.h>
87 +#include <asm/mach-ralink/mt7620.h>
88 +
89 +#include "core.h"
90 +
91 +#define SYSC_REG_GPIO_MODE 0x60
92 +
93 +struct rt2880_priv {
94 + struct device *dev;
95 +
96 + struct pinctrl_pin_desc *pads;
97 + struct pinctrl_desc *desc;
98 +
99 + struct rt2880_pmx_func **func;
100 + int func_count;
101 +
102 + struct rt2880_pmx_group *groups;
103 + const char **group_names;
104 + int group_count;
105 +
106 + uint8_t *gpio;
107 + int max_pins;
108 +};
109 +
110 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
111 +
112 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
113 +{
114 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
115 +
116 + return p->group_count;
117 +}
118 +
119 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
120 + unsigned group)
121 +{
122 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
123 +
124 + if (group >= p->group_count)
125 + return NULL;
126 +
127 + return p->group_names[group];
128 +}
129 +
130 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
131 + unsigned group,
132 + const unsigned **pins,
133 + unsigned *num_pins)
134 +{
135 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
136 +
137 + if (group >= p->group_count)
138 + return -EINVAL;
139 +
140 + *pins = p->groups[group].func[0].pins;
141 + *num_pins = p->groups[group].func[0].pin_count;
142 +
143 + return 0;
144 +}
145 +
146 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
147 + struct pinctrl_map *map, unsigned num_maps)
148 +{
149 + int i;
150 +
151 + for (i = 0; i < num_maps; i++)
152 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
153 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
154 + kfree(map[i].data.configs.configs);
155 + kfree(map);
156 +}
157 +
158 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
159 + struct seq_file *s,
160 + unsigned offset)
161 +{
162 + seq_printf(s, "ralink pio");
163 +}
164 +
165 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
166 + struct device_node *np,
167 + struct pinctrl_map **map)
168 +{
169 + const char *function;
170 + int func = of_property_read_string(np, "ralink,function", &function);
171 + int grps = of_property_count_strings(np, "ralink,group");
172 + int i;
173 +
174 + if (func || !grps)
175 + return;
176 +
177 + for (i = 0; i < grps; i++) {
178 + const char *group;
179 +
180 + of_property_read_string_index(np, "ralink,group", i, &group);
181 +
182 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
183 + (*map)->name = function;
184 + (*map)->data.mux.group = group;
185 + (*map)->data.mux.function = function;
186 + (*map)++;
187 + }
188 +}
189 +
190 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
191 + struct device_node *np_config,
192 + struct pinctrl_map **map,
193 + unsigned *num_maps)
194 +{
195 + int max_maps = 0;
196 + struct pinctrl_map *tmp;
197 + struct device_node *np;
198 +
199 + for_each_child_of_node(np_config, np) {
200 + int ret = of_property_count_strings(np, "ralink,group");
201 +
202 + if (ret >= 0)
203 + max_maps += ret;
204 + }
205 +
206 + if (!max_maps)
207 + return max_maps;
208 +
209 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
210 + if (!*map)
211 + return -ENOMEM;
212 +
213 + tmp = *map;
214 +
215 + for_each_child_of_node(np_config, np)
216 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
217 + *num_maps = max_maps;
218 +
219 + return 0;
220 +}
221 +
222 +static const struct pinctrl_ops rt2880_pctrl_ops = {
223 + .get_groups_count = rt2880_get_group_count,
224 + .get_group_name = rt2880_get_group_name,
225 + .get_group_pins = rt2880_get_group_pins,
226 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
227 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
228 + .dt_free_map = rt2880_pinctrl_dt_free_map,
229 +};
230 +
231 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
232 +{
233 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
234 +
235 + return p->func_count;
236 +}
237 +
238 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
239 + unsigned func)
240 +{
241 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
242 +
243 + return p->func[func]->name;
244 +}
245 +
246 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
247 + unsigned func,
248 + const char * const **groups,
249 + unsigned * const num_groups)
250 +{
251 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
252 +
253 + if (p->func[func]->group_count == 1)
254 + *groups = &p->group_names[p->func[func]->groups[0]];
255 + else
256 + *groups = p->group_names;
257 +
258 + *num_groups = p->func[func]->group_count;
259 +
260 + return 0;
261 +}
262 +
263 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
264 + unsigned func,
265 + unsigned group)
266 +{
267 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
268 + u32 mode = 0;
269 +
270 + /* dont allow double use */
271 + if (p->groups[group].enabled) {
272 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
273 + return -EBUSY;
274 + }
275 +
276 + p->groups[group].enabled = 1;
277 + p->func[func]->enabled = 1;
278 +
279 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
280 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
281 +
282 + /* function 0 is gpio and needs special handling */
283 + if (func == 0) {
284 + int i;
285 +
286 + mode |= p->groups[group].mask << p->groups[group].shift;
287 + /* mark the pins as gpio */
288 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
289 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
290 + } else {
291 + mode |= p->func[func]->value << p->groups[group].shift;
292 + }
293 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
294 +
295 + return 0;
296 +}
297 +
298 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
299 + struct pinctrl_gpio_range *range,
300 + unsigned pin)
301 +{
302 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
303 +
304 + if (!p->gpio[pin]) {
305 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
306 + return -EINVAL;
307 + }
308 +
309 + return 0;
310 +}
311 +
312 +static const struct pinmux_ops rt2880_pmx_group_ops = {
313 + .get_functions_count = rt2880_pmx_func_count,
314 + .get_function_name = rt2880_pmx_func_name,
315 + .get_function_groups = rt2880_pmx_group_get_groups,
316 + .enable = rt2880_pmx_group_enable,
317 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
318 +};
319 +
320 +static struct pinctrl_desc rt2880_pctrl_desc = {
321 + .owner = THIS_MODULE,
322 + .name = "rt2880-pinmux",
323 + .pctlops = &rt2880_pctrl_ops,
324 + .pmxops = &rt2880_pmx_group_ops,
325 +};
326 +
327 +static struct rt2880_pmx_func gpio_func = {
328 + .name = "gpio",
329 +};
330 +
331 +static int rt2880_pinmux_index(struct rt2880_priv *p)
332 +{
333 + struct rt2880_pmx_func **f;
334 + struct rt2880_pmx_group *mux = p->groups;
335 + int i, j, c = 0;
336 +
337 + /* count the mux functions */
338 + while (mux->name) {
339 + p->group_count++;
340 + mux++;
341 + }
342 +
343 + /* allocate the group names array needed by the gpio function */
344 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
345 + if (!p->group_names)
346 + return -1;
347 +
348 + for (i = 0; i < p->group_count; i++) {
349 + p->group_names[i] = p->groups[i].name;
350 + p->func_count += p->groups[i].func_count;
351 + }
352 +
353 + /* we have a dummy function[0] for gpio */
354 + p->func_count++;
355 +
356 + /* allocate our function and group mapping index buffers */
357 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
358 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
359 + if (!f || !gpio_func.groups)
360 + return -1;
361 +
362 + /* add a backpointer to the function so it knows its group */
363 + gpio_func.group_count = p->group_count;
364 + for (i = 0; i < gpio_func.group_count; i++)
365 + gpio_func.groups[i] = i;
366 +
367 + f[c] = &gpio_func;
368 + c++;
369 +
370 + /* add remaining functions */
371 + for (i = 0; i < p->group_count; i++) {
372 + for (j = 0; j < p->groups[i].func_count; j++) {
373 + int k;
374 +
375 + f[c] = &p->groups[i].func[j];
376 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
377 + f[c]->groups[0] = i;
378 + f[c]->group_count = 1;
379 + c++;
380 + }
381 + }
382 + return 0;
383 +}
384 +
385 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
386 +{
387 + int i, j;
388 +
389 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
390 + for (i = 0; i < p->func_count; i++) {
391 + int pin;
392 +
393 + if (!p->func[i]->pin_count)
394 + continue;
395 +
396 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
397 + for (j = 0; j < p->func[i]->pin_count; j++)
398 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
399 +
400 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
401 + if (pin > p->max_pins)
402 + p->max_pins = pin;
403 + }
404 +
405 + /* the buffer that tells us which pins are gpio */
406 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
407 + GFP_KERNEL);
408 + /* the pads needed to tell pinctrl about our pins */
409 + p->pads = devm_kzalloc(p->dev,
410 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
411 + GFP_KERNEL);
412 + if (!p->pads || !p->gpio ) {
413 + dev_err(p->dev, "Failed to allocate gpio data\n");
414 + return -ENOMEM;
415 + }
416 +
417 + /* pin 0 is always a gpio */
418 + p->gpio[0] = 1;
419 +
420 + /* set the pads */
421 + for (i = 0; i < p->max_pins; i++) {
422 + /* strlen("ioXY") + 1 = 5 */
423 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
424 +
425 + if (!name) {
426 + dev_err(p->dev, "Failed to allocate pad name\n");
427 + return -ENOMEM;
428 + }
429 + snprintf(name, 5, "io%d", i);
430 + p->pads[i].number = i;
431 + p->pads[i].name = name;
432 + }
433 + p->desc->pins = p->pads;
434 + p->desc->npins = p->max_pins;
435 +
436 + return 0;
437 +}
438 +
439 +static int rt2880_pinmux_probe(struct platform_device *pdev)
440 +{
441 + struct rt2880_priv *p;
442 + struct pinctrl_dev *dev;
443 + struct device_node *np;
444 +
445 + if (!rt2880_pinmux_data)
446 + return -ENOSYS;
447 +
448 + /* setup the private data */
449 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
450 + if (!p)
451 + return -ENOMEM;
452 +
453 + p->dev = &pdev->dev;
454 + p->desc = &rt2880_pctrl_desc;
455 + p->groups = rt2880_pinmux_data;
456 + platform_set_drvdata(pdev, p);
457 +
458 + /* init the device */
459 + if (rt2880_pinmux_index(p)) {
460 + dev_err(&pdev->dev, "failed to load index\n");
461 + return -EINVAL;
462 + }
463 + if (rt2880_pinmux_pins(p)) {
464 + dev_err(&pdev->dev, "failed to load pins\n");
465 + return -EINVAL;
466 + }
467 + dev = pinctrl_register(p->desc, &pdev->dev, p);
468 + if (IS_ERR(dev))
469 + return PTR_ERR(dev);
470 +
471 + /* finalize by adding gpio ranges for enables gpio controllers */
472 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
473 + const __be32 *ngpio, *gpiobase;
474 + struct pinctrl_gpio_range *range;
475 + char *name;
476 +
477 + if (!of_device_is_available(np))
478 + continue;
479 +
480 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
481 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
482 + if (!ngpio || !gpiobase) {
483 + dev_err(&pdev->dev, "failed to load chip info\n");
484 + return -EINVAL;
485 + }
486 +
487 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
488 + range->name = name = (char *) &range[1];
489 + sprintf(name, "pio");
490 + range->npins = __be32_to_cpu(*ngpio);
491 + range->base = __be32_to_cpu(*gpiobase);
492 + pinctrl_add_gpio_range(dev, range);
493 + }
494 +
495 + return 0;
496 +}
497 +
498 +static const struct of_device_id rt2880_pinmux_match[] = {
499 + { .compatible = "ralink,rt2880-pinmux" },
500 + {},
501 +};
502 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
503 +
504 +static struct platform_driver rt2880_pinmux_driver = {
505 + .probe = rt2880_pinmux_probe,
506 + .driver = {
507 + .name = "rt2880-pinmux",
508 + .owner = THIS_MODULE,
509 + .of_match_table = rt2880_pinmux_match,
510 + },
511 +};
512 +
513 +int __init rt2880_pinmux_init(void)
514 +{
515 + return platform_driver_register(&rt2880_pinmux_driver);
516 +}
517 +
518 +core_initcall_sync(rt2880_pinmux_init);
519 Index: linux-3.10.9/arch/mips/include/asm/mach-ralink/pinmux.h
520 ===================================================================
521 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
522 +++ linux-3.10.9/arch/mips/include/asm/mach-ralink/pinmux.h 2013-08-28 16:34:43.361951711 +0200
523 @@ -0,0 +1,47 @@
524 +/*
525 + * This program is free software; you can redistribute it and/or modify
526 + * it under the terms of the GNU General Public License version 2 as
527 + * publishhed by the Free Software Foundation.
528 + *
529 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
530 + */
531 +
532 +#ifndef _RT288X_PINMUX_H__
533 +#define _RT288X_PINMUX_H__
534 +
535 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
536 +#define GRP(_name, _func, _mask, _shift) \
537 + { .name = _name, .mask = _mask, .shift = _shift, \
538 + .func = _func, \
539 + .func_count = ARRAY_SIZE(_func) }
540 +
541 +struct rt2880_pmx_group;
542 +
543 +struct rt2880_pmx_func {
544 + const char *name;
545 + const char value;
546 +
547 + int pin_first;
548 + int pin_count;
549 + int *pins;
550 +
551 + int *groups;
552 + int group_count;
553 +
554 + int enabled;
555 +};
556 +
557 +struct rt2880_pmx_group {
558 + const char *name;
559 + int enabled;
560 +
561 + const u32 shift;
562 + const char mask;
563 +
564 + struct rt2880_pmx_func *func;
565 + int func_count;
566 +};
567 +
568 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
569 +
570 +#endif
571 Index: linux-3.10.9/arch/mips/ralink/mt7620.c
572 ===================================================================
573 --- linux-3.10.9.orig/arch/mips/ralink/mt7620.c 2013-08-28 16:34:42.829951688 +0200
574 +++ linux-3.10.9/arch/mips/ralink/mt7620.c 2013-08-28 16:34:43.361951711 +0200
575 @@ -17,6 +17,7 @@
576 #include <asm/mipsregs.h>
577 #include <asm/mach-ralink/ralink_regs.h>
578 #include <asm/mach-ralink/mt7620.h>
579 +#include <asm/mach-ralink/pinmux.h>
580
581 #include "common.h"
582
583 @@ -48,118 +49,40 @@
584 /* the pll dividers */
585 static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
586
587 -static struct ralink_pinmux_grp mode_mux[] = {
588 - {
589 - .name = "i2c",
590 - .mask = MT7620_GPIO_MODE_I2C,
591 - .gpio_first = 1,
592 - .gpio_last = 2,
593 - }, {
594 - .name = "spi",
595 - .mask = MT7620_GPIO_MODE_SPI,
596 - .gpio_first = 3,
597 - .gpio_last = 6,
598 - }, {
599 - .name = "uartlite",
600 - .mask = MT7620_GPIO_MODE_UART1,
601 - .gpio_first = 15,
602 - .gpio_last = 16,
603 - }, {
604 - .name = "wdt",
605 - .mask = MT7620_GPIO_MODE_WDT,
606 - .gpio_first = 17,
607 - .gpio_last = 17,
608 - }, {
609 - .name = "mdio",
610 - .mask = MT7620_GPIO_MODE_MDIO,
611 - .gpio_first = 22,
612 - .gpio_last = 23,
613 - }, {
614 - .name = "rgmii1",
615 - .mask = MT7620_GPIO_MODE_RGMII1,
616 - .gpio_first = 24,
617 - .gpio_last = 35,
618 - }, {
619 - .name = "spi refclk",
620 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
621 - .gpio_first = 37,
622 - .gpio_last = 39,
623 - }, {
624 - .name = "jtag",
625 - .mask = MT7620_GPIO_MODE_JTAG,
626 - .gpio_first = 40,
627 - .gpio_last = 44,
628 - }, {
629 - /* shared lines with jtag */
630 - .name = "ephy",
631 - .mask = MT7620_GPIO_MODE_EPHY,
632 - .gpio_first = 40,
633 - .gpio_last = 44,
634 - }, {
635 - .name = "nand",
636 - .mask = MT7620_GPIO_MODE_JTAG,
637 - .gpio_first = 45,
638 - .gpio_last = 59,
639 - }, {
640 - .name = "rgmii2",
641 - .mask = MT7620_GPIO_MODE_RGMII2,
642 - .gpio_first = 60,
643 - .gpio_last = 71,
644 - }, {
645 - .name = "wled",
646 - .mask = MT7620_GPIO_MODE_WLED,
647 - .gpio_first = 72,
648 - .gpio_last = 72,
649 - }, {0}
650 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 1, 1, 2) };
651 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 1, 3, 4) };
652 +static struct rt2880_pmx_func uartf_grp[] = {
653 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
654 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
655 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
656 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
657 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
658 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
659 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
660 };
661 -
662 -static struct ralink_pinmux_grp uart_mux[] = {
663 - {
664 - .name = "uartf",
665 - .mask = MT7620_GPIO_MODE_UARTF,
666 - .gpio_first = 7,
667 - .gpio_last = 14,
668 - }, {
669 - .name = "pcm uartf",
670 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
671 - .gpio_first = 7,
672 - .gpio_last = 14,
673 - }, {
674 - .name = "pcm i2s",
675 - .mask = MT7620_GPIO_MODE_PCM_I2S,
676 - .gpio_first = 7,
677 - .gpio_last = 14,
678 - }, {
679 - .name = "i2s uartf",
680 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
681 - .gpio_first = 7,
682 - .gpio_last = 14,
683 - }, {
684 - .name = "pcm gpio",
685 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
686 - .gpio_first = 11,
687 - .gpio_last = 14,
688 - }, {
689 - .name = "gpio uartf",
690 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
691 - .gpio_first = 7,
692 - .gpio_last = 10,
693 - }, {
694 - .name = "gpio i2s",
695 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
696 - .gpio_first = 7,
697 - .gpio_last = 10,
698 - }, {
699 - .name = "gpio",
700 - .mask = MT7620_GPIO_MODE_GPIO,
701 - }, {0}
702 -};
703 -
704 -struct ralink_pinmux rt_gpio_pinmux = {
705 - .mode = mode_mux,
706 - .uart = uart_mux,
707 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
708 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
709 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 1, 15, 2) };
710 +static struct rt2880_pmx_func wdt_grp[] = { FUNC("wdt", 1, 17, 1) };
711 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 1, 22, 2) };
712 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 1, 24, 12) };
713 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 1, 37, 3) };
714 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 1, 40, 5) };
715 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 1, 60, 12) };
716 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 1, 72, 1) };
717 +
718 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
719 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
720 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
721 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
722 + GRP("wdt", wdt_grp, 1, MT7620_GPIO_MODE_WDT),
723 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
724 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
725 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
726 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
727 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
728 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
729 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
730 + MT7620_GPIO_MODE_UART0_SHIFT),
731 + { 0 }
732 };
733
734 void __init ralink_clk_init(void)
735 @@ -281,4 +204,6 @@
736 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
737 pr_info("Digital PMU set to %s control\n",
738 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
739 +
740 + rt2880_pinmux_data = mt7620a_pinmux_data;
741 }
742 Index: linux-3.10.9/arch/mips/ralink/rt305x.c
743 ===================================================================
744 --- linux-3.10.9.orig/arch/mips/ralink/rt305x.c 2013-08-28 16:34:43.061951698 +0200
745 +++ linux-3.10.9/arch/mips/ralink/rt305x.c 2013-08-28 16:34:43.365951713 +0200
746 @@ -17,90 +17,71 @@
747 #include <asm/mipsregs.h>
748 #include <asm/mach-ralink/ralink_regs.h>
749 #include <asm/mach-ralink/rt305x.h>
750 +#include <asm/mach-ralink/pinmux.h>
751
752 #include "common.h"
753
754 enum rt305x_soc_type rt305x_soc;
755
756 -static struct ralink_pinmux_grp mode_mux[] = {
757 - {
758 - .name = "i2c",
759 - .mask = RT305X_GPIO_MODE_I2C,
760 - .gpio_first = RT305X_GPIO_I2C_SD,
761 - .gpio_last = RT305X_GPIO_I2C_SCLK,
762 - }, {
763 - .name = "spi",
764 - .mask = RT305X_GPIO_MODE_SPI,
765 - .gpio_first = RT305X_GPIO_SPI_EN,
766 - .gpio_last = RT305X_GPIO_SPI_CLK,
767 - }, {
768 - .name = "uartlite",
769 - .mask = RT305X_GPIO_MODE_UART1,
770 - .gpio_first = RT305X_GPIO_UART1_TXD,
771 - .gpio_last = RT305X_GPIO_UART1_RXD,
772 - }, {
773 - .name = "jtag",
774 - .mask = RT305X_GPIO_MODE_JTAG,
775 - .gpio_first = RT305X_GPIO_JTAG_TDO,
776 - .gpio_last = RT305X_GPIO_JTAG_TDI,
777 - }, {
778 - .name = "mdio",
779 - .mask = RT305X_GPIO_MODE_MDIO,
780 - .gpio_first = RT305X_GPIO_MDIO_MDC,
781 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
782 - }, {
783 - .name = "sdram",
784 - .mask = RT305X_GPIO_MODE_SDRAM,
785 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
786 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
787 - }, {
788 - .name = "rgmii",
789 - .mask = RT305X_GPIO_MODE_RGMII,
790 - .gpio_first = RT305X_GPIO_GE0_TXD0,
791 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
792 - }, {0}
793 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
794 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
795 +static struct rt2880_pmx_func uartf_func[] = {
796 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
797 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
798 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
799 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
800 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
801 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
802 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
803 +};
804 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
805 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
806 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
807 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
808 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
809 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
810 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
811 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
812 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
813 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
814 +
815 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
816 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
817 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
818 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
819 + RT305X_GPIO_MODE_UART0_SHIFT),
820 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
821 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
822 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
823 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
824 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
825 + { 0 }
826 +};
827 +
828 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
829 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
830 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
831 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
832 + RT305X_GPIO_MODE_UART0_SHIFT),
833 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
834 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
835 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
836 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
837 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
838 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
839 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
840 + { 0 }
841 };
842
843 -static struct ralink_pinmux_grp uart_mux[] = {
844 - {
845 - .name = "uartf",
846 - .mask = RT305X_GPIO_MODE_UARTF,
847 - .gpio_first = RT305X_GPIO_7,
848 - .gpio_last = RT305X_GPIO_14,
849 - }, {
850 - .name = "pcm uartf",
851 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
852 - .gpio_first = RT305X_GPIO_7,
853 - .gpio_last = RT305X_GPIO_14,
854 - }, {
855 - .name = "pcm i2s",
856 - .mask = RT305X_GPIO_MODE_PCM_I2S,
857 - .gpio_first = RT305X_GPIO_7,
858 - .gpio_last = RT305X_GPIO_14,
859 - }, {
860 - .name = "i2s uartf",
861 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
862 - .gpio_first = RT305X_GPIO_7,
863 - .gpio_last = RT305X_GPIO_14,
864 - }, {
865 - .name = "pcm gpio",
866 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
867 - .gpio_first = RT305X_GPIO_10,
868 - .gpio_last = RT305X_GPIO_14,
869 - }, {
870 - .name = "gpio uartf",
871 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
872 - .gpio_first = RT305X_GPIO_7,
873 - .gpio_last = RT305X_GPIO_10,
874 - }, {
875 - .name = "gpio i2s",
876 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
877 - .gpio_first = RT305X_GPIO_7,
878 - .gpio_last = RT305X_GPIO_10,
879 - }, {
880 - .name = "gpio",
881 - .mask = RT305X_GPIO_MODE_GPIO,
882 - }, {0}
883 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
884 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
885 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
886 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
887 + RT305X_GPIO_MODE_UART0_SHIFT),
888 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
889 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
890 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
891 + { 0 }
892 };
893
894 static void rt305x_wdt_reset(void)
895 @@ -114,14 +95,6 @@
896 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
897 }
898
899 -struct ralink_pinmux rt_gpio_pinmux = {
900 - .mode = mode_mux,
901 - .uart = uart_mux,
902 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
903 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
904 - .wdt_reset = rt305x_wdt_reset,
905 -};
906 -
907 static unsigned long rt5350_get_mem_size(void)
908 {
909 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
910 @@ -291,11 +264,14 @@
911 soc_info->mem_base = RT305X_SDRAM_BASE;
912 if (soc_is_rt5350()) {
913 soc_info->mem_size = rt5350_get_mem_size();
914 + rt2880_pinmux_data = rt5350_pinmux_data;
915 } else if (soc_is_rt305x() || soc_is_rt3350()) {
916 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
917 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
918 + rt2880_pinmux_data = rt3050_pinmux_data;
919 } else if (soc_is_rt3352()) {
920 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
921 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
922 + rt2880_pinmux_data = rt3352_pinmux_data;
923 }
924 }
925 Index: linux-3.10.9/arch/mips/include/asm/mach-ralink/rt305x.h
926 ===================================================================
927 --- linux-3.10.9.orig/arch/mips/include/asm/mach-ralink/rt305x.h 2013-08-21 00:40:47.000000000 +0200
928 +++ linux-3.10.9/arch/mips/include/asm/mach-ralink/rt305x.h 2013-08-28 16:34:43.365951713 +0200
929 @@ -125,24 +125,28 @@
930 #define RT305X_GPIO_GE0_TXD0 40
931 #define RT305X_GPIO_GE0_RXCLK 51
932
933 -#define RT305X_GPIO_MODE_I2C BIT(0)
934 -#define RT305X_GPIO_MODE_SPI BIT(1)
935 #define RT305X_GPIO_MODE_UART0_SHIFT 2
936 #define RT305X_GPIO_MODE_UART0_MASK 0x7
937 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
938 -#define RT305X_GPIO_MODE_UARTF 0x0
939 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
940 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
941 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
942 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
943 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
944 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
945 -#define RT305X_GPIO_MODE_GPIO 0x7
946 -#define RT305X_GPIO_MODE_UART1 BIT(5)
947 -#define RT305X_GPIO_MODE_JTAG BIT(6)
948 -#define RT305X_GPIO_MODE_MDIO BIT(7)
949 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
950 -#define RT305X_GPIO_MODE_RGMII BIT(9)
951 +#define RT305X_GPIO_MODE_UARTF 0
952 +#define RT305X_GPIO_MODE_PCM_UARTF 1
953 +#define RT305X_GPIO_MODE_PCM_I2S 2
954 +#define RT305X_GPIO_MODE_I2S_UARTF 3
955 +#define RT305X_GPIO_MODE_PCM_GPIO 4
956 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
957 +#define RT305X_GPIO_MODE_GPIO_I2S 6
958 +#define RT305X_GPIO_MODE_GPIO 7
959 +
960 +#define RT305X_GPIO_MODE_I2C 0
961 +#define RT305X_GPIO_MODE_SPI 1
962 +#define RT305X_GPIO_MODE_UART1 5
963 +#define RT305X_GPIO_MODE_JTAG 6
964 +#define RT305X_GPIO_MODE_MDIO 7
965 +#define RT305X_GPIO_MODE_SDRAM 8
966 +#define RT305X_GPIO_MODE_RGMII 9
967 +#define RT5350_GPIO_MODE_PHY_LED 14
968 +#define RT3352_GPIO_MODE_LNA 18
969 +#define RT3352_GPIO_MODE_PA 20
970
971 #define RT3352_SYSC_REG_SYSCFG0 0x010
972 #define RT3352_SYSC_REG_SYSCFG1 0x014
973 Index: linux-3.10.9/arch/mips/include/asm/mach-ralink/mt7620.h
974 ===================================================================
975 --- linux-3.10.9.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2013-08-28 16:34:42.625951682 +0200
976 +++ linux-3.10.9/arch/mips/include/asm/mach-ralink/mt7620.h 2013-08-28 18:32:38.370254386 +0200
977 @@ -59,7 +59,6 @@
978 #define MT7620_DDR2_SIZE_MIN 32
979 #define MT7620_DDR2_SIZE_MAX 256
980
981 -#define MT7620_GPIO_MODE_I2C BIT(0)
982 #define MT7620_GPIO_MODE_UART0_SHIFT 2
983 #define MT7620_GPIO_MODE_UART0_MASK 0x7
984 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
985 @@ -71,15 +70,17 @@
986 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
987 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
988 #define MT7620_GPIO_MODE_GPIO 0x7
989 -#define MT7620_GPIO_MODE_UART1 BIT(5)
990 -#define MT7620_GPIO_MODE_MDIO BIT(8)
991 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
992 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
993 -#define MT7620_GPIO_MODE_SPI BIT(11)
994 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
995 -#define MT7620_GPIO_MODE_WLED BIT(13)
996 -#define MT7620_GPIO_MODE_JTAG BIT(15)
997 -#define MT7620_GPIO_MODE_EPHY BIT(15)
998 -#define MT7620_GPIO_MODE_WDT BIT(22)
999 +
1000 +#define MT7620_GPIO_MODE_I2C 0
1001 +#define MT7620_GPIO_MODE_UART1 5
1002 +#define MT7620_GPIO_MODE_MDIO 8
1003 +#define MT7620_GPIO_MODE_RGMII1 9
1004 +#define MT7620_GPIO_MODE_RGMII2 10
1005 +#define MT7620_GPIO_MODE_SPI 11
1006 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
1007 +#define MT7620_GPIO_MODE_WLED 13
1008 +#define MT7620_GPIO_MODE_JTAG 15
1009 +#define MT7620_GPIO_MODE_EPHY 15
1010 +#define MT7620_GPIO_MODE_WDT 22
1011
1012 #endif
1013 Index: linux-3.10.9/arch/mips/include/asm/mach-ralink/rt3883.h
1014 ===================================================================
1015 --- linux-3.10.9.orig/arch/mips/include/asm/mach-ralink/rt3883.h 2013-08-21 00:40:47.000000000 +0200
1016 +++ linux-3.10.9/arch/mips/include/asm/mach-ralink/rt3883.h 2013-08-28 18:33:57.554258201 +0200
1017 @@ -112,8 +112,6 @@
1018 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
1019 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
1020
1021 -#define RT3883_GPIO_MODE_I2C BIT(0)
1022 -#define RT3883_GPIO_MODE_SPI BIT(1)
1023 #define RT3883_GPIO_MODE_UART0_SHIFT 2
1024 #define RT3883_GPIO_MODE_UART0_MASK 0x7
1025 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
1026 @@ -125,11 +123,15 @@
1027 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
1028 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
1029 #define RT3883_GPIO_MODE_GPIO 0x7
1030 -#define RT3883_GPIO_MODE_UART1 BIT(5)
1031 -#define RT3883_GPIO_MODE_JTAG BIT(6)
1032 -#define RT3883_GPIO_MODE_MDIO BIT(7)
1033 -#define RT3883_GPIO_MODE_GE1 BIT(9)
1034 -#define RT3883_GPIO_MODE_GE2 BIT(10)
1035 +
1036 +#define RT3883_GPIO_MODE_I2C 0
1037 +#define RT3883_GPIO_MODE_SPI 1
1038 +#define RT3883_GPIO_MODE_UART1 5
1039 +#define RT3883_GPIO_MODE_JTAG 6
1040 +#define RT3883_GPIO_MODE_MDIO 7
1041 +#define RT3883_GPIO_MODE_GE1 9
1042 +#define RT3883_GPIO_MODE_GE2 10
1043 +
1044 #define RT3883_GPIO_MODE_PCI_SHIFT 11
1045 #define RT3883_GPIO_MODE_PCI_MASK 0x7
1046 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
1047 Index: linux-3.10.9/arch/mips/ralink/common.h
1048 ===================================================================
1049 --- linux-3.10.9.orig/arch/mips/ralink/common.h 2013-08-28 16:34:42.453951675 +0200
1050 +++ linux-3.10.9/arch/mips/ralink/common.h 2013-08-28 18:10:55.014197854 +0200
1051 @@ -11,25 +11,6 @@
1052
1053 #define RAMIPS_SYS_TYPE_LEN 32
1054
1055 -struct ralink_pinmux_grp {
1056 - const char *name;
1057 - u32 mask;
1058 - int gpio_first;
1059 - int gpio_last;
1060 -};
1061 -
1062 -struct ralink_pinmux {
1063 - struct ralink_pinmux_grp *mode;
1064 - struct ralink_pinmux_grp *uart;
1065 - int uart_shift;
1066 - u32 uart_mask;
1067 - void (*wdt_reset)(void);
1068 - struct ralink_pinmux_grp *pci;
1069 - int pci_shift;
1070 - u32 pci_mask;
1071 -};
1072 -extern struct ralink_pinmux rt_gpio_pinmux;
1073 -
1074 struct ralink_soc_info {
1075 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
1076 unsigned char *compatible;
1077 Index: linux-3.10.9/arch/mips/ralink/rt3883.c
1078 ===================================================================
1079 --- linux-3.10.9.orig/arch/mips/ralink/rt3883.c 2013-08-21 00:40:47.000000000 +0200
1080 +++ linux-3.10.9/arch/mips/ralink/rt3883.c 2013-08-28 18:47:07.442290690 +0200
1081 @@ -17,132 +17,50 @@
1082 #include <asm/mipsregs.h>
1083 #include <asm/mach-ralink/ralink_regs.h>
1084 #include <asm/mach-ralink/rt3883.h>
1085 +#include <asm/mach-ralink/pinmux.h>
1086
1087 #include "common.h"
1088
1089 -static struct ralink_pinmux_grp mode_mux[] = {
1090 - {
1091 - .name = "i2c",
1092 - .mask = RT3883_GPIO_MODE_I2C,
1093 - .gpio_first = RT3883_GPIO_I2C_SD,
1094 - .gpio_last = RT3883_GPIO_I2C_SCLK,
1095 - }, {
1096 - .name = "spi",
1097 - .mask = RT3883_GPIO_MODE_SPI,
1098 - .gpio_first = RT3883_GPIO_SPI_CS0,
1099 - .gpio_last = RT3883_GPIO_SPI_MISO,
1100 - }, {
1101 - .name = "uartlite",
1102 - .mask = RT3883_GPIO_MODE_UART1,
1103 - .gpio_first = RT3883_GPIO_UART1_TXD,
1104 - .gpio_last = RT3883_GPIO_UART1_RXD,
1105 - }, {
1106 - .name = "jtag",
1107 - .mask = RT3883_GPIO_MODE_JTAG,
1108 - .gpio_first = RT3883_GPIO_JTAG_TDO,
1109 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
1110 - }, {
1111 - .name = "mdio",
1112 - .mask = RT3883_GPIO_MODE_MDIO,
1113 - .gpio_first = RT3883_GPIO_MDIO_MDC,
1114 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
1115 - }, {
1116 - .name = "ge1",
1117 - .mask = RT3883_GPIO_MODE_GE1,
1118 - .gpio_first = RT3883_GPIO_GE1_TXD0,
1119 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
1120 - }, {
1121 - .name = "ge2",
1122 - .mask = RT3883_GPIO_MODE_GE2,
1123 - .gpio_first = RT3883_GPIO_GE2_TXD0,
1124 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
1125 - }, {
1126 - .name = "pci",
1127 - .mask = RT3883_GPIO_MODE_PCI,
1128 - .gpio_first = RT3883_GPIO_PCI_AD0,
1129 - .gpio_last = RT3883_GPIO_PCI_AD31,
1130 - }, {
1131 - .name = "lna a",
1132 - .mask = RT3883_GPIO_MODE_LNA_A,
1133 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
1134 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
1135 - }, {
1136 - .name = "lna g",
1137 - .mask = RT3883_GPIO_MODE_LNA_G,
1138 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
1139 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
1140 - }, {0}
1141 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
1142 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
1143 +static struct rt2880_pmx_func uartf_func[] = {
1144 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
1145 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
1146 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
1147 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
1148 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
1149 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
1150 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
1151 };
1152 -
1153 -static struct ralink_pinmux_grp uart_mux[] = {
1154 - {
1155 - .name = "uartf",
1156 - .mask = RT3883_GPIO_MODE_UARTF,
1157 - .gpio_first = RT3883_GPIO_7,
1158 - .gpio_last = RT3883_GPIO_14,
1159 - }, {
1160 - .name = "pcm uartf",
1161 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
1162 - .gpio_first = RT3883_GPIO_7,
1163 - .gpio_last = RT3883_GPIO_14,
1164 - }, {
1165 - .name = "pcm i2s",
1166 - .mask = RT3883_GPIO_MODE_PCM_I2S,
1167 - .gpio_first = RT3883_GPIO_7,
1168 - .gpio_last = RT3883_GPIO_14,
1169 - }, {
1170 - .name = "i2s uartf",
1171 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
1172 - .gpio_first = RT3883_GPIO_7,
1173 - .gpio_last = RT3883_GPIO_14,
1174 - }, {
1175 - .name = "pcm gpio",
1176 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
1177 - .gpio_first = RT3883_GPIO_11,
1178 - .gpio_last = RT3883_GPIO_14,
1179 - }, {
1180 - .name = "gpio uartf",
1181 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
1182 - .gpio_first = RT3883_GPIO_7,
1183 - .gpio_last = RT3883_GPIO_10,
1184 - }, {
1185 - .name = "gpio i2s",
1186 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
1187 - .gpio_first = RT3883_GPIO_7,
1188 - .gpio_last = RT3883_GPIO_10,
1189 - }, {
1190 - .name = "gpio",
1191 - .mask = RT3883_GPIO_MODE_GPIO,
1192 - }, {0}
1193 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
1194 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
1195 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
1196 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
1197 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
1198 +static struct rt2880_pmx_func pci_func[] = {
1199 + FUNC("pci-dev", 0, 40, 32),
1200 + FUNC("pci-host2", 1, 40, 32),
1201 + FUNC("pci-host1", 2, 40, 32),
1202 + FUNC("pci-fnc", 3, 40, 32)
1203 };
1204 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
1205 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
1206
1207 -static struct ralink_pinmux_grp pci_mux[] = {
1208 - {
1209 - .name = "pci-dev",
1210 - .mask = 0,
1211 - .gpio_first = RT3883_GPIO_PCI_AD0,
1212 - .gpio_last = RT3883_GPIO_PCI_AD31,
1213 - }, {
1214 - .name = "pci-host2",
1215 - .mask = 1,
1216 - .gpio_first = RT3883_GPIO_PCI_AD0,
1217 - .gpio_last = RT3883_GPIO_PCI_AD31,
1218 - }, {
1219 - .name = "pci-host1",
1220 - .mask = 2,
1221 - .gpio_first = RT3883_GPIO_PCI_AD0,
1222 - .gpio_last = RT3883_GPIO_PCI_AD31,
1223 - }, {
1224 - .name = "pci-fnc",
1225 - .mask = 3,
1226 - .gpio_first = RT3883_GPIO_PCI_AD0,
1227 - .gpio_last = RT3883_GPIO_PCI_AD31,
1228 - }, {
1229 - .name = "pci-gpio",
1230 - .mask = 7,
1231 - .gpio_first = RT3883_GPIO_PCI_AD0,
1232 - .gpio_last = RT3883_GPIO_PCI_AD31,
1233 - }, {0}
1234 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
1235 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
1236 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
1237 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
1238 + RT3883_GPIO_MODE_UART0_SHIFT),
1239 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
1240 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
1241 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
1242 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
1243 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
1244 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
1245 + RT3883_GPIO_MODE_PCI_SHIFT),
1246 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
1247 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
1248 + { 0 }
1249 };
1250
1251 static void rt3883_wdt_reset(void)
1252 @@ -155,17 +73,6 @@
1253 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
1254 }
1255
1256 -struct ralink_pinmux rt_gpio_pinmux = {
1257 - .mode = mode_mux,
1258 - .uart = uart_mux,
1259 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
1260 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
1261 - .wdt_reset = rt3883_wdt_reset,
1262 - .pci = pci_mux,
1263 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
1264 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
1265 -};
1266 -
1267 void __init ralink_clk_init(void)
1268 {
1269 unsigned long cpu_rate, sys_rate;
1270 @@ -243,4 +150,6 @@
1271 soc_info->mem_base = RT3883_SDRAM_BASE;
1272 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
1273 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
1274 +
1275 + rt2880_pinmux_data = rt3883_pinmux_data;
1276 }
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