target/linux/ramips/patches-3.10/0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch

   1 From 5a43b20db2fd18f8ea5f3a919d4bc9d9c2038c6c Mon Sep 17 00:00:00 2001
   2 From: "Steven J. Hill" <Steven.Hill@imgtec.com>
   3 Date: Wed, 25 Sep 2013 14:58:19 -0500
   4 Subject: [PATCH 205/215] MIPS: GIC: Send IPIs using the GIC.
   5
   6 If a GIC present, then use it to send IPIs between the cores.
   7
   8 Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
   9 ---
  10  arch/mips/kernel/smp-mt.c |   32 ++++++++++++++++++++++++++++++++
  11  1 file changed, 32 insertions(+)
  12
  13 --- a/arch/mips/kernel/smp-mt.c
  14 +++ b/arch/mips/kernel/smp-mt.c
  15 @@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init
  16
  17                 /* Record this as available CPU */
  18                 set_cpu_possible(tc, true);
  19 +               set_cpu_present(tc, true);
  20                 __cpu_number_map[tc]    = ++ncpu;
  21                 __cpu_logical_map[ncpu] = tc;
  22         }
  23 @@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned
  24         write_tc_c0_tchalt(TCHALT_H);
  25  }
  26
  27 +static void mp_send_ipi_single(int cpu, unsigned int action)
  28 +{
  29 +       unsigned long flags;
  30 +
  31 +       local_irq_save(flags);
  32 +
  33 +       switch (action) {
  34 +       case SMP_CALL_FUNCTION:
  35 +               gic_send_ipi(plat_ipi_call_int_xlate(cpu));
  36 +               break;
  37 +
  38 +       case SMP_RESCHEDULE_YOURSELF:
  39 +               gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
  40 +               break;
  41 +       }
  42 +
  43 +       local_irq_restore(flags);
  44 +}
  45 +
  46  static void vsmp_send_ipi_single(int cpu, unsigned int action)
  47  {
  48         int i;
  49         unsigned long flags;
  50         int vpflags;
  51
  52 +       if (gic_present) {
  53 +               mp_send_ipi_single(cpu, action);
  54 +               return;
  55 +       }
  56         local_irq_save(flags);
  57
  58         vpflags = dvpe();       /* can't access the other CPU's registers whilst MVPE enabled */
  59 @@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondar
  60
  61  static void __cpuinit vsmp_smp_finish(void)
  62  {
  63 +       pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id());
  64 +
  65         /* CDFIXME: remove this? */
  66         write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
  67
  68 @@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(vo
  69
  70  static void vsmp_cpus_done(void)
  71  {
  72 +       pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id());
  73  }
  74
  75  /*
  76 @@ -191,6 +218,8 @@ static void vsmp_cpus_done(void)
  77  static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
  78  {
  79         struct thread_info *gp = task_thread_info(idle);
  80 +       pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n",
  81 +               smp_processor_id(), cpu);
  82         dvpe();
  83         set_c0_mvpcontrol(MVPCONTROL_VPC);
  84
  85 @@ -232,6 +261,7 @@ static void __init vsmp_smp_setup(void)
  86         unsigned int mvpconf0, ntc, tc, ncpu = 0;
  87         unsigned int nvpe;
  88
  89 +       pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id());
  90  #ifdef CONFIG_MIPS_MT_FPAFF
  91         /* If we have an FPU, enroll ourselves in the FPU-full mask */
  92         if (cpu_has_fpu)
  93 @@ -272,6 +302,8 @@ static void __init vsmp_smp_setup(void)
  94
  95  static void __init vsmp_prepare_cpus(unsigned int max_cpus)
  96  {
  97 +       pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n",
  98 +               smp_processor_id(), max_cpus);
  99         mips_mt_set_cpuoptions();
 100  }
 101