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[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.10 / 0214-usb-add-mt7621-xhci-support.patch
1 From b823088d8782e02cc39c7eb4d834396b83dabe49 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 27 Jan 2014 13:11:01 +0000
4 Subject: [PATCH 214/215] usb: add mt7621 xhci support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/usb/core/hub.c | 2 +-
9 drivers/usb/core/port.c | 3 +-
10 drivers/usb/host/Kconfig | 6 +-
11 drivers/usb/host/Makefile | 10 +-
12 drivers/usb/host/mtk-phy-7621.c | 445 +++++
13 drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
14 drivers/usb/host/mtk-phy-ahb.c | 58 +
15 drivers/usb/host/mtk-phy.c | 102 ++
16 drivers/usb/host/mtk-phy.h | 179 ++
17 drivers/usb/host/pci-quirks.h | 2 +-
18 drivers/usb/host/xhci-dbg.c | 3 +
19 drivers/usb/host/xhci-mem.c | 11 +
20 drivers/usb/host/xhci-mtk-power.c | 115 ++
21 drivers/usb/host/xhci-mtk-power.h | 13 +
22 drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
23 drivers/usb/host/xhci-mtk-scheduler.h | 77 +
24 drivers/usb/host/xhci-mtk.c | 265 +++
25 drivers/usb/host/xhci-mtk.h | 120 ++
26 drivers/usb/host/xhci-plat.c | 19 +
27 drivers/usb/host/xhci-ring.c | 109 +-
28 drivers/usb/host/xhci.c | 201 ++-
29 drivers/usb/host/xhci.h | 23 +-
30 22 files changed, 5229 insertions(+), 13 deletions(-)
31 create mode 100644 drivers/usb/host/mtk-phy-7621.c
32 create mode 100644 drivers/usb/host/mtk-phy-7621.h
33 create mode 100644 drivers/usb/host/mtk-phy-ahb.c
34 create mode 100644 drivers/usb/host/mtk-phy.c
35 create mode 100644 drivers/usb/host/mtk-phy.h
36 create mode 100644 drivers/usb/host/xhci-mtk-power.c
37 create mode 100644 drivers/usb/host/xhci-mtk-power.h
38 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
39 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
40 create mode 100644 drivers/usb/host/xhci-mtk.c
41 create mode 100644 drivers/usb/host/xhci-mtk.h
42
43 --- a/drivers/usb/core/hub.c
44 +++ b/drivers/usb/core/hub.c
45 @@ -1254,7 +1254,7 @@ static void hub_quiesce(struct usb_hub *
46 if (type != HUB_SUSPEND) {
47 /* Disconnect all the children */
48 for (i = 0; i < hdev->maxchild; ++i) {
49 - if (hub->ports[i]->child)
50 + if (hub->ports[i] && hub->ports[i]->child)
51 usb_disconnect(&hub->ports[i]->child);
52 }
53 }
54 --- a/drivers/usb/core/port.c
55 +++ b/drivers/usb/core/port.c
56 @@ -193,6 +193,7 @@ exit:
57 void usb_hub_remove_port_device(struct usb_hub *hub,
58 int port1)
59 {
60 - device_unregister(&hub->ports[port1 - 1]->dev);
61 + if (hub->ports[port1 - 1])
62 + device_unregister(&hub->ports[port1 - 1]->dev);
63 }
64
65 --- a/drivers/usb/host/Kconfig
66 +++ b/drivers/usb/host/Kconfig
67 @@ -28,7 +28,11 @@ config USB_XHCI_HCD
68 if USB_XHCI_HCD
69
70 config USB_XHCI_PLATFORM
71 - tristate
72 + bool "xHCI platform"
73 +
74 +config USB_MT7621_XHCI_PLATFORM
75 + bool "MTK MT7621 xHCI"
76 + depends on USB_XHCI_PLATFORM
77
78 config USB_XHCI_HCD_DEBUGGING
79 bool "Debugging for the xHCI host controller"
80 --- a/drivers/usb/host/Makefile
81 +++ b/drivers/usb/host/Makefile
82 @@ -13,15 +13,23 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
83
84 xhci-hcd-y := xhci.o xhci-mem.o
85 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
86 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
87 xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
88 +endif
89 +
90 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
91 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
92 +endif
93
94 ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
95 - xhci-hcd-y += xhci-plat.o
96 +xhci-hcd-y += xhci-plat.o
97 endif
98
99 obj-$(CONFIG_USB_WHCI_HCD) += whci/
100
101 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
102 obj-$(CONFIG_PCI) += pci-quirks.o
103 +endif
104
105 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
106 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
107 --- /dev/null
108 +++ b/drivers/usb/host/mtk-phy-7621.c
109 @@ -0,0 +1,445 @@
110 +#include "mtk-phy.h"
111 +
112 +#ifdef CONFIG_PROJECT_7621
113 +#include "mtk-phy-7621.h"
114 +
115 +//not used on SoC
116 +PHY_INT32 phy_init(struct u3phy_info *info){
117 + return PHY_TRUE;
118 +}
119 +
120 +//not used on SoC
121 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
122 + return PHY_TRUE;
123 +}
124 +
125 +//--------------------------------------------------------
126 +// Function : fgEyeScanHelper_CheckPtInRegion()
127 +// Description : Check if the test point is in a rectangle region.
128 +// If it is in the rectangle, also check if this point
129 +// is on the multiple of deltaX and deltaY.
130 +// Parameter : strucScanRegion * prEye - the region
131 +// BYTE bX
132 +// BYTE bY
133 +// Return : BYTE - TRUE : This point needs to be tested
134 +// FALSE: This point will be omitted
135 +// Note : First check within the rectangle.
136 +// Secondly, use modulous to check if the point will be tested.
137 +//--------------------------------------------------------
138 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
139 +{
140 + PHY_INT8 fgValid = true;
141 +
142 +
143 + /// Be careful, the axis origin is on the TOP-LEFT corner.
144 + /// Therefore the top-left point has the minimum X and Y
145 + /// Botton-right point is the maximum X and Y
146 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
147 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
148 + {
149 + // With the region, now check whether or not the input test point is
150 + // on the multiples of X and Y
151 + // Do not have to worry about negative value, because we have already
152 + // check the input bX, and bY is within the region.
153 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
154 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
155 + {
156 + // if the division will have remainder, that means
157 + // the input test point is on the multiples of X and Y
158 + fgValid = false;
159 + }
160 + else
161 + {
162 + }
163 + }
164 + else
165 + {
166 +
167 + fgValid = false;
168 + }
169 + return fgValid;
170 +}
171 +
172 +//--------------------------------------------------------
173 +// Function : EyeScanHelper_RunTest()
174 +// Description : Enable the test, and wait til it is completed
175 +// Parameter : None
176 +// Return : None
177 +// Note : None
178 +//--------------------------------------------------------
179 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
180 +{
181 + DRV_UDELAY(100);
182 + // Disable the test
183 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
184 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
185 + DRV_UDELAY(100);
186 + // Run the test
187 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
188 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
189 + DRV_UDELAY(100);
190 + // Wait til it's done
191 + //RGS_SSUSB_RX_EYE_CNT_RDY
192 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
193 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
194 +}
195 +
196 +//--------------------------------------------------------
197 +// Function : fgEyeScanHelper_CalNextPoint()
198 +// Description : Calcualte the test point for the measurement
199 +// Parameter : None
200 +// Return : BOOL - TRUE : the next point is within the
201 +// boundaryof HW limit
202 +// FALSE: the next point is out of the HW limit
203 +// Note : The next point is obtained by calculating
204 +// from the bottom left of the region rectangle
205 +// and then scanning up until it reaches the upper
206 +// limit. At this time, the x will increment, and
207 +// start scanning downwards until the y hits the
208 +// zero.
209 +//--------------------------------------------------------
210 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
211 +{
212 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
213 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
214 + )
215 + {
216 + /// Reaches the limit of Y axis
217 + /// Increment X
218 + _bXcurr++;
219 + _fgXChged = true;
220 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
221 +
222 + if (_bXcurr > MAX_X)
223 + {
224 + return false;
225 + }
226 + }
227 + else
228 + {
229 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
230 + _fgXChged = false;
231 + }
232 + return PHY_TRUE;
233 +}
234 +
235 +PHY_INT32 eyescan_init(struct u3phy_info *info){
236 + //initial PHY setting
237 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
238 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
239 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
240 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
241 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
242 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
243 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
244 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
245 + return PHY_TRUE;
246 +}
247 +
248 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
249 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
250 + PHY_INT32 cOfst = 0;
251 + PHY_UINT8 bIdxX = 0;
252 + PHY_UINT8 bIdxY = 0;
253 + //PHY_INT8 bCnt = 0;
254 + PHY_UINT8 bIdxCycCnt = 0;
255 + PHY_INT8 fgValid;
256 + PHY_INT8 cX;
257 + PHY_INT8 cY;
258 + PHY_UINT8 bExtendCnt;
259 + PHY_INT8 isContinue;
260 + //PHY_INT8 isBreak;
261 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
262 + //PHY_UINT32 temp;
263 +
264 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
265 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
266 +
267 + _rEye1.bX_tl = x_t1;
268 + _rEye1.bY_tl = y_t1;
269 + _rEye1.bX_br = x_br;
270 + _rEye1.bY_br = y_br;
271 + _rEye1.bDeltaX = delta_x;
272 + _rEye1.bDeltaY = delta_y;
273 +
274 + _rEye2.bX_tl = x_t1;
275 + _rEye2.bY_tl = y_t1;
276 + _rEye2.bX_br = x_br;
277 + _rEye2.bY_br = y_br;
278 + _rEye2.bDeltaX = delta_x;
279 + _rEye2.bDeltaY = delta_y;
280 +
281 + _rTestCycle.wEyeCnt = eye_cnt;
282 + _rTestCycle.bNumOfEyeCnt = num_cnt;
283 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
284 + _rTestCycle.bPICalEn = PI_cal_en;
285 +
286 + _bXcurr = 0;
287 + _bYcurr = 0;
288 + _eScanDir = SCAN_DN;
289 + _fgXChged = false;
290 +
291 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
292 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
293 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
294 +
295 + //force SIGDET to OFF
296 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
297 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
298 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
299 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
300 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
301 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
302 +
303 + // RX_TRI_DET_EN to Disable
304 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
305 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
306 +
307 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
308 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
309 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
310 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
311 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
312 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
313 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
314 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
315 +
316 +
317 + if (PI_cal_en){
318 + // PI Calibration
319 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
320 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
321 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
322 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
323 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
324 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
325 +
326 + DRV_UDELAY(20);
327 +
328 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
329 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
330 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
331 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
332 +
333 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
334 + }
335 + // Read Initial DAC
336 + // Set CYCLE
337 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
338 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
339 +
340 + // Eye Monitor Feature
341 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
342 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
343 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
344 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
345 +
346 + // Move X,Y to the top-left corner
347 + for (cOfst = 0; cOfst >= -64; cOfst--)
348 + {
349 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
350 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
351 + }
352 + for (cOfst = 0; cOfst < 64; cOfst++)
353 + {
354 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
355 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
356 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
357 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
358 + }
359 + //ClearErrorResult
360 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
361 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
362 + {
363 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
364 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
365 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
366 + }
367 + }
368 + }
369 + isContinue = true;
370 + while(isContinue){
371 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
372 + // The point is within the boundary, then let's check if it is within
373 + // the testing region.
374 + // The point is only test-able if one of the eye region
375 + // includes this point.
376 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
377 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
378 + // Translate bX and bY to 2's complement from where the origin was on the
379 + // top left corner.
380 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
381 + cX = (_bXcurr ^ 0x40);
382 + cY = (_bYcurr ^ 0x3F);
383 +
384 + // Set X if necessary
385 + if (_fgXChged == true)
386 + {
387 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
388 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
389 + }
390 + // Set Y
391 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
392 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
393 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
394 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
395 +
396 + /// Test this point!
397 + if (fgValid){
398 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
399 + {
400 + //run test
401 + EyeScanHelper_RunTest(info);
402 + }
403 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
404 + {
405 + EyeScanHelper_RunTest(info);
406 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
407 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
408 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
409 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
410 +
411 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
412 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
413 +
414 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
415 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
416 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
417 + }
418 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
419 + }
420 + else{
421 +
422 + }
423 + if (fgEyeScanHelper_CalNextPoint() == false){
424 +#if 0
425 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
426 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
427 +#endif
428 + printk(KERN_ERR "end of eye scan\n");
429 + isContinue = false;
430 + }
431 + }
432 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
433 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
434 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
435 +
436 + // Move X,Y to the top-left corner
437 + for (cOfst = 63; cOfst >= 0; cOfst--)
438 + {
439 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
440 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
441 + }
442 + for (cOfst = 63; cOfst >= 0; cOfst--)
443 + {
444 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
445 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
446 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
447 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
448 +
449 + }
450 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
451 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
452 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
453 +
454 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
455 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
456 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
457 +
458 + return PHY_TRUE;
459 +}
460 +
461 +//not used on SoC
462 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
463 + return PHY_TRUE;
464 +}
465 +
466 +//not used on SoC
467 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
468 + return PHY_TRUE;
469 +}
470 +
471 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
472 + PHY_INT32 i=0;
473 + //PHY_INT32 j=0;
474 + //PHY_INT8 u1SrCalVal = 0;
475 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
476 + PHY_INT32 fgRet = 0;
477 + PHY_INT32 u4FmOut = 0;
478 + PHY_INT32 u4Tmp = 0;
479 + //PHY_INT32 temp;
480 +
481 + // => RG_USB20_HSTX_SRCAL_EN = 1
482 + // enable HS TX SR calibration
483 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
484 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
485 + DRV_MSLEEP(1);
486 +
487 + // => RG_FRCK_EN = 1
488 + // Enable free run clock
489 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
490 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
491 +
492 + // MT6290 HS signal quality patch
493 + // => RG_CYCLECNT = 400
494 + // Setting cyclecnt =400
495 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
496 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
497 +
498 + // => RG_FREQDET_EN = 1
499 + // Enable frequency meter
500 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
501 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
502 +
503 + // wait for FM detection done, set 10ms timeout
504 + for(i=0; i<10; i++){
505 + // => u4FmOut = USB_FM_OUT
506 + // read FM_OUT
507 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
508 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
509 +
510 + // check if FM detection done
511 + if (u4FmOut != 0)
512 + {
513 + fgRet = 0;
514 + printk("FM detection done! loop = %d\n", i);
515 +
516 + break;
517 + }
518 +
519 + fgRet = 1;
520 + DRV_MSLEEP(1);
521 + }
522 + // => RG_FREQDET_EN = 0
523 + // disable frequency meter
524 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
525 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
526 +
527 + // => RG_FRCK_EN = 0
528 + // disable free run clock
529 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
530 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
531 +
532 + // => RG_USB20_HSTX_SRCAL_EN = 0
533 + // disable HS TX SR calibration
534 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
535 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
536 + DRV_MSLEEP(1);
537 +
538 + if(u4FmOut == 0){
539 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
540 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
541 +
542 + fgRet = 1;
543 + }
544 + else{
545 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
546 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
547 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
548 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
549 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
550 + }
551 + return fgRet;
552 +}
553 +
554 +#endif
555 --- /dev/null
556 +++ b/drivers/usb/host/mtk-phy-7621.h
557 @@ -0,0 +1,2871 @@
558 +#ifdef CONFIG_PROJECT_7621
559 +#ifndef __MTK_PHY_7621_H
560 +#define __MTK_PHY_7621_H
561 +
562 +#define U2_SR_COEF_7621 28
563 +
564 +///////////////////////////////////////////////////////////////////////////////
565 +
566 +struct u2phy_reg {
567 + //0x0
568 + PHY_LE32 u2phyac0;
569 + PHY_LE32 u2phyac1;
570 + PHY_LE32 u2phyac2;
571 + PHY_LE32 reserve0;
572 + //0x10
573 + PHY_LE32 u2phyacr0;
574 + PHY_LE32 u2phyacr1;
575 + PHY_LE32 u2phyacr2;
576 + PHY_LE32 u2phyacr3;
577 + //0x20
578 + PHY_LE32 u2phyacr4;
579 + PHY_LE32 u2phyamon0;
580 + PHY_LE32 reserve1[2];
581 + //0x30~0x50
582 + PHY_LE32 reserve2[12];
583 + //0x60
584 + PHY_LE32 u2phydcr0;
585 + PHY_LE32 u2phydcr1;
586 + PHY_LE32 u2phydtm0;
587 + PHY_LE32 u2phydtm1;
588 + //0x70
589 + PHY_LE32 u2phydmon0;
590 + PHY_LE32 u2phydmon1;
591 + PHY_LE32 u2phydmon2;
592 + PHY_LE32 u2phydmon3;
593 + //0x80
594 + PHY_LE32 u2phybc12c;
595 + PHY_LE32 u2phybc12c1;
596 + PHY_LE32 reserve3[2];
597 + //0x90~0xe0
598 + PHY_LE32 reserve4[24];
599 + //0xf0
600 + PHY_LE32 reserve6[3];
601 + PHY_LE32 regfcom;
602 +};
603 +
604 +//U3D_U2PHYAC0
605 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
606 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
607 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
608 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
609 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
610 +#define RG_USB20_REF_EN (0x1<<15) //15:15
611 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
612 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
613 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
614 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
615 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
616 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
617 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
618 +
619 +//U3D_U2PHYAC1
620 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
621 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
622 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
623 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
624 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
625 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
626 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
627 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
628 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
629 +
630 +//U3D_U2PHYAC2
631 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
632 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
633 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
634 +
635 +//U3D_U2PHYACR0
636 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
637 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
638 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
639 +#define RG_USB20_LS_CR (0x7<<12) //14:12
640 +#define RG_USB20_FS_CR (0x7<<8) //10:8
641 +#define RG_USB20_LS_SR (0x7<<4) //6:4
642 +#define RG_USB20_FS_SR (0x7<<0) //2:0
643 +
644 +//U3D_U2PHYACR1
645 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
646 +#define RG_USB20_SQD (0x3<<24) //25:24
647 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
648 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
649 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
650 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
651 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
652 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
653 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
654 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
655 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
656 +
657 +//U3D_U2PHYACR2
658 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
659 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
660 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
661 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
662 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
663 +#define RG_USB20_DISCD (0x3<<20) //21:20
664 +#define RG_USB20_DISCTH (0xf<<16) //19:16
665 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
666 +#define RG_USB20_SQCAL (0xf<<8) //11:8
667 +#define RG_USB20_SQTH (0xf<<0) //3:0
668 +
669 +//U3D_U2PHYACR3
670 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
671 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
672 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
673 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
674 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
675 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
676 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
677 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
678 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
679 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
680 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
681 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
682 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
683 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
684 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
685 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
686 +
687 +//U3D_U2PHYACR4
688 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
689 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
690 +#define USB20_DP_100K_EN (0x1<<16) //16:16
691 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
692 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
693 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
694 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
695 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
696 +#define USB20_GPIO_MODE (0x1<<8) //8:8
697 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
698 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
699 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
700 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
701 +
702 +//U3D_U2PHYAMON0
703 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
704 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
705 +
706 +//U3D_U2PHYDCR0
707 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
708 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
709 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
710 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
711 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
712 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
713 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
714 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
715 +#define RG_USB20_TX_TST (0x1<<5) //5:5
716 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
717 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
718 +
719 +//U3D_U2PHYDCR1
720 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
721 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
722 +#define RG_DEBUG_EN (0x1<<22) //22:22
723 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
724 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
725 +#define RG_USB20_BERTH (0x3<<16) //17:16
726 +#define RG_USB20_LBMODE (0x3<<13) //14:13
727 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
728 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
729 +
730 +//U3D_U2PHYDTM0
731 +#define RG_UART_MODE (0x3<<30) //31:30
732 +#define FORCE_UART_I (0x1<<29) //29:29
733 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
734 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
735 +#define FORCE_UART_EN (0x1<<26) //26:26
736 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
737 +#define FORCE_DRVVBUS (0x1<<24) //24:24
738 +#define FORCE_DATAIN (0x1<<23) //23:23
739 +#define FORCE_TXVALID (0x1<<22) //22:22
740 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
741 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
742 +#define FORCE_XCVRSEL (0x1<<19) //19:19
743 +#define FORCE_SUSPENDM (0x1<<18) //18:18
744 +#define FORCE_TERMSEL (0x1<<17) //17:17
745 +#define FORCE_OPMODE (0x1<<16) //16:16
746 +#define UTMI_MUXSEL (0x1<<15) //15:15
747 +#define RG_RESET (0x1<<14) //14:14
748 +#define RG_DATAIN (0xf<<10) //13:10
749 +#define RG_TXVALIDH (0x1<<9) //9:9
750 +#define RG_TXVALID (0x1<<8) //8:8
751 +#define RG_DMPULLDOWN (0x1<<7) //7:7
752 +#define RG_DPPULLDOWN (0x1<<6) //6:6
753 +#define RG_XCVRSEL (0x3<<4) //5:4
754 +#define RG_SUSPENDM (0x1<<3) //3:3
755 +#define RG_TERMSEL (0x1<<2) //2:2
756 +#define RG_OPMODE (0x3<<0) //1:0
757 +
758 +//U3D_U2PHYDTM1
759 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
760 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
761 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
762 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
763 +#define RG_UART_I (0x1<<19) //19:19
764 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
765 +#define RG_UART_TX_OE (0x1<<17) //17:17
766 +#define RG_UART_EN (0x1<<16) //16:16
767 +#define FORCE_VBUSVALID (0x1<<13) //13:13
768 +#define FORCE_SESSEND (0x1<<12) //12:12
769 +#define FORCE_BVALID (0x1<<11) //11:11
770 +#define FORCE_AVALID (0x1<<10) //10:10
771 +#define FORCE_IDDIG (0x1<<9) //9:9
772 +#define FORCE_IDPULLUP (0x1<<8) //8:8
773 +#define RG_VBUSVALID (0x1<<5) //5:5
774 +#define RG_SESSEND (0x1<<4) //4:4
775 +#define RG_BVALID (0x1<<3) //3:3
776 +#define RG_AVALID (0x1<<2) //2:2
777 +#define RG_IDDIG (0x1<<1) //1:1
778 +#define RG_IDPULLUP (0x1<<0) //0:0
779 +
780 +//U3D_U2PHYDMON0
781 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
782 +
783 +//U3D_U2PHYDMON1
784 +#define USB20_UART_O (0x1<<31) //31:31
785 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
786 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
787 +#define AD_USB20_BVALID (0x1<<28) //28:28
788 +#define USB20_IDDIG (0x1<<27) //27:27
789 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
790 +#define AD_USB20_SESSEND (0x1<<25) //25:25
791 +#define AD_USB20_AVALID (0x1<<24) //24:24
792 +#define USB20_LINE_STATE (0x3<<22) //23:22
793 +#define USB20_HST_DISCON (0x1<<21) //21:21
794 +#define USB20_TX_READY (0x1<<20) //20:20
795 +#define USB20_RX_ERROR (0x1<<19) //19:19
796 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
797 +#define USB20_RX_VALIDH (0x1<<17) //17:17
798 +#define USB20_RX_VALID (0x1<<16) //16:16
799 +#define USB20_DATA_OUT (0xffff<<0) //15:0
800 +
801 +//U3D_U2PHYDMON2
802 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
803 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
804 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
805 +#define USB20_PROBE_OUT (0xff<<0) //7:0
806 +
807 +//U3D_U2PHYDMON3
808 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
809 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
810 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
811 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
812 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
813 +
814 +//U3D_U2PHYBC12C
815 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
816 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
817 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
818 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
819 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
820 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
821 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
822 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
823 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
824 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
825 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
826 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
827 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
828 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
829 +#define RG_CHGDT_EN (0x1<<0) //0:0
830 +
831 +//U3D_U2PHYBC12C1
832 +#define RG_CHGDT_REV (0xff<<0) //7:0
833 +
834 +//U3D_REGFCOM
835 +#define RG_PAGE (0xff<<24) //31:24
836 +#define I2C_MODE (0x1<<16) //16:16
837 +
838 +
839 +/* OFFSET */
840 +
841 +//U3D_U2PHYAC0
842 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
843 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
844 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
845 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
846 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
847 +#define RG_USB20_REF_EN_OFST (15)
848 +#define RG_USB20_INTR_EN_OFST (14)
849 +#define RG_USB20_BG_TRIM_OFST (8)
850 +#define RG_USB20_BG_RBSEL_OFST (6)
851 +#define RG_USB20_BG_RASEL_OFST (4)
852 +#define RG_USB20_BGR_DIV_OFST (2)
853 +#define RG_SIFSLV_CHP_EN_OFST (1)
854 +#define RG_SIFSLV_BGR_EN_OFST (0)
855 +
856 +//U3D_U2PHYAC1
857 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
858 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
859 +#define RG_USB20_MPX_SEL_OFST (16)
860 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
861 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
862 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
863 +#define RG_USB20_USBPLL_LF_OFST (2)
864 +#define RG_USB20_USBPLL_BR_OFST (1)
865 +#define RG_USB20_USBPLL_BP_OFST (0)
866 +
867 +//U3D_U2PHYAC2
868 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
869 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
870 +#define RG_USB20_CLKREF_REV_OFST (0)
871 +
872 +//U3D_U2PHYACR0
873 +#define RG_USB20_ICUSB_EN_OFST (24)
874 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
875 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
876 +#define RG_USB20_LS_CR_OFST (12)
877 +#define RG_USB20_FS_CR_OFST (8)
878 +#define RG_USB20_LS_SR_OFST (4)
879 +#define RG_USB20_FS_SR_OFST (0)
880 +
881 +//U3D_U2PHYACR1
882 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
883 +#define RG_USB20_SQD_OFST (24)
884 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
885 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
886 +#define RG_USB20_PHYD_MONEN_OFST (18)
887 +#define RG_USB20_INLPBK_EN_OFST (17)
888 +#define RG_USB20_CHIRP_EN_OFST (16)
889 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
890 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
891 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
892 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
893 +
894 +//U3D_U2PHYACR2
895 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
896 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
897 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
898 +#define RG_USB20_OTG_VBUSTH_OFST (24)
899 +#define RG_USB20_DISC_FIT_EN_OFST (22)
900 +#define RG_USB20_DISCD_OFST (20)
901 +#define RG_USB20_DISCTH_OFST (16)
902 +#define RG_USB20_SQCAL_EN_OFST (15)
903 +#define RG_USB20_SQCAL_OFST (8)
904 +#define RG_USB20_SQTH_OFST (0)
905 +
906 +//U3D_U2PHYACR3
907 +#define RG_USB20_HSTX_DBIST_OFST (28)
908 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
909 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
910 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
911 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
912 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
913 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
914 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
915 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
916 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
917 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
918 +#define RG_USB20_EN_PU_DM_OFST (11)
919 +#define RG_USB20_EN_PD_DM_OFST (10)
920 +#define RG_USB20_EN_PU_DP_OFST (9)
921 +#define RG_USB20_EN_PD_DP_OFST (8)
922 +#define RG_USB20_PHY_REV_OFST (0)
923 +
924 +//U3D_U2PHYACR4
925 +#define RG_USB20_DP_100K_MODE_OFST (18)
926 +#define RG_USB20_DM_100K_EN_OFST (17)
927 +#define USB20_DP_100K_EN_OFST (16)
928 +#define USB20_GPIO_DM_I_OFST (15)
929 +#define USB20_GPIO_DP_I_OFST (14)
930 +#define USB20_GPIO_DM_OE_OFST (13)
931 +#define USB20_GPIO_DP_OE_OFST (12)
932 +#define RG_USB20_GPIO_CTL_OFST (9)
933 +#define USB20_GPIO_MODE_OFST (8)
934 +#define RG_USB20_TX_BIAS_EN_OFST (5)
935 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
936 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
937 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
938 +
939 +//U3D_U2PHYAMON0
940 +#define RGO_USB20_GPIO_DM_O_OFST (1)
941 +#define RGO_USB20_GPIO_DP_O_OFST (0)
942 +
943 +//U3D_U2PHYDCR0
944 +#define RG_USB20_CDR_TST_OFST (30)
945 +#define RG_USB20_GATED_ENB_OFST (29)
946 +#define RG_USB20_TESTMODE_OFST (26)
947 +#define RG_USB20_PLL_STABLE_OFST (25)
948 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
949 +#define RG_USB20_PHYD_RESERVE_OFST (8)
950 +#define RG_USB20_EBTHRLD_OFST (7)
951 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
952 +#define RG_USB20_TX_TST_OFST (5)
953 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
954 +#define RG_USB20_CDR_FILT_OFST (0)
955 +
956 +//U3D_U2PHYDCR1
957 +#define RG_USB20_PROBE_SEL_OFST (24)
958 +#define RG_USB20_DRVVBUS_OFST (23)
959 +#define RG_DEBUG_EN_OFST (22)
960 +#define RG_USB20_OTG_PROBE_OFST (20)
961 +#define RG_USB20_SW_PLLMODE_OFST (18)
962 +#define RG_USB20_BERTH_OFST (16)
963 +#define RG_USB20_LBMODE_OFST (13)
964 +#define RG_USB20_FORCE_TAP_OFST (12)
965 +#define RG_USB20_TAPSEL_OFST (0)
966 +
967 +//U3D_U2PHYDTM0
968 +#define RG_UART_MODE_OFST (30)
969 +#define FORCE_UART_I_OFST (29)
970 +#define FORCE_UART_BIAS_EN_OFST (28)
971 +#define FORCE_UART_TX_OE_OFST (27)
972 +#define FORCE_UART_EN_OFST (26)
973 +#define FORCE_USB_CLKEN_OFST (25)
974 +#define FORCE_DRVVBUS_OFST (24)
975 +#define FORCE_DATAIN_OFST (23)
976 +#define FORCE_TXVALID_OFST (22)
977 +#define FORCE_DM_PULLDOWN_OFST (21)
978 +#define FORCE_DP_PULLDOWN_OFST (20)
979 +#define FORCE_XCVRSEL_OFST (19)
980 +#define FORCE_SUSPENDM_OFST (18)
981 +#define FORCE_TERMSEL_OFST (17)
982 +#define FORCE_OPMODE_OFST (16)
983 +#define UTMI_MUXSEL_OFST (15)
984 +#define RG_RESET_OFST (14)
985 +#define RG_DATAIN_OFST (10)
986 +#define RG_TXVALIDH_OFST (9)
987 +#define RG_TXVALID_OFST (8)
988 +#define RG_DMPULLDOWN_OFST (7)
989 +#define RG_DPPULLDOWN_OFST (6)
990 +#define RG_XCVRSEL_OFST (4)
991 +#define RG_SUSPENDM_OFST (3)
992 +#define RG_TERMSEL_OFST (2)
993 +#define RG_OPMODE_OFST (0)
994 +
995 +//U3D_U2PHYDTM1
996 +#define RG_USB20_PRBS7_EN_OFST (31)
997 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
998 +#define RG_USB20_CLK48M_EN_OFST (23)
999 +#define RG_USB20_CLK60M_EN_OFST (22)
1000 +#define RG_UART_I_OFST (19)
1001 +#define RG_UART_BIAS_EN_OFST (18)
1002 +#define RG_UART_TX_OE_OFST (17)
1003 +#define RG_UART_EN_OFST (16)
1004 +#define FORCE_VBUSVALID_OFST (13)
1005 +#define FORCE_SESSEND_OFST (12)
1006 +#define FORCE_BVALID_OFST (11)
1007 +#define FORCE_AVALID_OFST (10)
1008 +#define FORCE_IDDIG_OFST (9)
1009 +#define FORCE_IDPULLUP_OFST (8)
1010 +#define RG_VBUSVALID_OFST (5)
1011 +#define RG_SESSEND_OFST (4)
1012 +#define RG_BVALID_OFST (3)
1013 +#define RG_AVALID_OFST (2)
1014 +#define RG_IDDIG_OFST (1)
1015 +#define RG_IDPULLUP_OFST (0)
1016 +
1017 +//U3D_U2PHYDMON0
1018 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1019 +
1020 +//U3D_U2PHYDMON1
1021 +#define USB20_UART_O_OFST (31)
1022 +#define RGO_USB20_LB_PASS_OFST (30)
1023 +#define RGO_USB20_LB_DONE_OFST (29)
1024 +#define AD_USB20_BVALID_OFST (28)
1025 +#define USB20_IDDIG_OFST (27)
1026 +#define AD_USB20_VBUSVALID_OFST (26)
1027 +#define AD_USB20_SESSEND_OFST (25)
1028 +#define AD_USB20_AVALID_OFST (24)
1029 +#define USB20_LINE_STATE_OFST (22)
1030 +#define USB20_HST_DISCON_OFST (21)
1031 +#define USB20_TX_READY_OFST (20)
1032 +#define USB20_RX_ERROR_OFST (19)
1033 +#define USB20_RX_ACTIVE_OFST (18)
1034 +#define USB20_RX_VALIDH_OFST (17)
1035 +#define USB20_RX_VALID_OFST (16)
1036 +#define USB20_DATA_OUT_OFST (0)
1037 +
1038 +//U3D_U2PHYDMON2
1039 +#define RGO_TXVALID_CNT_OFST (24)
1040 +#define RGO_RXACTIVE_CNT_OFST (16)
1041 +#define RGO_USB20_LB_BERCNT_OFST (8)
1042 +#define USB20_PROBE_OUT_OFST (0)
1043 +
1044 +//U3D_U2PHYDMON3
1045 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1046 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1047 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1048 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1049 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1050 +
1051 +//U3D_U2PHYBC12C
1052 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1053 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1054 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1055 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1056 +#define RG_CHGDT_VDATSRC_OFST (13)
1057 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1058 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1059 +#define RG_CHGDT_ISRC_DP_OFST (7)
1060 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1061 +#define RG_CHGDT_VDAT_DM_OFST (5)
1062 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1063 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1064 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1065 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1066 +#define RG_CHGDT_EN_OFST (0)
1067 +
1068 +//U3D_U2PHYBC12C1
1069 +#define RG_CHGDT_REV_OFST (0)
1070 +
1071 +//U3D_REGFCOM
1072 +#define RG_PAGE_OFST (24)
1073 +#define I2C_MODE_OFST (16)
1074 +
1075 +
1076 +///////////////////////////////////////////////////////////////////////////////
1077 +
1078 +struct u3phya_reg {
1079 + //0x0
1080 + PHY_LE32 reg0;
1081 + PHY_LE32 reg1;
1082 + PHY_LE32 reg2;
1083 + PHY_LE32 reg3;
1084 + //0x10
1085 + PHY_LE32 reg4;
1086 + PHY_LE32 reg5;
1087 + PHY_LE32 reg6;
1088 + PHY_LE32 reg7;
1089 + //0x20
1090 + PHY_LE32 reg8;
1091 + PHY_LE32 reg9;
1092 + PHY_LE32 rega;
1093 + PHY_LE32 regb;
1094 + //0x30
1095 + PHY_LE32 regc;
1096 + PHY_LE32 regd;
1097 + PHY_LE32 rege;
1098 +};
1099 +
1100 +//U3D_reg0
1101 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1102 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1103 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1104 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1105 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1106 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1107 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1108 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1109 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1110 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1111 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1112 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1113 +
1114 +//U3D_reg1
1115 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1116 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1117 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1118 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1119 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1120 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1121 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1122 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1123 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1124 +
1125 +//U3D_reg2
1126 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1127 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1128 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1129 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1130 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1131 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1132 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1133 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1134 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1135 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1136 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1137 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1138 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1139 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1140 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1141 +
1142 +//U3D_reg3
1143 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1144 +
1145 +//U3D_reg4
1146 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1147 +
1148 +//U3D_reg5
1149 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1150 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1151 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1152 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1153 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1154 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1155 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1156 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1157 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1158 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1159 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1160 +
1161 +//U3D_reg6
1162 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1163 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1164 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1165 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1166 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1167 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1168 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1169 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1170 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1171 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1172 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1173 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1174 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1175 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1176 +
1177 +//U3D_reg7
1178 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1179 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1180 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1181 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1182 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1183 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1184 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1185 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1186 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1187 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1188 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1189 +
1190 +//U3D_reg8
1191 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1192 +
1193 +//U3D_reg9
1194 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1195 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1196 +
1197 +//U3D_regA
1198 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1199 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1200 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1201 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1202 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1203 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1204 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1205 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1206 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1207 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1208 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1209 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1210 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1211 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1212 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1213 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1214 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1215 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1216 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1217 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1218 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1219 +
1220 +//U3D_regB
1221 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1222 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1223 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1224 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1225 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1226 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1227 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1228 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1229 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1230 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1231 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1232 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1233 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1234 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1235 +
1236 +//U3D_regC
1237 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1238 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1239 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1240 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1241 +
1242 +//U3D_redD
1243 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1244 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1245 +
1246 +//U3D_regE
1247 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1248 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1249 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1250 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1251 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1252 +
1253 +
1254 +/* OFFSET */
1255 +
1256 +//U3D_reg0
1257 +#define RG_SSUSB_BGR_EN_OFST (31)
1258 +#define RG_SSUSB_CHPEN_OFST (30)
1259 +#define RG_SSUSB_BG_DIV_OFST (28)
1260 +#define RG_SSUSB_INTR_EN_OFST (26)
1261 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1262 +#define RG_SSUSB_MPX_SEL_OFST (16)
1263 +#define RG_SSUSB_REF_EN_OFST (15)
1264 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1265 +#define RG_SSUSB_BG_RASEL_OFST (9)
1266 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1267 +#define RG_SSUSB_BG_MONEN_OFST (6)
1268 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1269 +
1270 +//U3D_reg1
1271 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1272 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1273 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1274 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1275 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1276 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1277 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1278 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1279 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1280 +
1281 +//U3D_reg2
1282 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1283 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1284 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1285 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1286 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1287 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1288 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1289 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1290 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1291 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1292 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1293 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1294 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1295 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1296 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1297 +
1298 +//U3D_reg3
1299 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1300 +
1301 +//U3D_reg4
1302 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1303 +
1304 +//U3D_reg5
1305 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1306 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1307 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1308 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1309 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1310 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1311 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1312 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1313 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1314 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1315 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1316 +
1317 +//U3D_reg6
1318 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1319 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1320 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1321 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1322 +#define RG_SSUSB_TX_SR_OFST (20)
1323 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1324 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1325 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1326 +#define RG_SSUSB_CKMON_EN_OFST (11)
1327 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1328 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1329 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1330 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1331 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1332 +
1333 +//U3D_reg7
1334 +#define RG_SSUSB_RESERVE_OFST (12)
1335 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1336 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1337 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1338 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1339 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1340 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1341 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1342 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1343 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1344 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1345 +
1346 +//U3D_reg8
1347 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1348 +
1349 +//U3D_reg9
1350 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1351 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1352 +
1353 +//U3D_regA
1354 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1355 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1356 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1357 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1358 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1359 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1360 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1361 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1362 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1363 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1364 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1365 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1366 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1367 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1368 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1369 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1370 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1371 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1372 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1373 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1374 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1375 +
1376 +//U3D_regB
1377 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1378 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1379 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1380 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1381 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1382 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1383 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1384 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1385 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1386 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1387 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1388 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1389 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1390 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1391 +
1392 +//U3D_regC
1393 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1394 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1395 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1396 +#define RG_PCIE_RX_RESERVE_OFST (0)
1397 +
1398 +//U3D_redD
1399 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1400 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1401 +
1402 +//U3D_regE
1403 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1404 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1405 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1406 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1407 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1408 +
1409 +///////////////////////////////////////////////////////////////////////////////
1410 +
1411 +struct u3phya_da_reg {
1412 + //0x0
1413 + PHY_LE32 reg0;
1414 + PHY_LE32 reg1;
1415 + PHY_LE32 reg4;
1416 + PHY_LE32 reg5;
1417 + //0x10
1418 + PHY_LE32 reg6;
1419 + PHY_LE32 reg7;
1420 + PHY_LE32 reg8;
1421 + PHY_LE32 reg9;
1422 + //0x20
1423 + PHY_LE32 reg10;
1424 + PHY_LE32 reg12;
1425 + PHY_LE32 reg13;
1426 + PHY_LE32 reg14;
1427 + //0x30
1428 + PHY_LE32 reg15;
1429 + PHY_LE32 reg16;
1430 + PHY_LE32 reg19;
1431 + PHY_LE32 reg20;
1432 + //0x40
1433 + PHY_LE32 reg21;
1434 + PHY_LE32 reg23;
1435 + PHY_LE32 reg25;
1436 + PHY_LE32 reg26;
1437 + //0x50
1438 + PHY_LE32 reg28;
1439 + PHY_LE32 reg29;
1440 + PHY_LE32 reg30;
1441 + PHY_LE32 reg31;
1442 + //0x60
1443 + PHY_LE32 reg32;
1444 + PHY_LE32 reg33;
1445 +};
1446 +
1447 +//U3D_reg0
1448 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1449 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1450 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1451 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1452 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1453 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1454 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1455 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1456 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1457 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1458 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1459 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1460 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1461 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1462 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1463 +
1464 +//U3D_reg1
1465 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1466 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1467 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1468 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1469 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1470 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1471 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1472 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1473 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1474 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1475 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1476 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1477 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1478 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1479 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1480 +
1481 +//U3D_reg4
1482 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1483 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1484 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1485 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1486 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1487 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1488 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1489 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1490 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1491 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1492 +
1493 +//U3D_reg5
1494 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1495 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1496 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1497 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1498 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1499 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1500 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1501 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1502 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1503 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1504 +
1505 +//U3D_reg6
1506 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1507 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1508 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1509 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1510 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1511 +
1512 +//U3D_reg7
1513 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1514 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1515 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1516 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1517 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1518 +
1519 +//U3D_reg8
1520 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1521 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1522 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1523 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1524 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1525 +
1526 +//U3D_reg9
1527 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1528 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1529 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1530 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1531 +
1532 +//U3D_reg10
1533 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1534 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1535 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1536 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1537 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1538 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1539 +
1540 +//U3D_reg12
1541 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1542 +
1543 +//U3D_reg13
1544 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1545 +
1546 +//U3D_reg14
1547 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1548 +
1549 +//U3D_reg15
1550 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1551 +
1552 +//U3D_reg16
1553 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1554 +
1555 +//U3D_reg19
1556 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1557 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1558 +
1559 +//U3D_reg20
1560 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1561 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1562 +
1563 +//U3D_reg21
1564 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1565 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1566 +
1567 +//U3D_reg23
1568 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1569 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1570 +
1571 +//U3D_reg25
1572 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1573 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1574 +
1575 +//U3D_reg26
1576 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1577 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1578 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1579 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1580 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1581 +
1582 +//U3D_reg28
1583 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1584 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1585 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1586 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1587 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1588 +
1589 +//U3D_reg29
1590 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1591 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1592 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1593 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1594 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1595 +
1596 +//U3D_reg30
1597 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1598 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1599 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1600 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1601 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1602 +
1603 +//U3D_reg31
1604 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1605 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1606 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1607 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1608 +
1609 +//U3D_reg32
1610 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1611 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1612 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1613 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1614 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1615 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1616 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1617 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1618 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1619 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1620 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1621 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1622 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1623 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1624 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1625 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1626 +
1627 +//U3D_reg33
1628 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1629 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1630 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1631 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1632 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1633 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1634 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1635 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1636 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1637 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1638 +
1639 +
1640 +/* OFFSET */
1641 +
1642 +//U3D_reg0
1643 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1644 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1645 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1646 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1647 +#define RG_PCIE_SPEED_U3_OFST (20)
1648 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1649 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1650 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1651 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1652 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1653 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1654 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1655 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1656 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1657 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1658 +
1659 +//U3D_reg1
1660 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1661 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1662 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1663 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1664 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1665 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1666 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1667 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1668 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1669 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1670 +#define RG_PCIE_MODE_PE2D_OFST (8)
1671 +#define RG_PCIE_MODE_PE2H_OFST (3)
1672 +#define RG_PCIE_MODE_PE1D_OFST (2)
1673 +#define RG_PCIE_MODE_PE1H_OFST (1)
1674 +#define RG_PCIE_MODE_U3_OFST (0)
1675 +
1676 +//U3D_reg4
1677 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1678 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1679 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1680 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1681 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1682 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1683 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1684 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1685 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1686 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1687 +
1688 +//U3D_reg5
1689 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1690 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1691 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1692 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1693 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1694 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1695 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1696 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1697 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1698 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1699 +
1700 +//U3D_reg6
1701 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1702 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1703 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1704 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1705 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1706 +
1707 +//U3D_reg7
1708 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1709 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1710 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1711 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1712 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1713 +
1714 +//U3D_reg8
1715 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1716 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1717 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1718 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1719 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1720 +
1721 +//U3D_reg9
1722 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1723 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1724 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1725 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1726 +
1727 +//U3D_reg10
1728 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1729 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1730 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1731 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1732 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1733 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1734 +
1735 +//U3D_reg12
1736 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1737 +
1738 +//U3D_reg13
1739 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1740 +
1741 +//U3D_reg14
1742 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1743 +
1744 +//U3D_reg15
1745 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1746 +
1747 +//U3D_reg16
1748 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1749 +
1750 +//U3D_reg19
1751 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1752 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1753 +
1754 +//U3D_reg20
1755 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1756 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1757 +
1758 +//U3D_reg21
1759 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1760 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1761 +
1762 +//U3D_reg23
1763 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1764 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1765 +
1766 +//U3D_reg25
1767 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1768 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1769 +
1770 +//U3D_reg26
1771 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1772 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1773 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1774 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1775 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1776 +
1777 +//U3D_reg28
1778 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1779 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1780 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1781 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1782 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1783 +
1784 +//U3D_reg29
1785 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1786 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1787 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1788 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1789 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1790 +
1791 +//U3D_reg30
1792 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1793 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1794 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1795 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1796 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1797 +
1798 +//U3D_reg31
1799 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1800 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1801 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1802 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1803 +
1804 +//U3D_reg32
1805 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1806 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1807 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1808 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1809 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1810 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1811 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1812 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1813 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1814 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1815 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1816 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1817 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1818 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1819 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1820 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1821 +
1822 +//U3D_reg33
1823 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1824 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1825 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1826 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1827 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1828 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1829 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1830 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1831 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1832 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1833 +
1834 +
1835 +///////////////////////////////////////////////////////////////////////////////
1836 +
1837 +struct u3phyd_reg {
1838 + //0x0
1839 + PHY_LE32 phyd_mix0;
1840 + PHY_LE32 phyd_mix1;
1841 + PHY_LE32 phyd_lfps0;
1842 + PHY_LE32 phyd_lfps1;
1843 + //0x10
1844 + PHY_LE32 phyd_impcal0;
1845 + PHY_LE32 phyd_impcal1;
1846 + PHY_LE32 phyd_txpll0;
1847 + PHY_LE32 phyd_txpll1;
1848 + //0x20
1849 + PHY_LE32 phyd_txpll2;
1850 + PHY_LE32 phyd_fl0;
1851 + PHY_LE32 phyd_mix2;
1852 + PHY_LE32 phyd_rx0;
1853 + //0x30
1854 + PHY_LE32 phyd_t2rlb;
1855 + PHY_LE32 phyd_cppat;
1856 + PHY_LE32 phyd_mix3;
1857 + PHY_LE32 phyd_ebufctl;
1858 + //0x40
1859 + PHY_LE32 phyd_pipe0;
1860 + PHY_LE32 phyd_pipe1;
1861 + PHY_LE32 phyd_mix4;
1862 + PHY_LE32 phyd_ckgen0;
1863 + //0x50
1864 + PHY_LE32 phyd_mix5;
1865 + PHY_LE32 phyd_reserved;
1866 + PHY_LE32 phyd_cdr0;
1867 + PHY_LE32 phyd_cdr1;
1868 + //0x60
1869 + PHY_LE32 phyd_pll_0;
1870 + PHY_LE32 phyd_pll_1;
1871 + PHY_LE32 phyd_bcn_det_1;
1872 + PHY_LE32 phyd_bcn_det_2;
1873 + //0x70
1874 + PHY_LE32 eq0;
1875 + PHY_LE32 eq1;
1876 + PHY_LE32 eq2;
1877 + PHY_LE32 eq3;
1878 + //0x80
1879 + PHY_LE32 eq_eye0;
1880 + PHY_LE32 eq_eye1;
1881 + PHY_LE32 eq_eye2;
1882 + PHY_LE32 eq_dfe0;
1883 + //0x90
1884 + PHY_LE32 eq_dfe1;
1885 + PHY_LE32 eq_dfe2;
1886 + PHY_LE32 eq_dfe3;
1887 + PHY_LE32 reserve0;
1888 + //0xa0
1889 + PHY_LE32 phyd_mon0;
1890 + PHY_LE32 phyd_mon1;
1891 + PHY_LE32 phyd_mon2;
1892 + PHY_LE32 phyd_mon3;
1893 + //0xb0
1894 + PHY_LE32 phyd_mon4;
1895 + PHY_LE32 phyd_mon5;
1896 + PHY_LE32 phyd_mon6;
1897 + PHY_LE32 phyd_mon7;
1898 + //0xc0
1899 + PHY_LE32 phya_rx_mon0;
1900 + PHY_LE32 phya_rx_mon1;
1901 + PHY_LE32 phya_rx_mon2;
1902 + PHY_LE32 phya_rx_mon3;
1903 + //0xd0
1904 + PHY_LE32 phya_rx_mon4;
1905 + PHY_LE32 phya_rx_mon5;
1906 + PHY_LE32 phyd_cppat2;
1907 + PHY_LE32 eq_eye3;
1908 + //0xe0
1909 + PHY_LE32 kband_out;
1910 + PHY_LE32 kband_out1;
1911 +};
1912 +
1913 +//U3D_PHYD_MIX0
1914 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1915 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1916 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1917 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1918 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1919 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1920 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1921 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1922 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1923 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1924 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1925 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1926 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1927 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1928 +
1929 +//U3D_PHYD_MIX1
1930 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1931 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1932 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1933 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1934 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1935 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1936 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1937 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1938 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1939 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1940 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1941 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1942 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1943 +
1944 +//U3D_PHYD_LFPS0
1945 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1946 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1947 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1948 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1949 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1950 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1951 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1952 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1953 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1954 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1955 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1956 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1957 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1958 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1959 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1960 +
1961 +//U3D_PHYD_LFPS1
1962 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1963 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1964 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
1965 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
1966 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
1967 +
1968 +//U3D_PHYD_IMPCAL0
1969 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
1970 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
1971 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
1972 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
1973 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
1974 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
1975 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1976 +
1977 +//U3D_PHYD_IMPCAL1
1978 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
1979 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
1980 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
1981 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
1982 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
1983 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
1984 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1985 +
1986 +//U3D_PHYD_TXPLL0
1987 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
1988 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
1989 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
1990 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
1991 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
1992 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
1993 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
1994 +
1995 +//U3D_PHYD_TXPLL1
1996 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
1997 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
1998 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
1999 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
2000 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
2001 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
2002 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
2003 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
2004 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
2005 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
2006 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2007 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2008 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2009 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2010 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2011 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2012 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2013 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2014 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2015 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2016 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2017 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2018 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2019 +
2020 +//U3D_PHYD_TXPLL2
2021 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2022 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2023 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2024 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2025 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2026 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2027 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2028 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2029 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2030 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2031 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2032 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2033 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2034 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2035 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2036 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2037 +
2038 +//U3D_PHYD_FL0
2039 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2040 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2041 +
2042 +//U3D_PHYD_MIX2
2043 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2044 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2045 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2046 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2047 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2048 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2049 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2050 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2051 +
2052 +//U3D_PHYD_RX0
2053 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2054 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2055 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2056 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2057 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2058 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2059 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2060 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2061 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2062 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2063 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2064 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2065 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2066 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2067 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2068 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2069 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2070 +
2071 +//U3D_PHYD_T2RLB
2072 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2073 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2074 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2075 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2076 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2077 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2078 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2079 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2080 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2081 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2082 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2083 +
2084 +//U3D_PHYD_CPPAT
2085 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2086 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2087 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2088 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2089 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2090 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2091 +
2092 +//U3D_PHYD_MIX3
2093 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2094 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2095 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2096 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2097 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2098 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2099 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2100 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2101 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2102 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2103 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2104 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2105 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2106 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2107 +
2108 +//U3D_PHYD_EBUFCTL
2109 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2110 +
2111 +//U3D_PHYD_PIPE0
2112 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2113 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2114 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2115 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2116 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2117 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2118 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2119 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2120 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2121 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2122 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2123 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2124 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2125 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2126 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2127 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2128 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2129 +
2130 +//U3D_PHYD_PIPE1
2131 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2132 +
2133 +//U3D_PHYD_MIX4
2134 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2135 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2136 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2137 +
2138 +//U3D_PHYD_CKGEN0
2139 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2140 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2141 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2142 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2143 +
2144 +//U3D_PHYD_MIX5
2145 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2146 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2147 +
2148 +//U3D_PHYD_RESERVED
2149 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2150 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2151 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2152 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2153 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2154 +
2155 +//U3D_PHYD_CDR0
2156 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2157 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2158 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2159 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2160 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2161 +
2162 +//U3D_PHYD_CDR1
2163 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2164 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2165 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2166 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2167 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2168 +
2169 +//U3D_PHYD_PLL_0
2170 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2171 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2172 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2173 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2174 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2175 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2176 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2177 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2178 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2179 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2180 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2181 +
2182 +//U3D_PHYD_PLL_1
2183 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2184 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2185 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2186 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2187 +
2188 +//U3D_PHYD_BCN_DET_1
2189 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2190 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2191 +
2192 +//U3D_PHYD_BCN_DET_2
2193 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2194 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2195 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2196 +
2197 +//U3D_EQ0
2198 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2199 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2200 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2201 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2202 +
2203 +//U3D_EQ1
2204 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2205 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2206 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2207 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2208 +
2209 +//U3D_EQ2
2210 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2211 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2212 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2213 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2214 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2215 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2216 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2217 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2218 +
2219 +//U3D_EQ3
2220 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2221 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2222 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2223 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2224 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2225 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2226 +
2227 +//U3D_EQ_EYE0
2228 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2229 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2230 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2231 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2232 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2233 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2234 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2235 +
2236 +//U3D_EQ_EYE1
2237 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2238 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2239 +
2240 +//U3D_EQ_EYE2
2241 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2242 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2243 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2244 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2245 +
2246 +//U3D_EQ_DFE0
2247 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2248 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2249 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2250 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2251 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2252 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2253 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2254 +
2255 +//U3D_EQ_DFE1
2256 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2257 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2258 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2259 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2260 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2261 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2262 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2263 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2264 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2265 +
2266 +//U3D_EQ_DFE2
2267 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2268 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2269 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2270 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2271 +
2272 +//U3D_EQ_DFE3
2273 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2274 +
2275 +//U3D_PHYD_MON0
2276 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2277 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2278 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2279 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2280 +
2281 +//U3D_PHYD_MON1
2282 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2283 +
2284 +//U3D_PHYD_MON2
2285 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2286 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2287 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2288 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2289 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2290 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2291 +
2292 +//U3D_PHYD_MON3
2293 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2294 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2295 +
2296 +//U3D_PHYD_MON4
2297 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2298 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2299 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2300 +
2301 +//U3D_PHYD_MON5
2302 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2303 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2304 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2305 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2306 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2307 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2308 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2309 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2310 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2311 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2312 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2313 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2314 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2315 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2316 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2317 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2318 +
2319 +//U3D_PHYD_MON6
2320 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2321 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2322 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2323 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2324 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2325 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2326 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2327 +
2328 +//U3D_PHYD_MON7
2329 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2330 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2331 +
2332 +//U3D_PHYA_RX_MON0
2333 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2334 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2335 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2336 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2337 +
2338 +//U3D_PHYA_RX_MON1
2339 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2340 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2341 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2342 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2343 +
2344 +//U3D_PHYA_RX_MON2
2345 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2346 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2347 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2348 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2349 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2350 +
2351 +//U3D_PHYA_RX_MON3
2352 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2353 +
2354 +//U3D_PHYA_RX_MON4
2355 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2356 +
2357 +//U3D_PHYA_RX_MON5
2358 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2359 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2360 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2361 +
2362 +//U3D_PHYD_CPPAT2
2363 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2364 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2365 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2366 +
2367 +//U3D_EQ_EYE3
2368 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2369 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2370 +
2371 +//U3D_KBAND_OUT
2372 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2373 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2374 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2375 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2376 +
2377 +//U3D_KBAND_OUT1
2378 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2379 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2380 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2381 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2382 +
2383 +
2384 +/* OFFSET */
2385 +
2386 +//U3D_PHYD_MIX0
2387 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2388 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2389 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2390 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2391 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2392 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2393 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2394 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2395 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2396 +#define RG_SSUSB_PRBS_EN_OFST (13)
2397 +#define RG_SSUSB_BPSLOCK_OFST (12)
2398 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2399 +#define RG_SSUSB_COMCNT_OFST (4)
2400 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2401 +
2402 +//U3D_PHYD_MIX1
2403 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2404 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2405 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2406 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2407 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2408 +#define RG_SSUSB_PDNCTL_OFST (16)
2409 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2410 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2411 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2412 +#define RG_SSUSB_BERT_EN_OFST (7)
2413 +#define RG_SSUSB_SCP_TH_OFST (4)
2414 +#define RG_SSUSB_SCP_EN_OFST (3)
2415 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2416 +
2417 +//U3D_PHYD_LFPS0
2418 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2419 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2420 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2421 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2422 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2423 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2424 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2425 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2426 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2427 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2428 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2429 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2430 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2431 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2432 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2433 +
2434 +//U3D_PHYD_LFPS1
2435 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2436 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2437 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2438 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2439 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2440 +
2441 +//U3D_PHYD_IMPCAL0
2442 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2443 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2444 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2445 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2446 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2447 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2448 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2449 +
2450 +//U3D_PHYD_IMPCAL1
2451 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2452 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2453 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2454 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2455 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2456 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2457 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2458 +
2459 +//U3D_PHYD_TXPLL0
2460 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2461 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2462 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2463 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2464 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2465 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2466 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2467 +
2468 +//U3D_PHYD_TXPLL1
2469 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2470 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2471 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2472 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2473 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2474 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2475 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2476 +#define RG_SSUSB_PLL_PWD_OFST (23)
2477 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2478 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2479 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2480 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2481 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2482 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2483 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2484 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2485 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2486 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2487 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2488 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2489 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2490 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2491 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2492 +
2493 +//U3D_PHYD_TXPLL2
2494 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2495 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2496 +#define RG_SSUSB_TX_LFPS_OFST (29)
2497 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2498 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2499 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2500 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2501 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2502 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2503 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2504 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2505 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2506 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2507 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2508 +#define RG_SSUSB_CDR_PWD_OFST (6)
2509 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2510 +
2511 +//U3D_PHYD_FL0
2512 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2513 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2514 +
2515 +//U3D_PHYD_MIX2
2516 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2517 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2518 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2519 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2520 +#define RG_SSUSB_CDROS_EN_OFST (18)
2521 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2522 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2523 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2524 +
2525 +//U3D_PHYD_RX0
2526 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2527 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2528 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2529 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2530 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2531 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2532 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2533 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2534 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2535 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2536 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2537 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2538 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2539 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2540 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2541 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2542 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2543 +
2544 +//U3D_PHYD_T2RLB
2545 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2546 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2547 +#define RG_SSUSB_BPANSIENC_OFST (26)
2548 +#define RG_SSUSB_VALID_EN_OFST (25)
2549 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2550 +#define RG_SSUSB_K_EMP_OFST (20)
2551 +#define RG_SSUSB_K_FUL_OFST (16)
2552 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2553 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2554 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2555 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2556 +
2557 +//U3D_PHYD_CPPAT
2558 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2559 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2560 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2561 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2562 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2563 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2564 +
2565 +//U3D_PHYD_MIX3
2566 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2567 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2568 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2569 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2570 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2571 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2572 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2573 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2574 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2575 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2576 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2577 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2578 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2579 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2580 +
2581 +//U3D_PHYD_EBUFCTL
2582 +#define RG_SSUSB_EBUFCTL_OFST (0)
2583 +
2584 +//U3D_PHYD_PIPE0
2585 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2586 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2587 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2588 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2589 +#define RG_SSUSB_POWERDOWN_OFST (24)
2590 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2591 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2592 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2593 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2594 +#define RG_SSUSB_TXDATAK_OFST (16)
2595 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2596 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2597 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2598 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2599 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2600 +#define RG_SSUSB_TXMARGIN_OFST (1)
2601 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2602 +
2603 +//U3D_PHYD_PIPE1
2604 +#define RG_SSUSB_TXDATA_OFST (0)
2605 +
2606 +//U3D_PHYD_MIX4
2607 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2608 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2609 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2610 +
2611 +//U3D_PHYD_CKGEN0
2612 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2613 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2614 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2615 +#define RG_SSUSB_RXCK_INV_OFST (0)
2616 +
2617 +//U3D_PHYD_MIX5
2618 +#define RG_SSUSB_PRB_SEL_OFST (16)
2619 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2620 +
2621 +//U3D_PHYD_RESERVED
2622 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2623 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2624 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2625 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2626 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2627 +
2628 +//U3D_PHYD_CDR0
2629 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2630 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2631 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2632 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2633 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2634 +
2635 +//U3D_PHYD_CDR1
2636 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2637 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2638 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2639 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2640 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2641 +
2642 +//U3D_PHYD_PLL_0
2643 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2644 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2645 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2646 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2647 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2648 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2649 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2650 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2651 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2652 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2653 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2654 +
2655 +//U3D_PHYD_PLL_1
2656 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2657 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2658 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2659 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2660 +
2661 +//U3D_PHYD_BCN_DET_1
2662 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2663 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2664 +
2665 +//U3D_PHYD_BCN_DET_2
2666 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2667 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2668 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2669 +
2670 +//U3D_EQ0
2671 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2672 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2673 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2674 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2675 +
2676 +//U3D_EQ1
2677 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2678 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2679 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2680 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2681 +
2682 +//U3D_EQ2
2683 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2684 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2685 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2686 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2687 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2688 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2689 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2690 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2691 +
2692 +//U3D_EQ3
2693 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2694 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2695 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2696 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2697 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2698 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2699 +
2700 +//U3D_EQ_EYE0
2701 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2702 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2703 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2704 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2705 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2706 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2707 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2708 +
2709 +//U3D_EQ_EYE1
2710 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2711 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2712 +
2713 +//U3D_EQ_EYE2
2714 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2715 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2716 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2717 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2718 +
2719 +//U3D_EQ_DFE0
2720 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2721 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2722 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2723 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2724 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2725 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2726 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2727 +
2728 +//U3D_EQ_DFE1
2729 +#define RG_SSUSB_EQ_REV_OFST (16)
2730 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2731 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2732 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2733 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2734 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2735 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2736 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2737 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2738 +
2739 +//U3D_EQ_DFE2
2740 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2741 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2742 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2743 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2744 +
2745 +//U3D_EQ_DFE3
2746 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2747 +
2748 +//U3D_PHYD_MON0
2749 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2750 +#define RGS_SSUSB_LFPS_OFST (12)
2751 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2752 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2753 +
2754 +//U3D_PHYD_MON1
2755 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2756 +
2757 +//U3D_PHYD_MON2
2758 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2759 +#define RGS_SSUSB_RETRACK_OFST (12)
2760 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2761 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2762 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2763 +#define RGS_SSUSB_PDNCTL_OFST (0)
2764 +
2765 +//U3D_PHYD_MON3
2766 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2767 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2768 +
2769 +//U3D_PHYD_MON4
2770 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2771 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2772 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2773 +
2774 +//U3D_PHYD_MON5
2775 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2776 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2777 +#define RGS_SSUSB_SCP_DET_OFST (14)
2778 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2779 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2780 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2781 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2782 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2783 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2784 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2785 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2786 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2787 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2788 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2789 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2790 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2791 +
2792 +//U3D_PHYD_MON6
2793 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2794 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2795 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2796 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2797 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2798 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2799 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2800 +
2801 +//U3D_PHYD_MON7
2802 +#define RGS_SSUSB_FT_OUT_OFST (8)
2803 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2804 +
2805 +//U3D_PHYA_RX_MON0
2806 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2807 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2808 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2809 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2810 +
2811 +//U3D_PHYA_RX_MON1
2812 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2813 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2814 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2815 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2816 +
2817 +//U3D_PHYA_RX_MON2
2818 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2819 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2820 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2821 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2822 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2823 +
2824 +//U3D_PHYA_RX_MON3
2825 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2826 +
2827 +//U3D_PHYA_RX_MON4
2828 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2829 +
2830 +//U3D_PHYA_RX_MON5
2831 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2832 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2833 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2834 +
2835 +//U3D_PHYD_CPPAT2
2836 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2837 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2838 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2839 +
2840 +//U3D_EQ_EYE3
2841 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2842 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2843 +
2844 +//U3D_KBAND_OUT
2845 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2846 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2847 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2848 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2849 +
2850 +//U3D_KBAND_OUT1
2851 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2852 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2853 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2854 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2855 +
2856 +
2857 +///////////////////////////////////////////////////////////////////////////////
2858 +
2859 +struct u3phyd_bank2_reg {
2860 + //0x0
2861 + PHY_LE32 b2_phyd_top1;
2862 + PHY_LE32 b2_phyd_top2;
2863 + PHY_LE32 b2_phyd_top3;
2864 + PHY_LE32 b2_phyd_top4;
2865 + //0x10
2866 + PHY_LE32 b2_phyd_top5;
2867 + PHY_LE32 b2_phyd_top6;
2868 + PHY_LE32 b2_phyd_top7;
2869 + PHY_LE32 b2_phyd_p_sigdet1;
2870 + //0x20
2871 + PHY_LE32 b2_phyd_p_sigdet2;
2872 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2873 + PHY_LE32 b2_phyd_rxdet1;
2874 + PHY_LE32 b2_phyd_rxdet2;
2875 + //0x30
2876 + PHY_LE32 b2_phyd_misc0;
2877 + PHY_LE32 b2_phyd_misc2;
2878 + PHY_LE32 b2_phyd_misc3;
2879 + PHY_LE32 reserve0;
2880 + //0x40
2881 + PHY_LE32 b2_rosc_0;
2882 + PHY_LE32 b2_rosc_1;
2883 + PHY_LE32 b2_rosc_2;
2884 + PHY_LE32 b2_rosc_3;
2885 + //0x50
2886 + PHY_LE32 b2_rosc_4;
2887 + PHY_LE32 b2_rosc_5;
2888 + PHY_LE32 b2_rosc_6;
2889 + PHY_LE32 b2_rosc_7;
2890 + //0x60
2891 + PHY_LE32 b2_rosc_8;
2892 + PHY_LE32 b2_rosc_9;
2893 + PHY_LE32 b2_rosc_a;
2894 + PHY_LE32 reserve1;
2895 + //0x70~0xd0
2896 + PHY_LE32 reserve2[28];
2897 + //0xe0
2898 + PHY_LE32 phyd_version;
2899 + PHY_LE32 phyd_model;
2900 +};
2901 +
2902 +//U3D_B2_PHYD_TOP1
2903 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2904 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2905 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2906 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2907 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2908 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2909 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2910 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2911 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2912 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2913 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2914 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2915 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2916 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2917 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2918 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2919 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2920 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2921 +
2922 +//U3D_B2_PHYD_TOP2
2923 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2924 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2925 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2926 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2927 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2928 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2929 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2930 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2931 +
2932 +//U3D_B2_PHYD_TOP3
2933 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2934 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2935 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2936 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2937 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2938 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2939 +
2940 +//U3D_B2_PHYD_TOP4
2941 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2942 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2943 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2944 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2945 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2946 +
2947 +//U3D_B2_PHYD_TOP5
2948 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2949 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2950 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2951 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2952 +
2953 +//U3D_B2_PHYD_TOP6
2954 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2955 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2956 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2957 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2958 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2959 +
2960 +//U3D_B2_PHYD_TOP7
2961 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2962 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2963 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2964 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
2965 +
2966 +//U3D_B2_PHYD_P_SIGDET1
2967 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
2968 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2969 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2970 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
2971 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
2972 +
2973 +//U3D_B2_PHYD_P_SIGDET2
2974 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
2975 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
2976 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
2977 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
2978 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
2979 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
2980 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
2981 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
2982 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
2983 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
2984 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
2985 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
2986 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
2987 +
2988 +//U3D_B2_PHYD_P_SIGDET_CAL1
2989 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
2990 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
2991 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
2992 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
2993 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
2994 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
2995 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
2996 +
2997 +//U3D_B2_PHYD_RXDET1
2998 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
2999 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
3000 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
3001 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
3002 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
3003 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
3004 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
3005 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3006 +
3007 +//U3D_B2_PHYD_RXDET2
3008 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3009 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3010 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3011 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3012 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3013 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3014 +
3015 +//U3D_B2_PHYD_MISC0
3016 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3017 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3018 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3019 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3020 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3021 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3022 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3023 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3024 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3025 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3026 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3027 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3028 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3029 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3030 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3031 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3032 +
3033 +//U3D_B2_PHYD_MISC2
3034 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3035 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3036 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3037 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3038 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3039 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3040 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3041 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3042 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3043 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3044 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3045 +
3046 +//U3D_B2_PHYD_MISC3
3047 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3048 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3049 +
3050 +//U3D_B2_ROSC_0
3051 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3052 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3053 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3054 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3055 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3056 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3057 +
3058 +//U3D_B2_ROSC_1
3059 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3060 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3061 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3062 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3063 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3064 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3065 +
3066 +//U3D_B2_ROSC_2
3067 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3068 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3069 +
3070 +//U3D_B2_ROSC_3
3071 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3072 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3073 +
3074 +//U3D_B2_ROSC_4
3075 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3076 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3077 +
3078 +//U3D_B2_ROSC_5
3079 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3080 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3081 +
3082 +//U3D_B2_ROSC_6
3083 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3084 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3085 +
3086 +//U3D_B2_ROSC_7
3087 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3088 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3089 +
3090 +//U3D_B2_ROSC_8
3091 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3092 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3093 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3094 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3095 +
3096 +//U3D_B2_ROSC_9
3097 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3098 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3099 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3100 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3101 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3102 +
3103 +//U3D_B2_ROSC_A
3104 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3105 +
3106 +//U3D_PHYD_VERSION
3107 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3108 +
3109 +//U3D_PHYD_MODEL
3110 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3111 +
3112 +
3113 +/* OFFSET */
3114 +
3115 +//U3D_B2_PHYD_TOP1
3116 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3117 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3118 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3119 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3120 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3121 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3122 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3123 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3124 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3125 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3126 +#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
3127 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
3128 +#define RG_SSUSB_RATE_OFST (6)
3129 +#define RG_SSUSB_FORCE_RATE_OFST (5)
3130 +#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
3131 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
3132 +#define RG_SSUSB_PHY_MODE_OFST (1)
3133 +#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
3134 +
3135 +//U3D_B2_PHYD_TOP2
3136 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
3137 +#define RG_SSUSB_IDRV_6DB_OFST (24)
3138 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
3139 +#define RG_SSUSB_IDEM_3P5DB_OFST (16)
3140 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
3141 +#define RG_SSUSB_IDRV_3P5DB_OFST (8)
3142 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
3143 +#define RG_SSUSB_IDRV_0DB_OFST (0)
3144 +
3145 +//U3D_B2_PHYD_TOP3
3146 +#define RG_SSUSB_TX_BIASI_OFST (25)
3147 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
3148 +#define RG_SSUSB_TX_BIASI_EN_OFST (16)
3149 +#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
3150 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
3151 +#define RG_SSUSB_IDEM_6DB_OFST (0)
3152 +
3153 +//U3D_B2_PHYD_TOP4
3154 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
3155 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
3156 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
3157 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
3158 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
3159 +
3160 +//U3D_B2_PHYD_TOP5
3161 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
3162 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
3163 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
3164 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
3165 +
3166 +//U3D_B2_PHYD_TOP6
3167 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
3168 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
3169 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
3170 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
3171 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
3172 +
3173 +//U3D_B2_PHYD_TOP7
3174 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
3175 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
3176 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
3177 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
3178 +
3179 +//U3D_B2_PHYD_P_SIGDET1
3180 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
3181 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
3182 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
3183 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
3184 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
3185 +
3186 +//U3D_B2_PHYD_P_SIGDET2
3187 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
3188 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
3189 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
3190 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
3191 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
3192 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
3193 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
3194 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
3195 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
3196 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
3197 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
3198 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
3199 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
3200 +
3201 +//U3D_B2_PHYD_P_SIGDET_CAL1
3202 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
3203 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
3204 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
3205 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
3206 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
3207 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
3208 +#define RG_SSUSB_P_SIGDET_REK_OFST (0)
3209 +
3210 +//U3D_B2_PHYD_RXDET1
3211 +#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
3212 +#define RG_SSUSB_FORCE_CMDET_OFST (30)
3213 +#define RG_SSUSB_RXDET_EN_OFST (29)
3214 +#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
3215 +#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
3216 +#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
3217 +#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
3218 +#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
3219 +
3220 +//U3D_B2_PHYD_RXDET2
3221 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
3222 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
3223 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
3224 +#define RG_SSUSB_PDN_T_SEL_OFST (18)
3225 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
3226 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
3227 +
3228 +//U3D_B2_PHYD_MISC0
3229 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
3230 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
3231 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
3232 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
3233 +#define RG_SSUSB_LFPS_PSEL_OFST (15)
3234 +#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
3235 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
3236 +#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
3237 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
3238 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
3239 +#define RG_SSUSB_T2RLB_PSEL_OFST (8)
3240 +#define RG_SSUSB_PPCTL_PSEL_OFST (5)
3241 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
3242 +#define RG_SSUSB_BERTLB_PSEL_OFST (2)
3243 +#define RG_SSUSB_RETRACK_DIS_OFST (1)
3244 +#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
3245 +
3246 +//U3D_B2_PHYD_MISC2
3247 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
3248 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
3249 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
3250 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
3251 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
3252 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
3253 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
3254 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
3255 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
3256 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
3257 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
3258 +
3259 +//U3D_B2_PHYD_MISC3
3260 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
3261 +#define RGS_SSUSB_PPERRCNT_OFST (0)
3262 +
3263 +//U3D_B2_ROSC_0
3264 +#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
3265 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
3266 +#define RG_SSUSB_RING_OSC_EN_OFST (3)
3267 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
3268 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
3269 +#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
3270 +
3271 +//U3D_B2_ROSC_1
3272 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
3273 +#define RG_SSUSB_RING_OSC_P3_OFST (19)
3274 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
3275 +#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
3276 +#define RG_SSUSB_RING_OSC_SEL_OFST (8)
3277 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
3278 +
3279 +//U3D_B2_ROSC_2
3280 +#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
3281 +#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
3282 +
3283 +//U3D_B2_ROSC_3
3284 +#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
3285 +#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
3286 +
3287 +//U3D_B2_ROSC_4
3288 +#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
3289 +#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
3290 +
3291 +//U3D_B2_ROSC_5
3292 +#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
3293 +#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
3294 +
3295 +//U3D_B2_ROSC_6
3296 +#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
3297 +#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
3298 +
3299 +//U3D_B2_ROSC_7
3300 +#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
3301 +#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
3302 +
3303 +//U3D_B2_ROSC_8
3304 +#define RG_SSUSB_RING_RESERVE_OFST (16)
3305 +#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
3306 +#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
3307 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
3308 +
3309 +//U3D_B2_ROSC_9
3310 +#define RGS_FM_RING_CNT_OFST (16)
3311 +#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
3312 +#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
3313 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
3314 +#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
3315 +
3316 +//U3D_B2_ROSC_A
3317 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
3318 +
3319 +//U3D_PHYD_VERSION
3320 +#define RGS_SSUSB_PHYD_VERSION_OFST (0)
3321 +
3322 +//U3D_PHYD_MODEL
3323 +#define RGS_SSUSB_PHYD_MODEL_OFST (0)
3324 +
3325 +
3326 +///////////////////////////////////////////////////////////////////////////////
3327 +
3328 +struct sifslv_chip_reg {
3329 + PHY_LE32 xtalbias;
3330 + PHY_LE32 syspll1;
3331 + PHY_LE32 gpio_ctla;
3332 + PHY_LE32 gpio_ctlb;
3333 + PHY_LE32 gpio_ctlc;
3334 +};
3335 +
3336 +//U3D_GPIO_CTLA
3337 +#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
3338 +
3339 +//U3D_GPIO_CTLB
3340 +#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
3341 +
3342 +//U3D_GPIO_CTLC
3343 +#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
3344 +
3345 +/* OFFSET */
3346 +
3347 +//U3D_GPIO_CTLA
3348 +#define RG_C60802_GPIO_CTLA_OFST (0)
3349 +
3350 +//U3D_GPIO_CTLB
3351 +#define RG_C60802_GPIO_CTLB_OFST (0)
3352 +
3353 +//U3D_GPIO_CTLC
3354 +#define RG_C60802_GPIO_CTLC_OFST (0)
3355 +
3356 +///////////////////////////////////////////////////////////////////////////////
3357 +
3358 +struct sifslv_fm_feg {
3359 + //0x0
3360 + PHY_LE32 fmcr0;
3361 + PHY_LE32 fmcr1;
3362 + PHY_LE32 fmcr2;
3363 + PHY_LE32 fmmonr0;
3364 + //0x10
3365 + PHY_LE32 fmmonr1;
3366 +};
3367 +
3368 +//U3D_FMCR0
3369 +#define RG_LOCKTH (0xf<<28) //31:28
3370 +#define RG_MONCLK_SEL (0x3<<26) //27:26
3371 +#define RG_FM_MODE (0x1<<25) //25:25
3372 +#define RG_FREQDET_EN (0x1<<24) //24:24
3373 +#define RG_CYCLECNT (0xffffff<<0) //23:0
3374 +
3375 +//U3D_FMCR1
3376 +#define RG_TARGET (0xffffffff<<0) //31:0
3377 +
3378 +//U3D_FMCR2
3379 +#define RG_OFFSET (0xffffffff<<0) //31:0
3380 +
3381 +//U3D_FMMONR0
3382 +#define USB_FM_OUT (0xffffffff<<0) //31:0
3383 +
3384 +//U3D_FMMONR1
3385 +#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
3386 +#define RG_FRCK_EN (0x1<<8) //8:8
3387 +#define USBPLL_LOCK (0x1<<1) //1:1
3388 +#define USB_FM_VLD (0x1<<0) //0:0
3389 +
3390 +
3391 +/* OFFSET */
3392 +
3393 +//U3D_FMCR0
3394 +#define RG_LOCKTH_OFST (28)
3395 +#define RG_MONCLK_SEL_OFST (26)
3396 +#define RG_FM_MODE_OFST (25)
3397 +#define RG_FREQDET_EN_OFST (24)
3398 +#define RG_CYCLECNT_OFST (0)
3399 +
3400 +//U3D_FMCR1
3401 +#define RG_TARGET_OFST (0)
3402 +
3403 +//U3D_FMCR2
3404 +#define RG_OFFSET_OFST (0)
3405 +
3406 +//U3D_FMMONR0
3407 +#define USB_FM_OUT_OFST (0)
3408 +
3409 +//U3D_FMMONR1
3410 +#define RG_MONCLK_SEL_3_OFST (9)
3411 +#define RG_FRCK_EN_OFST (8)
3412 +#define USBPLL_LOCK_OFST (1)
3413 +#define USB_FM_VLD_OFST (0)
3414 +
3415 +
3416 +///////////////////////////////////////////////////////////////////////////////
3417 +
3418 +PHY_INT32 phy_init(struct u3phy_info *info);
3419 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3420 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3421 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3422 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3423 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3424 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3425 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3426 +
3427 +#endif
3428 +#endif
3429 --- /dev/null
3430 +++ b/drivers/usb/host/mtk-phy-ahb.c
3431 @@ -0,0 +1,58 @@
3432 +#include "mtk-phy.h"
3433 +#ifdef CONFIG_U3D_HAL_SUPPORT
3434 +#include "mu3d_hal_osal.h"
3435 +#endif
3436 +
3437 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3438 +#include <linux/gfp.h>
3439 +#include <linux/kernel.h>
3440 +#include <linux/slab.h>
3441 +
3442 +#ifndef CONFIG_U3D_HAL_SUPPORT
3443 +#define os_writel(addr,data) {\
3444 + (*((volatile PHY_UINT32*)(addr)) = data);\
3445 + }
3446 +#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
3447 +#define os_writelmsk(addr, data, msk) \
3448 + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3449 + }
3450 +#define os_setmsk(addr, msk) \
3451 + { os_writel(addr, os_readl(addr) | msk); \
3452 + }
3453 +#define os_clrmsk(addr, msk) \
3454 + { os_writel(addr, os_readl(addr) &~ msk); \
3455 + }
3456 +/*msk the data first, then umsk with the umsk.*/
3457 +#define os_writelmskumsk(addr, data, msk, umsk) \
3458 +{\
3459 + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3460 +}
3461 +
3462 +#endif
3463 +
3464 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3465 +{
3466 + os_writel(addr, data);
3467 +
3468 + return 0;
3469 +}
3470 +
3471 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3472 +{
3473 + return os_readl(addr);
3474 +}
3475 +
3476 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3477 +{
3478 + os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3479 +
3480 + return 0;
3481 +}
3482 +
3483 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3484 +{
3485 + return ((os_readl(addr)>>((addr%4)*8))&0xff);
3486 +}
3487 +
3488 +#endif
3489 +
3490 --- /dev/null
3491 +++ b/drivers/usb/host/mtk-phy.c
3492 @@ -0,0 +1,102 @@
3493 +#include <linux/gfp.h>
3494 +#include <linux/kernel.h>
3495 +#include <linux/slab.h>
3496 +#define U3_PHY_LIB
3497 +#include "mtk-phy.h"
3498 +#ifdef CONFIG_PROJECT_7621
3499 +#include "mtk-phy-7621.h"
3500 +#endif
3501 +#ifdef CONFIG_PROJECT_PHY
3502 +static struct u3phy_operator project_operators = {
3503 + .init = phy_init,
3504 + .change_pipe_phase = phy_change_pipe_phase,
3505 + .eyescan_init = eyescan_init,
3506 + .eyescan = phy_eyescan,
3507 + .u2_slew_rate_calibration = u2_slew_rate_calibration,
3508 +};
3509 +#endif
3510 +
3511 +
3512 +PHY_INT32 u3phy_init(){
3513 +#ifndef CONFIG_PROJECT_PHY
3514 + PHY_INT32 u3phy_version;
3515 +#endif
3516 +
3517 + if(u3phy != NULL){
3518 + return PHY_TRUE;
3519 + }
3520 +
3521 + u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3522 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3523 + u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3524 +#endif
3525 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3526 + u3phy->phyd_version_addr = 0x2000e4;
3527 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3528 + u3phy_p1->phyd_version_addr = 0x2000e4;
3529 +#endif
3530 +#else
3531 + u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3532 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3533 + u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3534 +#endif
3535 +#endif
3536 +
3537 +#ifdef CONFIG_PROJECT_PHY
3538 +
3539 + u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3540 + u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3541 + u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3542 + u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3543 + u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3544 + u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3545 + u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3546 + u3phy_ops = &project_operators;
3547 +
3548 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3549 + u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3550 + u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3551 + u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3552 + u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3553 + u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3554 + u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3555 + u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3556 +#endif
3557 +#endif
3558 +
3559 + return PHY_TRUE;
3560 +}
3561 +
3562 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3563 + PHY_INT8 cur_value;
3564 + PHY_INT8 new_value;
3565 +
3566 + cur_value = U3PhyReadReg8(addr);
3567 + new_value = (cur_value & (~mask)) | (value << offset);
3568 + //udelay(i2cdelayus);
3569 + U3PhyWriteReg8(addr, new_value);
3570 + return PHY_TRUE;
3571 +}
3572 +
3573 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3574 + PHY_INT32 cur_value;
3575 + PHY_INT32 new_value;
3576 +
3577 + cur_value = U3PhyReadReg32(addr);
3578 + new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3579 + U3PhyWriteReg32(addr, new_value);
3580 + //DRV_MDELAY(100);
3581 +
3582 + return PHY_TRUE;
3583 +}
3584 +
3585 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3586 +
3587 + return ((U3PhyReadReg8(addr) & mask) >> offset);
3588 +}
3589 +
3590 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3591 +
3592 + return ((U3PhyReadReg32(addr) & mask) >> offset);
3593 +}
3594 +
3595 --- /dev/null
3596 +++ b/drivers/usb/host/mtk-phy.h
3597 @@ -0,0 +1,179 @@
3598 +#ifndef __MTK_PHY_NEW_H
3599 +#define __MTK_PHY_NEW_H
3600 +
3601 +//#define CONFIG_U3D_HAL_SUPPORT
3602 +
3603 +/* include system library */
3604 +#include <linux/gfp.h>
3605 +#include <linux/kernel.h>
3606 +#include <linux/slab.h>
3607 +#include <linux/delay.h>
3608 +
3609 +/* Choose PHY R/W implementation */
3610 +//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
3611 +#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
3612 +
3613 +/* Choose PHY version */
3614 +//Select your project by defining one of the followings
3615 +#define CONFIG_PROJECT_7621 //7621
3616 +#define CONFIG_PROJECT_PHY
3617 +
3618 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3619 +#define PHY_BASE 0xBE1D0000
3620 +#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
3621 +#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
3622 +#define U2_PHY_BASE (PHY_BASE+0x800)
3623 +#define U3_PHYD_BASE (PHY_BASE+0x900)
3624 +#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
3625 +#define U3_PHYA_BASE (PHY_BASE+0xb00)
3626 +#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
3627 +
3628 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3629 +#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
3630 +#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
3631 +#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
3632 +#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
3633 +#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
3634 +#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
3635 +#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
3636 +#endif
3637 +
3638 +/*
3639 +
3640 +0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
3641 +0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
3642 +0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
3643 +0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
3644 +0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
3645 +0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
3646 +0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
3647 +*/
3648 +
3649 +
3650 +/* TYPE DEFINE */
3651 +typedef unsigned int PHY_UINT32;
3652 +typedef int PHY_INT32;
3653 +typedef unsigned short PHY_UINT16;
3654 +typedef short PHY_INT16;
3655 +typedef unsigned char PHY_UINT8;
3656 +typedef char PHY_INT8;
3657 +
3658 +typedef PHY_UINT32 __bitwise PHY_LE32;
3659 +
3660 +/* CONSTANT DEFINE */
3661 +#define PHY_FALSE 0
3662 +#define PHY_TRUE 1
3663 +
3664 +/* MACRO DEFINE */
3665 +#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3666 +#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
3667 +
3668 +#define DRV_MDELAY mdelay
3669 +#define DRV_MSLEEP msleep
3670 +#define DRV_UDELAY udelay
3671 +#define DRV_USLEEP usleep
3672 +
3673 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3674 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3675 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3676 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3677 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3678 +
3679 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3680 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3681 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3682 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3683 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3684 +
3685 +struct u3phy_info {
3686 + PHY_INT32 phy_version;
3687 + PHY_INT32 phyd_version_addr;
3688 +
3689 +#ifdef CONFIG_PROJECT_PHY
3690 + struct u2phy_reg *u2phy_regs;
3691 + struct u3phya_reg *u3phya_regs;
3692 + struct u3phya_da_reg *u3phya_da_regs;
3693 + struct u3phyd_reg *u3phyd_regs;
3694 + struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3695 + struct sifslv_chip_reg *sifslv_chip_regs;
3696 + struct sifslv_fm_feg *sifslv_fm_regs;
3697 +#endif
3698 +};
3699 +
3700 +struct u3phy_operator {
3701 + PHY_INT32 (*init) (struct u3phy_info *info);
3702 + PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3703 + PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3704 + PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3705 + PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3706 + PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3707 + PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3708 +};
3709 +
3710 +#ifdef U3_PHY_LIB
3711 +#define AUTOEXT
3712 +#else
3713 +#define AUTOEXT extern
3714 +#endif
3715 +
3716 +AUTOEXT struct u3phy_info *u3phy;
3717 +AUTOEXT struct u3phy_info *u3phy_p1;
3718 +AUTOEXT struct u3phy_operator *u3phy_ops;
3719 +
3720 +/*********eye scan required*********/
3721 +
3722 +#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
3723 +#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3724 +
3725 +typedef enum
3726 +{
3727 + SCAN_UP,
3728 + SCAN_DN
3729 +} enumScanDir;
3730 +
3731 +struct strucScanRegion
3732 +{
3733 + PHY_INT8 bX_tl;
3734 + PHY_INT8 bY_tl;
3735 + PHY_INT8 bX_br;
3736 + PHY_INT8 bY_br;
3737 + PHY_INT8 bDeltaX;
3738 + PHY_INT8 bDeltaY;
3739 +};
3740 +
3741 +struct strucTestCycle
3742 +{
3743 + PHY_UINT16 wEyeCnt;
3744 + PHY_INT8 bNumOfEyeCnt;
3745 + PHY_INT8 bPICalEn;
3746 + PHY_INT8 bNumOfIgnoreCnt;
3747 +};
3748 +
3749 +#define ERRCNT_MAX 128
3750 +#define CYCLE_COUNT_MAX 15
3751 +
3752 +/// the map resolution is 128 x 128 pts
3753 +#define MAX_X 127
3754 +#define MAX_Y 127
3755 +#define MIN_X 0
3756 +#define MIN_Y 0
3757 +
3758 +PHY_INT32 u3phy_init(void);
3759 +
3760 +AUTOEXT struct strucScanRegion _rEye1;
3761 +AUTOEXT struct strucScanRegion _rEye2;
3762 +AUTOEXT struct strucTestCycle _rTestCycle;
3763 +AUTOEXT PHY_UINT8 _bXcurr;
3764 +AUTOEXT PHY_UINT8 _bYcurr;
3765 +AUTOEXT enumScanDir _eScanDir;
3766 +AUTOEXT PHY_INT8 _fgXChged;
3767 +AUTOEXT PHY_INT8 _bPIResult;
3768 +/* use local variable instead to save memory use */
3769 +#if 0
3770 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3771 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3772 +#endif
3773 +
3774 +/***********************************/
3775 +#endif
3776 +
3777 --- a/drivers/usb/host/pci-quirks.h
3778 +++ b/drivers/usb/host/pci-quirks.h
3779 @@ -1,7 +1,7 @@
3780 #ifndef __LINUX_USB_PCI_QUIRKS_H
3781 #define __LINUX_USB_PCI_QUIRKS_H
3782
3783 -#ifdef CONFIG_PCI
3784 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3785 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3786 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3787 #endif /* CONFIG_PCI */
3788 --- a/drivers/usb/host/xhci-dbg.c
3789 +++ b/drivers/usb/host/xhci-dbg.c
3790 @@ -21,6 +21,9 @@
3791 */
3792
3793 #include "xhci.h"
3794 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3795 +#include "xhci-mtk.h"
3796 +#endif
3797
3798 #define XHCI_INIT_VALUE 0x0
3799
3800 --- a/drivers/usb/host/xhci-mem.c
3801 +++ b/drivers/usb/host/xhci-mem.c
3802 @@ -65,6 +65,9 @@ static struct xhci_segment *xhci_segment
3803
3804 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3805 {
3806 + if (!seg)
3807 + return;
3808 +
3809 if (seg->trbs) {
3810 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3811 seg->trbs = NULL;
3812 @@ -1446,9 +1449,17 @@ int xhci_endpoint_init(struct xhci_hcd *
3813 max_burst = (usb_endpoint_maxp(&ep->desc)
3814 & 0x1800) >> 11;
3815 }
3816 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3817 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3818 + max_packet += 2;
3819 +#endif
3820 break;
3821 case USB_SPEED_FULL:
3822 case USB_SPEED_LOW:
3823 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3824 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3825 + max_packet += 2;
3826 +#endif
3827 break;
3828 default:
3829 BUG();
3830 --- /dev/null
3831 +++ b/drivers/usb/host/xhci-mtk-power.c
3832 @@ -0,0 +1,115 @@
3833 +#include "xhci-mtk.h"
3834 +#include "xhci-mtk-power.h"
3835 +#include "xhci.h"
3836 +#include <linux/kernel.h> /* printk() */
3837 +#include <linux/slab.h>
3838 +#include <linux/delay.h>
3839 +
3840 +static int g_num_u3_port;
3841 +static int g_num_u2_port;
3842 +
3843 +
3844 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3845 + int i;
3846 + u32 port_id, temp;
3847 + u32 __iomem *addr;
3848 +
3849 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3850 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3851 +
3852 + for(i=1; i<=g_num_u3_port; i++){
3853 + port_id=i;
3854 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3855 + temp = xhci_readl(xhci, addr);
3856 + temp = xhci_port_state_to_neutral(temp);
3857 + temp |= PORT_POWER;
3858 + xhci_writel(xhci, temp, addr);
3859 + }
3860 + for(i=1; i<=g_num_u2_port; i++){
3861 + port_id=i+g_num_u3_port;
3862 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3863 + temp = xhci_readl(xhci, addr);
3864 + temp = xhci_port_state_to_neutral(temp);
3865 + temp |= PORT_POWER;
3866 + xhci_writel(xhci, temp, addr);
3867 + }
3868 +}
3869 +
3870 +void enableAllClockPower(){
3871 +
3872 + int i;
3873 + u32 temp;
3874 +
3875 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3876 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3877 +
3878 + //2. Enable xHC
3879 + writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3880 + writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3881 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3882 +
3883 + //1. Enable target ports
3884 + for(i=0; i<g_num_u3_port; i++){
3885 + temp = readl(SSUSB_U3_CTRL(i));
3886 + temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3887 + writel(temp, SSUSB_U3_CTRL(i));
3888 + }
3889 + for(i=0; i<g_num_u2_port; i++){
3890 + temp = readl(SSUSB_U2_CTRL(i));
3891 + temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3892 + writel(temp, SSUSB_U2_CTRL(i));
3893 + }
3894 + msleep(100);
3895 +}
3896 +
3897 +
3898 +//(X)disable clock/power of a port
3899 +//(X)if all ports are disabled, disable IP ctrl power
3900 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3901 +//and IP could be disable if suspended.
3902 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3903 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3904 +//port_index: port number
3905 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3906 +void disablePortClockPower(void){
3907 + int i;
3908 + u32 temp;
3909 +
3910 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3911 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3912 +
3913 + for(i=0; i<g_num_u3_port; i++){
3914 + temp = readl(SSUSB_U3_CTRL(i));
3915 + temp = temp | (SSUSB_U3_PORT_PDN);
3916 + writel(temp, SSUSB_U3_CTRL(i));
3917 + }
3918 + for(i=0; i<g_num_u2_port; i++){
3919 + temp = readl(SSUSB_U2_CTRL(i));
3920 + temp = temp | (SSUSB_U2_PORT_PDN);
3921 + writel(temp, SSUSB_U2_CTRL(i));
3922 + }
3923 + writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3924 +}
3925 +
3926 +//if IP ctrl power is disabled, enable it
3927 +//enable clock/power of a port
3928 +//port_index: port number
3929 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3930 +void enablePortClockPower(int port_index, int port_rev){
3931 + int i;
3932 + u32 temp;
3933 +
3934 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3935 +
3936 + if(port_rev == 0x3){
3937 + temp = readl(SSUSB_U3_CTRL(port_index));
3938 + temp = temp & (~SSUSB_U3_PORT_PDN);
3939 + writel(temp, SSUSB_U3_CTRL(port_index));
3940 + }
3941 + else if(port_rev == 0x2){
3942 + temp = readl(SSUSB_U2_CTRL(port_index));
3943 + temp = temp & (~SSUSB_U2_PORT_PDN);
3944 + writel(temp, SSUSB_U2_CTRL(port_index));
3945 + }
3946 +}
3947 +
3948 --- /dev/null
3949 +++ b/drivers/usb/host/xhci-mtk-power.h
3950 @@ -0,0 +1,13 @@
3951 +#ifndef _XHCI_MTK_POWER_H
3952 +#define _XHCI_MTK_POWER_H
3953 +
3954 +#include <linux/usb.h>
3955 +#include "xhci.h"
3956 +#include "xhci-mtk.h"
3957 +
3958 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3959 +void enableAllClockPower(void);
3960 +void disablePortClockPower(void);
3961 +void enablePortClockPower(int port_index, int port_rev);
3962 +
3963 +#endif
3964 --- /dev/null
3965 +++ b/drivers/usb/host/xhci-mtk-scheduler.c
3966 @@ -0,0 +1,608 @@
3967 +#include "xhci-mtk-scheduler.h"
3968 +#include <linux/kernel.h> /* printk() */
3969 +
3970 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
3971 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
3972 +static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
3973 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
3974 +
3975 +
3976 +int mtk_xhci_scheduler_init(void){
3977 + int i;
3978 +
3979 + for(i=0; i<MAX_EP_NUM; i++){
3980 + ss_out_eps[i] = NULL;
3981 + }
3982 + for(i=0; i<MAX_EP_NUM; i++){
3983 + ss_in_eps[i] = NULL;
3984 + }
3985 + for(i=0; i<MAX_EP_NUM; i++){
3986 + hs_eps[i] = NULL;
3987 + }
3988 + for(i=0; i<MAX_EP_NUM; i++){
3989 + tt_intr_eps[i] = NULL;
3990 + }
3991 + return 0;
3992 +}
3993 +
3994 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
3995 + , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
3996 + , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
3997 +
3998 + struct sch_ep **ep_array;
3999 + int i;
4000 +
4001 + if(is_in && dev_speed == USB_SPEED_SUPER ){
4002 + ep_array = (struct sch_ep **)ss_in_eps;
4003 + }
4004 + else if(dev_speed == USB_SPEED_SUPER){
4005 + ep_array = (struct sch_ep **)ss_out_eps;
4006 + }
4007 + else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4008 + ep_array = (struct sch_ep **)hs_eps;
4009 + }
4010 + else{
4011 + ep_array = (struct sch_ep **)tt_intr_eps;
4012 + }
4013 + for(i=0; i<MAX_EP_NUM; i++){
4014 + if(ep_array[i] == NULL){
4015 + tmp_ep->dev_speed = dev_speed;
4016 + tmp_ep->isTT = isTT;
4017 + tmp_ep->is_in = is_in;
4018 + tmp_ep->ep_type = ep_type;
4019 + tmp_ep->maxp = maxp;
4020 + tmp_ep->interval = interval;
4021 + tmp_ep->burst = burst;
4022 + tmp_ep->mult = mult;
4023 + tmp_ep->offset = offset;
4024 + tmp_ep->repeat = repeat;
4025 + tmp_ep->pkts = pkts;
4026 + tmp_ep->cs_count = cs_count;
4027 + tmp_ep->burst_mode = burst_mode;
4028 + tmp_ep->bw_cost = bw_cost;
4029 + tmp_ep->ep = ep;
4030 + ep_array[i] = tmp_ep;
4031 + return SCH_SUCCESS;
4032 + }
4033 + }
4034 + return SCH_FAIL;
4035 +}
4036 +
4037 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4038 + , int td_size){
4039 + int i, j, k;
4040 + int bw_required[3];
4041 + int final_bw_required;
4042 + int bw_required_per_repeat;
4043 + int tmp_bw_required;
4044 + struct sch_ep *cur_sch_ep;
4045 + struct sch_ep **ep_array;
4046 + int cur_offset;
4047 + int cur_ep_offset;
4048 + int tmp_offset;
4049 + int tmp_interval;
4050 + int ep_offset;
4051 + int ep_interval;
4052 + int ep_repeat;
4053 + int ep_mult;
4054 +
4055 + if(is_in){
4056 + ep_array = (struct sch_ep **)ss_in_eps;
4057 + }
4058 + else{
4059 + ep_array = (struct sch_ep **)ss_out_eps;
4060 + }
4061 +
4062 + bw_required[0] = 0;
4063 + bw_required[1] = 0;
4064 + bw_required[2] = 0;
4065 +
4066 + if(repeat == 0){
4067 + final_bw_required = 0;
4068 + for(i=0; i<MAX_EP_NUM; i++){
4069 + cur_sch_ep = ep_array[i];
4070 + if(cur_sch_ep == NULL){
4071 + continue;
4072 + }
4073 + ep_interval = cur_sch_ep->interval;
4074 + ep_offset = cur_sch_ep->offset;
4075 + if(cur_sch_ep->repeat == 0){
4076 + if(ep_interval >= interval){
4077 + tmp_offset = ep_offset + ep_interval - offset;
4078 + tmp_interval = interval;
4079 + }
4080 + else{
4081 + tmp_offset = offset + interval - ep_offset;
4082 + tmp_interval = ep_interval;
4083 + }
4084 + if(tmp_offset % tmp_interval == 0){
4085 + final_bw_required += cur_sch_ep->bw_cost;
4086 + }
4087 + }
4088 + else{
4089 + ep_repeat = cur_sch_ep->repeat;
4090 + ep_mult = cur_sch_ep->mult;
4091 + for(k=0; k<=ep_mult; k++){
4092 + cur_ep_offset = ep_offset+(k*ep_mult);
4093 + if(ep_interval >= interval){
4094 + tmp_offset = cur_ep_offset + ep_interval - offset;
4095 + tmp_interval = interval;
4096 + }
4097 + else{
4098 + tmp_offset = offset + interval - cur_ep_offset;
4099 + tmp_interval = ep_interval;
4100 + }
4101 + if(tmp_offset % tmp_interval == 0){
4102 + final_bw_required += cur_sch_ep->bw_cost;
4103 + break;
4104 + }
4105 + }
4106 + }
4107 + }
4108 + final_bw_required += td_size;
4109 + }
4110 + else{
4111 + bw_required_per_repeat = maxp * (burst+1);
4112 + for(j=0; j<=mult; j++){
4113 + tmp_bw_required = 0;
4114 + cur_offset = offset+(j*repeat);
4115 + for(i=0; i<MAX_EP_NUM; i++){
4116 + cur_sch_ep = ep_array[i];
4117 + if(cur_sch_ep == NULL){
4118 + continue;
4119 + }
4120 + ep_interval = cur_sch_ep->interval;
4121 + ep_offset = cur_sch_ep->offset;
4122 + if(cur_sch_ep->repeat == 0){
4123 + if(ep_interval >= interval){
4124 + tmp_offset = ep_offset + ep_interval - cur_offset;
4125 + tmp_interval = interval;
4126 + }
4127 + else{
4128 + tmp_offset = cur_offset + interval - ep_offset;
4129 + tmp_interval = ep_interval;
4130 + }
4131 + if(tmp_offset % tmp_interval == 0){
4132 + tmp_bw_required += cur_sch_ep->bw_cost;
4133 + }
4134 + }
4135 + else{
4136 + ep_repeat = cur_sch_ep->repeat;
4137 + ep_mult = cur_sch_ep->mult;
4138 + for(k=0; k<=ep_mult; k++){
4139 + cur_ep_offset = ep_offset+(k*ep_repeat);
4140 + if(ep_interval >= interval){
4141 + tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4142 + tmp_interval = interval;
4143 + }
4144 + else{
4145 + tmp_offset = cur_offset + interval - cur_ep_offset;
4146 + tmp_interval = ep_interval;
4147 + }
4148 + if(tmp_offset % tmp_interval == 0){
4149 + tmp_bw_required += cur_sch_ep->bw_cost;
4150 + break;
4151 + }
4152 + }
4153 + }
4154 + }
4155 + bw_required[j] = tmp_bw_required;
4156 + }
4157 + final_bw_required = SS_BW_BOUND;
4158 + for(j=0; j<=mult; j++){
4159 + if(bw_required[j] < final_bw_required){
4160 + final_bw_required = bw_required[j];
4161 + }
4162 + }
4163 + final_bw_required += bw_required_per_repeat;
4164 + }
4165 + return final_bw_required;
4166 +}
4167 +
4168 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4169 + int i;
4170 + int bw_required;
4171 + struct sch_ep *cur_sch_ep;
4172 + int tmp_offset;
4173 + int tmp_interval;
4174 + int ep_offset;
4175 + int ep_interval;
4176 + int cur_tt_isoc_interval; //for isoc tt check
4177 +
4178 + bw_required = 0;
4179 + for(i=0; i<MAX_EP_NUM; i++){
4180 +
4181 + cur_sch_ep = (struct sch_ep *)hs_eps[i];
4182 + if(cur_sch_ep == NULL){
4183 + continue;
4184 + }
4185 + ep_offset = cur_sch_ep->offset;
4186 + ep_interval = cur_sch_ep->interval;
4187 +
4188 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4189 + cur_tt_isoc_interval = ep_interval<<3;
4190 + if(ep_interval >= interval){
4191 + tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4192 + tmp_interval = interval;
4193 + }
4194 + else{
4195 + tmp_offset = offset + interval - ep_offset;
4196 + tmp_interval = cur_tt_isoc_interval;
4197 + }
4198 + if(cur_sch_ep->is_in){
4199 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4200 + bw_required += 188;
4201 + }
4202 + }
4203 + else{
4204 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4205 + bw_required += 188;
4206 + }
4207 + }
4208 + }
4209 + else{
4210 + if(ep_interval >= interval){
4211 + tmp_offset = ep_offset + ep_interval - offset;
4212 + tmp_interval = interval;
4213 + }
4214 + else{
4215 + tmp_offset = offset + interval - ep_offset;
4216 + tmp_interval = ep_interval;
4217 + }
4218 + if(tmp_offset%tmp_interval == 0){
4219 + bw_required += cur_sch_ep->bw_cost;
4220 + }
4221 + }
4222 + }
4223 + bw_required += td_size;
4224 + return bw_required;
4225 +}
4226 +
4227 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4228 + char is_cs;
4229 + int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4230 + int bw_required, max_bw;
4231 + int ss_cs_count;
4232 + int cs_mframe;
4233 + int max_frame;
4234 + int i,j;
4235 + struct sch_ep *cur_sch_ep;
4236 + int ep_offset;
4237 + int ep_interval;
4238 + int ep_cs_count;
4239 + int tt_isoc_interval; //for isoc tt check
4240 + int cur_tt_isoc_interval; //for isoc tt check
4241 + int tmp_offset;
4242 + int tmp_interval;
4243 +
4244 + is_cs = 0;
4245 +
4246 + tt_isoc_interval = interval<<3; //frame to mframe
4247 + if(is_in){
4248 + is_cs = 1;
4249 + }
4250 + s_frame = offset/8;
4251 + s_mframe = offset%8;
4252 + ss_cs_count = (maxp + (188 - 1))/188;
4253 + if(is_cs){
4254 + cs_mframe = offset%8 + 2 + ss_cs_count;
4255 + if (cs_mframe <= 6)
4256 + ss_cs_count += 2;
4257 + else if (cs_mframe == 7)
4258 + ss_cs_count++;
4259 + else if (cs_mframe > 8)
4260 + return -1;
4261 + }
4262 + max_bw = 0;
4263 + if(is_in){
4264 + i=2;
4265 + }
4266 + for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4267 + bw_required = 0;
4268 + for(j=0; j<MAX_EP_NUM; j++){
4269 + cur_sch_ep = (struct sch_ep *)hs_eps[j];
4270 + if(cur_sch_ep == NULL){
4271 + continue;
4272 + }
4273 + ep_offset = cur_sch_ep->offset;
4274 + ep_interval = cur_sch_ep->interval;
4275 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4276 + //isoc tt
4277 + //check if mframe offset overlap
4278 + //if overlap, add 188 to the bw
4279 + cur_tt_isoc_interval = ep_interval<<3;
4280 + if(cur_tt_isoc_interval >= tt_isoc_interval){
4281 + tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
4282 + tmp_interval = tt_isoc_interval;
4283 + }
4284 + else{
4285 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4286 + tmp_interval = cur_tt_isoc_interval;
4287 + }
4288 + if(cur_sch_ep->is_in){
4289 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4290 + bw_required += 188;
4291 + }
4292 + }
4293 + else{
4294 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4295 + bw_required += 188;
4296 + }
4297 + }
4298 +
4299 + }
4300 + else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4301 + //check if mframe
4302 + if(ep_interval >= tt_isoc_interval){
4303 + tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4304 + tmp_interval = tt_isoc_interval;
4305 + }
4306 + else{
4307 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4308 + tmp_interval = ep_interval;
4309 + }
4310 + if(tmp_offset%tmp_interval == 0){
4311 + bw_required += cur_sch_ep->bw_cost;
4312 + }
4313 + }
4314 + }
4315 + bw_required += 188;
4316 + if(bw_required > max_bw){
4317 + max_bw = bw_required;
4318 + }
4319 + }
4320 + return max_bw;
4321 +}
4322 +
4323 +int count_tt_intr_bw(int interval, int frame_offset){
4324 + //check all eps in tt_intr_eps
4325 + int ret;
4326 + int i,j;
4327 + int ep_offset;
4328 + int ep_interval;
4329 + int tmp_offset;
4330 + int tmp_interval;
4331 + ret = SCH_SUCCESS;
4332 + struct sch_ep *cur_sch_ep;
4333 +
4334 + for(i=0; i<MAX_EP_NUM; i++){
4335 + cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4336 + if(cur_sch_ep == NULL){
4337 + continue;
4338 + }
4339 + ep_offset = cur_sch_ep->offset;
4340 + ep_interval = cur_sch_ep->interval;
4341 + if(ep_interval >= interval){
4342 + tmp_offset = ep_offset + ep_interval - frame_offset;
4343 + tmp_interval = interval;
4344 + }
4345 + else{
4346 + tmp_offset = frame_offset + interval - ep_offset;
4347 + tmp_interval = ep_interval;
4348 + }
4349 +
4350 + if(tmp_offset%tmp_interval==0){
4351 + return SCH_FAIL;
4352 + }
4353 + }
4354 + return SCH_SUCCESS;
4355 +}
4356 +
4357 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4358 + int i;
4359 + struct sch_ep **ep_array;
4360 + struct sch_ep *cur_ep;
4361 +
4362 + if (is_in && dev_speed == USB_SPEED_SUPER) {
4363 + ep_array = (struct sch_ep **)ss_in_eps;
4364 + }
4365 + else if (dev_speed == USB_SPEED_SUPER) {
4366 + ep_array = (struct sch_ep **)ss_out_eps;
4367 + }
4368 + else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4369 + ep_array = (struct sch_ep **)hs_eps;
4370 + }
4371 + else {
4372 + ep_array = (struct sch_ep **)tt_intr_eps;
4373 + }
4374 + for (i = 0; i < MAX_EP_NUM; i++) {
4375 + cur_ep = (struct sch_ep *)ep_array[i];
4376 + if(cur_ep != NULL && cur_ep->ep == ep){
4377 + ep_array[i] = NULL;
4378 + return cur_ep;
4379 + }
4380 + }
4381 + return NULL;
4382 +}
4383 +
4384 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4385 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4386 + mtk_u32 bPkts = 0;
4387 + mtk_u32 bCsCount = 0;
4388 + mtk_u32 bBm = 1;
4389 + mtk_u32 bOffset = 0;
4390 + mtk_u32 bRepeat = 0;
4391 + int ret;
4392 + struct mtk_xhci_ep_ctx *temp_ep_ctx;
4393 + int td_size;
4394 + int mframe_idx, frame_idx;
4395 + int bw_cost;
4396 + int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4397 + int cur_offset, cs_mframe;
4398 + int break_out;
4399 + int frame_interval;
4400 +
4401 + printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4402 + , interval, burst, mult, ep, ep_ctx, sch_ep);
4403 + if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4404 + frame_interval = interval >> 3;
4405 + for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4406 + printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4407 + if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4408 + printk(KERN_ERR "check OK............\n");
4409 + bOffset = frame_idx<<3;
4410 + bPkts = 1;
4411 + bCsCount = 3;
4412 + bw_cost = maxp;
4413 + bRepeat = 0;
4414 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4415 + , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4416 + return SCH_FAIL;
4417 + }
4418 + ret = SCH_SUCCESS;
4419 + break;
4420 + }
4421 + }
4422 + }
4423 + else if(isTT && ep_type == USB_EP_ISOC){
4424 + best_bw = HS_BW_BOUND;
4425 + best_bw_idx = -1;
4426 + cur_bw = 0;
4427 + td_size = maxp;
4428 + break_out = 0;
4429 + frame_interval = interval>>3;
4430 + for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4431 + for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4432 + cur_offset = (frame_idx*8) + mframe_idx;
4433 + cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4434 + if(cur_bw > 0 && cur_bw < best_bw){
4435 + best_bw_idx = cur_offset;
4436 + best_bw = cur_bw;
4437 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4438 + break_out = 1;
4439 + break;
4440 + }
4441 + }
4442 + }
4443 + }
4444 + if(best_bw_idx == -1){
4445 + return SCH_FAIL;
4446 + }
4447 + else{
4448 + bOffset = best_bw_idx;
4449 + bPkts = 1;
4450 + bCsCount = (maxp + (188 - 1)) / 188;
4451 + if(is_in){
4452 + cs_mframe = bOffset%8 + 2 + bCsCount;
4453 + if (cs_mframe <= 6)
4454 + bCsCount += 2;
4455 + else if (cs_mframe == 7)
4456 + bCsCount++;
4457 + }
4458 + bw_cost = 188;
4459 + bRepeat = 0;
4460 + if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4461 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4462 + return SCH_FAIL;
4463 + }
4464 + ret = SCH_SUCCESS;
4465 + }
4466 + }
4467 + else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4468 + bPkts = 1;
4469 + ret = SCH_SUCCESS;
4470 + }
4471 + else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4472 + bPkts = 1;
4473 + ret = SCH_SUCCESS;
4474 + }
4475 + else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4476 + best_bw = HS_BW_BOUND;
4477 + best_bw_idx = -1;
4478 + cur_bw = 0;
4479 + td_size = maxp*(burst+1);
4480 + for(cur_offset = 0; cur_offset<interval; cur_offset++){
4481 + cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4482 + if(cur_bw > 0 && cur_bw < best_bw){
4483 + best_bw_idx = cur_offset;
4484 + best_bw = cur_bw;
4485 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4486 + break;
4487 + }
4488 + }
4489 + }
4490 + if(best_bw_idx == -1){
4491 + return SCH_FAIL;
4492 + }
4493 + else{
4494 + bOffset = best_bw_idx;
4495 + bPkts = burst + 1;
4496 + bCsCount = 0;
4497 + bw_cost = td_size;
4498 + bRepeat = 0;
4499 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4500 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4501 + return SCH_FAIL;
4502 + }
4503 + ret = SCH_SUCCESS;
4504 + }
4505 + }
4506 + else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4507 + best_bw = SS_BW_BOUND;
4508 + best_bw_idx = -1;
4509 + cur_bw = 0;
4510 + td_size = maxp * (mult+1) * (burst+1);
4511 + if(mult == 0){
4512 + max_repeat = 0;
4513 + }
4514 + else{
4515 + max_repeat = (interval-1)/(mult+1);
4516 + }
4517 + break_out = 0;
4518 + for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4519 + for(repeat = max_repeat; repeat >= 0; repeat--){
4520 + cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4521 + , repeat, td_size);
4522 + printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4523 + , frame_idx, repeat, td_size, cur_bw);
4524 + if(cur_bw > 0 && cur_bw < best_bw){
4525 + best_bw_idx = frame_idx;
4526 + best_bw_repeat = repeat;
4527 + best_bw = cur_bw;
4528 + if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4529 + break_out = 1;
4530 + break;
4531 + }
4532 + }
4533 + }
4534 + }
4535 + printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4536 + if(best_bw_idx == -1){
4537 + return SCH_FAIL;
4538 + }
4539 + else{
4540 + bOffset = best_bw_idx;
4541 + bCsCount = 0;
4542 + bRepeat = best_bw_repeat;
4543 + if(bRepeat == 0){
4544 + bw_cost = (burst+1)*(mult+1)*maxp;
4545 + bPkts = (burst+1)*(mult+1);
4546 + }
4547 + else{
4548 + bw_cost = (burst+1)*maxp;
4549 + bPkts = (burst+1);
4550 + }
4551 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4552 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4553 + return SCH_FAIL;
4554 + }
4555 + ret = SCH_SUCCESS;
4556 + }
4557 + }
4558 + else{
4559 + bPkts = 1;
4560 + ret = SCH_SUCCESS;
4561 + }
4562 + if(ret == SCH_SUCCESS){
4563 + temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4564 + temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4565 + temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4566 +
4567 + printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4568 + printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4569 + return SCH_SUCCESS;
4570 + }
4571 + else{
4572 + return SCH_FAIL;
4573 + }
4574 +}
4575 --- /dev/null
4576 +++ b/drivers/usb/host/xhci-mtk-scheduler.h
4577 @@ -0,0 +1,77 @@
4578 +#ifndef _XHCI_MTK_SCHEDULER_H
4579 +#define _XHCI_MTK_SCHEDULER_H
4580 +
4581 +#define MTK_SCH_NEW 1
4582 +
4583 +#define SCH_SUCCESS 1
4584 +#define SCH_FAIL 0
4585 +
4586 +#define MAX_EP_NUM 64
4587 +#define SS_BW_BOUND 51000
4588 +#define HS_BW_BOUND 6144
4589 +
4590 +#define USB_EP_CONTROL 0
4591 +#define USB_EP_ISOC 1
4592 +#define USB_EP_BULK 2
4593 +#define USB_EP_INT 3
4594 +
4595 +#define USB_SPEED_LOW 1
4596 +#define USB_SPEED_FULL 2
4597 +#define USB_SPEED_HIGH 3
4598 +#define USB_SPEED_SUPER 5
4599 +
4600 +/* mtk scheduler bitmasks */
4601 +#define BPKTS(p) ((p) & 0x3f)
4602 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
4603 +#define BBM(p) ((p) << 11)
4604 +#define BOFFSET(p) ((p) & 0x3fff)
4605 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
4606 +
4607 +
4608 +#if 1
4609 +typedef unsigned int mtk_u32;
4610 +typedef unsigned long long mtk_u64;
4611 +#endif
4612 +
4613 +#define NULL ((void *)0)
4614 +
4615 +struct mtk_xhci_ep_ctx {
4616 + mtk_u32 ep_info;
4617 + mtk_u32 ep_info2;
4618 + mtk_u64 deq;
4619 + mtk_u32 tx_info;
4620 + /* offset 0x14 - 0x1f reserved for HC internal use */
4621 + mtk_u32 reserved[3];
4622 +};
4623 +
4624 +
4625 +struct sch_ep
4626 +{
4627 + //device info
4628 + int dev_speed;
4629 + int isTT;
4630 + //ep info
4631 + int is_in;
4632 + int ep_type;
4633 + int maxp;
4634 + int interval;
4635 + int burst;
4636 + int mult;
4637 + //scheduling info
4638 + int offset;
4639 + int repeat;
4640 + int pkts;
4641 + int cs_count;
4642 + int burst_mode;
4643 + //other
4644 + int bw_cost; //bandwidth cost in each repeat; including overhead
4645 + mtk_u32 *ep; //address of usb_endpoint pointer
4646 +};
4647 +
4648 +int mtk_xhci_scheduler_init(void);
4649 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4650 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4651 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4652 +
4653 +
4654 +#endif
4655 --- /dev/null
4656 +++ b/drivers/usb/host/xhci-mtk.c
4657 @@ -0,0 +1,265 @@
4658 +#include "xhci-mtk.h"
4659 +#include "xhci-mtk-power.h"
4660 +#include "xhci.h"
4661 +#include "mtk-phy.h"
4662 +#ifdef CONFIG_C60802_SUPPORT
4663 +#include "mtk-phy-c60802.h"
4664 +#endif
4665 +#include "xhci-mtk-scheduler.h"
4666 +#include <linux/kernel.h> /* printk() */
4667 +#include <linux/slab.h>
4668 +#include <linux/delay.h>
4669 +#include <asm/uaccess.h>
4670 +#include <linux/dma-mapping.h>
4671 +#include <linux/platform_device.h>
4672 +
4673 +void setInitialReg(void )
4674 +{
4675 + __u32 __iomem *addr;
4676 + u32 temp;
4677 +
4678 + /* set SSUSB DMA burst size to 128B */
4679 + addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4680 + temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4681 + writel(temp, addr);
4682 +
4683 + /* extend U3 LTSSM Polling.LFPS timeout value */
4684 + addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4685 + temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4686 + writel(temp, addr);
4687 +
4688 + /* EOF */
4689 + addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4690 + temp = SYNC_HS_EOF_VALUE;
4691 + writel(temp, addr);
4692 +
4693 +#if defined (CONFIG_PERIODIC_ENP)
4694 + /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4695 + addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4696 + temp = readl(addr);
4697 + temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4698 + writel(temp, addr);
4699 +#endif
4700 +
4701 + /* Doorbell handling */
4702 + addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4703 + temp = 0x1;
4704 + writel(temp, addr);
4705 +
4706 + /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4707 + /* Port 0 */
4708 + addr = U2_PHY_BASE + U2_PHYD_CR1;
4709 + temp = readl(addr);
4710 + temp &= ~(0x3 << 18);
4711 + temp |= (1 << 18);
4712 + writel(temp, addr);
4713 +
4714 + /* Port 1 */
4715 + addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4716 + temp = readl(addr);
4717 + temp &= ~(0x3 << 18);
4718 + temp |= (1 << 18);
4719 + writel(temp, addr);
4720 +}
4721 +
4722 +
4723 +void setLatchSel(void){
4724 + __u32 __iomem *latch_sel_addr;
4725 + u32 latch_sel_value;
4726 + latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4727 + latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4728 + writel(latch_sel_value, latch_sel_addr);
4729 +}
4730 +
4731 +void reinitIP(void){
4732 + __u32 __iomem *ip_reset_addr;
4733 + u32 ip_reset_value;
4734 +
4735 + enableAllClockPower();
4736 + mtk_xhci_scheduler_init();
4737 +}
4738 +
4739 +void dbg_prb_out(void){
4740 + mtk_probe_init(0x0f0f0f0f);
4741 + mtk_probe_out(0xffffffff);
4742 + mtk_probe_out(0x01010101);
4743 + mtk_probe_out(0x02020202);
4744 + mtk_probe_out(0x04040404);
4745 + mtk_probe_out(0x08080808);
4746 + mtk_probe_out(0x10101010);
4747 + mtk_probe_out(0x20202020);
4748 + mtk_probe_out(0x40404040);
4749 + mtk_probe_out(0x80808080);
4750 + mtk_probe_out(0x55555555);
4751 + mtk_probe_out(0xaaaaaaaa);
4752 +}
4753 +
4754 +
4755 +
4756 +///////////////////////////////////////////////////////////////////////////////
4757 +
4758 +#define RET_SUCCESS 0
4759 +#define RET_FAIL 1
4760 +
4761 +static int dbg_u3w(int argc, char**argv)
4762 +{
4763 + int u4TimingValue;
4764 + char u1TimingValue;
4765 + int u4TimingAddress;
4766 +
4767 + if (argc<3)
4768 + {
4769 + printk(KERN_ERR "Arg: address value\n");
4770 + return RET_FAIL;
4771 + }
4772 + u3phy_init();
4773 +
4774 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4775 + u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4776 + u1TimingValue = u4TimingValue & 0xff;
4777 + /* access MMIO directly */
4778 + writel(u1TimingValue, u4TimingAddress);
4779 + printk(KERN_ERR "Write done\n");
4780 + return RET_SUCCESS;
4781 +
4782 +}
4783 +
4784 +static int dbg_u3r(int argc, char**argv)
4785 +{
4786 + char u1ReadTimingValue;
4787 + int u4TimingAddress;
4788 + if (argc<2)
4789 + {
4790 + printk(KERN_ERR "Arg: address\n");
4791 + return 0;
4792 + }
4793 + u3phy_init();
4794 + mdelay(500);
4795 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4796 + /* access MMIO directly */
4797 + u1ReadTimingValue = readl(u4TimingAddress);
4798 + printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4799 + return 0;
4800 +}
4801 +
4802 +static int dbg_u3init(int argc, char**argv)
4803 +{
4804 + int ret;
4805 + ret = u3phy_init();
4806 + printk(KERN_ERR "phy registers and operations initial done\n");
4807 + if(u3phy_ops->u2_slew_rate_calibration){
4808 + u3phy_ops->u2_slew_rate_calibration(u3phy);
4809 + }
4810 + else{
4811 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4812 + }
4813 + if(u3phy_ops->init(u3phy) == PHY_TRUE)
4814 + return RET_SUCCESS;
4815 + return RET_FAIL;
4816 +}
4817 +
4818 +void dbg_setU1U2(int argc, char**argv){
4819 + struct xhci_hcd *xhci;
4820 + int u1_value;
4821 + int u2_value;
4822 + u32 port_id, temp;
4823 + u32 __iomem *addr;
4824 +
4825 + if (argc<3)
4826 + {
4827 + printk(KERN_ERR "Arg: u1value u2value\n");
4828 + return RET_FAIL;
4829 + }
4830 +
4831 + u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4832 + u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4833 + addr = (SSUSB_U3_XHCI_BASE + 0x424);
4834 + temp = readl(addr);
4835 + temp = temp & (~(0x0000ffff));
4836 + temp = temp | u1_value | (u2_value<<8);
4837 + writel(temp, addr);
4838 +}
4839 +///////////////////////////////////////////////////////////////////////////////
4840 +
4841 +int call_function(char *buf)
4842 +{
4843 + int i;
4844 + int argc;
4845 + char *argv[80];
4846 +
4847 + argc = 0;
4848 + do
4849 + {
4850 + argv[argc] = strsep(&buf, " ");
4851 + printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4852 + argc++;
4853 + } while (buf);
4854 + if (!strcmp("dbg.r", argv[0]))
4855 + dbg_prb_out();
4856 + else if (!strcmp("dbg.u3w", argv[0]))
4857 + dbg_u3w(argc, argv);
4858 + else if (!strcmp("dbg.u3r", argv[0]))
4859 + dbg_u3r(argc, argv);
4860 + else if (!strcmp("dbg.u3i", argv[0]))
4861 + dbg_u3init(argc, argv);
4862 + else if (!strcmp("pw.u1u2", argv[0]))
4863 + dbg_setU1U2(argc, argv);
4864 + return 0;
4865 +}
4866 +
4867 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4868 +{
4869 + char w_buf[200];
4870 + char r_buf[200] = "this is a test";
4871 + int len = 200;
4872 +
4873 + switch (cmd) {
4874 + case IOCTL_READ:
4875 + copy_to_user((char *) arg, r_buf, len);
4876 + printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4877 + break;
4878 + case IOCTL_WRITE:
4879 + copy_from_user(w_buf, (char *) arg, len);
4880 + printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4881 +
4882 + //invoke function
4883 + return call_function(w_buf);
4884 + break;
4885 + default:
4886 + return -ENOTTY;
4887 + }
4888 +
4889 + return len;
4890 +}
4891 +
4892 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4893 +{
4894 +
4895 + printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4896 + return 0;
4897 +}
4898 +
4899 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4900 +{
4901 +
4902 + printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4903 + return 0;
4904 +}
4905 +
4906 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4907 +{
4908 +
4909 + printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4910 + return 0;
4911 +}
4912 +
4913 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4914 +{
4915 +
4916 + printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4917 + return 0;
4918 +}
4919 +
4920 +
4921 +
4922 +
4923 --- /dev/null
4924 +++ b/drivers/usb/host/xhci-mtk.h
4925 @@ -0,0 +1,120 @@
4926 +#ifndef _XHCI_MTK_H
4927 +#define _XHCI_MTK_H
4928 +
4929 +#include <linux/usb.h>
4930 +#include "xhci.h"
4931 +
4932 +#define SSUSB_U3_XHCI_BASE 0xBE1C0000
4933 +#define SSUSB_U3_MAC_BASE 0xBE1C2400
4934 +#define SSUSB_U3_SYS_BASE 0xBE1C2600
4935 +#define SSUSB_U2_SYS_BASE 0xBE1C3400
4936 +#define SSUB_SIF_SLV_TOP 0xBE1D0000
4937 +#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
4938 +
4939 +#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
4940 +#define U3_PIPE_LATCH_TX 0
4941 +#define U3_PIPE_LATCH_RX 0
4942 +
4943 +#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
4944 +#define U3_REF_CK_PAR 0xb0
4945 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
4946 +#define U3_RX_UX_EXIT_LFPS_REF 3
4947 +#define U3_REF_CK_VAL 10
4948 +
4949 +#define U3_TIMING_PULSE_CTRL 0xb4
4950 +#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4951 +
4952 +#define USB20_TIMING_PARAMETER 0x40
4953 +#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4954 +
4955 +#define LINK_PM_TIMER 0x8
4956 +#define PM_LC_TIMEOUT_VALUE 3
4957 +
4958 +#define XHCI_IMOD 0x624
4959 +#define XHCI_IMOD_MT7621_VALUE 0x10
4960 +
4961 +#define SSUSB_HDMA_CFG 0x950
4962 +#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
4963 +
4964 +#define U3_LTSSM_TIMING_PARAMETER3 0x2514
4965 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
4966 +
4967 +#define U2_PHYD_CR1 0x64
4968 +
4969 +#define SSUSB_IP_SPAR0 0xC8
4970 +
4971 +#define SYNC_HS_EOF 0x938
4972 +#define SYNC_HS_EOF_VALUE 0x201F3
4973 +
4974 +#define HSCH_CFG1 0x960
4975 +#define SCH2_FIFO_DEPTH_OFFSET 16
4976 +
4977 +
4978 +#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
4979 +#define SSUSB_IP_SW_RST (1<<0)
4980 +#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
4981 +#define SSUSB_IP_PDN (1<<0)
4982 +#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
4983 +#define SSUSB_U3_PORT_DIS (1<<0)
4984 +#define SSUSB_U3_PORT_PDN (1<<1)
4985 +#define SSUSB_U3_PORT_HOST_SEL (1<<2)
4986 +#define SSUSB_U3_PORT_CKBG_EN (1<<3)
4987 +#define SSUSB_U3_PORT_MAC_RST (1<<4)
4988 +#define SSUSB_U3_PORT_PHYD_RST (1<<5)
4989 +#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
4990 +#define SSUSB_U2_PORT_DIS (1<<0)
4991 +#define SSUSB_U2_PORT_PDN (1<<1)
4992 +#define SSUSB_U2_PORT_HOST_SEL (1<<2)
4993 +#define SSUSB_U2_PORT_CKBG_EN (1<<3)
4994 +#define SSUSB_U2_PORT_MAC_RST (1<<4)
4995 +#define SSUSB_U2_PORT_PHYD_RST (1<<5)
4996 +#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
4997 +
4998 +#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
4999 +#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
5000 +
5001 +
5002 +#define XHCI_MTK_TEST_MAJOR 234
5003 +#define DEVICE_NAME "xhci_mtk_test"
5004 +
5005 +#define CLI_MAGIC 'CLI'
5006 +#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
5007 +#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
5008 +
5009 +void reinitIP(void);
5010 +void setInitialReg(void);
5011 +void dbg_prb_out(void);
5012 +int call_function(char *buf);
5013 +
5014 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5015 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5016 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5017 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5018 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5019 +
5020 +/*
5021 + mediatek probe out
5022 +*/
5023 +/************************************************************************************/
5024 +
5025 +#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
5026 +#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
5027 +
5028 +static inline void mtk_probe_init(const u32 byte){
5029 + __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5030 + writel(byte, ptr);
5031 +}
5032 +
5033 +static inline void mtk_probe_out(const u32 value){
5034 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5035 + writel(value, ptr);
5036 +}
5037 +
5038 +static inline u32 mtk_probe_value(void){
5039 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5040 +
5041 + return readl(ptr);
5042 +}
5043 +
5044 +
5045 +#endif
5046 --- a/drivers/usb/host/xhci-plat.c
5047 +++ b/drivers/usb/host/xhci-plat.c
5048 @@ -25,6 +25,13 @@ static void xhci_plat_quirks(struct devi
5049 * dev struct in order to setup MSI
5050 */
5051 xhci->quirks |= XHCI_PLAT;
5052 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5053 + /* MTK host controller gives a spurious successful event after a
5054 + * short transfer. Ignore it.
5055 + */
5056 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5057 + xhci->quirks |= XHCI_LPM_SUPPORT;
5058 +#endif
5059 }
5060
5061 /* called during probe() after chip reset completes */
5062 @@ -96,20 +103,32 @@ static int xhci_plat_probe(struct platfo
5063
5064 driver = &xhci_plat_xhci_driver;
5065
5066 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5067 + irq = XHC_IRQ;
5068 +#else
5069 irq = platform_get_irq(pdev, 0);
5070 +#endif
5071 +
5072 if (irq < 0)
5073 return -ENODEV;
5074
5075 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5076 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5077 if (!res)
5078 return -ENODEV;
5079 +#endif
5080
5081 hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
5082 if (!hcd)
5083 return -ENOMEM;
5084
5085 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5086 + hcd->rsrc_start = (uint32_t)XHC_IO_START;
5087 + hcd->rsrc_len = XHC_IO_LENGTH;
5088 +#else
5089 hcd->rsrc_start = res->start;
5090 hcd->rsrc_len = resource_size(res);
5091 +#endif
5092
5093 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
5094 driver->description)) {
5095 --- a/drivers/usb/host/xhci-ring.c
5096 +++ b/drivers/usb/host/xhci-ring.c
5097 @@ -236,7 +236,6 @@ static void inc_enq(struct xhci_hcd *xhc
5098 */
5099 if (!chain && !more_trbs_coming)
5100 break;
5101 -
5102 /* If we're not dealing with 0.95 hardware or
5103 * isoc rings on AMD 0.96 host,
5104 * carry over the chain bit of the previous TRB
5105 @@ -273,16 +272,20 @@ static void inc_enq(struct xhci_hcd *xhc
5106 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5107 unsigned int num_trbs)
5108 {
5109 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5110 int num_trbs_in_deq_seg;
5111 +#endif
5112
5113 if (ring->num_trbs_free < num_trbs)
5114 return 0;
5115
5116 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5117 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5118 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5119 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5120 return 0;
5121 }
5122 +#endif
5123
5124 return 1;
5125 }
5126 @@ -2910,6 +2913,7 @@ static int prepare_ring(struct xhci_hcd
5127 next = ring->enqueue;
5128
5129 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5130 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5131 /* If we're not dealing with 0.95 hardware or isoc rings
5132 * on AMD 0.96 host, clear the chain bit.
5133 */
5134 @@ -2919,7 +2923,9 @@ static int prepare_ring(struct xhci_hcd
5135 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5136 else
5137 next->link.control |= cpu_to_le32(TRB_CHAIN);
5138 -
5139 +#else
5140 + next->link.control &= cpu_to_le32(~TRB_CHAIN);
5141 +#endif
5142 wmb();
5143 next->link.control ^= cpu_to_le32(TRB_CYCLE);
5144
5145 @@ -3049,6 +3055,9 @@ static void giveback_first_trb(struct xh
5146 start_trb->field[3] |= cpu_to_le32(start_cycle);
5147 else
5148 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5149 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5150 + wmb();
5151 +#endif
5152 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5153 }
5154
5155 @@ -3108,6 +3117,29 @@ static u32 xhci_td_remainder(unsigned in
5156 return (remainder >> 10) << 17;
5157 }
5158
5159 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5160 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5161 +{
5162 + u32 max = 31;
5163 + int remainder, td_packet_count, packet_transferred;
5164 +
5165 + //0 for the last TRB
5166 + //FIXME: need to workaround if there is ZLP in this TD
5167 + if (td_running_total + trb_buffer_length == td_transfer_size)
5168 + return 0;
5169 +
5170 + //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5171 + packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5172 + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5173 + remainder = td_packet_count - packet_transferred;
5174 +
5175 + if (remainder > max)
5176 + return max << 17;
5177 + else
5178 + return remainder << 17;
5179 +}
5180 +#endif
5181 +
5182 /*
5183 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5184 * packets remaining in the TD (*not* including this TRB).
5185 @@ -3245,6 +3277,7 @@ static int queue_bulk_sg_tx(struct xhci_
5186 }
5187
5188 /* Set the TRB length, TD size, and interrupter fields. */
5189 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5190 if (xhci->hci_version < 0x100) {
5191 remainder = xhci_td_remainder(
5192 urb->transfer_buffer_length -
5193 @@ -3254,6 +3287,13 @@ static int queue_bulk_sg_tx(struct xhci_
5194 trb_buff_len, total_packet_count, urb,
5195 num_trbs - 1);
5196 }
5197 +#else
5198 + if (num_trbs > 1)
5199 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5200 + running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5201 +#endif
5202 +
5203 +
5204 length_field = TRB_LEN(trb_buff_len) |
5205 remainder |
5206 TRB_INTR_TARGET(0);
5207 @@ -3316,6 +3356,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5208 int running_total, trb_buff_len, ret;
5209 unsigned int total_packet_count;
5210 u64 addr;
5211 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5212 + int max_packet;
5213 +#endif
5214
5215 if (urb->num_sgs)
5216 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5217 @@ -3341,6 +3384,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5218 running_total += TRB_MAX_BUFF_SIZE;
5219 }
5220 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
5221 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5222 + switch(urb->dev->speed){
5223 + case USB_SPEED_SUPER:
5224 + max_packet = urb->ep->desc.wMaxPacketSize;
5225 + break;
5226 + case USB_SPEED_HIGH:
5227 + case USB_SPEED_FULL:
5228 + case USB_SPEED_LOW:
5229 + case USB_SPEED_WIRELESS:
5230 + case USB_SPEED_UNKNOWN:
5231 + default:
5232 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5233 + break;
5234 + }
5235 + if((urb->transfer_flags & URB_ZERO_PACKET)
5236 + && ((urb->transfer_buffer_length % max_packet) == 0)){
5237 + num_trbs++;
5238 + }
5239 +#endif
5240
5241 ret = prepare_transfer(xhci, xhci->devs[slot_id],
5242 ep_index, urb->stream_id,
5243 @@ -3400,6 +3462,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5244 field |= TRB_ISP;
5245
5246 /* Set the TRB length, TD size, and interrupter fields. */
5247 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5248 if (xhci->hci_version < 0x100) {
5249 remainder = xhci_td_remainder(
5250 urb->transfer_buffer_length -
5251 @@ -3409,6 +3472,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5252 trb_buff_len, total_packet_count, urb,
5253 num_trbs - 1);
5254 }
5255 +#else
5256 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5257 +#endif
5258 +
5259 length_field = TRB_LEN(trb_buff_len) |
5260 remainder |
5261 TRB_INTR_TARGET(0);
5262 @@ -3498,7 +3565,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5263 field |= 0x1;
5264
5265 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
5266 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5267 + if (1) {
5268 +#else
5269 if (xhci->hci_version == 0x100) {
5270 +#endif
5271 if (urb->transfer_buffer_length > 0) {
5272 if (setup->bRequestType & USB_DIR_IN)
5273 field |= TRB_TX_TYPE(TRB_DATA_IN);
5274 @@ -3522,7 +3593,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5275 field = TRB_TYPE(TRB_DATA);
5276
5277 length_field = TRB_LEN(urb->transfer_buffer_length) |
5278 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5279 xhci_td_remainder(urb->transfer_buffer_length) |
5280 +#else
5281 + //CC: MTK style, no scatter-gather for control transfer
5282 + 0 |
5283 +#endif
5284 TRB_INTR_TARGET(0);
5285 if (urb->transfer_buffer_length > 0) {
5286 if (setup->bRequestType & USB_DIR_IN)
5287 @@ -3533,7 +3609,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5288 length_field,
5289 field | ep_ring->cycle_state);
5290 }
5291 -
5292 +
5293 /* Save the DMA address of the last TRB in the TD */
5294 td->last_trb = ep_ring->enqueue;
5295
5296 @@ -3645,6 +3721,9 @@ static int xhci_queue_isoc_tx(struct xhc
5297 u64 start_addr, addr;
5298 int i, j;
5299 bool more_trbs_coming;
5300 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5301 + int max_packet;
5302 +#endif
5303
5304 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5305
5306 @@ -3658,6 +3737,21 @@ static int xhci_queue_isoc_tx(struct xhc
5307 start_trb = &ep_ring->enqueue->generic;
5308 start_cycle = ep_ring->cycle_state;
5309
5310 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5311 + switch(urb->dev->speed){
5312 + case USB_SPEED_SUPER:
5313 + max_packet = urb->ep->desc.wMaxPacketSize;
5314 + break;
5315 + case USB_SPEED_HIGH:
5316 + case USB_SPEED_FULL:
5317 + case USB_SPEED_LOW:
5318 + case USB_SPEED_WIRELESS:
5319 + case USB_SPEED_UNKNOWN:
5320 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5321 + break;
5322 + }
5323 +#endif
5324 +
5325 urb_priv = urb->hcpriv;
5326 /* Queue the first TRB, even if it's zero-length */
5327 for (i = 0; i < num_tds; i++) {
5328 @@ -3729,9 +3823,13 @@ static int xhci_queue_isoc_tx(struct xhc
5329 } else {
5330 td->last_trb = ep_ring->enqueue;
5331 field |= TRB_IOC;
5332 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5333 + if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5334 +#else
5335 if (xhci->hci_version == 0x100 &&
5336 !(xhci->quirks &
5337 XHCI_AVOID_BEI)) {
5338 +#endif
5339 /* Set BEI bit except for the last td */
5340 if (i < num_tds - 1)
5341 field |= TRB_BEI;
5342 @@ -3746,6 +3844,7 @@ static int xhci_queue_isoc_tx(struct xhc
5343 trb_buff_len = td_remain_len;
5344
5345 /* Set the TRB length, TD size, & interrupter fields. */
5346 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5347 if (xhci->hci_version < 0x100) {
5348 remainder = xhci_td_remainder(
5349 td_len - running_total);
5350 @@ -3755,6 +3854,10 @@ static int xhci_queue_isoc_tx(struct xhc
5351 total_packet_count, urb,
5352 (trbs_per_td - j - 1));
5353 }
5354 +#else
5355 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5356 +#endif
5357 +
5358 length_field = TRB_LEN(trb_buff_len) |
5359 remainder |
5360 TRB_INTR_TARGET(0);
5361 --- a/drivers/usb/host/xhci.c
5362 +++ b/drivers/usb/host/xhci.c
5363 @@ -30,6 +30,16 @@
5364
5365 #include "xhci.h"
5366
5367 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5368 +#include <asm/uaccess.h>
5369 +#include <linux/dma-mapping.h>
5370 +#include <linux/platform_device.h>
5371 +#include "mtk-phy.h"
5372 +#include "xhci-mtk-scheduler.h"
5373 +#include "xhci-mtk-power.h"
5374 +#include "xhci-mtk.h"
5375 +#endif
5376 +
5377 #define DRIVER_AUTHOR "Sarah Sharp"
5378 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5379
5380 @@ -38,6 +48,18 @@ static int link_quirk;
5381 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
5382 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
5383
5384 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5385 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5386 +static struct file_operations xhci_mtk_test_fops = {
5387 + .owner = THIS_MODULE,
5388 + .read = xhci_mtk_test_read,
5389 + .write = xhci_mtk_test_write,
5390 + .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
5391 + .open = xhci_mtk_test_open,
5392 + .release = xhci_mtk_test_release,
5393 +};
5394 +#endif
5395 +
5396 /* TODO: copied from ehci-hcd.c - can this be refactored? */
5397 /*
5398 * xhci_handshake - spin reading hc until handshake completes or fails
5399 @@ -189,7 +211,7 @@ int xhci_reset(struct xhci_hcd *xhci)
5400 return ret;
5401 }
5402
5403 -#ifdef CONFIG_PCI
5404 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5405 static int xhci_free_msi(struct xhci_hcd *xhci)
5406 {
5407 int i;
5408 @@ -389,6 +411,7 @@ static int xhci_try_enable_msi(struct us
5409 return ret;
5410 }
5411 hcd->irq = pdev->irq;
5412 +
5413 return 0;
5414 }
5415
5416 @@ -430,6 +453,11 @@ static void compliance_mode_recovery(uns
5417 xhci_dbg(xhci, "Attempting compliance mode recovery\n");
5418 hcd = xhci->shared_hcd;
5419
5420 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5421 + temp |= (1 << 31);
5422 + xhci_writel(xhci, temp, xhci->usb3_ports[i]);
5423 +#endif
5424 +
5425 if (hcd->state == HC_STATE_SUSPENDED)
5426 usb_hcd_resume_root_hub(hcd);
5427
5428 @@ -478,6 +506,9 @@ bool xhci_compliance_mode_recovery_timer
5429 {
5430 const char *dmi_product_name, *dmi_sys_vendor;
5431
5432 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5433 + return true;
5434 +#endif
5435 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5436 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5437 if (!dmi_product_name || !dmi_sys_vendor)
5438 @@ -521,6 +552,10 @@ int xhci_init(struct usb_hcd *hcd)
5439 } else {
5440 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
5441 }
5442 +
5443 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5444 + mtk_xhci_scheduler_init();
5445 +#endif
5446 retval = xhci_mem_init(xhci, GFP_KERNEL);
5447 xhci_dbg(xhci, "Finished xhci_init\n");
5448
5449 @@ -664,7 +699,11 @@ int xhci_run(struct usb_hcd *hcd)
5450 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
5451 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
5452 temp &= ~ER_IRQ_INTERVAL_MASK;
5453 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5454 + temp |= (u32) 16;
5455 +#else
5456 temp |= (u32) 160;
5457 +#endif
5458 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
5459
5460 /* Set the HCD state before we enable the irqs */
5461 @@ -685,6 +724,9 @@ int xhci_run(struct usb_hcd *hcd)
5462 xhci_queue_vendor_command(xhci, 0, 0, 0,
5463 TRB_TYPE(TRB_NEC_GET_FW));
5464
5465 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5466 + enableXhciAllPortPower(xhci);
5467 +#endif
5468 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
5469 return 0;
5470 }
5471 @@ -1002,7 +1044,6 @@ int xhci_resume(struct xhci_hcd *xhci, b
5472
5473 /* If restore operation fails, re-initialize the HC during resume */
5474 if ((temp & STS_SRE) || hibernated) {
5475 -
5476 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
5477 !(xhci_all_ports_seen_u0(xhci))) {
5478 del_timer_sync(&xhci->comp_mode_recovery_timer);
5479 @@ -1586,6 +1627,13 @@ int xhci_drop_endpoint(struct usb_hcd *h
5480 u32 drop_flag;
5481 u32 new_add_flags, new_drop_flags, new_slot_info;
5482 int ret;
5483 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5484 +#if MTK_SCH_NEW
5485 + struct sch_ep *sch_ep = NULL;
5486 + int isTT;
5487 + int ep_type;
5488 +#endif
5489 +#endif
5490
5491 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5492 if (ret <= 0)
5493 @@ -1637,6 +1685,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
5494
5495 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5496
5497 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5498 +#if MTK_SCH_NEW
5499 + slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5500 + if ((slot_ctx->tt_info & 0xff) > 0) {
5501 + isTT = 1;
5502 + }
5503 + else {
5504 + isTT = 0;
5505 + }
5506 + if (usb_endpoint_xfer_int(&ep->desc)) {
5507 + ep_type = USB_EP_INT;
5508 + }
5509 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5510 + ep_type = USB_EP_ISOC;
5511 + }
5512 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5513 + ep_type = USB_EP_BULK;
5514 + }
5515 + else
5516 + ep_type = USB_EP_CONTROL;
5517 +
5518 + sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5519 + , isTT, ep_type, (mtk_u32 *)ep);
5520 + if (sch_ep != NULL) {
5521 + kfree(sch_ep);
5522 + }
5523 + else {
5524 + xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5525 + }
5526 +#else
5527 + mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5528 +#endif
5529 +#endif
5530 +
5531 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
5532 (unsigned int) ep->desc.bEndpointAddress,
5533 udev->slot_id,
5534 @@ -1672,6 +1754,18 @@ int xhci_add_endpoint(struct usb_hcd *hc
5535 u32 new_add_flags, new_drop_flags, new_slot_info;
5536 struct xhci_virt_device *virt_dev;
5537 int ret = 0;
5538 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5539 + struct xhci_ep_ctx *in_ep_ctx;
5540 +#if MTK_SCH_NEW
5541 + struct sch_ep *sch_ep;
5542 + int isTT;
5543 + int ep_type;
5544 + int maxp = 0;
5545 + int burst = 0;
5546 + int mult = 0;
5547 + int interval;
5548 +#endif
5549 +#endif
5550
5551 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5552 if (ret <= 0) {
5553 @@ -1734,6 +1828,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
5554 return -ENOMEM;
5555 }
5556
5557 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5558 + in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5559 +#if MTK_SCH_NEW
5560 + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5561 + if ((slot_ctx->tt_info & 0xff) > 0) {
5562 + isTT = 1;
5563 + }
5564 + else {
5565 + isTT = 0;
5566 + }
5567 + if (usb_endpoint_xfer_int(&ep->desc)) {
5568 + ep_type = USB_EP_INT;
5569 + }
5570 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5571 + ep_type = USB_EP_ISOC;
5572 + }
5573 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5574 + ep_type = USB_EP_BULK;
5575 + }
5576 + else
5577 + ep_type = USB_EP_CONTROL;
5578 +
5579 + if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5580 + || udev->speed == USB_SPEED_LOW) {
5581 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5582 + burst = ep->desc.wMaxPacketSize >> 11;
5583 + mult = 0;
5584 + }
5585 + else if (udev->speed == USB_SPEED_SUPER) {
5586 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5587 + burst = ep->ss_ep_comp.bMaxBurst;
5588 + mult = ep->ss_ep_comp.bmAttributes & 0x3;
5589 + }
5590 + interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5591 + sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5592 + if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5593 + isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5594 + , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5595 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5596 +
5597 + return -ENOSPC;
5598 + }
5599 +#else
5600 + if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5601 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5602 +
5603 + return -ENOSPC;
5604 + }
5605 +#endif
5606 +#endif
5607 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5608 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5609
5610 @@ -2697,7 +2841,7 @@ int xhci_check_bandwidth(struct usb_hcd
5611 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
5612 ctrl_ctx->drop_flags == 0)
5613 return 0;
5614 -
5615 +
5616 xhci_dbg(xhci, "New Input Control Context:\n");
5617 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
5618 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
5619 @@ -4233,10 +4377,14 @@ static u16 xhci_call_host_update_timeout
5620 u16 *timeout)
5621 {
5622 if (state == USB3_LPM_U1) {
5623 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5624 if (xhci->quirks & XHCI_INTEL_HOST)
5625 +#endif
5626 return xhci_calculate_intel_u1_timeout(udev, desc);
5627 } else {
5628 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5629 if (xhci->quirks & XHCI_INTEL_HOST)
5630 +#endif
5631 return xhci_calculate_intel_u2_timeout(udev, desc);
5632 }
5633
5634 @@ -4662,7 +4810,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5635 /* Accept arbitrarily long scatter-gather lists */
5636 hcd->self.sg_tablesize = ~0;
5637 /* XHCI controllers don't stop the ep queue on short packets :| */
5638 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5639 hcd->self.no_stop_on_short = 1;
5640 +#endif
5641
5642 if (usb_hcd_is_primary_hcd(hcd)) {
5643 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
5644 @@ -4731,6 +4881,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5645 goto error;
5646 xhci_dbg(xhci, "Reset complete\n");
5647
5648 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5649 + setInitialReg();
5650 +#endif
5651 +
5652 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
5653 if (HCC_64BIT_ADDR(temp)) {
5654 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5655 @@ -4755,8 +4909,21 @@ MODULE_DESCRIPTION(DRIVER_DESC);
5656 MODULE_AUTHOR(DRIVER_AUTHOR);
5657 MODULE_LICENSE("GPL");
5658
5659 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5660 +static struct platform_device xhci_platform_dev = {
5661 + .name = "xhci-hcd",
5662 + .id = -1,
5663 + .dev = {
5664 + .coherent_dma_mask = 0xffffffff,
5665 + },
5666 +};
5667 +#endif
5668 +
5669 static int __init xhci_hcd_init(void)
5670 {
5671 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5672 + struct platform_device *pPlatformDev;
5673 +#endif
5674 int retval;
5675
5676 retval = xhci_register_pci();
5677 @@ -4769,6 +4936,33 @@ static int __init xhci_hcd_init(void)
5678 printk(KERN_DEBUG "Problem registering platform driver.");
5679 goto unreg_pci;
5680 }
5681 +
5682 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5683 + retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5684 +
5685 + u3phy_init();
5686 + if (u3phy_ops->u2_slew_rate_calibration) {
5687 + u3phy_ops->u2_slew_rate_calibration(u3phy);
5688 + u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5689 + }
5690 + else{
5691 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5692 + }
5693 + u3phy_ops->init(u3phy);
5694 + reinitIP();
5695 +
5696 + pPlatformDev = &xhci_platform_dev;
5697 + memset(pPlatformDev, 0, sizeof(struct platform_device));
5698 + pPlatformDev->name = "xhci-hcd";
5699 + pPlatformDev->id = -1;
5700 + pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5701 + pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5702 +
5703 + retval = platform_device_register(&xhci_platform_dev);
5704 + if (retval < 0)
5705 + xhci_unregister_plat();
5706 +#endif
5707 +
5708 /*
5709 * Check the compiler generated sizes of structures that must be laid
5710 * out in specific ways for hardware access.
5711 @@ -4786,6 +4980,7 @@ static int __init xhci_hcd_init(void)
5712 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5713 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5714 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5715 +
5716 return 0;
5717 unreg_pci:
5718 xhci_unregister_pci();
5719 --- a/drivers/usb/host/xhci.h
5720 +++ b/drivers/usb/host/xhci.h
5721 @@ -29,9 +29,24 @@
5722 #include <linux/usb/hcd.h>
5723
5724 /* Code sharing between pci-quirks and xhci hcd */
5725 -#include "xhci-ext-caps.h"
5726 +#include "xhci-ext-caps.h"
5727 #include "pci-quirks.h"
5728
5729 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5730 +#define XHC_IRQ (22 + 8)
5731 +#define XHC_IO_START 0x1E1C0000
5732 +#define XHC_IO_LENGTH 0x10000
5733 +/* mtk scheduler bitmasks */
5734 +#define BPKTS(p) ((p) & 0x3f)
5735 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
5736 +#define BBM(p) ((p) << 11)
5737 +#define BOFFSET(p) ((p) & 0x3fff)
5738 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
5739 +#endif
5740 +
5741 +
5742 +
5743 +
5744 /* xHCI PCI Configuration Registers */
5745 #define XHCI_SBRN_OFFSET (0x60)
5746
5747 @@ -1536,8 +1551,12 @@ struct xhci_hcd {
5748 /* Compliance Mode Recovery Data */
5749 struct timer_list comp_mode_recovery_timer;
5750 u32 port_status_u0;
5751 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5752 +#define COMP_MODE_RCVRY_MSECS 5000
5753 +#else
5754 /* Compliance Mode Timer Triggered every 2 seconds */
5755 #define COMP_MODE_RCVRY_MSECS 2000
5756 +#endif
5757 };
5758
5759 /* convert between an HCD pointer and the corresponding EHCI_HCD */
5760 @@ -1703,7 +1722,7 @@ void xhci_urb_free_priv(struct xhci_hcd
5761 void xhci_free_command(struct xhci_hcd *xhci,
5762 struct xhci_command *command);
5763
5764 -#ifdef CONFIG_PCI
5765 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5766 /* xHCI PCI glue */
5767 int xhci_register_pci(void);
5768 void xhci_unregister_pci(void);
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