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[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.10 / 0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
1 From 6e10c9b7ab93cb105dc2779769c48949ebc60ee7 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 08:51:14 +0000
4 Subject: [PATCH 1/3] foo
5
6 ---
7 drivers/net/ethernet/raeth/Kconfig | 343 +++++++
8 drivers/net/ethernet/raeth/Makefile | 7 +
9 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
10 drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
11 drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
12 drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
13 drivers/net/ethernet/raeth/ra_mac.c | 93 ++
14 drivers/net/ethernet/raeth/ra_mac.h | 35 +
15 drivers/net/ethernet/raeth/raether.c | 663 +++++++++++++
16 drivers/net/ethernet/raeth/raether.h | 92 ++
17 drivers/net/ethernet/raeth/raether_pdma.c | 202 ++++
18 drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.c | 15 +-
20 drivers/net/ethernet/ralink/mt7530.c | 2 +-
21 drivers/net/ethernet/ralink/mt7621.c | 253 +++++
22 drivers/net/ethernet/ralink/mt762x.c | 295 ++++++
23 drivers/net/ethernet/ralink/mt762x.h | 38 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 25 +-
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 9 +-
26 drivers/net/ethernet/ralink/soc_mt7621.c | 5 +-
27 20 files changed, 4429 insertions(+), 23 deletions(-)
28 create mode 100644 drivers/net/ethernet/raeth/Kconfig
29 create mode 100644 drivers/net/ethernet/raeth/Makefile
30 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
31 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
32 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
33 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
34 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
35 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
36 create mode 100644 drivers/net/ethernet/raeth/raether.c
37 create mode 100644 drivers/net/ethernet/raeth/raether.h
38 create mode 100755 drivers/net/ethernet/raeth/raether_pdma.c
39 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
40 create mode 100644 drivers/net/ethernet/ralink/mt7621.c
41 create mode 100644 drivers/net/ethernet/ralink/mt762x.c
42 create mode 100644 drivers/net/ethernet/ralink/mt762x.h
43
44 --- /dev/null
45 +++ b/drivers/net/ethernet/raeth/Kconfig
46 @@ -0,0 +1,344 @@
47 +
48 +config RA_NAT_NONE
49 + bool
50 + default y
51 + depends on RALINK
52 +
53 +config MT7621_ASIC
54 + bool
55 + default y
56 + depends on SOC_MT7621
57 +
58 +config RALINK_MT7621
59 + bool
60 + default y
61 + depends on SOC_MT7621
62 +
63 +config RAETH
64 + tristate "Ralink GMAC"
65 + depends on SOC_MT7621
66 + ---help---
67 + This driver supports Ralink gigabit ethernet family of
68 + adapters.
69 +
70 +config PDMA_NEW
71 + bool
72 + default y if (RALINK_MT7620 || RALINK_MT7621)
73 + depends on RAETH
74 +
75 +config RAETH_SCATTER_GATHER_RX_DMA
76 + bool
77 + default y if (RALINK_MT7620 || RALINK_MT7621)
78 + depends on RAETH
79 +
80 +
81 +choice
82 + prompt "Network BottomHalves"
83 + depends on RAETH
84 + default RA_NETWORK_WORKQUEUE_BH
85 +
86 + config RA_NETWORK_TASKLET_BH
87 + bool "Tasklet"
88 +
89 + config RA_NETWORK_WORKQUEUE_BH
90 + bool "Work Queue"
91 +
92 + config RAETH_NAPI
93 + bool "NAPI"
94 +
95 +endchoice
96 +
97 +#config TASKLET_WORKQUEUE_SW
98 +# bool "Tasklet and Workqueue switch"
99 +# depends on RA_NETWORK_TASKLET_BH
100 +
101 +config RAETH_SKB_RECYCLE_2K
102 + bool "SKB Recycling"
103 + depends on RAETH
104 +
105 +config RAETH_SPECIAL_TAG
106 + bool "Ralink Special Tag (0x810x)"
107 + depends on RAETH && RT_3052_ESW
108 +
109 +#config RAETH_JUMBOFRAME
110 +# bool "Jumbo Frame up to 4K bytes"
111 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
112 +
113 +config RAETH_CHECKSUM_OFFLOAD
114 + bool "TCP/UDP/IP checksum offload"
115 + default y
116 + depends on RAETH && !RALINK_RT2880
117 +
118 +#config RAETH_SW_FC
119 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
120 +# default n
121 +# depends on RAETH
122 +
123 +config 32B_DESC
124 + bool "32bytes TX/RX description"
125 + default n
126 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
127 + ---help---
128 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
129 +
130 +config RAETH_LRO
131 + bool "LRO (Large Receive Offload )"
132 + select INET_LRO
133 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
134 +
135 +config RAETH_HW_VLAN_TX
136 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
137 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
138 + ---help---
139 + Please disable HW_VLAN_TX if you need double vlan
140 +
141 +config RAETH_HW_VLAN_RX
142 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
143 + depends on RAETH && RALINK_MT7621
144 + ---help---
145 + Please disable HW_VLAN_RX if you need double vlan
146 +
147 +config RAETH_TSO
148 + bool "TSOV4 (Tcp Segmentaton Offload)"
149 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
150 +
151 +config RAETH_TSOV6
152 + bool "TSOV6 (Tcp Segmentaton Offload)"
153 + depends on RAETH_TSO
154 +
155 +config RAETH_RW_PDMAPTR_FROM_VAR
156 + bool
157 + default y if RALINK_RT6855A || RALINK_MT7620
158 + depends on RAETH
159 +
160 +#config RAETH_QOS
161 +# bool "QoS Feature"
162 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
163 +
164 +choice
165 + prompt "QoS Type"
166 + depends on RAETH_QOS
167 + default DSCP_QOS_DSCP
168 +
169 +config RAETH_QOS_DSCP_BASED
170 + bool "DSCP-based"
171 + depends on RAETH_QOS
172 +
173 +config RAETH_QOS_VPRI_BASED
174 + bool "VPRI-based"
175 + depends on RAETH_QOS
176 +
177 +endchoice
178 +
179 +config RAETH_QDMA
180 + bool "Choose QDMA instead PDMA"
181 + default n
182 + depends on RAETH && RALINK_MT7621
183 +
184 +choice
185 + prompt "GMAC is connected to"
186 + depends on RAETH
187 + default GE1_RGMII_FORCE_1000
188 +
189 +config GE1_MII_FORCE_100
190 + bool "MII_FORCE_100 (10/100M Switch)"
191 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
192 +
193 +config GE1_MII_AN
194 + bool "MII_AN (100Phy)"
195 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
196 +
197 +config GE1_RVMII_FORCE_100
198 + bool "RvMII_FORCE_100 (CPU)"
199 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
200 +
201 +config GE1_RGMII_FORCE_1000
202 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
203 + depends on (RALINK_RT2880 || RALINK_RT3883)
204 + select RALINK_SPI
205 +
206 +config GE1_RGMII_FORCE_1000
207 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
208 + depends on (RALINK_MT7621)
209 + select RT_3052_ESW
210 +
211 +config GE1_TRGMII_FORCE_1200
212 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
213 + depends on (RALINK_MT7621)
214 + select RT_3052_ESW
215 +
216 +config GE1_RGMII_AN
217 + bool "RGMII_AN (GigaPhy)"
218 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
219 +
220 +config GE1_RGMII_NONE
221 + bool "NONE (NO CONNECT)"
222 + depends on (RALINK_MT7621)
223 +
224 +endchoice
225 +
226 +config RT_3052_ESW
227 + bool "Ralink Embedded Switch"
228 + default y
229 + depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
230 +
231 +config LAN_WAN_SUPPORT
232 + bool "LAN/WAN Partition"
233 + depends on RAETH_ROUTER || RT_3052_ESW
234 +
235 +choice
236 + prompt "Switch Board Layout Type"
237 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
238 + default WAN_AT_P0
239 +
240 + config WAN_AT_P4
241 + bool "LLLL/W"
242 +
243 + config WAN_AT_P0
244 + bool "W/LLLL"
245 +endchoice
246 +
247 +config RALINK_VISTA_BASIC
248 + bool 'Vista Basic Logo for IC+ 175C'
249 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
250 +
251 +config ESW_DOUBLE_VLAN_TAG
252 + bool
253 + default y if RT_3052_ESW
254 +
255 +config RAETH_HAS_PORT4
256 + bool "Port 4 Support"
257 + depends on RAETH && RALINK_MT7620
258 +choice
259 + prompt "Target Mode"
260 + depends on RAETH_HAS_PORT4
261 + default P4_RGMII_TO_MAC_MODE
262 +
263 + config P4_MAC_TO_PHY_MODE
264 + bool "Giga_Phy (RGMII)"
265 + config GE_RGMII_MT7530_P0_AN
266 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
267 + config GE_RGMII_MT7530_P4_AN
268 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
269 + config P4_RGMII_TO_MAC_MODE
270 + bool "Giga_SW/iNIC (RGMII)"
271 + config P4_MII_TO_MAC_MODE
272 + bool "External_CPU (MII_RvMII)"
273 + config P4_RMII_TO_MAC_MODE
274 + bool "External_CPU (RvMII_MII)"
275 +endchoice
276 +
277 +config MAC_TO_GIGAPHY_MODE_ADDR2
278 + hex "Port4 Phy Address"
279 + default 0x4
280 + depends on P4_MAC_TO_PHY_MODE
281 +
282 +config RAETH_HAS_PORT5
283 + bool "Port 5 Support"
284 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
285 +choice
286 + prompt "Target Mode"
287 + depends on RAETH_HAS_PORT5
288 + default P5_RGMII_TO_MAC_MODE
289 +
290 + config P5_MAC_TO_PHY_MODE
291 + bool "Giga_Phy (RGMII)"
292 + config P5_RGMII_TO_MAC_MODE
293 + bool "Giga_SW/iNIC (RGMII)"
294 + config P5_RGMII_TO_MT7530_MODE
295 + bool "MT7530 Giga_SW (RGMII)"
296 + depends on RALINK_MT7620
297 + config P5_MII_TO_MAC_MODE
298 + bool "External_CPU (MII_RvMII)"
299 + config P5_RMII_TO_MAC_MODE
300 + bool "External_CPU (RvMII_MII)"
301 +endchoice
302 +
303 +config MAC_TO_GIGAPHY_MODE_ADDR
304 + hex "GE1 Phy Address"
305 + default 0x1F
306 + depends on GE1_MII_AN || GE1_RGMII_AN
307 +
308 +config MAC_TO_GIGAPHY_MODE_ADDR
309 + hex "Port5 Phy Address"
310 + default 0x5
311 + depends on P5_MAC_TO_PHY_MODE
312 +
313 +config RAETH_GMAC2
314 + bool "GMAC2 Support"
315 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
316 +
317 +choice
318 + prompt "GMAC2 is connected to"
319 + depends on RAETH_GMAC2
320 + default GE2_RGMII_AN
321 +
322 +config GE2_MII_FORCE_100
323 + bool "MII_FORCE_100 (10/100M Switch)"
324 + depends on RAETH_GMAC2
325 +
326 +config GE2_MII_AN
327 + bool "MII_AN (100Phy)"
328 + depends on RAETH_GMAC2
329 +
330 +config GE2_RVMII_FORCE_100
331 + bool "RvMII_FORCE_100 (CPU)"
332 + depends on RAETH_GMAC2
333 +
334 +config GE2_RGMII_FORCE_1000
335 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
336 + depends on RAETH_GMAC2
337 + select RALINK_SPI
338 +
339 +config GE2_RGMII_AN
340 + bool "RGMII_AN (GigaPhy)"
341 + depends on RAETH_GMAC2
342 +
343 +config GE2_INTERNAL_GPHY
344 + bool "Internal GigaPHY"
345 + depends on RAETH_GMAC2
346 + select LAN_WAN_SUPPORT
347 +
348 +endchoice
349 +
350 +config GE_RGMII_INTERNAL_P0_AN
351 + bool
352 + depends on GE2_INTERNAL_GPHY
353 + default y if WAN_AT_P0
354 +
355 +config GE_RGMII_INTERNAL_P4_AN
356 + bool
357 + depends on GE2_INTERNAL_GPHY
358 + default y if WAN_AT_P4
359 +
360 +config MAC_TO_GIGAPHY_MODE_ADDR2
361 + hex
362 + default 0 if GE_RGMII_INTERNAL_P0_AN
363 + default 4 if GE_RGMII_INTERNAL_P4_AN
364 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
365 +
366 +config MAC_TO_GIGAPHY_MODE_ADDR2
367 + hex "GE2 Phy Address"
368 + default 0x1E
369 + depends on GE2_MII_AN || GE2_RGMII_AN
370 +
371 +#force 100M
372 +config RAETH_ROUTER
373 +bool
374 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
375 +
376 +#force 1000M
377 +config MAC_TO_MAC_MODE
378 +bool
379 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
380 +depends on (RALINK_RT2880 || RALINK_RT3883)
381 +
382 +#AN
383 +config GIGAPHY
384 +bool
385 +default y if GE1_RGMII_AN || GE2_RGMII_AN
386 +
387 +#AN
388 +config 100PHY
389 +bool
390 +default y if GE1_MII_AN || GE2_MII_AN
391 --- /dev/null
392 +++ b/drivers/net/ethernet/raeth/Makefile
393 @@ -0,0 +1,7 @@
394 +obj-$(CONFIG_RAETH) += raeth.o
395 +raeth-objs := ra_mac.o mii_mgr.o
396 +raeth-objs += raether_pdma.o
397 +EXTRA_CFLAGS += -DWORKQUEUE_BH
398 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
399 +
400 +raeth-objs += raether.o
401 --- /dev/null
402 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
403 @@ -0,0 +1,44 @@
404 +
405 +Ethtool readme for selecting different PHY address.
406 +
407 +Before doing any ethtool command you should make sure the current PHY
408 +address is expected. The default PHY address is 1(port 1).
409 +
410 +You can change current PHY address to X(0~4) by doing follow command:
411 +# echo X > /proc/rt2880/gmac
412 +
413 +Ethtool command also would show the current PHY address as following.
414 +
415 +# ethtool eth2
416 +Settings for eth2:
417 + Supported ports: [ TP MII ]
418 + Supported link modes: 10baseT/Half 10baseT/Full
419 + 100baseT/Half 100baseT/Full
420 + Supports auto-negotiation: Yes
421 + Advertised link modes: 10baseT/Half 10baseT/Full
422 + 100baseT/Half 100baseT/Full
423 + Advertised auto-negotiation: No
424 + Speed: 10Mb/s
425 + Duplex: Full
426 + Port: MII
427 + PHYAD: 1
428 + Transceiver: internal
429 + Auto-negotiation: off
430 + Current message level: 0x00000000 (0)
431 + Link detected: no
432 +
433 +
434 +The "PHYAD" field shows the current PHY address.
435 +
436 +
437 +
438 +Usage example
439 +1) show port1 info
440 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
441 +# ethtool eth2
442 +
443 +2) show port0 info
444 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
445 +# ethtool eth2
446 +
447 +
448 --- /dev/null
449 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
450 @@ -0,0 +1,166 @@
451 +#include <linux/module.h>
452 +#include <linux/version.h>
453 +#include <linux/netdevice.h>
454 +
455 +#include <linux/kernel.h>
456 +#include <linux/sched.h>
457 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
458 +#include <asm/rt2880/rt_mmap.h>
459 +#endif
460 +
461 +#include "ra2882ethreg.h"
462 +#include "raether.h"
463 +
464 +
465 +#define PHY_CONTROL_0 0x0004
466 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
467 +#define enable_mdio(x)
468 +
469 +
470 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
471 +{
472 + u32 volatile status = 0;
473 + u32 rc = 0;
474 + unsigned long volatile t_start = jiffies;
475 + u32 volatile data = 0;
476 +
477 + /* We enable mdio gpio purpose register, and disable it when exit. */
478 + enable_mdio(1);
479 +
480 + // make sure previous read operation is complete
481 + while (1) {
482 + // 0 : Read/write operation complete
483 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
484 + {
485 + break;
486 + }
487 + else if (time_after(jiffies, t_start + 5*HZ)) {
488 + enable_mdio(0);
489 + printk("\n MDIO Read operation is ongoing !!\n");
490 + return rc;
491 + }
492 + }
493 +
494 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
495 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
496 + data |= (1<<31);
497 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
498 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
499 +
500 +
501 + // make sure read operation is complete
502 + t_start = jiffies;
503 + while (1) {
504 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
505 + status = sysRegRead(MDIO_PHY_CONTROL_0);
506 + *read_data = (u32)(status & 0x0000FFFF);
507 +
508 + enable_mdio(0);
509 + return 1;
510 + }
511 + else if (time_after(jiffies, t_start+5*HZ)) {
512 + enable_mdio(0);
513 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
514 + return 0;
515 + }
516 + }
517 +}
518 +
519 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
520 +{
521 + unsigned long volatile t_start=jiffies;
522 + u32 volatile data;
523 +
524 + enable_mdio(1);
525 +
526 + // make sure previous write operation is complete
527 + while(1) {
528 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
529 + {
530 + break;
531 + }
532 + else if (time_after(jiffies, t_start + 5 * HZ)) {
533 + enable_mdio(0);
534 + printk("\n MDIO Write operation ongoing\n");
535 + return 0;
536 + }
537 + }
538 + /*add 1 us delay to make sequencial write more robus*/
539 + udelay(1);
540 +
541 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
542 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
543 + data |= (1<<31);
544 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
545 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
546 +
547 + t_start = jiffies;
548 +
549 + // make sure write operation is complete
550 + while (1) {
551 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
552 + {
553 + enable_mdio(0);
554 + return 1;
555 + }
556 + else if (time_after(jiffies, t_start + 5 * HZ)) {
557 + enable_mdio(0);
558 + printk("\n MDIO Write operation Time Out\n");
559 + return 0;
560 + }
561 + }
562 +}
563 +
564 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
565 +{
566 + u32 low_word;
567 + u32 high_word;
568 + if(phy_addr==31)
569 + {
570 + //phase1: write page address phase
571 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
572 + //phase2: write address & read low word phase
573 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
574 + //phase3: write address & read high word phase
575 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
576 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
577 + return 1;
578 + }
579 + }
580 + }
581 + } else
582 + {
583 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
584 + return 1;
585 + }
586 + }
587 +
588 + return 0;
589 +}
590 +
591 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
592 +{
593 + if(phy_addr == 31)
594 + {
595 + //phase1: write page address phase
596 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
597 + //phase2: write address & read low word phase
598 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
599 + //phase3: write address & read high word phase
600 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
601 + return 1;
602 + }
603 + }
604 + }
605 + } else
606 + {
607 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
608 + return 1;
609 + }
610 + }
611 +
612 + return 0;
613 +}
614 +
615 +EXPORT_SYMBOL(mii_mgr_write);
616 +EXPORT_SYMBOL(mii_mgr_read);
617 --- /dev/null
618 +++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
619 @@ -0,0 +1,1268 @@
620 +#ifndef RA2882ETHREG_H
621 +#define RA2882ETHREG_H
622 +
623 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
624 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
625 +
626 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
627 +#include <asm/rt2880/rt_mmap.h>
628 +#endif
629 +#include "raether.h"
630 +
631 +#ifdef WORKQUEUE_BH
632 +#include <linux/workqueue.h>
633 +#endif // WORKQUEUE_BH //
634 +#ifdef CONFIG_RAETH_LRO
635 +#include <linux/inet_lro.h>
636 +#endif
637 +
638 +#define MAX_PACKET_SIZE 1514
639 +#define MIN_PACKET_SIZE 60
640 +
641 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
642 +
643 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
644 +#define BIT(x) ((1 << x))
645 +#endif
646 +#define ETHER_ADDR_LEN 6
647 +
648 +/* Phy Vender ID list */
649 +
650 +#define EV_ICPLUS_PHY_ID0 0x0243
651 +#define EV_ICPLUS_PHY_ID1 0x0D90
652 +#define EV_MARVELL_PHY_ID0 0x0141
653 +#define EV_MARVELL_PHY_ID1 0x0CC2
654 +#define EV_VTSS_PHY_ID0 0x0007
655 +#define EV_VTSS_PHY_ID1 0x0421
656 +
657 +/*
658 + FE_INT_STATUS
659 +*/
660 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
661 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
662 +
663 +#define RX_COHERENT BIT(31)
664 +#define RX_DLY_INT BIT(30)
665 +#define TX_COHERENT BIT(29)
666 +#define TX_DLY_INT BIT(28)
667 +
668 +#define RX_DONE_INT1 BIT(17)
669 +#define RX_DONE_INT0 BIT(16)
670 +
671 +#define TX_DONE_INT3 BIT(3)
672 +#define TX_DONE_INT2 BIT(2)
673 +#define TX_DONE_INT1 BIT(1)
674 +#define TX_DONE_INT0 BIT(0)
675 +
676 +#if defined (CONFIG_RALINK_MT7621)
677 +#define RLS_COHERENT BIT(29)
678 +#define RLS_DLY_INT BIT(28)
679 +#define RLS_DONE_INT BIT(0)
680 +#endif
681 +
682 +#else
683 +//#define CNT_PPE_AF BIT(31)
684 +//#define CNT_GDM_AF BIT(29)
685 +#define PSE_P2_FC BIT(26)
686 +#define GDM_CRC_DROP BIT(25)
687 +#define PSE_BUF_DROP BIT(24)
688 +#define GDM_OTHER_DROP BIT(23)
689 +#define PSE_P1_FC BIT(22)
690 +#define PSE_P0_FC BIT(21)
691 +#define PSE_FQ_EMPTY BIT(20)
692 +#define GE1_STA_CHG BIT(18)
693 +#define TX_COHERENT BIT(17)
694 +#define RX_COHERENT BIT(16)
695 +
696 +#define TX_DONE_INT3 BIT(11)
697 +#define TX_DONE_INT2 BIT(10)
698 +#define TX_DONE_INT1 BIT(9)
699 +#define TX_DONE_INT0 BIT(8)
700 +#define RX_DONE_INT1 RX_DONE_INT0
701 +#define RX_DONE_INT0 BIT(2)
702 +#define TX_DLY_INT BIT(1)
703 +#define RX_DLY_INT BIT(0)
704 +#endif
705 +
706 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
707 + TX_DONE_INT1 | TX_DONE_INT0 | \
708 + RX_DONE_INT0 )
709 +
710 +#if defined (CONFIG_RALINK_MT7621)
711 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
712 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
713 +
714 +#define NUM_QDMA_PAGE 256
715 +#define QDMA_PAGE_SIZE 2048
716 +#endif
717 +/*
718 + * SW_INT_STATUS
719 + */
720 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
721 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
722 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
723 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
724 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
725 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
726 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
727 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
728 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
729 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
730 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
731 +#define PORT_ST_CHG BIT(26) //Port status change
732 +#define UNSECURED_ALERT BIT(27) //Intruder alert
733 +#define ABNORMAL_ALERT BIT(28) //Abnormal
734 +
735 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
736 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
737 +#define ESW_INT_ALL (PORT_ST_CHG)
738 +
739 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
740 + defined (CONFIG_RALINK_MT7620)
741 +#define MIB_INT BIT(25)
742 +#define ACL_INT BIT(24)
743 +#define P5_LINK_CH BIT(5)
744 +#define P4_LINK_CH BIT(4)
745 +#define P3_LINK_CH BIT(3)
746 +#define P2_LINK_CH BIT(2)
747 +#define P1_LINK_CH BIT(1)
748 +#define P0_LINK_CH BIT(0)
749 +
750 +#define RX_GOCT_CNT BIT(4)
751 +#define RX_GOOD_CNT BIT(6)
752 +#define TX_GOCT_CNT BIT(17)
753 +#define TX_GOOD_CNT BIT(19)
754 +
755 +#define MSK_RX_GOCT_CNT BIT(4)
756 +#define MSK_RX_GOOD_CNT BIT(6)
757 +#define MSK_TX_GOCT_CNT BIT(17)
758 +#define MSK_TX_GOOD_CNT BIT(19)
759 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
760 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
761 +
762 +
763 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
764 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
765 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
766 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
767 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
768 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
769 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
770 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
771 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
772 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
773 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
774 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
775 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
776 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
777 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
778 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
779 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
780 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
781 +
782 +#if defined (CONFIG_RALINK_MT7620)
783 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
784 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
785 +#endif
786 +
787 +
788 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
789 +
790 +#elif defined (CONFIG_RALINK_MT7621)
791 +
792 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
793 +
794 +#define P5_LINK_CH BIT(5)
795 +#define P4_LINK_CH BIT(4)
796 +#define P3_LINK_CH BIT(3)
797 +#define P2_LINK_CH BIT(2)
798 +#define P1_LINK_CH BIT(1)
799 +#define P0_LINK_CH BIT(0)
800 +
801 +
802 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
803 +
804 +#define RX_BUF_ALLOC_SIZE 2000
805 +#define FASTPATH_HEADROOM 64
806 +
807 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
808 +
809 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
810 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
811 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
812 +
813 +#ifdef CONFIG_PSEUDO_SUPPORT
814 +typedef struct _PSEUDO_ADAPTER {
815 + struct net_device *RaethDev;
816 + struct net_device *PseudoDev;
817 + struct net_device_stats stat;
818 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
819 + struct mii_if_info mii_info;
820 +#endif
821 +
822 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
823 +
824 +#define MAX_PSEUDO_ENTRY 1
825 +#endif
826 +
827 +
828 +
829 +/* Register Categories Definition */
830 +#define RAFRAMEENGINE_OFFSET 0x0000
831 +#define RAGDMA_OFFSET 0x0020
832 +#define RAPSE_OFFSET 0x0040
833 +#define RAGDMA2_OFFSET 0x0060
834 +#define RACDMA_OFFSET 0x0080
835 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
836 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
837 +
838 +#define RAPDMA_OFFSET 0x0800
839 +#define SDM_OFFSET 0x0C00
840 +#else
841 +#define RAPDMA_OFFSET 0x0100
842 +#endif
843 +#define RAPPE_OFFSET 0x0200
844 +#define RACMTABLE_OFFSET 0x0400
845 +#define RAPOLICYTABLE_OFFSET 0x1000
846 +
847 +
848 +/* Register Map Detail */
849 +/* RT3883 */
850 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
851 +
852 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
853 +
854 +/* 1. PDMA */
855 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
856 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
857 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
858 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
859 +
860 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
861 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
862 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
863 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
864 +
865 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
866 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
867 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
868 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
869 +
870 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
871 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
872 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
873 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
874 +
875 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
876 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
877 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
878 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
879 +
880 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
881 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
882 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
883 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
884 +
885 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
886 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
887 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
888 +#define PDMA_RST_CFG (PDMA_RST_IDX)
889 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
890 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
891 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
892 +#define FE_INT_STATUS (INT_STATUS)
893 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
894 +#define FE_INT_ENABLE (INT_MASK)
895 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
896 +#define PDMA_SCH_CFG (PDMA_WRR)
897 +
898 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
899 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
900 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
901 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
902 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
903 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
904 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
905 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
906 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
907 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
908 +
909 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
910 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
911 +
912 +/* Old FE with New PDMA */
913 +#define PDMA_RELATED 0x0800
914 +/* 1. PDMA */
915 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
916 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
917 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
918 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
919 +
920 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
921 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
922 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
923 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
924 +
925 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
926 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
927 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
928 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
929 +
930 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
931 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
932 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
933 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
934 +
935 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
936 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
937 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
938 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
939 +
940 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
941 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
942 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
943 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
944 +
945 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
946 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
947 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
948 +#define PDMA_RST_CFG (PDMA_RST_IDX)
949 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
950 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
951 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
952 +#define FE_INT_STATUS (INT_STATUS)
953 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
954 +#define FE_INT_ENABLE (INT_MASK)
955 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
956 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
957 +
958 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
959 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
960 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
961 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
962 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
963 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
964 +
965 +#if defined (CONFIG_RALINK_MT7620)
966 +#define GDMA1_RELATED 0x0600
967 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
968 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
969 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
970 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
971 +#elif defined (CONFIG_RALINK_MT7621)
972 +#define GDMA1_RELATED 0x0500
973 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
974 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
975 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
976 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
977 +
978 +#define GDMA2_RELATED 0x1500
979 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
980 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
981 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
982 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
983 +#else
984 +#define GDMA1_RELATED 0x0020
985 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
986 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
987 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
988 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
989 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
990 +
991 +#define GDMA2_RELATED 0x0060
992 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
993 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
994 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
995 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
996 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
997 +#endif
998 +
999 +#if defined (CONFIG_RALINK_MT7620)
1000 +#define PSE_RELATED 0x0500
1001 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
1002 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
1003 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
1004 +#else
1005 +#define PSE_RELATED 0x0040
1006 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
1007 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
1008 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
1009 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
1010 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
1011 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
1012 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
1013 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
1014 +#endif
1015 +
1016 +
1017 +#if defined (CONFIG_RALINK_MT7620)
1018 +#define CDMA_RELATED 0x0400
1019 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
1020 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
1021 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
1022 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
1023 +#elif defined (CONFIG_RALINK_MT7621)
1024 +#define CDMA_RELATED 0x0400
1025 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
1026 +#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
1027 +#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
1028 +#else
1029 +#define CDMA_RELATED 0x0080
1030 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
1031 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
1032 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
1033 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
1034 +#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
1035 +#endif
1036 +
1037 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
1038 +
1039 +
1040 +#if defined (CONFIG_RALINK_MT7621)
1041 +/*kurtis: add QDMA define*/
1042 +
1043 +#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
1044 +#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
1045 +
1046 +#define QDMA_RELATED 0x1800
1047 +#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
1048 +#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
1049 +#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
1050 +#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
1051 +#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
1052 +#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
1053 +#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
1054 +#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
1055 +#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
1056 +#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
1057 +#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
1058 +#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
1059 +#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
1060 +#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
1061 +#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
1062 +#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
1063 +#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
1064 +#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
1065 +#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
1066 +#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
1067 +#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
1068 +#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
1069 +#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
1070 +#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
1071 +#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
1072 +#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
1073 +#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
1074 +#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
1075 +#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
1076 +#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
1077 +#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
1078 +#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
1079 +#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
1080 +#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
1081 +#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
1082 +#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
1083 +#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
1084 +#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
1085 +#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
1086 +#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
1087 +#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
1088 +#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
1089 +#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
1090 +#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
1091 +#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
1092 +#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
1093 +#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
1094 +#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
1095 +#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
1096 +#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
1097 +#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
1098 +#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
1099 +#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
1100 +#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
1101 +#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
1102 +#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
1103 +#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
1104 +#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
1105 +#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
1106 +#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
1107 +#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
1108 +#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
1109 +#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
1110 +#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
1111 +#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
1112 +#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
1113 +#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
1114 +#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
1115 +#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
1116 +#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
1117 +#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
1118 +#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
1119 +#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
1120 +#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
1121 +#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
1122 +#define QDMA_RST_CFG (QDMA_RST_IDX)
1123 +#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
1124 +#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
1125 +#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
1126 +#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
1127 +#define QFE_INT_STATUS (QDMA_INT_STS)
1128 +#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
1129 +#define QFE_INT_ENABLE (QDMA_INT_MASK)
1130 +#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
1131 +#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
1132 +#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
1133 +#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
1134 +#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
1135 +#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
1136 +#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
1137 +#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
1138 +#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
1139 +#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
1140 +#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
1141 +#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
1142 +#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
1143 +#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
1144 +#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
1145 +#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
1146 +#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
1147 +#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
1148 +#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
1149 +#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
1150 +#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
1151 +#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
1152 +#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
1153 +#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
1154 +#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
1155 +#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
1156 +#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
1157 +#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
1158 +#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
1159 +
1160 +
1161 +#endif/*MT7621 QDMA*/
1162 +
1163 +#else
1164 +
1165 +/* 1. Frame Engine Global Registers */
1166 +#define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
1167 +#define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
1168 +#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
1169 +#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
1170 +#define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
1171 +#define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
1172 +#define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
1173 +#define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
1174 +
1175 +
1176 +/* 2. GDMA Registers */
1177 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
1178 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
1179 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
1180 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
1181 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
1182 +
1183 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
1184 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
1185 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
1186 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
1187 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
1188 +
1189 +/* 3. PSE */
1190 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
1191 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
1192 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
1193 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
1194 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0)
1195 +
1196 +/* 4. CDMA */
1197 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
1198 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
1199 +/* skip ppoe sid and vlan id definition */
1200 +
1201 +
1202 +/* 5. PDMA */
1203 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
1204 +#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
1205 +#define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
1206 +
1207 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
1208 +
1209 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
1210 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
1211 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
1212 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
1213 +
1214 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
1215 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
1216 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
1217 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
1218 +
1219 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
1220 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
1221 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
1222 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
1223 +
1224 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
1225 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
1226 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
1227 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
1228 +
1229 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
1230 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
1231 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
1232 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
1233 +
1234 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
1235 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
1236 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
1237 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
1238 +
1239 +#endif
1240 +
1241 +#define DELAY_INT_INIT 0x84048404
1242 +#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
1243 +
1244 +
1245 +#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
1246 +
1247 +/* 6. Counter and Meter Table */
1248 +#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
1249 +#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
1250 +/* 0 ~ 63 */
1251 +
1252 +#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
1253 +/* skip... */
1254 +#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
1255 +
1256 +#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
1257 +#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
1258 +#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
1259 +#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
1260 +
1261 +/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
1262 +#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
1263 +#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
1264 +#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
1265 +#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
1266 +#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
1267 +#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
1268 +#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
1269 +#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
1270 +
1271 +#endif
1272 +
1273 +
1274 +/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
1275 +#define PORT0_PKCOUNT (0xb01100e8)
1276 +#define PORT1_PKCOUNT (0xb01100ec)
1277 +#define PORT2_PKCOUNT (0xb01100f0)
1278 +#define PORT3_PKCOUNT (0xb01100f4)
1279 +#define PORT4_PKCOUNT (0xb01100f8)
1280 +#define PORT5_PKCOUNT (0xb01100fc)
1281 +
1282 +
1283 +// PHYS_TO_K1
1284 +#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
1285 +
1286 +
1287 +#define sysRegRead(phys) \
1288 + (*(volatile unsigned int *)PHYS_TO_K1(phys))
1289 +
1290 +#define sysRegWrite(phys, val) \
1291 + ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
1292 +
1293 +#define u_long unsigned long
1294 +#define u32 unsigned int
1295 +#define u16 unsigned short
1296 +
1297 +
1298 +/* ====================================== */
1299 +#define GDM1_DISPAD BIT(18)
1300 +#define GDM1_DISCRC BIT(17)
1301 +
1302 +//GDMA1 uni-cast frames destination port
1303 +#define GDM1_ICS_EN (0x1 << 22)
1304 +#define GDM1_TCS_EN (0x1 << 21)
1305 +#define GDM1_UCS_EN (0x1 << 20)
1306 +#define GDM1_JMB_EN (0x1 << 19)
1307 +#define GDM1_STRPCRC (0x1 << 16)
1308 +#define GDM1_UFRC_P_CPU (0 << 12)
1309 +#if defined (CONFIG_RALINK_MT7621)
1310 +#define GDM1_UFRC_P_PPE (4 << 12)
1311 +#else
1312 +#define GDM1_UFRC_P_PPE (6 << 12)
1313 +#endif
1314 +
1315 +//GDMA1 broad-cast MAC address frames
1316 +#define GDM1_BFRC_P_CPU (0 << 8)
1317 +#if defined (CONFIG_RALINK_MT7621)
1318 +#define GDM1_BFRC_P_PPE (4 << 8)
1319 +#else
1320 +#define GDM1_BFRC_P_PPE (6 << 8)
1321 +#endif
1322 +
1323 +//GDMA1 multi-cast MAC address frames
1324 +#define GDM1_MFRC_P_CPU (0 << 4)
1325 +#if defined (CONFIG_RALINK_MT7621)
1326 +#define GDM1_MFRC_P_PPE (4 << 4)
1327 +#else
1328 +#define GDM1_MFRC_P_PPE (6 << 4)
1329 +#endif
1330 +
1331 +//GDMA1 other MAC address frames destination port
1332 +#define GDM1_OFRC_P_CPU (0 << 0)
1333 +#if defined (CONFIG_RALINK_MT7621)
1334 +#define GDM1_OFRC_P_PPE (4 << 0)
1335 +#else
1336 +#define GDM1_OFRC_P_PPE (6 << 0)
1337 +#endif
1338 +
1339 +#if defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
1340 +/* checksum generator registers are removed */
1341 +#define ICS_GEN_EN (0 << 2)
1342 +#define UCS_GEN_EN (0 << 1)
1343 +#define TCS_GEN_EN (0 << 0)
1344 +#else
1345 +#define ICS_GEN_EN (1 << 2)
1346 +#define UCS_GEN_EN (1 << 1)
1347 +#define TCS_GEN_EN (1 << 0)
1348 +#endif
1349 +
1350 +// MDIO_CFG bit
1351 +#define MDIO_CFG_GP1_FC_TX (1 << 11)
1352 +#define MDIO_CFG_GP1_FC_RX (1 << 10)
1353 +
1354 +/* ====================================== */
1355 +/* ====================================== */
1356 +#define GP1_LNK_DWN BIT(9)
1357 +#define GP1_AN_FAIL BIT(8)
1358 +/* ====================================== */
1359 +/* ====================================== */
1360 +#define PSE_RESET BIT(0)
1361 +/* ====================================== */
1362 +#define PST_DRX_IDX1 BIT(17)
1363 +#define PST_DRX_IDX0 BIT(16)
1364 +#define PST_DTX_IDX3 BIT(3)
1365 +#define PST_DTX_IDX2 BIT(2)
1366 +#define PST_DTX_IDX1 BIT(1)
1367 +#define PST_DTX_IDX0 BIT(0)
1368 +
1369 +#define RX_2B_OFFSET BIT(31)
1370 +#define DESC_32B_EN BIT(8)
1371 +#define TX_WB_DDONE BIT(6)
1372 +#define RX_DMA_BUSY BIT(3)
1373 +#define TX_DMA_BUSY BIT(1)
1374 +#define RX_DMA_EN BIT(2)
1375 +#define TX_DMA_EN BIT(0)
1376 +
1377 +#define PDMA_BT_SIZE_4DWORDS (0<<4)
1378 +#define PDMA_BT_SIZE_8DWORDS (1<<4)
1379 +#define PDMA_BT_SIZE_16DWORDS (2<<4)
1380 +#define PDMA_BT_SIZE_32DWORDS (3<<4)
1381 +
1382 +/* Register bits.
1383 + */
1384 +
1385 +#define MACCFG_RXEN (1<<2)
1386 +#define MACCFG_TXEN (1<<3)
1387 +#define MACCFG_PROMISC (1<<18)
1388 +#define MACCFG_RXMCAST (1<<19)
1389 +#define MACCFG_FDUPLEX (1<<20)
1390 +#define MACCFG_PORTSEL (1<<27)
1391 +#define MACCFG_HBEATDIS (1<<28)
1392 +
1393 +
1394 +#define DMACTL_SR (1<<1) /* Start/Stop Receive */
1395 +#define DMACTL_ST (1<<13) /* Start/Stop Transmission Command */
1396 +
1397 +#define DMACFG_SWR (1<<0) /* Software Reset */
1398 +#define DMACFG_BURST32 (32<<8)
1399 +
1400 +#define DMASTAT_TS 0x00700000 /* Transmit Process State */
1401 +#define DMASTAT_RS 0x000e0000 /* Receive Process State */
1402 +
1403 +#define MACCFG_INIT 0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
1404 +
1405 +
1406 +
1407 +/* Descriptor bits.
1408 + */
1409 +#define R_OWN 0x80000000 /* Own Bit */
1410 +#define RD_RER 0x02000000 /* Receive End Of Ring */
1411 +#define RD_LS 0x00000100 /* Last Descriptor */
1412 +#define RD_ES 0x00008000 /* Error Summary */
1413 +#define RD_CHAIN 0x01000000 /* Chained */
1414 +
1415 +/* Word 0 */
1416 +#define T_OWN 0x80000000 /* Own Bit */
1417 +#define TD_ES 0x00008000 /* Error Summary */
1418 +
1419 +/* Word 1 */
1420 +#define TD_LS 0x40000000 /* Last Segment */
1421 +#define TD_FS 0x20000000 /* First Segment */
1422 +#define TD_TER 0x08000000 /* Transmit End Of Ring */
1423 +#define TD_CHAIN 0x01000000 /* Chained */
1424 +
1425 +
1426 +#define TD_SET 0x08000000 /* Setup Packet */
1427 +
1428 +
1429 +#define POLL_DEMAND 1
1430 +
1431 +#define RSTCTL (0x34)
1432 +#define RSTCTL_RSTENET1 (1<<19)
1433 +#define RSTCTL_RSTENET2 (1<<20)
1434 +
1435 +#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
1436 +#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
1437 +#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
1438 +#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
1439 +
1440 +// Define Whole FE Reset Register
1441 +#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
1442 +
1443 +/*=========================================
1444 + PDMA RX Descriptor Format define
1445 +=========================================*/
1446 +
1447 +//-------------------------------------------------
1448 +typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T;
1449 +
1450 +struct _PDMA_RXD_INFO1_
1451 +{
1452 + unsigned int PDP0;
1453 +};
1454 +//-------------------------------------------------
1455 +typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T;
1456 +
1457 +struct _PDMA_RXD_INFO2_
1458 +{
1459 + unsigned int PLEN1 : 14;
1460 + unsigned int LS1 : 1;
1461 + unsigned int TAG : 1;
1462 + unsigned int PLEN0 : 14;
1463 + unsigned int LS0 : 1;
1464 + unsigned int DDONE_bit : 1;
1465 +};
1466 +//-------------------------------------------------
1467 +typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T;
1468 +
1469 +struct _PDMA_RXD_INFO3_
1470 +{
1471 + unsigned int VID:16;
1472 + unsigned int TPID:16;
1473 +};
1474 +//-------------------------------------------------
1475 +typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T;
1476 +
1477 +struct _PDMA_RXD_INFO4_
1478 +{
1479 +#if defined (CONFIG_RALINK_MT7620)
1480 + unsigned int FOE_Entry : 14;
1481 + unsigned int CRSN : 5;
1482 + unsigned int SPORT : 3;
1483 + unsigned int L4F : 1;
1484 + unsigned int L4VLD : 1;
1485 + unsigned int TACK : 1;
1486 + unsigned int IP4F : 1;
1487 + unsigned int IP4 : 1;
1488 + unsigned int IP6 : 1;
1489 + unsigned int UN_USE1 : 4;
1490 +#elif defined (CONFIG_RALINK_MT7621)
1491 + unsigned int FOE_Entry : 14;
1492 + unsigned int CRSN : 5;
1493 + unsigned int SP : 4;
1494 + unsigned int L4F : 1;
1495 + unsigned int L4VLD : 1;
1496 + unsigned int TACK : 1;
1497 + unsigned int IP4F : 1;
1498 + unsigned int IP4 : 1;
1499 + unsigned int IP6 : 1;
1500 + unsigned int UN_USE1 : 3;
1501 +#else
1502 + unsigned int FOE_Entry : 14;
1503 + unsigned int FVLD : 1;
1504 + unsigned int UN_USE1 : 1;
1505 + unsigned int AI : 8;
1506 + unsigned int SP : 3;
1507 + unsigned int AIS : 1;
1508 + unsigned int L4F : 1;
1509 + unsigned int IPF : 1;
1510 + unsigned int L4FVLD_bit : 1;
1511 + unsigned int IPFVLD_bit : 1;
1512 +#endif
1513 +};
1514 +
1515 +
1516 +struct PDMA_rxdesc {
1517 + PDMA_RXD_INFO1_T rxd_info1;
1518 + PDMA_RXD_INFO2_T rxd_info2;
1519 + PDMA_RXD_INFO3_T rxd_info3;
1520 + PDMA_RXD_INFO4_T rxd_info4;
1521 +#ifdef CONFIG_32B_DESC
1522 + unsigned int rxd_info5;
1523 + unsigned int rxd_info6;
1524 + unsigned int rxd_info7;
1525 + unsigned int rxd_info8;
1526 +#endif
1527 +};
1528 +
1529 +/*=========================================
1530 + PDMA TX Descriptor Format define
1531 +=========================================*/
1532 +//-------------------------------------------------
1533 +typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T;
1534 +
1535 +struct _PDMA_TXD_INFO1_
1536 +{
1537 + unsigned int SDP0;
1538 +};
1539 +//-------------------------------------------------
1540 +typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T;
1541 +
1542 +struct _PDMA_TXD_INFO2_
1543 +{
1544 + unsigned int SDL1 : 14;
1545 + unsigned int LS1_bit : 1;
1546 + unsigned int BURST_bit : 1;
1547 + unsigned int SDL0 : 14;
1548 + unsigned int LS0_bit : 1;
1549 + unsigned int DDONE_bit : 1;
1550 +};
1551 +//-------------------------------------------------
1552 +typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T;
1553 +
1554 +struct _PDMA_TXD_INFO3_
1555 +{
1556 + unsigned int SDP1;
1557 +};
1558 +//-------------------------------------------------
1559 +typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T;
1560 +
1561 +struct _PDMA_TXD_INFO4_
1562 +{
1563 +#if defined (CONFIG_RALINK_MT7620)
1564 + unsigned int VPRI_VIDX : 8;
1565 + unsigned int SIDX : 4;
1566 + unsigned int INSP : 1;
1567 + unsigned int RESV : 2;
1568 + unsigned int UDF : 5;
1569 + unsigned int FP_BMAP : 8;
1570 + unsigned int TSO : 1;
1571 + unsigned int TUI_CO : 3;
1572 +#elif defined (CONFIG_RALINK_MT7621)
1573 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
1574 + unsigned int RESV : 2;
1575 + unsigned int UDF : 6;
1576 + unsigned int FPORT : 3;
1577 + unsigned int TSO : 1;
1578 + unsigned int TUI_CO : 3;
1579 +#else
1580 + unsigned int VPRI_VIDX : 8;
1581 + unsigned int SIDX : 4;
1582 + unsigned int INSP : 1;
1583 + unsigned int RESV : 1;
1584 + unsigned int UN_USE3 : 2;
1585 + unsigned int QN : 3;
1586 + unsigned int UN_USE2 : 1;
1587 + unsigned int UDF : 4;
1588 + unsigned int PN : 3;
1589 + unsigned int UN_USE1 : 1;
1590 + unsigned int TSO : 1;
1591 + unsigned int TUI_CO : 3;
1592 +#endif
1593 +};
1594 +
1595 +
1596 +struct PDMA_txdesc {
1597 + PDMA_TXD_INFO1_T txd_info1;
1598 + PDMA_TXD_INFO2_T txd_info2;
1599 + PDMA_TXD_INFO3_T txd_info3;
1600 + PDMA_TXD_INFO4_T txd_info4;
1601 +#ifdef CONFIG_32B_DESC
1602 + unsigned int txd_info5;
1603 + unsigned int txd_info6;
1604 + unsigned int txd_info7;
1605 + unsigned int txd_info8;
1606 +#endif
1607 +};
1608 +
1609 +
1610 +#if defined (CONFIG_RALINK_MT7621)
1611 +/*=========================================
1612 + QDMA TX Descriptor Format define
1613 +=========================================*/
1614 +//-------------------------------------------------
1615 +typedef struct _QDMA_TXD_INFO1_ QDMA_TXD_INFO1_T;
1616 +
1617 +struct _QDMA_TXD_INFO1_
1618 +{
1619 + unsigned int SDP;
1620 +};
1621 +//-------------------------------------------------
1622 +typedef struct _QDMA_TXD_INFO2_ QDMA_TXD_INFO2_T;
1623 +
1624 +struct _QDMA_TXD_INFO2_
1625 +{
1626 + unsigned int NDP;
1627 +};
1628 +//-------------------------------------------------
1629 +typedef struct _QDMA_TXD_INFO3_ QDMA_TXD_INFO3_T;
1630 +
1631 +struct _QDMA_TXD_INFO3_
1632 +{
1633 + unsigned int QID : 4;
1634 + unsigned int RESV : 10;
1635 + unsigned int SWC_bit : 1;
1636 + unsigned int BURST_bit : 1;
1637 + unsigned int SDL : 14;
1638 + unsigned int LS_bit : 1;
1639 + unsigned int OWN_bit : 1;
1640 +};
1641 +//-------------------------------------------------
1642 +typedef struct _QDMA_TXD_INFO4_ QDMA_TXD_INFO4_T;
1643 +
1644 +struct _QDMA_TXD_INFO4_
1645 +{
1646 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
1647 + unsigned int RESV : 2;
1648 + unsigned int UDF : 6;
1649 + unsigned int FPORT : 3;
1650 + unsigned int TSO : 1;
1651 + unsigned int TUI_CO : 3;
1652 +};
1653 +
1654 +
1655 +struct QDMA_txdesc {
1656 + QDMA_TXD_INFO1_T txd_info1;
1657 + QDMA_TXD_INFO2_T txd_info2;
1658 + QDMA_TXD_INFO3_T txd_info3;
1659 + QDMA_TXD_INFO4_T txd_info4;
1660 +#ifdef CONFIG_32B_DESC
1661 + unsigned int txd_info5;
1662 + unsigned int txd_info6;
1663 + unsigned int txd_info7;
1664 + unsigned int txd_info8;
1665 +#endif
1666 +};
1667 +#endif
1668 +
1669 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
1670 +
1671 +#define PHY_Enable_Auto_Nego 0x1000
1672 +#define PHY_Restart_Auto_Nego 0x0200
1673 +
1674 +/* PHY_STAT_REG = 1; */
1675 +#define PHY_Auto_Neco_Comp 0x0020
1676 +#define PHY_Link_Status 0x0004
1677 +
1678 +/* PHY_AUTO_NEGO_REG = 4; */
1679 +#define PHY_Cap_10_Half 0x0020
1680 +#define PHY_Cap_10_Full 0x0040
1681 +#define PHY_Cap_100_Half 0x0080
1682 +#define PHY_Cap_100_Full 0x0100
1683 +
1684 +/* proc definition */
1685 +
1686 +#if !defined (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \
1687 + !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621)
1688 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
1689 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
1690 +#define PPE_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
1691 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
1692 +#endif
1693 +
1694 +#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
1695 +#if defined (CONFIG_RALINK_RT2880)
1696 +#define PROCREG_DIR "rt2880"
1697 +#elif defined (CONFIG_RALINK_RT3052)
1698 +#define PROCREG_DIR "rt3052"
1699 +#elif defined (CONFIG_RALINK_RT3352)
1700 +#define PROCREG_DIR "rt3352"
1701 +#elif defined (CONFIG_RALINK_RT5350)
1702 +#define PROCREG_DIR "rt5350"
1703 +#elif defined (CONFIG_RALINK_RT2883)
1704 +#define PROCREG_DIR "rt2883"
1705 +#elif defined (CONFIG_RALINK_RT3883)
1706 +#define PROCREG_DIR "rt3883"
1707 +#elif defined (CONFIG_RALINK_RT6855)
1708 +#define PROCREG_DIR "rt6855"
1709 +#elif defined (CONFIG_RALINK_MT7620)
1710 +#define PROCREG_DIR "mt7620"
1711 +#elif defined (CONFIG_RALINK_MT7621)
1712 +#define PROCREG_DIR "mt7621"
1713 +#elif defined (CONFIG_RALINK_MT7628)
1714 +#define PROCREG_DIR "mt7628"
1715 +#elif defined (CONFIG_RALINK_RT6855A)
1716 +#define PROCREG_DIR "rt6855a"
1717 +#else
1718 +#define PROCREG_DIR "rt2880"
1719 +#endif
1720 +#define PROCREG_SKBFREE "skb_free"
1721 +#define PROCREG_TXRING "tx_ring"
1722 +#define PROCREG_RXRING "rx_ring"
1723 +#define PROCREG_NUM_OF_TXD "num_of_txd"
1724 +#define PROCREG_TSO_LEN "tso_len"
1725 +#define PROCREG_LRO_STATS "lro_stats"
1726 +#define PROCREG_GMAC "gmac"
1727 +#define PROCREG_GMAC2 "gmac2"
1728 +#define PROCREG_CP0 "cp0"
1729 +#define PROCREG_RAQOS "qos"
1730 +#define PROCREG_READ_VAL "regread_value"
1731 +#define PROCREG_WRITE_VAL "regwrite_value"
1732 +#define PROCREG_ADDR "reg_addr"
1733 +#define PROCREG_CTL "procreg_control"
1734 +#define PROCREG_RXDONE_INTR "rxdone_intr_count"
1735 +#define PROCREG_ESW_INTR "esw_intr_count"
1736 +#define PROCREG_ESW_CNT "esw_cnt"
1737 +#define PROCREG_SNMP "snmp"
1738 +#if defined (TASKLET_WORKQUEUE_SW)
1739 +#define PROCREG_SCHE "schedule"
1740 +#endif
1741 +#define PROCREG_QDMA "qdma"
1742 +
1743 +struct rt2880_reg_op_data {
1744 + char name[64];
1745 + unsigned int reg_addr;
1746 + unsigned int op;
1747 + unsigned int reg_value;
1748 +};
1749 +
1750 +#ifdef CONFIG_RAETH_LRO
1751 +struct lro_counters {
1752 + u32 lro_aggregated;
1753 + u32 lro_flushed;
1754 + u32 lro_no_desc;
1755 +};
1756 +
1757 +struct lro_para_struct {
1758 + unsigned int lan_ip1;
1759 +};
1760 +
1761 +#endif // CONFIG_RAETH_LRO //
1762 +
1763 +
1764 +
1765 +
1766 +typedef struct end_device
1767 +{
1768 +
1769 + unsigned int tx_cpu_owner_idx0;
1770 + unsigned int rx_cpu_owner_idx0;
1771 + unsigned int fe_int_status;
1772 + unsigned int tx_full;
1773 +
1774 +#if !defined (CONFIG_RAETH_QDMA)
1775 + unsigned int phy_tx_ring0;
1776 +#else
1777 + /* QDMA Tx PTR */
1778 + struct sk_buff *free_skb[NUM_TX_DESC];
1779 + unsigned int tx_dma_ptr;
1780 + unsigned int tx_cpu_ptr;
1781 + unsigned int free_txd_num;
1782 + unsigned int free_txd_head;
1783 + unsigned int free_txd_tail;
1784 + struct QDMA_txdesc *txd_pool;
1785 + dma_addr_t phy_txd_pool;
1786 +// unsigned int phy_txd_pool;
1787 + unsigned int txd_pool_info[NUM_TX_DESC];
1788 +#endif
1789 +
1790 + unsigned int phy_rx_ring0, phy_rx_ring1;
1791 +
1792 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || \
1793 + defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \
1794 + defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || \
1795 + defined(CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1796 + //send signal to user application to notify link status changed
1797 + struct work_struct kill_sig_wq;
1798 +#endif
1799 +
1800 + struct work_struct reset_task;
1801 +#ifdef WORKQUEUE_BH
1802 + struct work_struct rx_wq;
1803 +#else
1804 +#if defined (TASKLET_WORKQUEUE_SW)
1805 + struct work_struct rx_wq;
1806 +#endif
1807 +#endif // WORKQUEUE_BH //
1808 +
1809 +#if defined(CONFIG_RAETH_QOS)
1810 + struct sk_buff * skb_free[NUM_TX_RINGS][NUM_TX_DESC];
1811 + unsigned int free_idx[NUM_TX_RINGS];
1812 +#else
1813 + struct sk_buff* skb_free[NUM_TX_DESC];
1814 + unsigned int free_idx;
1815 +#endif
1816 +
1817 + struct net_device_stats stat; /* The new statistics table. */
1818 + spinlock_t page_lock; /* Page register locks */
1819 + struct PDMA_txdesc *tx_ring0;
1820 +#if defined(CONFIG_RAETH_QOS)
1821 + struct PDMA_txdesc *tx_ring1;
1822 + struct PDMA_txdesc *tx_ring2;
1823 + struct PDMA_txdesc *tx_ring3;
1824 +#endif
1825 + struct PDMA_rxdesc *rx_ring0;
1826 + struct sk_buff *netrx0_skbuf[NUM_RX_DESC];
1827 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
1828 + struct PDMA_rxdesc *rx_ring1;
1829 + struct sk_buff *netrx1_skbuf[NUM_RX_DESC];
1830 +#endif
1831 +#ifdef CONFIG_RAETH_NAPI
1832 + atomic_t irq_sem;
1833 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1834 + struct napi_struct napi;
1835 +#endif
1836 +#endif
1837 +#ifdef CONFIG_PSEUDO_SUPPORT
1838 + struct net_device *PseudoDev;
1839 + unsigned int isPseudo;
1840 +#endif
1841 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
1842 + struct mii_if_info mii_info;
1843 +#endif
1844 +#ifdef CONFIG_RAETH_LRO
1845 + struct lro_counters lro_counters;
1846 + struct net_lro_mgr lro_mgr;
1847 + struct net_lro_desc lro_arr[8];
1848 +#endif
1849 +#ifdef CONFIG_RAETH_HW_VLAN_RX
1850 + struct vlan_group *vlgrp;
1851 +#endif
1852 +} END_DEVICE, *pEND_DEVICE;
1853 +
1854 +
1855 +#define RAETH_VERSION "v3.0"
1856 +
1857 +#endif
1858 +
1859 +#ifdef CONFIG_RAETH_QDMA
1860 +#define DMA_GLO_CFG QDMA_GLO_CFG
1861 +#define GDMA1_FWD_PORT 0x5555
1862 +#define GDMA2_FWD_PORT 0x5555
1863 +#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
1864 +#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
1865 +#define RAETH_FE_INT_STATUS QFE_INT_STATUS
1866 +#define RAETH_FE_INT_ALL QFE_INT_ALL
1867 +#define RAETH_FE_INT_ENABLE QFE_INT_ENABLE
1868 +#define RAETH_FE_INT_DLY_INIT QFE_INT_DLY_INIT
1869 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT
1870 +#define RAETH_TX_DLY_INT RLS_DLY_INT
1871 +#define RAETH_TX_DONE_INT0 RLS_DONE_INT
1872 +#define RAETH_DLY_INT_CFG QDMA_DELAY_INT
1873 +#else
1874 +#define DMA_GLO_CFG PDMA_GLO_CFG
1875 +#define GDMA1_FWD_PORT 0x0000
1876 +#define GDMA2_FWD_PORT 0x0000
1877 +#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
1878 +#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
1879 +#define RAETH_FE_INT_STATUS FE_INT_STATUS
1880 +#define RAETH_FE_INT_ALL FE_INT_ALL
1881 +#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
1882 +#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
1883 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
1884 +#define RAETH_TX_DLY_INT TX_DLY_INT
1885 +#define RAETH_TX_DONE_INT0 TX_DONE_INT0
1886 +#define RAETH_DLY_INT_CFG DLY_INT_CFG
1887 +#endif
1888 --- /dev/null
1889 +++ b/drivers/net/ethernet/raeth/ra_ioctl.h
1890 @@ -0,0 +1,92 @@
1891 +#ifndef _RAETH_IOCTL_H
1892 +#define _RAETH_IOCTL_H
1893 +
1894 +/* ioctl commands */
1895 +#define RAETH_ESW_REG_READ 0x89F1
1896 +#define RAETH_ESW_REG_WRITE 0x89F2
1897 +#define RAETH_MII_READ 0x89F3
1898 +#define RAETH_MII_WRITE 0x89F4
1899 +#define RAETH_ESW_INGRESS_RATE 0x89F5
1900 +#define RAETH_ESW_EGRESS_RATE 0x89F6
1901 +#define RAETH_ESW_PHY_DUMP 0x89F7
1902 +#define RAETH_QDMA_REG_READ 0x89F8
1903 +#define RAETH_QDMA_REG_WRITE 0x89F9
1904 +#define RAETH_QDMA_QUEUE_MAPPING 0x89FA
1905 +#define RAETH_QDMA_READ_CPU_CLK 0x89FB
1906 +
1907 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
1908 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
1909 +
1910 +#define REG_ESW_WT_MAC_MFC 0x10
1911 +#define REG_ESW_WT_MAC_ATA1 0x74
1912 +#define REG_ESW_WT_MAC_ATA2 0x78
1913 +#define REG_ESW_WT_MAC_ATWD 0x7C
1914 +#define REG_ESW_WT_MAC_ATC 0x80
1915 +
1916 +#define REG_ESW_TABLE_TSRA1 0x84
1917 +#define REG_ESW_TABLE_TSRA2 0x88
1918 +#define REG_ESW_TABLE_ATRD 0x8C
1919 +
1920 +
1921 +#define REG_ESW_VLAN_VTCR 0x90
1922 +#define REG_ESW_VLAN_VAWD1 0x94
1923 +#define REG_ESW_VLAN_VAWD2 0x98
1924 +
1925 +
1926 +#define REG_ESW_VLAN_ID_BASE 0x100
1927 +
1928 +//#define REG_ESW_VLAN_ID_BASE 0x50
1929 +#define REG_ESW_VLAN_MEMB_BASE 0x70
1930 +#define REG_ESW_TABLE_SEARCH 0x24
1931 +#define REG_ESW_TABLE_STATUS0 0x28
1932 +#define REG_ESW_TABLE_STATUS1 0x2C
1933 +#define REG_ESW_TABLE_STATUS2 0x30
1934 +#define REG_ESW_WT_MAC_AD0 0x34
1935 +#define REG_ESW_WT_MAC_AD1 0x38
1936 +#define REG_ESW_WT_MAC_AD2 0x3C
1937 +
1938 +#else
1939 +/* rt3052 embedded ethernet switch registers */
1940 +#define REG_ESW_VLAN_ID_BASE 0x50
1941 +#define REG_ESW_VLAN_MEMB_BASE 0x70
1942 +#define REG_ESW_TABLE_SEARCH 0x24
1943 +#define REG_ESW_TABLE_STATUS0 0x28
1944 +#define REG_ESW_TABLE_STATUS1 0x2C
1945 +#define REG_ESW_TABLE_STATUS2 0x30
1946 +#define REG_ESW_WT_MAC_AD0 0x34
1947 +#define REG_ESW_WT_MAC_AD1 0x38
1948 +#define REG_ESW_WT_MAC_AD2 0x3C
1949 +#endif
1950 +
1951 +
1952 +#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
1953 +#define REG_ESW_MAX 0x16C
1954 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
1955 + defined (CONFIG_RALINK_MT7620)
1956 +#define REG_ESW_MAX 0x7FFFF
1957 +#else //RT305x, RT3350
1958 +#define REG_ESW_MAX 0xFC
1959 +#endif
1960 +#define REG_HQOS_MAX 0x3FFF
1961 +
1962 +
1963 +typedef struct rt3052_esw_reg {
1964 + unsigned int off;
1965 + unsigned int val;
1966 +} esw_reg;
1967 +
1968 +typedef struct ralink_mii_ioctl_data {
1969 + __u32 phy_id;
1970 + __u32 reg_num;
1971 + __u32 val_in;
1972 + __u32 val_out;
1973 +} ra_mii_ioctl_data;
1974 +
1975 +typedef struct rt335x_esw_reg {
1976 + unsigned int on_off;
1977 + unsigned int port;
1978 + unsigned int bw;/*Mbps*/
1979 +} esw_rate;
1980 +
1981 +
1982 +#endif
1983 --- /dev/null
1984 +++ b/drivers/net/ethernet/raeth/ra_mac.c
1985 @@ -0,0 +1,98 @@
1986 +#include <linux/module.h>
1987 +#include <linux/version.h>
1988 +#include <linux/kernel.h>
1989 +#include <linux/sched.h>
1990 +#include <linux/types.h>
1991 +#include <linux/fcntl.h>
1992 +#include <linux/interrupt.h>
1993 +#include <linux/ptrace.h>
1994 +#include <linux/ioport.h>
1995 +#include <linux/in.h>
1996 +#include <linux/slab.h>
1997 +#include <linux/string.h>
1998 +#include <linux/signal.h>
1999 +#include <linux/irq.h>
2000 +#include <linux/ctype.h>
2001 +
2002 +#include <asm/io.h>
2003 +#include <asm/bitops.h>
2004 +#include <asm/io.h>
2005 +#include <asm/dma.h>
2006 +
2007 +#include <asm/rt2880/surfboardint.h> /* for cp0 reg access, added by bobtseng */
2008 +
2009 +#include <linux/errno.h>
2010 +#include <linux/init.h>
2011 +//#include <linux/mca.h>
2012 +
2013 +#include <linux/netdevice.h>
2014 +#include <linux/etherdevice.h>
2015 +#include <linux/skbuff.h>
2016 +
2017 +#include <linux/init.h>
2018 +#include <linux/module.h>
2019 +#include <linux/proc_fs.h>
2020 +#include <asm/uaccess.h>
2021 +
2022 +#if defined(CONFIG_USER_SNMPD)
2023 +#include <linux/seq_file.h>
2024 +#endif
2025 +
2026 +
2027 +
2028 +#include "ra2882ethreg.h"
2029 +#include "raether.h"
2030 +#include "ra_mac.h"
2031 +
2032 +extern struct net_device *dev_raether;
2033 +
2034 +
2035 +void ra2880stop(END_DEVICE *ei_local)
2036 +{
2037 + unsigned int regValue;
2038 + printk("ra2880stop()...");
2039 +
2040 + regValue = sysRegRead(PDMA_GLO_CFG);
2041 + regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
2042 + sysRegWrite(PDMA_GLO_CFG, regValue);
2043 + printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regValue);
2044 + printk("Done\n");
2045 +}
2046 +
2047 +void ei_irq_clear(void)
2048 +{
2049 + sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF);
2050 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_STATUS", FE_INT_STATUS, 0xFFFFFFFF);
2051 +}
2052 +
2053 +void rt2880_gmac_hard_reset(void)
2054 +{
2055 + sysRegWrite(RSTCTRL, RALINK_FE_RST);
2056 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, RALINK_FE_RST);
2057 + sysRegWrite(RSTCTRL, 0);
2058 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, 0);
2059 +}
2060 +
2061 +void ra2880EnableInterrupt()
2062 +{
2063 + unsigned int regValue = sysRegRead(FE_INT_ENABLE);
2064 + sysRegWrite(FE_INT_ENABLE, regValue);
2065 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_ENABLE", FE_INT_ENABLE, regValue);
2066 +}
2067 +
2068 +void ra2880MacAddressSet(unsigned char p[6])
2069 +{
2070 + unsigned long regValue;
2071 +
2072 + regValue = (p[0] << 8) | (p[1]);
2073 + sysRegWrite(GDMA1_MAC_ADRH, regValue);
2074 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRH", GDMA1_MAC_ADRH, regValue);
2075 +
2076 + regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
2077 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRL", GDMA1_MAC_ADRL, regValue);
2078 + sysRegWrite(GDMA1_MAC_ADRL, regValue);
2079 +
2080 + return;
2081 +}
2082 +
2083 +
2084 --- /dev/null
2085 +++ b/drivers/net/ethernet/raeth/ra_mac.h
2086 @@ -0,0 +1,35 @@
2087 +#ifndef RA_MAC_H
2088 +#define RA_MAC_H
2089 +
2090 +void ra2880stop(END_DEVICE *ei_local);
2091 +void ra2880MacAddressSet(unsigned char p[6]);
2092 +void ra2880Mac2AddressSet(unsigned char p[6]);
2093 +void ethtool_init(struct net_device *dev);
2094 +
2095 +void ra2880EnableInterrupt(void);
2096 +
2097 +void dump_qos(void);
2098 +void dump_reg(void);
2099 +void dump_cp0(void);
2100 +
2101 +int debug_proc_init(void);
2102 +void debug_proc_exit(void);
2103 +
2104 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2105 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
2106 +void enable_auto_negotiate(int unused);
2107 +#else
2108 +void enable_auto_negotiate(int ge);
2109 +#endif
2110 +
2111 +void rt2880_gmac_hard_reset(void);
2112 +
2113 +int TsoLenUpdate(int tso_len);
2114 +int NumOfTxdUpdate(int num_of_txd);
2115 +
2116 +#ifdef CONFIG_RAETH_LRO
2117 +int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed);
2118 +#endif
2119 +int getnext(const char *src, int separator, char *dest);
2120 +int str_to_ip(unsigned int *ip, const char *str);
2121 +#endif
2122 --- /dev/null
2123 +++ b/drivers/net/ethernet/raeth/raether.c
2124 @@ -0,0 +1,693 @@
2125 +#include <linux/module.h>
2126 +#include <linux/version.h>
2127 +#include <linux/kernel.h>
2128 +#include <linux/types.h>
2129 +#include <linux/pci.h>
2130 +#include <linux/interrupt.h>
2131 +#include <linux/init.h>
2132 +#include <linux/skbuff.h>
2133 +#include <linux/if_vlan.h>
2134 +#include <linux/if_ether.h>
2135 +#include <linux/fs.h>
2136 +#include <asm/uaccess.h>
2137 +#include <linux/delay.h>
2138 +#include <linux/sched.h>
2139 +
2140 +#include <asm/rt2880/rt_mmap.h>
2141 +#include "ra2882ethreg.h"
2142 +#include "raether.h"
2143 +#include "ra_mac.h"
2144 +#include "ra_ioctl.h"
2145 +
2146 +static int rt2880_eth_recv(struct net_device* dev);
2147 +int reg_dbg = 0;
2148 +
2149 +void setup_internal_gsw(void);
2150 +
2151 +#define MAX_RX_LENGTH 1536
2152 +
2153 +struct net_device *dev_raether;
2154 +
2155 +static int rx_dma_owner_idx;
2156 +static int rx_dma_owner_idx0;
2157 +static int pending_recv;
2158 +static struct PDMA_rxdesc *rx_ring;
2159 +static unsigned long tx_ring_full=0;
2160 +
2161 +#define KSEG1 0xa0000000
2162 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
2163 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
2164 +
2165 +extern int fe_dma_init(struct net_device *dev);
2166 +extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no);
2167 +extern void ei_xmit_housekeeping(unsigned long unused);
2168 +extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no);
2169 +
2170 +static int ei_set_mac_addr(struct net_device *dev, void *p)
2171 +{
2172 + struct sockaddr *addr = p;
2173 +
2174 + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2175 +
2176 + if(netif_running(dev))
2177 + return -EBUSY;
2178 +
2179 + ra2880MacAddressSet(addr->sa_data);
2180 + return 0;
2181 +}
2182 +
2183 +
2184 +void set_fe_dma_glo_cfg(void)
2185 +{
2186 + int dma_glo_cfg=0;
2187 +
2188 + dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS);
2189 +
2190 + dma_glo_cfg |= (RX_2B_OFFSET);
2191 +
2192 + sysRegWrite(DMA_GLO_CFG, dma_glo_cfg);
2193 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "DMA_GLO_CFG", DMA_GLO_CFG, dma_glo_cfg);
2194 +}
2195 +
2196 +int forward_config(struct net_device *dev)
2197 +{
2198 + unsigned int regVal, regCsg;
2199 +
2200 + regVal = sysRegRead(GDMA1_FWD_CFG);
2201 + regCsg = sysRegRead(CDMA_CSG_CFG);
2202 +
2203 + //set unicast/multicast/broadcast frame to cpu
2204 + regVal &= ~0xFFFF;
2205 + regVal |= GDMA1_FWD_PORT;
2206 + regCsg &= ~0x7;
2207 +
2208 + //disable ipv4 header checksum check
2209 + regVal &= ~GDM1_ICS_EN;
2210 + regCsg &= ~ICS_GEN_EN;
2211 +
2212 + //disable tcp checksum check
2213 + regVal &= ~GDM1_TCS_EN;
2214 + regCsg &= ~TCS_GEN_EN;
2215 +
2216 + //disable udp checksum check
2217 + regVal &= ~GDM1_UCS_EN;
2218 + regCsg &= ~UCS_GEN_EN;
2219 +
2220 +
2221 + dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */
2222 +
2223 +
2224 + sysRegWrite(GDMA1_FWD_CFG, regVal);
2225 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "GDMA1_FWD_CFG", GDMA1_FWD_CFG, regVal);
2226 + sysRegWrite(CDMA_CSG_CFG, regCsg);
2227 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "CDMA_CSG_CFG", CDMA_CSG_CFG, regCsg);
2228 +
2229 + regVal = 0x1;
2230 + sysRegWrite(FE_RST_GL, regVal);
2231 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, regVal);
2232 + sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue
2233 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, 1);
2234 +
2235 + regCsg = sysRegRead(CDMA_CSG_CFG);
2236 + printk("CDMA_CSG_CFG = %0X\n",regCsg);
2237 + regVal = sysRegRead(GDMA1_FWD_CFG);
2238 + printk("GDMA1_FWD_CFG = %0X\n",regVal);
2239 +
2240 + return 1;
2241 +}
2242 +
2243 +
2244 +static int rt2880_eth_recv(struct net_device* dev)
2245 +{
2246 + struct sk_buff *skb, *rx_skb;
2247 + unsigned int length = 0;
2248 + unsigned long RxProcessed;
2249 +
2250 +
2251 + int bReschedule = 0;
2252 + END_DEVICE* ei_local = netdev_priv(dev);
2253 +
2254 +
2255 +
2256 + RxProcessed = 0;
2257 +
2258 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
2259 +
2260 + for ( ; ; ) {
2261 +
2262 + if (RxProcessed++ > NUM_RX_MAX_PROCESS)
2263 + {
2264 + // need to reschedule rx handle
2265 + bReschedule = 1;
2266 + break;
2267 + }
2268 +
2269 +
2270 +
2271 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
2272 + rx_ring = ei_local->rx_ring0;
2273 + rx_dma_owner_idx = rx_dma_owner_idx0;
2274 + } else {
2275 + break;
2276 + }
2277 +
2278 + /* skb processing */
2279 + length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
2280 + rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
2281 + rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
2282 + rx_skb->len = length;
2283 +
2284 + rx_skb->data += NET_IP_ALIGN;
2285 +
2286 + rx_skb->tail = rx_skb->data + length;
2287 +
2288 + rx_skb->dev = dev;
2289 + rx_skb->protocol = eth_type_trans(rx_skb,dev);
2290 +
2291 + rx_skb->ip_summed = CHECKSUM_NONE;
2292 +
2293 +
2294 + /* We have to check the free memory size is big enough
2295 + * before pass the packet to cpu*/
2296 + skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
2297 +
2298 + if (unlikely(skb == NULL))
2299 + {
2300 + printk(KERN_ERR "skb not available...\n");
2301 + ei_local->stat.rx_dropped++;
2302 + bReschedule = 1;
2303 + break;
2304 + }
2305 +
2306 + {
2307 + netif_rx(rx_skb);
2308 + }
2309 +
2310 + {
2311 + ei_local->stat.rx_packets++;
2312 + ei_local->stat.rx_bytes += length;
2313 + }
2314 +
2315 +
2316 + rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH;
2317 + rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0;
2318 + rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
2319 + rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
2320 +
2321 + /* Move point to next RXD which wants to alloc*/
2322 + sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
2323 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_RX_CALC_IDX0", RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
2324 + ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
2325 +
2326 + /* Update to Next packet point that was received.
2327 + */
2328 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
2329 + } /* for */
2330 +
2331 + return bReschedule;
2332 +}
2333 +
2334 +void ei_receive_workq(struct work_struct *work)
2335 +{
2336 + struct net_device *dev = dev_raether;
2337 + END_DEVICE *ei_local = netdev_priv(dev);
2338 + unsigned long reg_int_mask=0;
2339 + int bReschedule=0;
2340 +
2341 +
2342 + if(tx_ring_full==0){
2343 + bReschedule = rt2880_eth_recv(dev);
2344 + if(bReschedule)
2345 + {
2346 + schedule_work(&ei_local->rx_wq);
2347 + }else{
2348 + reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
2349 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
2350 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
2351 + }
2352 + }else{
2353 + schedule_work(&ei_local->rx_wq);
2354 + }
2355 +}
2356 +
2357 +
2358 +static irqreturn_t ei_interrupt(int irq, void *dev_id)
2359 +{
2360 + unsigned long reg_int_val;
2361 + unsigned long reg_int_mask=0;
2362 + unsigned int recv = 0;
2363 + unsigned int transmit __maybe_unused = 0;
2364 + unsigned long flags;
2365 +
2366 + struct net_device *dev = (struct net_device *) dev_id;
2367 + END_DEVICE *ei_local = netdev_priv(dev);
2368 +
2369 + if (dev == NULL)
2370 + {
2371 + printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
2372 + return IRQ_NONE;
2373 + }
2374 +
2375 +
2376 + spin_lock_irqsave(&(ei_local->page_lock), flags);
2377 + reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
2378 +
2379 + if((reg_int_val & RX_DLY_INT))
2380 + recv = 1;
2381 +
2382 + if (reg_int_val & RAETH_TX_DLY_INT)
2383 + transmit = 1;
2384 +
2385 + sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
2386 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_STATUS", RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
2387 +
2388 + ei_xmit_housekeeping(0);
2389 +
2390 + if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0))
2391 + {
2392 + reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
2393 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
2394 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
2395 + pending_recv=0;
2396 + schedule_work(&ei_local->rx_wq);
2397 + }
2398 + else if (recv == 1 && tx_ring_full==1)
2399 + {
2400 + pending_recv=1;
2401 + }
2402 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
2403 +
2404 + return IRQ_HANDLED;
2405 +}
2406 +
2407 +static void esw_link_status_changed(int port_no, void *dev_id)
2408 +{
2409 + unsigned int reg_val;
2410 + mii_mgr_read(31, (0x3008 + (port_no*0x100)), &reg_val);
2411 + if(reg_val & 0x1) {
2412 + printk("ESW: Link Status Changed - Port%d Link UP\n", port_no);
2413 + } else {
2414 + printk("ESW: Link Status Changed - Port%d Link Down\n", port_no);
2415 + }
2416 +}
2417 +
2418 +
2419 +static irqreturn_t esw_interrupt(int irq, void *dev_id)
2420 +{
2421 + unsigned long flags;
2422 + unsigned int reg_int_val;
2423 + struct net_device *dev = (struct net_device *) dev_id;
2424 + END_DEVICE *ei_local = netdev_priv(dev);
2425 +
2426 + spin_lock_irqsave(&(ei_local->page_lock), flags);
2427 + mii_mgr_read(31, 0x700c, &reg_int_val);
2428 +
2429 + if (reg_int_val & P4_LINK_CH) {
2430 + esw_link_status_changed(4, dev_id);
2431 + }
2432 +
2433 + if (reg_int_val & P3_LINK_CH) {
2434 + esw_link_status_changed(3, dev_id);
2435 + }
2436 + if (reg_int_val & P2_LINK_CH) {
2437 + esw_link_status_changed(2, dev_id);
2438 + }
2439 + if (reg_int_val & P1_LINK_CH) {
2440 + esw_link_status_changed(1, dev_id);
2441 + }
2442 + if (reg_int_val & P0_LINK_CH) {
2443 + esw_link_status_changed(0, dev_id);
2444 + }
2445 +
2446 + mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change
2447 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
2448 + return IRQ_HANDLED;
2449 +}
2450 +
2451 +
2452 +
2453 +static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
2454 +{
2455 + return ei_start_xmit(skb, dev, 1);
2456 +}
2457 +
2458 +static int ei_change_mtu(struct net_device *dev, int new_mtu)
2459 +{
2460 + unsigned long flags;
2461 + END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure
2462 +
2463 + if ( ei_local == NULL ) {
2464 + printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
2465 + return -ENXIO;
2466 + }
2467 +
2468 + spin_lock_irqsave(&ei_local->page_lock, flags);
2469 +
2470 + if ( (new_mtu > 4096) || (new_mtu < 64)) {
2471 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
2472 + return -EINVAL;
2473 + }
2474 +
2475 + if ( new_mtu > 1500 ) {
2476 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
2477 + return -EINVAL;
2478 + }
2479 +
2480 + dev->mtu = new_mtu;
2481 +
2482 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
2483 + return 0;
2484 +}
2485 +
2486 +
2487 +static const struct net_device_ops ei_netdev_ops = {
2488 + .ndo_init = rather_probe,
2489 + .ndo_open = ei_open,
2490 + .ndo_stop = ei_close,
2491 + .ndo_start_xmit = ei_start_xmit_fake,
2492 + .ndo_set_mac_address = eth_mac_addr,
2493 + .ndo_change_mtu = ei_change_mtu,
2494 + .ndo_validate_addr = eth_validate_addr,
2495 +};
2496 +
2497 +void ra2880_setup_dev_fptable(struct net_device *dev)
2498 +{
2499 + RAETH_PRINT(__FUNCTION__ "is called!\n");
2500 +
2501 + dev->netdev_ops = &ei_netdev_ops;
2502 +#define TX_TIMEOUT (5*HZ)
2503 + dev->watchdog_timeo = TX_TIMEOUT;
2504 +
2505 +}
2506 +
2507 +void fe_reset(void)
2508 +{
2509 + u32 val;
2510 + val = sysRegRead(RSTCTRL);
2511 +
2512 + val = val | RALINK_FE_RST;
2513 + sysRegWrite(RSTCTRL, val);
2514 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
2515 + val = val & ~(RALINK_FE_RST);
2516 + sysRegWrite(RSTCTRL, val);
2517 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
2518 +}
2519 +
2520 +void ei_reset_task(struct work_struct *work)
2521 +{
2522 + struct net_device *dev = dev_raether;
2523 +
2524 + ei_close(dev);
2525 + ei_open(dev);
2526 +
2527 + return;
2528 +}
2529 +
2530 +void ei_tx_timeout(struct net_device *dev)
2531 +{
2532 + END_DEVICE *ei_local = netdev_priv(dev);
2533 +
2534 + schedule_work(&ei_local->reset_task);
2535 +}
2536 +
2537 +int __init rather_probe(struct net_device *dev)
2538 +{
2539 + END_DEVICE *ei_local = netdev_priv(dev);
2540 + struct sockaddr addr;
2541 + unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
2542 +
2543 + fe_reset();
2544 + net_srandom(jiffies);
2545 + memcpy(addr.sa_data, mac_addr01234, 5);
2546 + addr.sa_data[5] = net_random()&0xFF;
2547 + ei_set_mac_addr(dev, &addr);
2548 + spin_lock_init(&ei_local->page_lock);
2549 + ether_setup(dev);
2550 +
2551 + return 0;
2552 +}
2553 +
2554 +
2555 +int ei_open(struct net_device *dev)
2556 +{
2557 + int i, err;
2558 + unsigned long flags;
2559 + END_DEVICE *ei_local;
2560 +
2561 +
2562 + if (!try_module_get(THIS_MODULE))
2563 + {
2564 + printk("%s: Cannot reserve module\n", __FUNCTION__);
2565 + return -1;
2566 + }
2567 + printk("Raeth %s (",RAETH_VERSION);
2568 + printk("Workqueue");
2569 +
2570 + printk(")\n");
2571 + ei_local = netdev_priv(dev); // get device pointer from System
2572 + // unsigned int flags;
2573 +
2574 + if (ei_local == NULL)
2575 + {
2576 + printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
2577 + return -ENXIO;
2578 + }
2579 +
2580 + /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
2581 + for ( i = 0; i < NUM_RX_DESC; i++)
2582 + {
2583 + ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
2584 + if (ei_local->netrx0_skbuf[i] == NULL ) {
2585 + printk("rx skbuff buffer allocation failed!");
2586 + } else {
2587 + }
2588 + }
2589 +
2590 + spin_lock_irqsave(&(ei_local->page_lock), flags);
2591 + fe_dma_init(dev);
2592 + fe_sw_init(); //initialize fe and switch register
2593 + err = request_irq( dev->irq, ei_interrupt, 0, dev->name, dev); // try to fix irq in open
2594 + if (err)
2595 + return err;
2596 +
2597 + if ( dev->dev_addr != NULL) {
2598 + ra2880MacAddressSet((void *)(dev->dev_addr));
2599 + } else {
2600 + printk("dev->dev_addr is empty !\n");
2601 + }
2602 + mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr
2603 + err = request_irq(31, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
2604 + if (err)
2605 + return err;
2606 +
2607 + sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
2608 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_DLY_INT_CFG", RAETH_DLY_INT_CFG, DELAY_INT_INIT);
2609 + sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
2610 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
2611 +
2612 + INIT_WORK(&ei_local->reset_task, ei_reset_task);
2613 +
2614 + INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
2615 +
2616 + netif_start_queue(dev);
2617 +
2618 +
2619 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
2620 +
2621 +
2622 + forward_config(dev);
2623 + return 0;
2624 +}
2625 +
2626 +int ei_close(struct net_device *dev)
2627 +{
2628 + int i;
2629 + END_DEVICE *ei_local = netdev_priv(dev); // device pointer
2630 + unsigned long flags;
2631 + spin_lock_irqsave(&(ei_local->page_lock), flags);
2632 +
2633 + cancel_work_sync(&ei_local->reset_task);
2634 + netif_stop_queue(dev);
2635 + ra2880stop(ei_local);
2636 + msleep(10);
2637 +
2638 + cancel_work_sync(&ei_local->rx_wq);
2639 + free_irq(dev->irq, dev);
2640 + free_irq(31, dev);
2641 + for ( i = 0; i < NUM_RX_DESC; i++)
2642 + {
2643 + if (ei_local->netrx0_skbuf[i] != NULL) {
2644 + dev_kfree_skb(ei_local->netrx0_skbuf[i]);
2645 + ei_local->netrx0_skbuf[i] = NULL;
2646 + }
2647 + }
2648 + if (ei_local->tx_ring0 != NULL) {
2649 + pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
2650 + }
2651 + pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0);
2652 +
2653 + printk("Free TX/RX Ring Memory!\n");
2654 +
2655 +// fe_reset();
2656 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
2657 +
2658 + module_put(THIS_MODULE);
2659 + return 0;
2660 +}
2661 +
2662 +
2663 +void setup_internal_gsw(void)
2664 +{
2665 + u32 i;
2666 + u32 regValue;
2667 +
2668 + /* reduce RGMII2 PAD driving strength */
2669 + *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
2670 +
2671 + //RGMII1=Normal mode
2672 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
2673 +
2674 + //GMAC1= RGMII mode
2675 + *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
2676 +
2677 + //enable MDIO to control MT7530
2678 + regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
2679 + regValue &= ~(0x3 << 12);
2680 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
2681 +
2682 + for(i=0;i<=4;i++)
2683 + {
2684 + //turn off PHY
2685 + mii_mgr_read(i, 0x0 ,&regValue);
2686 + regValue |= (0x1<<11);
2687 + mii_mgr_write(i, 0x0, regValue);
2688 + }
2689 + mii_mgr_write(31, 0x7000, 0x3); //reset switch
2690 + udelay(10);
2691 +
2692 + if(sysRegRead(0xbe00000c)==0x00030101) {
2693 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e30b);//(GE1, Force 1000M/FD, FC ON)
2694 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e30b);
2695 + mii_mgr_write(31, 0x3600, 0x5e30b);
2696 + } else {
2697 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e33b);//(GE1, Force 1000M/FD, FC ON)
2698 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e33b);
2699 + mii_mgr_write(31, 0x3600, 0x5e33b);
2700 + }
2701 +
2702 + sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
2703 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x200", RALINK_ETH_SW_BASE+0x200, 0x00008000);
2704 +
2705 + //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
2706 + mii_mgr_read(31, 0x7804 ,&regValue);
2707 + regValue &= ~(1<<8); //Enable Port 6
2708 + regValue |= (1<<6); //Disable Port 5
2709 + regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
2710 +
2711 + regValue |= (1<<16);//change HW-TRAP
2712 + printk("change HW-TRAP to 0x%x!!!!!!!!!!!!",regValue);
2713 + mii_mgr_write(31, 0x7804 ,regValue);
2714 + regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10);
2715 + regValue = (regValue >> 6) & 0x7;
2716 + if(regValue >= 6) { //25Mhz Xtal
2717 + /* do nothing */
2718 + } else if(regValue >=3) { //40Mhz
2719 +
2720 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock
2721 + mii_mgr_write(0, 14, 0x410);
2722 + mii_mgr_write(0, 13, 0x401f);
2723 + mii_mgr_write(0, 14, 0x0);
2724 +
2725 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL
2726 + mii_mgr_write(0, 14, 0x40d);
2727 + mii_mgr_write(0, 13, 0x401f);
2728 + mii_mgr_write(0, 14, 0x2020);
2729 +
2730 + mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz
2731 + mii_mgr_write(0, 14, 0x40e);
2732 + mii_mgr_write(0, 13, 0x401f);
2733 + mii_mgr_write(0, 14, 0x119);
2734 +
2735 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL
2736 + mii_mgr_write(0, 14, 0x40d);
2737 + mii_mgr_write(0, 13, 0x401f);
2738 + mii_mgr_write(0, 14, 0x2820);
2739 +
2740 + udelay(20); //suggest by CD
2741 +
2742 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock
2743 + mii_mgr_write(0, 14, 0x410);
2744 + mii_mgr_write(0, 13, 0x401f);
2745 + }else { //20Mhz Xtal
2746 +
2747 + /* TODO */
2748 +
2749 + }
2750 + mii_mgr_write(0, 14, 0x1); /*RGMII*/
2751 +
2752 +#if 1
2753 + mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M
2754 + mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M
2755 +#else
2756 + mii_mgr_write(31, 0x7b00, 8); // delay setting for 100M
2757 + mii_mgr_write(31, 0x7b04, 0x14); // for 100M
2758 +#endif
2759 + /*Tx Driving*/
2760 + mii_mgr_write(31, 0x7a54, 0x44); //lower driving
2761 + mii_mgr_write(31, 0x7a5c, 0x44); //lower driving
2762 + mii_mgr_write(31, 0x7a64, 0x44); //lower driving
2763 + mii_mgr_write(31, 0x7a6c, 0x44); //lower driving
2764 + mii_mgr_write(31, 0x7a74, 0x44); //lower driving
2765 + mii_mgr_write(31, 0x7a7c, 0x44); //lower driving
2766 +
2767 + for(i=0;i<=4;i++)
2768 + {
2769 + //turn on PHY
2770 + mii_mgr_read(i, 0x0 ,&regValue);
2771 + regValue &= ~(0x1<<11);
2772 + mii_mgr_write(i, 0x0, regValue);
2773 + }
2774 +
2775 + mii_mgr_read(31, 0x7808 ,&regValue);
2776 + regValue |= (3<<16); //Enable INTR
2777 + mii_mgr_write(31, 0x7808 ,regValue);
2778 +}
2779 +
2780 +int __init ra2882eth_init(void)
2781 +{
2782 + int ret;
2783 + struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
2784 + if (!dev)
2785 + return -ENOMEM;
2786 +
2787 + strcpy(dev->name, DEV_NAME);
2788 + dev->irq = IRQ_ENET0;
2789 + dev->addr_len = 6;
2790 + dev->base_addr = RALINK_FRAME_ENGINE_BASE;
2791 +
2792 + rather_probe(dev);
2793 + ra2880_setup_dev_fptable(dev);
2794 +
2795 + if ( register_netdev(dev) != 0) {
2796 + printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
2797 + return -ENXIO;
2798 + }
2799 + ret = 0;
2800 +
2801 + dev_raether = dev;
2802 + return ret;
2803 +}
2804 +
2805 +void fe_sw_init(void)
2806 +{
2807 + setup_internal_gsw();
2808 +}
2809 +
2810 +
2811 +void ra2882eth_cleanup_module(void)
2812 +{
2813 +}
2814 +EXPORT_SYMBOL(set_fe_dma_glo_cfg);
2815 +module_init(ra2882eth_init);
2816 +module_exit(ra2882eth_cleanup_module);
2817 +MODULE_LICENSE("GPL");
2818 --- /dev/null
2819 +++ b/drivers/net/ethernet/raeth/raether.h
2820 @@ -0,0 +1,92 @@
2821 +#ifndef RA2882ETHEND_H
2822 +#define RA2882ETHEND_H
2823 +
2824 +#ifdef DSP_VIA_NONCACHEABLE
2825 +#define ESRAM_BASE 0xa0800000 /* 0x0080-0000 ~ 0x00807FFF */
2826 +#else
2827 +#define ESRAM_BASE 0x80800000 /* 0x0080-0000 ~ 0x00807FFF */
2828 +#endif
2829 +
2830 +#define RX_RING_BASE ((int)(ESRAM_BASE + 0x7000))
2831 +#define TX_RING_BASE ((int)(ESRAM_BASE + 0x7800))
2832 +
2833 +#if defined(CONFIG_RALINK_RT2880)
2834 +#define NUM_TX_RINGS 1
2835 +#else
2836 +#define NUM_TX_RINGS 4
2837 +#endif
2838 +#ifdef MEMORY_OPTIMIZATION
2839 +#ifdef CONFIG_RAETH_ROUTER
2840 +#define NUM_RX_DESC 128
2841 +#define NUM_TX_DESC 128
2842 +#elif CONFIG_RT_3052_ESW
2843 +#define NUM_RX_DESC 64
2844 +#define NUM_TX_DESC 64
2845 +#else
2846 +#define NUM_RX_DESC 128
2847 +#define NUM_TX_DESC 128
2848 +#endif
2849 +//#define NUM_RX_MAX_PROCESS 32
2850 +#define NUM_RX_MAX_PROCESS 64
2851 +#else
2852 +#if defined (CONFIG_RAETH_ROUTER)
2853 +#define NUM_RX_DESC 256
2854 +#define NUM_TX_DESC 256
2855 +#elif defined (CONFIG_RT_3052_ESW)
2856 +#define NUM_RX_DESC 256
2857 +#define NUM_TX_DESC 256
2858 +#else
2859 +#define NUM_RX_DESC 256
2860 +#define NUM_TX_DESC 256
2861 +#endif
2862 +#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620)
2863 +#define NUM_RX_MAX_PROCESS 2
2864 +#else
2865 +#define NUM_RX_MAX_PROCESS 16
2866 +#endif
2867 +#endif
2868 +
2869 +#define DEV_NAME "eth0"
2870 +#define DEV2_NAME "eth3"
2871 +
2872 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621)
2873 +#define GMAC0_OFFSET 0xE000
2874 +#define GMAC2_OFFSET 0xE006
2875 +#else
2876 +#define GMAC0_OFFSET 0x28
2877 +#define GMAC2_OFFSET 0x22
2878 +#endif
2879 +
2880 +#if defined(CONFIG_RALINK_RT6855A)
2881 +#define IRQ_ENET0 22
2882 +#else
2883 +#define IRQ_ENET0 11 /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */
2884 +#endif
2885 +
2886 +#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS))
2887 +#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg
2888 +
2889 +//#define RAETH_DEBUG
2890 +#ifdef RAETH_DEBUG
2891 +#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
2892 +#else
2893 +#define RAETH_PRINT(fmt, args...) { }
2894 +#endif
2895 +
2896 +struct net_device_stats *ra_get_stats(struct net_device *dev);
2897 +
2898 +void ei_tx_timeout(struct net_device *dev);
2899 +int rather_probe(struct net_device *dev);
2900 +int ei_open(struct net_device *dev);
2901 +int ei_close(struct net_device *dev);
2902 +
2903 +int ra2882eth_init(void);
2904 +void ra2882eth_cleanup_module(void);
2905 +
2906 +void ei_xmit_housekeeping(unsigned long data);
2907 +
2908 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
2909 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
2910 +void fe_sw_init(void);
2911 +
2912 +#endif
2913 --- /dev/null
2914 +++ b/drivers/net/ethernet/raeth/raether_pdma.c
2915 @@ -0,0 +1,212 @@
2916 +#include <linux/module.h>
2917 +#include <linux/version.h>
2918 +#include <linux/kernel.h>
2919 +#include <linux/types.h>
2920 +#include <linux/pci.h>
2921 +#include <linux/init.h>
2922 +#include <linux/skbuff.h>
2923 +#include <linux/if_vlan.h>
2924 +#include <linux/if_ether.h>
2925 +#include <linux/fs.h>
2926 +#include <asm/uaccess.h>
2927 +#include <linux/delay.h>
2928 +#include <linux/sched.h>
2929 +#include <asm/rt2880/rt_mmap.h>
2930 +#include "ra2882ethreg.h"
2931 +#include "raether.h"
2932 +#include "ra_mac.h"
2933 +
2934 +#define MAX_RX_LENGTH 1536
2935 +
2936 +extern int reg_dbg;
2937 +extern struct net_device *dev_raether;
2938 +static unsigned long tx_ring_full=0;
2939 +
2940 +#define KSEG1 0xa0000000
2941 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
2942 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
2943 +
2944 +extern void set_fe_dma_glo_cfg(void);
2945 +
2946 +int fe_dma_init(struct net_device *dev)
2947 +{
2948 +
2949 + int i;
2950 + unsigned int regVal;
2951 + END_DEVICE* ei_local = netdev_priv(dev);
2952 +
2953 + while(1)
2954 + {
2955 + regVal = sysRegRead(PDMA_GLO_CFG);
2956 + if((regVal & RX_DMA_BUSY))
2957 + {
2958 + printk("\n RX_DMA_BUSY !!! ");
2959 + continue;
2960 + }
2961 + if((regVal & TX_DMA_BUSY))
2962 + {
2963 + printk("\n TX_DMA_BUSY !!! ");
2964 + continue;
2965 + }
2966 + break;
2967 + }
2968 +
2969 + for (i=0;i<NUM_TX_DESC;i++){
2970 + ei_local->skb_free[i]=0;
2971 + }
2972 + ei_local->free_idx =0;
2973 + ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
2974 + printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
2975 +
2976 + for (i=0; i < NUM_TX_DESC; i++) {
2977 + memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
2978 + ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
2979 + ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
2980 +
2981 + }
2982 +
2983 + /* Initial RX Ring 0*/
2984 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
2985 + for (i = 0; i < NUM_RX_DESC; i++) {
2986 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
2987 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
2988 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
2989 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
2990 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
2991 + }
2992 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
2993 +
2994 +
2995 + regVal = sysRegRead(PDMA_GLO_CFG);
2996 + regVal &= 0x000000FF;
2997 + sysRegWrite(PDMA_GLO_CFG, regVal);
2998 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regVal);
2999 +
3000 + regVal=sysRegRead(PDMA_GLO_CFG);
3001 +
3002 + /* Tell the adapter where the TX/RX rings are located. */
3003 + sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
3004 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_BASE_PTR0", TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
3005 + sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
3006 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_MAX_CNT0", TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
3007 + sysRegWrite(TX_CTX_IDX0, 0);
3008 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_CTX_IDX0", TX_CTX_IDX0, 0);
3009 + sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
3010 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DTX_IDX0);
3011 +
3012 + sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
3013 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_BASE_PTR0", RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
3014 + sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
3015 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_MAX_CNT0", RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
3016 + sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
3017 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_CALC_IDX0", RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
3018 + sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
3019 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DRX_IDX0);
3020 +
3021 + set_fe_dma_glo_cfg();
3022 +
3023 + return 1;
3024 +}
3025 +
3026 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
3027 +{
3028 + unsigned int length=skb->len;
3029 + END_DEVICE* ei_local = netdev_priv(dev);
3030 + unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
3031 +
3032 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
3033 + {
3034 + ei_local->stat.tx_errors++;
3035 + }
3036 +
3037 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
3038 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
3039 + if (gmac_no == 1) {
3040 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
3041 + }else {
3042 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
3043 + }
3044 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
3045 + tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
3046 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
3047 + {
3048 + ei_local->stat.tx_errors++;
3049 + }
3050 + sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
3051 +
3052 + {
3053 + ei_local->stat.tx_packets++;
3054 + ei_local->stat.tx_bytes += length;
3055 + }
3056 +
3057 + return length;
3058 +}
3059 +
3060 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
3061 +{
3062 + END_DEVICE *ei_local = netdev_priv(dev);
3063 + unsigned long flags;
3064 + unsigned long tx_cpu_owner_idx;
3065 + unsigned int tx_cpu_owner_idx_next;
3066 + unsigned int num_of_txd;
3067 + unsigned int tx_cpu_owner_idx_next2;
3068 +
3069 + dev->trans_start = jiffies; /* save the timestamp */
3070 + spin_lock_irqsave(&ei_local->page_lock, flags);
3071 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
3072 +
3073 + tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0);
3074 + num_of_txd = 1;
3075 + tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC;
3076 +
3077 + if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
3078 + rt2880_eth_send(dev, skb, gmac_no);
3079 +
3080 + tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC;
3081 +
3082 + if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
3083 + }
3084 + }else {
3085 + ei_local->stat.tx_dropped++;
3086 + kfree_skb(skb);
3087 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
3088 + return 0;
3089 + }
3090 +
3091 + ei_local->skb_free[tx_cpu_owner_idx] = skb;
3092 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
3093 + return 0;
3094 +}
3095 +
3096 +void ei_xmit_housekeeping(unsigned long unused)
3097 +{
3098 + struct net_device *dev = dev_raether;
3099 + END_DEVICE *ei_local = netdev_priv(dev);
3100 + struct PDMA_txdesc *tx_desc;
3101 + unsigned long skb_free_idx;
3102 + unsigned long tx_dtx_idx __maybe_unused;
3103 + unsigned long reg_int_mask=0;
3104 +
3105 + tx_dtx_idx = sysRegRead(TX_DTX_IDX0);
3106 + tx_desc = ei_local->tx_ring0;
3107 + skb_free_idx = ei_local->free_idx;
3108 + if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
3109 + while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
3110 + dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
3111 + ei_local->skb_free[skb_free_idx]=0;
3112 + skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
3113 + }
3114 +
3115 + netif_wake_queue(dev);
3116 + tx_ring_full=0;
3117 + ei_local->free_idx = skb_free_idx;
3118 + }
3119 +
3120 + reg_int_mask=sysRegRead(FE_INT_ENABLE);
3121 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT);
3122 +}
3123 +
3124 +EXPORT_SYMBOL(ei_start_xmit);
3125 +EXPORT_SYMBOL(ei_xmit_housekeeping);
3126 +EXPORT_SYMBOL(fe_dma_init);
3127 +EXPORT_SYMBOL(rt2880_eth_send);
3128 --- /dev/null
3129 +++ b/drivers/net/ethernet/raeth/raether_qdma.c
3130 @@ -0,0 +1,805 @@
3131 +#include <linux/module.h>
3132 +#include <linux/version.h>
3133 +#include <linux/kernel.h>
3134 +#include <linux/types.h>
3135 +#include <linux/pci.h>
3136 +#include <linux/init.h>
3137 +#include <linux/skbuff.h>
3138 +#include <linux/if_vlan.h>
3139 +#include <linux/if_ether.h>
3140 +#include <linux/fs.h>
3141 +#include <asm/uaccess.h>
3142 +#include <asm/rt2880/surfboardint.h>
3143 +#if defined (CONFIG_RAETH_TSO)
3144 +#include <linux/tcp.h>
3145 +#include <net/ipv6.h>
3146 +#include <linux/ip.h>
3147 +#include <net/ip.h>
3148 +#include <net/tcp.h>
3149 +#include <linux/in.h>
3150 +#include <linux/ppp_defs.h>
3151 +#include <linux/if_pppox.h>
3152 +#endif
3153 +#include <linux/delay.h>
3154 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
3155 +#include <linux/sched.h>
3156 +#endif
3157 +
3158 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
3159 +#include <asm/rt2880/rt_mmap.h>
3160 +#else
3161 +#include <linux/libata-compat.h>
3162 +#endif
3163 +
3164 +#include "ra2882ethreg.h"
3165 +#include "raether.h"
3166 +#include "ra_mac.h"
3167 +#include "ra_ioctl.h"
3168 +#include "ra_rfrw.h"
3169 +#ifdef CONFIG_RAETH_NETLINK
3170 +#include "ra_netlink.h"
3171 +#endif
3172 +#if defined (CONFIG_RAETH_QOS)
3173 +#include "ra_qos.h"
3174 +#endif
3175 +
3176 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
3177 +#include "../../../net/nat/hw_nat/ra_nat.h"
3178 +#endif
3179 +
3180 +#if defined (TASKLET_WORKQUEUE_SW)
3181 +int init_schedule;
3182 +int working_schedule;
3183 +#endif
3184 +
3185 +
3186 +#if !defined(CONFIG_RA_NAT_NONE)
3187 +/* bruce+
3188 + */
3189 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
3190 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
3191 +#endif
3192 +
3193 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
3194 +/* Qwert+
3195 + */
3196 +#include <asm/mipsregs.h>
3197 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
3198 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
3199 +#endif /* CONFIG_RA_CLASSIFIER */
3200 +
3201 +#if defined (CONFIG_RALINK_RT3052_MP2)
3202 +int32_t mcast_rx(struct sk_buff * skb);
3203 +int32_t mcast_tx(struct sk_buff * skb);
3204 +#endif
3205 +
3206 +#ifdef RA_MTD_RW_BY_NUM
3207 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
3208 +#else
3209 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
3210 +#endif
3211 +
3212 +/* gmac driver feature set config */
3213 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
3214 +#undef DELAY_INT
3215 +#else
3216 +#define DELAY_INT 1
3217 +#endif
3218 +
3219 +//#define CONFIG_UNH_TEST
3220 +/* end of config */
3221 +
3222 +#if defined (CONFIG_RAETH_JUMBOFRAME)
3223 +#define MAX_RX_LENGTH 4096
3224 +#else
3225 +#define MAX_RX_LENGTH 1536
3226 +#endif
3227 +
3228 +extern struct net_device *dev_raether;
3229 +
3230 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
3231 +static int rx_dma_owner_idx1;
3232 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
3233 +static int rx_calc_idx1;
3234 +#endif
3235 +#endif
3236 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
3237 +static int rx_calc_idx0;
3238 +static unsigned long tx_cpu_owner_idx0=0;
3239 +#endif
3240 +static unsigned long tx_ring_full=0;
3241 +
3242 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
3243 +#include "ra_ethtool.h"
3244 +extern struct ethtool_ops ra_ethtool_ops;
3245 +#ifdef CONFIG_PSEUDO_SUPPORT
3246 +extern struct ethtool_ops ra_virt_ethtool_ops;
3247 +#endif // CONFIG_PSEUDO_SUPPORT //
3248 +#endif // (CONFIG_ETHTOOL //
3249 +
3250 +#ifdef CONFIG_RALINK_VISTA_BASIC
3251 +int is_switch_175c = 1;
3252 +#endif
3253 +
3254 +//skb->mark to queue mapping table
3255 +extern unsigned int M2Q_table[64];
3256 +
3257 +
3258 +#define KSEG1 0xa0000000
3259 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
3260 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
3261 +
3262 +extern void set_fe_dma_glo_cfg(void);
3263 +
3264 +
3265 +/**
3266 + *
3267 + * @brief: get the TXD index from its address
3268 + *
3269 + * @param: cpu_ptr
3270 + *
3271 + * @return: TXD index
3272 +*/
3273 +
3274 +static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
3275 +{
3276 + struct net_device *dev = dev_raether;
3277 + END_DEVICE *ei_local = netdev_priv(dev);
3278 + int ctx_offset;
3279 + ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
3280 + ctx_offset = (*cpu_ptr - ei_local->txd_pool);
3281 +
3282 + return ctx_offset;
3283 +}
3284 +
3285 +
3286 +
3287 +/**
3288 + * @brief get free TXD from TXD queue
3289 + *
3290 + * @param free_txd
3291 + *
3292 + * @return
3293 + */
3294 +static int get_free_txd(struct QDMA_txdesc **free_txd)
3295 +{
3296 + struct net_device *dev = dev_raether;
3297 + END_DEVICE *ei_local = netdev_priv(dev);
3298 + unsigned int tmp_idx;
3299 +
3300 + if(ei_local->free_txd_num > 0){
3301 + tmp_idx = ei_local->free_txd_head;
3302 + ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
3303 + ei_local->free_txd_num -= 1;
3304 + *free_txd = &ei_local->txd_pool[tmp_idx];
3305 + return tmp_idx;
3306 + }else
3307 + return NUM_TX_DESC;
3308 +}
3309 +
3310 +
3311 +/**
3312 + * @brief add free TXD into TXD queue
3313 + *
3314 + * @param free_txd
3315 + *
3316 + * @return
3317 + */
3318 +int put_free_txd(int free_txd_idx)
3319 +{
3320 + struct net_device *dev = dev_raether;
3321 + END_DEVICE *ei_local = netdev_priv(dev);
3322 + ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
3323 + ei_local->free_txd_tail = free_txd_idx;
3324 + ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
3325 + ei_local->free_txd_num += 1;
3326 + return 1;
3327 +}
3328 +
3329 +/*define qdma initial alloc*/
3330 +/**
3331 + * @brief
3332 + *
3333 + * @param net_dev
3334 + *
3335 + * @return 0: fail
3336 + * 1: success
3337 + */
3338 +bool qdma_tx_desc_alloc(void)
3339 +{
3340 + struct net_device *dev = dev_raether;
3341 + END_DEVICE *ei_local = netdev_priv(dev);
3342 + struct QDMA_txdesc *free_txd = NULL;
3343 + unsigned int txd_idx;
3344 + int i = 0;
3345 +
3346 +
3347 + ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
3348 + printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
3349 +
3350 + if (ei_local->txd_pool == NULL) {
3351 + printk("adapter->txd_pool allocation failed!\n");
3352 + return 0;
3353 + }
3354 + printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
3355 + //set all txd_pool_info to 0.
3356 + for ( i = 0; i < NUM_TX_DESC; i++)
3357 + {
3358 + ei_local->skb_free[i]= 0;
3359 + ei_local->txd_pool_info[i] = i + 1;
3360 + ei_local->txd_pool[i].txd_info3.LS_bit = 1;
3361 + ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
3362 + }
3363 +
3364 + ei_local->free_txd_head = 0;
3365 + ei_local->free_txd_tail = NUM_TX_DESC - 1;
3366 + ei_local->free_txd_num = NUM_TX_DESC;
3367 +
3368 +
3369 + //get free txd from txd pool
3370 + txd_idx = get_free_txd(&free_txd);
3371 + if( txd_idx == NUM_TX_DESC) {
3372 + printk("get_free_txd fail\n");
3373 + return 0;
3374 + }
3375 +
3376 + //add null TXD for transmit
3377 + ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd);
3378 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
3379 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
3380 + sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
3381 +
3382 + //get free txd from txd pool
3383 +
3384 + txd_idx = get_free_txd(&free_txd);
3385 + if( txd_idx == NUM_TX_DESC) {
3386 + printk("get_free_txd fail\n");
3387 + return 0;
3388 + }
3389 + // add null TXD for release
3390 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd));
3391 + sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd));
3392 +
3393 + printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
3394 +
3395 + printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n");
3396 + printk("----------------+---------+--------\n");
3397 +#if 1
3398 + printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool,
3399 + ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
3400 +#endif
3401 + return 1;
3402 +}
3403 +
3404 +bool fq_qdma_init(void)
3405 +{
3406 + struct QDMA_txdesc *free_head = NULL;
3407 + unsigned int free_head_phy;
3408 + unsigned int free_tail_phy;
3409 + unsigned int *free_page_head = NULL;
3410 + unsigned int free_page_head_phy;
3411 + int i;
3412 +
3413 + free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy);
3414 + if (unlikely(free_head == NULL)){
3415 + printk(KERN_ERR "QDMA FQ decriptor not available...\n");
3416 + return 0;
3417 + }
3418 + memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
3419 +
3420 + free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy);
3421 + if (unlikely(free_page_head == NULL)){
3422 + printk(KERN_ERR "QDMA FQ pager not available...\n");
3423 + return 0;
3424 + }
3425 + for (i=0; i < NUM_QDMA_PAGE; i++) {
3426 + free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE));
3427 + if(i < (NUM_QDMA_PAGE-1)){
3428 + free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc)));
3429 +
3430 +
3431 +#if 0
3432 + printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
3433 + printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
3434 + printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
3435 + printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
3436 +#endif
3437 + }
3438 + free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
3439 +
3440 + }
3441 + free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
3442 +
3443 + printk("free_head_phy is 0x%x!!!\n", free_head_phy);
3444 + printk("free_tail_phy is 0x%x!!!\n", free_tail_phy);
3445 + sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy);
3446 + sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy);
3447 + sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
3448 + sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
3449 + return 1;
3450 +}
3451 +
3452 +int fe_dma_init(struct net_device *dev)
3453 +{
3454 +
3455 + int i;
3456 + unsigned int regVal;
3457 + END_DEVICE* ei_local = netdev_priv(dev);
3458 +
3459 + fq_qdma_init();
3460 +
3461 + while(1)
3462 + {
3463 + regVal = sysRegRead(QDMA_GLO_CFG);
3464 + if((regVal & RX_DMA_BUSY))
3465 + {
3466 + printk("\n RX_DMA_BUSY !!! ");
3467 + continue;
3468 + }
3469 + if((regVal & TX_DMA_BUSY))
3470 + {
3471 + printk("\n TX_DMA_BUSY !!! ");
3472 + continue;
3473 + }
3474 + break;
3475 + }
3476 + /*tx desc alloc, add a NULL TXD to HW*/
3477 +
3478 + qdma_tx_desc_alloc();
3479 +
3480 +
3481 + /* Initial RX Ring 0*/
3482 +#ifdef CONFIG_32B_DESC
3483 + ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
3484 + ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
3485 +#else
3486 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
3487 +#endif
3488 + for (i = 0; i < NUM_RX_DESC; i++) {
3489 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
3490 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
3491 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
3492 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
3493 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
3494 +#else
3495 + ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
3496 +#endif
3497 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
3498 + }
3499 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
3500 +
3501 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
3502 + /* Initial RX Ring 1*/
3503 +#ifdef CONFIG_32B_DESC
3504 + ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
3505 + ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
3506 +#else
3507 + ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
3508 +#endif
3509 + for (i = 0; i < NUM_RX_DESC; i++) {
3510 + memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
3511 + ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
3512 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
3513 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
3514 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
3515 +#else
3516 + ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
3517 +#endif
3518 + ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
3519 + }
3520 + printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
3521 +#endif
3522 +
3523 + regVal = sysRegRead(QDMA_GLO_CFG);
3524 + regVal &= 0x000000FF;
3525 + sysRegWrite(QDMA_GLO_CFG, regVal);
3526 + regVal=sysRegRead(QDMA_GLO_CFG);
3527 +
3528 + /* Tell the adapter where the TX/RX rings are located. */
3529 +
3530 + sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0));
3531 + sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_RX_DESC));
3532 + sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
3533 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
3534 + rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0);
3535 +#endif
3536 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
3537 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
3538 + sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1));
3539 + sysRegWrite(QRX_MAX_CNT_1, cpu_to_le32((u32) NUM_RX_DESC));
3540 + sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
3541 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
3542 + rx_calc_idx1 = rx_dma_owner_idx1 = sysRegRead(QRX_CRX_IDX_1);
3543 +#endif
3544 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1);
3545 +#endif
3546 +
3547 + set_fe_dma_glo_cfg();
3548 +
3549 + return 1;
3550 +}
3551 +
3552 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
3553 +{
3554 + unsigned int length=skb->len;
3555 + END_DEVICE* ei_local = netdev_priv(dev);
3556 +
3557 + struct QDMA_txdesc *cpu_ptr;
3558 +
3559 + struct QDMA_txdesc *dma_ptr __maybe_unused;
3560 + struct QDMA_txdesc *free_txd;
3561 + int ctx_offset;
3562 +#if defined (CONFIG_RAETH_TSO)
3563 + struct iphdr *iph = NULL;
3564 + struct QDMA_txdesc *init_cpu_ptr;
3565 + struct tcphdr *th = NULL;
3566 + struct skb_frag_struct *frag;
3567 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3568 + int i=0;
3569 + int init_txd_idx;
3570 +#endif // CONFIG_RAETH_TSO //
3571 +
3572 +#if defined (CONFIG_RAETH_TSOV6)
3573 + struct ipv6hdr *ip6h = NULL;
3574 +#endif
3575 +
3576 +#ifdef CONFIG_PSEUDO_SUPPORT
3577 + PSEUDO_ADAPTER *pAd;
3578 +#endif
3579 + cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr);
3580 + dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr);
3581 + ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
3582 + ei_local->skb_free[ctx_offset] = skb;
3583 +#if defined (CONFIG_RAETH_TSO)
3584 + init_cpu_ptr = cpu_ptr;
3585 + init_txd_idx = ctx_offset;
3586 +#endif
3587 +
3588 +#if !defined (CONFIG_RAETH_TSO)
3589 +
3590 + //2. prepare data
3591 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
3592 + cpu_ptr->txd_info3.SDL = skb->len;
3593 +
3594 + if (gmac_no == 1) {
3595 + cpu_ptr->txd_info4.FPORT = 1;
3596 + }else {
3597 + cpu_ptr->txd_info4.FPORT = 2;
3598 + }
3599 +
3600 +
3601 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
3602 +#if 0
3603 + iph = (struct iphdr *)skb_network_header(skb);
3604 + if (iph->tos == 0xe0)
3605 + cpu_ptr->txd_info3.QID = 3;
3606 + else if (iph->tos == 0xa0)
3607 + cpu_ptr->txd_info3.QID = 2;
3608 + else if (iph->tos == 0x20)
3609 + cpu_ptr->txd_info3.QID = 1;
3610 + else
3611 + cpu_ptr->txd_info3.QID = 0;
3612 +#endif
3613 +
3614 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3615 + if (skb->ip_summed == CHECKSUM_PARTIAL){
3616 + cpu_ptr->txd_info4.TUI_CO = 7;
3617 + }else {
3618 + cpu_ptr->txd_info4.TUI_CO = 0;
3619 + }
3620 +#endif
3621 +
3622 +#ifdef CONFIG_RAETH_HW_VLAN_TX
3623 + if(vlan_tx_tag_present(skb)) {
3624 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
3625 + }else {
3626 + cpu_ptr->txd_info4.VLAN_TAG = 0;
3627 + }
3628 +#endif
3629 +
3630 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
3631 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
3632 + if(ra_sw_nat_hook_rx!= NULL){
3633 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
3634 + FOE_MAGIC_TAG(skb) = 0;
3635 + }
3636 + }
3637 +#endif
3638 +#if 0
3639 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
3640 + cpu_ptr->txd_info4.UDF = 0x2F;
3641 +#endif
3642 +
3643 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
3644 + cpu_ptr->txd_info3.SWC_bit = 1;
3645 +
3646 + //3. get NULL TXD and decrease free_tx_num by 1.
3647 + ctx_offset = get_free_txd(&free_txd);
3648 + if(ctx_offset == NUM_TX_DESC) {
3649 + printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
3650 + return 0;
3651 + }
3652 +
3653 + //4. hook new TXD in the end of queue
3654 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
3655 +
3656 +
3657 + //5. move CPU_PTR to new TXD
3658 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
3659 + cpu_ptr->txd_info3.OWN_bit = 0;
3660 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
3661 +
3662 +#if 0
3663 + printk("----------------------------------------------\n");
3664 + printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
3665 + printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
3666 + printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
3667 + printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
3668 +#endif
3669 +
3670 +#else //#if !defined (CONFIG_RAETH_TSO)
3671 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
3672 + cpu_ptr->txd_info3.SDL = (length - skb->data_len);
3673 + cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
3674 + if (gmac_no == 1) {
3675 + cpu_ptr->txd_info4.FPORT = 1;
3676 + }else {
3677 + cpu_ptr->txd_info4.FPORT = 2;
3678 + }
3679 +
3680 + cpu_ptr->txd_info4.TSO = 0;
3681 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
3682 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3683 + if (skb->ip_summed == CHECKSUM_PARTIAL){
3684 + cpu_ptr->txd_info4.TUI_CO = 7;
3685 + }else {
3686 + cpu_ptr->txd_info4.TUI_CO = 0;
3687 + }
3688 +#endif
3689 +
3690 +#ifdef CONFIG_RAETH_HW_VLAN_TX
3691 + if(vlan_tx_tag_present(skb)) {
3692 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
3693 + }else {
3694 + cpu_ptr->txd_info4.VLAN_TAG = 0;
3695 + }
3696 +#endif
3697 +
3698 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
3699 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
3700 + if(ra_sw_nat_hook_rx!= NULL){
3701 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
3702 + FOE_MAGIC_TAG(skb) = 0;
3703 + }
3704 + }
3705 +#endif
3706 +
3707 + cpu_ptr->txd_info3.SWC_bit = 1;
3708 +
3709 + ctx_offset = get_free_txd(&free_txd);
3710 + if(ctx_offset == NUM_TX_DESC) {
3711 + printk("get_free_txd fail\n");
3712 + return 0;
3713 + }
3714 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
3715 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
3716 +
3717 + if(nr_frags > 0) {
3718 + for(i=0;i<nr_frags;i++) {
3719 + frag = &skb_shinfo(skb)->frags[i];
3720 + cpu_ptr = free_txd;
3721 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
3722 + cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
3723 + cpu_ptr->txd_info3.SDL = frag->size;
3724 + cpu_ptr->txd_info3.LS_bit = (i==nr_frags-1)?1:0;
3725 + cpu_ptr->txd_info3.OWN_bit = 0;
3726 + cpu_ptr->txd_info3.SWC_bit = 1;
3727 + ei_local->skb_free[ctx_offset] = (i==nr_frags-1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID
3728 +
3729 + ctx_offset = get_free_txd(&free_txd);
3730 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
3731 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
3732 + }
3733 + ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID
3734 + }
3735 +
3736 + if(skb_shinfo(skb)->gso_segs > 1) {
3737 +
3738 +// TsoLenUpdate(skb->len);
3739 +
3740 + /* TCP over IPv4 */
3741 + iph = (struct iphdr *)skb_network_header(skb);
3742 +#if defined (CONFIG_RAETH_TSOV6)
3743 + /* TCP over IPv6 */
3744 + ip6h = (struct ipv6hdr *)skb_network_header(skb);
3745 +#endif
3746 + if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
3747 + th = (struct tcphdr *)skb_transport_header(skb);
3748 +
3749 + init_cpu_ptr->txd_info4.TSO = 1;
3750 +
3751 + th->check = htons(skb_shinfo(skb)->gso_size);
3752 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3753 + }
3754 +
3755 +#if defined (CONFIG_RAETH_TSOV6)
3756 + /* TCP over IPv6 */
3757 + //ip6h = (struct ipv6hdr *)skb_network_header(skb);
3758 + else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
3759 + th = (struct tcphdr *)skb_transport_header(skb);
3760 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
3761 + init_cpu_ptr->txd_info4.TSO = 1;
3762 +#else
3763 + init_cpu_ptr->txd_info4.TSO = 1;
3764 +#endif
3765 + th->check = htons(skb_shinfo(skb)->gso_size);
3766 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3767 + }
3768 +#endif
3769 + }
3770 +
3771 +
3772 +// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
3773 +
3774 + init_cpu_ptr->txd_info3.OWN_bit = 0;
3775 +#endif // CONFIG_RAETH_TSO //
3776 +
3777 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
3778 +
3779 +#ifdef CONFIG_PSEUDO_SUPPORT
3780 + if (gmac_no == 2) {
3781 + if (ei_local->PseudoDev != NULL) {
3782 + pAd = netdev_priv(ei_local->PseudoDev);
3783 + pAd->stat.tx_packets++;
3784 + pAd->stat.tx_bytes += length;
3785 + }
3786 + } else
3787 +
3788 +#endif
3789 + {
3790 + ei_local->stat.tx_packets++;
3791 + ei_local->stat.tx_bytes += skb->len;
3792 + }
3793 + return length;
3794 +}
3795 +
3796 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
3797 +{
3798 + END_DEVICE *ei_local = netdev_priv(dev);
3799 + unsigned long flags;
3800 + unsigned int num_of_txd;
3801 +#if defined (CONFIG_RAETH_TSO)
3802 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3803 +#endif
3804 +#ifdef CONFIG_PSEUDO_SUPPORT
3805 + PSEUDO_ADAPTER *pAd;
3806 +#endif
3807 +
3808 +#if !defined(CONFIG_RA_NAT_NONE)
3809 + if(ra_sw_nat_hook_tx!= NULL)
3810 + {
3811 + spin_lock_irqsave(&ei_local->page_lock, flags);
3812 + if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
3813 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
3814 + }else{
3815 + kfree_skb(skb);
3816 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
3817 + return 0;
3818 + }
3819 + }
3820 +#endif
3821 +
3822 +
3823 +
3824 + dev->trans_start = jiffies; /* save the timestamp */
3825 + spin_lock_irqsave(&ei_local->page_lock, flags);
3826 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
3827 +
3828 +
3829 +//check free_txd_num before calling rt288_eth_send()
3830 +
3831 +#if defined (CONFIG_RAETH_TSO)
3832 + num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
3833 +#else
3834 + num_of_txd = 1;
3835 +#endif
3836 +
3837 +#if defined(CONFIG_RALINK_MT7621)
3838 + if(sysRegRead(0xbe00000c)==0x00030101) {
3839 + ei_xmit_housekeeping(0);
3840 + }
3841 +#endif
3842 +
3843 +
3844 + if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
3845 + {
3846 + rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
3847 + if (ei_local->free_txd_num < 3)
3848 + {
3849 +#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
3850 + netif_stop_queue(dev);
3851 +#ifdef CONFIG_PSEUDO_SUPPORT
3852 + netif_stop_queue(ei_local->PseudoDev);
3853 +#endif
3854 + tx_ring_full = 1;
3855 +#endif
3856 + }
3857 + } else {
3858 +#ifdef CONFIG_PSEUDO_SUPPORT
3859 + if (gmac_no == 2)
3860 + {
3861 + if (ei_local->PseudoDev != NULL)
3862 + {
3863 + pAd = netdev_priv(ei_local->PseudoDev);
3864 + pAd->stat.tx_dropped++;
3865 + }
3866 + } else
3867 +#endif
3868 + ei_local->stat.tx_dropped++;
3869 + kfree_skb(skb);
3870 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
3871 + return 0;
3872 + }
3873 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
3874 + return 0;
3875 +}
3876 +
3877 +void ei_xmit_housekeeping(unsigned long unused)
3878 +{
3879 + struct net_device *dev = dev_raether;
3880 + END_DEVICE *ei_local = netdev_priv(dev);
3881 +#ifndef CONFIG_RAETH_NAPI
3882 + unsigned long reg_int_mask=0;
3883 +#endif
3884 + struct QDMA_txdesc *dma_ptr = NULL;
3885 + struct QDMA_txdesc *cpu_ptr = NULL;
3886 + struct QDMA_txdesc *tmp_ptr = NULL;
3887 + unsigned int htx_offset = 0;
3888 +
3889 + dma_ptr = PHYS_TO_VIRT(sysRegRead(QTX_DRX_PTR));
3890 + cpu_ptr = PHYS_TO_VIRT(sysRegRead(QTX_CRX_PTR));
3891 + if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
3892 + while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
3893 +
3894 + //1. keep cpu next TXD
3895 + tmp_ptr = PHYS_TO_VIRT(cpu_ptr->txd_info2.NDP);
3896 + htx_offset = GET_TXD_OFFSET(&tmp_ptr);
3897 + //2. free skb meomry
3898 +#if defined (CONFIG_RAETH_TSO)
3899 + if(ei_local->skb_free[htx_offset]!=(struct sk_buff *)0xFFFFFFFF) {
3900 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
3901 + }
3902 +#else
3903 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
3904 +#endif
3905 +
3906 + //3. release TXD
3907 + htx_offset = GET_TXD_OFFSET(&cpu_ptr);
3908 + put_free_txd(htx_offset);
3909 +
3910 + netif_wake_queue(dev);
3911 +#ifdef CONFIG_PSEUDO_SUPPORT
3912 + netif_wake_queue(ei_local->PseudoDev);
3913 +#endif
3914 + tx_ring_full=0;
3915 +
3916 + //4. update cpu_ptr to next ptr
3917 + cpu_ptr = tmp_ptr;
3918 + }
3919 + }
3920 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(cpu_ptr));
3921 +#ifndef CONFIG_RAETH_NAPI
3922 + reg_int_mask=sysRegRead(QFE_INT_ENABLE);
3923 +#if defined (DELAY_INT)
3924 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
3925 +#else
3926 +
3927 + sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
3928 +#endif
3929 +#endif //CONFIG_RAETH_NAPI//
3930 +}
3931 +
3932 +EXPORT_SYMBOL(ei_start_xmit);
3933 +EXPORT_SYMBOL(ei_xmit_housekeeping);
3934 +EXPORT_SYMBOL(fe_dma_init);
3935 +EXPORT_SYMBOL(rt2880_eth_send);
3936 --- a/drivers/net/ethernet/Kconfig
3937 +++ b/drivers/net/ethernet/Kconfig
3938 @@ -136,6 +136,7 @@ source "drivers/net/ethernet/packetengin
3939 source "drivers/net/ethernet/pasemi/Kconfig"
3940 source "drivers/net/ethernet/qlogic/Kconfig"
3941 source "drivers/net/ethernet/ralink/Kconfig"
3942 +source "drivers/net/ethernet/raeth/Kconfig"
3943 source "drivers/net/ethernet/realtek/Kconfig"
3944 source "drivers/net/ethernet/renesas/Kconfig"
3945 source "drivers/net/ethernet/rdc/Kconfig"
3946 --- a/drivers/net/ethernet/Makefile
3947 +++ b/drivers/net/ethernet/Makefile
3948 @@ -54,6 +54,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe
3949 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
3950 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
3951 obj-$(CONFIG_NET_RALINK) += ralink/
3952 +obj-$(CONFIG_RAETH) += raeth/
3953 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
3954 obj-$(CONFIG_SH_ETH) += renesas/
3955 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
3956 --- /dev/null
3957 +++ b/arch/mips/include/asm/rt2880/board-custom.h
3958 @@ -0,0 +1,153 @@
3959 +/* Copyright Statement:
3960 + *
3961 + * This software/firmware and related documentation ("MediaTek Software") are
3962 + * protected under relevant copyright laws. The information contained herein
3963 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
3964 + * Without the prior written permission of MediaTek inc. and/or its licensors,
3965 + * any reproduction, modification, use or disclosure of MediaTek Software,
3966 + * and information contained herein, in whole or in part, shall be strictly prohibited.
3967 + */
3968 +/* MediaTek Inc. (C) 2010. All rights reserved.
3969 + *
3970 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
3971 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
3972 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
3973 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
3974 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
3975 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
3976 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
3977 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
3978 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
3979 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
3980 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
3981 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
3982 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
3983 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
3984 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
3985 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
3986 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
3987 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
3988 + *
3989 + * The following software/firmware and/or related documentation ("MediaTek Software")
3990 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
3991 + * applicable license agreements with MediaTek Inc.
3992 + */
3993 +
3994 +#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
3995 +#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
3996 +
3997 +#include <linux/autoconf.h>
3998 +
3999 +/*=======================================================================*/
4000 +/* MT6575 SD */
4001 +/*=======================================================================*/
4002 +#ifdef MTK_EMMC_SUPPORT
4003 +#define CFG_DEV_MSDC0
4004 +#endif
4005 +#define CFG_DEV_MSDC1
4006 +#define CFG_DEV_MSDC2
4007 +#define CFG_DEV_MSDC3
4008 +#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
4009 +/*
4010 +SDIO slot index number used by connectivity combo chip:
4011 +0: invalid (used by memory card)
4012 +1: MSDC1
4013 +2: MSDC2
4014 +*/
4015 +#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
4016 +#else
4017 +#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
4018 +#endif
4019 +
4020 +#if 0 /* FIXME. */
4021 +/*=======================================================================*/
4022 +/* MT6575 UART */
4023 +/*=======================================================================*/
4024 +#define CFG_DEV_UART1
4025 +#define CFG_DEV_UART2
4026 +#define CFG_DEV_UART3
4027 +#define CFG_DEV_UART4
4028 +
4029 +#define CFG_UART_PORTS (4)
4030 +
4031 +/*=======================================================================*/
4032 +/* MT6575 I2C */
4033 +/*=======================================================================*/
4034 +#define CFG_DEV_I2C
4035 +//#define CFG_I2C_HIGH_SPEED_MODE
4036 +//#define CFG_I2C_DMA_MODE
4037 +
4038 +/*=======================================================================*/
4039 +/* MT6575 ADB */
4040 +/*=======================================================================*/
4041 +#define ADB_SERIAL "E1K"
4042 +
4043 +#endif
4044 +
4045 +/*=======================================================================*/
4046 +/* MT6575 NAND FLASH */
4047 +/*=======================================================================*/
4048 +#if 0
4049 +#define RAMDOM_READ 1<<0
4050 +#define CACHE_READ 1<<1
4051 +/*******************************************************************************
4052 + * NFI & ECC Configuration
4053 + *******************************************************************************/
4054 +typedef struct
4055 +{
4056 + u16 id; //deviceid+menuid
4057 + u8 addr_cycle;
4058 + u8 iowidth;
4059 + u16 totalsize;
4060 + u16 blocksize;
4061 + u16 pagesize;
4062 + u32 timmingsetting;
4063 + char devciename[14];
4064 + u32 advancedmode; //
4065 +}flashdev_info,*pflashdev_info;
4066 +
4067 +static const flashdev_info g_FlashTable[]={
4068 + //micro
4069 + {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
4070 + {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
4071 + {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
4072 + {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
4073 + {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
4074 + //samsung
4075 + {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
4076 + {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
4077 + {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
4078 + {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
4079 + {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
4080 + //hynix
4081 + {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
4082 + {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
4083 + {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
4084 + {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
4085 + //toshiba
4086 + {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
4087 + {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
4088 + {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
4089 + {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
4090 + //st-micro
4091 + {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
4092 +
4093 + // elpida
4094 + {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
4095 + {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
4096 +};
4097 +#endif
4098 +
4099 +
4100 +#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
4101 +
4102 +//uboot only support 1 cs
4103 +#define NFI_CS_NUM (2)
4104 +#define NFI_DEFAULT_CS (0)
4105 +
4106 +#define USE_AHB_MODE (1)
4107 +
4108 +#define PLATFORM_EVB (1)
4109 +
4110 +#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
4111 +
4112 --- /dev/null
4113 +++ b/arch/mips/include/asm/rt2880/eureka_ep430.h
4114 @@ -0,0 +1,204 @@
4115 +/**************************************************************************
4116 + *
4117 + * This program is free software; you can redistribute it and/or modify it
4118 + * under the terms of the GNU General Public License as published by the
4119 + * Free Software Foundation; either version 2 of the License, or (at your
4120 + * option) any later version.
4121 + *
4122 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4123 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4124 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4125 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4126 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4127 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4128 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4129 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4130 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4131 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4132 + *
4133 + * You should have received a copy of the GNU General Public License along
4134 + * with this program; if not, write to the Free Software Foundation, Inc.,
4135 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4136 + *
4137 + *
4138 + **************************************************************************
4139 + */
4140 +
4141 +#ifndef _EUREKA_EP430_H
4142 +#define _EUREKA_EP430_H
4143 +
4144 +
4145 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
4146 +#include <asm/byteorder.h> /* for cpu_to_le32() */
4147 +#include <asm/mach-ralink/rt_mmap.h>
4148 +
4149 +
4150 +/*
4151 + * Because of an error/peculiarity in the Galileo chip, we need to swap the
4152 + * bytes when running bigendian.
4153 + */
4154 +
4155 +#define MV_WRITE(ofs, data) \
4156 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
4157 +#define MV_READ(ofs, data) \
4158 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
4159 +#define MV_READ_DATA(ofs) \
4160 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
4161 +
4162 +#define MV_WRITE_16(ofs, data) \
4163 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
4164 +#define MV_READ_16(ofs, data) \
4165 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
4166 +
4167 +#define MV_WRITE_8(ofs, data) \
4168 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
4169 +#define MV_READ_8(ofs, data) \
4170 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
4171 +
4172 +#define MV_SET_REG_BITS(ofs,bits) \
4173 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
4174 +#define MV_RESET_REG_BITS(ofs,bits) \
4175 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
4176 +
4177 +#define RALINK_PCI_CONFIG_ADDR 0x20
4178 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
4179 +
4180 +#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
4181 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
4182 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
4183 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
4184 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
4185 +#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
4186 +#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
4187 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
4188 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
4189 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
4190 +#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
4191 +#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
4192 +#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
4193 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
4194 +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
4195 +
4196 +#elif defined(CONFIG_RALINK_RT3883)
4197 +
4198 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
4199 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
4200 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
4201 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
4202 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
4203 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
4204 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
4205 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
4206 +
4207 +/*
4208 +PCI0 --> PCI
4209 +PCI1 --> PCIe
4210 +*/
4211 +#define RT3883_PCI_OFFSET 0x1000
4212 +#define RT3883_PCIE_OFFSET 0x2000
4213 +
4214 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
4215 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
4216 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
4217 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
4218 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
4219 +
4220 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
4221 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
4222 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
4223 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
4224 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
4225 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
4226 +
4227 +#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
4228 +
4229 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
4230 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
4231 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
4232 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
4233 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
4234 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
4235 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
4236 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
4237 +
4238 +/*
4239 +PCI0 --> PCIe 0
4240 +PCI1 --> PCIe 1
4241 +*/
4242 +#define RT6855_PCIE0_OFFSET 0x2000
4243 +#define RT6855_PCIE1_OFFSET 0x3000
4244 +
4245 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
4246 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
4247 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
4248 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
4249 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
4250 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
4251 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
4252 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
4253 +
4254 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
4255 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
4256 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
4257 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
4258 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
4259 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
4260 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
4261 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
4262 +
4263 +#elif defined (CONFIG_RALINK_MT7621)
4264 +
4265 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
4266 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
4267 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
4268 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
4269 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
4270 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
4271 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
4272 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
4273 +
4274 +/*
4275 +PCI0 --> PCIe 0
4276 +PCI1 --> PCIe 1
4277 +PCI2 --> PCIe 2
4278 +*/
4279 +#define RT6855_PCIE0_OFFSET 0x2000
4280 +#define RT6855_PCIE1_OFFSET 0x3000
4281 +#define RT6855_PCIE2_OFFSET 0x4000
4282 +
4283 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
4284 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
4285 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
4286 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
4287 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
4288 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
4289 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
4290 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
4291 +
4292 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
4293 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
4294 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
4295 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
4296 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
4297 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
4298 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
4299 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
4300 +
4301 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
4302 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
4303 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
4304 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
4305 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
4306 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
4307 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
4308 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
4309 +
4310 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
4311 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
4312 +
4313 +#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
4314 +#else
4315 +#error "undefined in PCI"
4316 +#endif
4317 +
4318 +#endif
4319 --- /dev/null
4320 +++ b/arch/mips/include/asm/rt2880/generic.h
4321 @@ -0,0 +1,42 @@
4322 +/*
4323 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
4324 + *
4325 + * This program is free software; you can distribute it and/or modify it
4326 + * under the terms of the GNU General Public License (Version 2) as
4327 + * published by the Free Software Foundation.
4328 + *
4329 + * This program is distributed in the hope it will be useful, but WITHOUT
4330 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4331 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4332 + * for more details.
4333 + *
4334 + * You should have received a copy of the GNU General Public License along
4335 + * with this program; if not, write to the Free Software Foundation, Inc.,
4336 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4337 + *
4338 + * Defines of the Palmchip boards specific address-MAP, registers, etc.
4339 + */
4340 +#ifndef __ASM_SURFBOARD_GENERIC_H
4341 +#define __ASM_SURFBOARD_GENERIC_H
4342 +
4343 +#include <asm/addrspace.h>
4344 +#include <asm/byteorder.h>
4345 +#include <asm/mach-ralink/rt_mmap.h>
4346 +
4347 +/*
4348 + * Reset register.
4349 + */
4350 +#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
4351 +#define GORESET (0x1)
4352 +
4353 +/*
4354 + * Power-off register
4355 + */
4356 +#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
4357 +#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
4358 +#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
4359 +#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
4360 +#define POWEROFF (0x0) /* drive low */
4361 +
4362 +
4363 +#endif /* __ASM_SURFBOARD_GENERIC_H */
4364 --- /dev/null
4365 +++ b/arch/mips/include/asm/rt2880/lm.h
4366 @@ -0,0 +1,32 @@
4367 +#include <linux/version.h>
4368 +
4369 +struct lm_device {
4370 + struct device dev;
4371 + struct resource resource;
4372 + unsigned int irq;
4373 + unsigned int id;
4374 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
4375 + void *lm_drvdata;
4376 +#endif
4377 +};
4378 +
4379 +struct lm_driver {
4380 + struct device_driver drv;
4381 + int (*probe)(struct lm_device *);
4382 + void (*remove)(struct lm_device *);
4383 + int (*suspend)(struct lm_device *, u32);
4384 + int (*resume)(struct lm_device *);
4385 +};
4386 +
4387 +int lm_driver_register(struct lm_driver *drv);
4388 +void lm_driver_unregister(struct lm_driver *drv);
4389 +
4390 +int lm_device_register(struct lm_device *dev);
4391 +
4392 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
4393 +# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
4394 +# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
4395 +#else
4396 +# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
4397 +# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
4398 +#endif
4399 --- /dev/null
4400 +++ b/arch/mips/include/asm/rt2880/prom.h
4401 @@ -0,0 +1,50 @@
4402 +/*
4403 + * Carsten Langgaard, carstenl@mips.com
4404 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4405 + *
4406 + * ########################################################################
4407 + *
4408 + * This program is free software; you can distribute it and/or modify it
4409 + * under the terms of the GNU General Public License (Version 2) as
4410 + * published by the Free Software Foundation.
4411 + *
4412 + * This program is distributed in the hope it will be useful, but WITHOUT
4413 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4414 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4415 + * for more details.
4416 + *
4417 + * You should have received a copy of the GNU General Public License along
4418 + * with this program; if not, write to the Free Software Foundation, Inc.,
4419 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4420 + *
4421 + * ########################################################################
4422 + *
4423 + * MIPS boards bootprom interface for the Linux kernel.
4424 + *
4425 + */
4426 +
4427 +#ifndef _MIPS_PROM_H
4428 +#define _MIPS_PROM_H
4429 +
4430 +extern char *prom_getcmdline(void);
4431 +extern char *prom_getenv(char *name);
4432 +extern void setup_prom_printf(int tty_no);
4433 +extern void prom_setup_printf(int tty_no);
4434 +extern void prom_printf(char *fmt, ...);
4435 +extern void prom_init_cmdline(void);
4436 +extern void prom_meminit(void);
4437 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
4438 +extern void prom_free_prom_memory (void);
4439 +extern void mips_display_message(const char *str);
4440 +extern void mips_display_word(unsigned int num);
4441 +extern int get_ethernet_addr(char *ethernet_addr);
4442 +
4443 +/* Memory descriptor management. */
4444 +#define PROM_MAX_PMEMBLOCKS 32
4445 +struct prom_pmemblock {
4446 + unsigned long base; /* Within KSEG0. */
4447 + unsigned int size; /* In bytes. */
4448 + unsigned int type; /* free or prom memory */
4449 +};
4450 +
4451 +#endif /* !(_MIPS_PROM_H) */
4452 --- /dev/null
4453 +++ b/arch/mips/include/asm/rt2880/rt_mmap.h
4454 @@ -0,0 +1,796 @@
4455 +/**************************************************************************
4456 + *
4457 + * BRIEF MODULE DESCRIPTION
4458 + * register definition for Ralink RT-series SoC
4459 + *
4460 + * Copyright 2007 Ralink Inc.
4461 + *
4462 + * This program is free software; you can redistribute it and/or modify it
4463 + * under the terms of the GNU General Public License as published by the
4464 + * Free Software Foundation; either version 2 of the License, or (at your
4465 + * option) any later version.
4466 + *
4467 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4468 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4469 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4470 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4471 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4472 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4473 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4474 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4475 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4476 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4477 + *
4478 + * You should have received a copy of the GNU General Public License along
4479 + * with this program; if not, write to the Free Software Foundation, Inc.,
4480 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4481 + *
4482 + *
4483 + **************************************************************************
4484 + */
4485 +
4486 +#ifndef __RALINK_MMAP__
4487 +#define __RALINK_MMAP__
4488 +
4489 +#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
4490 +
4491 +#define RALINK_SYSCTL_BASE 0xA0300000
4492 +#define RALINK_TIMER_BASE 0xA0300100
4493 +#define RALINK_INTCL_BASE 0xA0300200
4494 +#define RALINK_MEMCTRL_BASE 0xA0300300
4495 +#define RALINK_UART_BASE 0xA0300500
4496 +#define RALINK_PIO_BASE 0xA0300600
4497 +#define RALINK_I2C_BASE 0xA0300900
4498 +#define RALINK_SPI_BASE 0xA0300B00
4499 +#define RALINK_UART_LITE_BASE 0xA0300C00
4500 +#define RALINK_FRAME_ENGINE_BASE 0xA0310000
4501 +#define RALINK_EMBEDD_ROM_BASE 0xA0400000
4502 +#define RALINK_PCI_BASE 0xA0500000
4503 +#define RALINK_11N_MAC_BASE 0xA0600000
4504 +
4505 +//Interrupt Controller
4506 +#define RALINK_INTCTL_TIMER0 (1<<0)
4507 +#define RALINK_INTCTL_WDTIMER (1<<1)
4508 +#define RALINK_INTCTL_UART (1<<2)
4509 +#define RALINK_INTCTL_PIO (1<<3)
4510 +#define RALINK_INTCTL_PCM (1<<4)
4511 +#define RALINK_INTCTL_UARTLITE (1<<8)
4512 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
4513 +
4514 +//Reset Control Register
4515 +#define RALINK_TIMER_RST (1<<1)
4516 +#define RALINK_INTC_RST (1<<2)
4517 +#define RALINK_MC_RST (1<<3)
4518 +#define RALINK_CPU_RST (1<<4)
4519 +#define RALINK_UART_RST (1<<5)
4520 +#define RALINK_PIO_RST (1<<6)
4521 +#define RALINK_I2C_RST (1<<9)
4522 +#define RALINK_SPI_RST (1<<11)
4523 +#define RALINK_UART2_RST (1<<12)
4524 +#define RALINK_PCI_RST (1<<16)
4525 +#define RALINK_2860_RST (1<<17)
4526 +#define RALINK_FE_RST (1<<18)
4527 +#define RALINK_PCM_RST (1<<19)
4528 +
4529 +
4530 +#elif defined (CONFIG_RALINK_RT2880_MP)
4531 +
4532 +#define RALINK_SYSCTL_BASE 0xA0300000
4533 +#define RALINK_TIMER_BASE 0xA0300100
4534 +#define RALINK_INTCL_BASE 0xA0300200
4535 +#define RALINK_MEMCTRL_BASE 0xA0300300
4536 +#define RALINK_UART_BASE 0xA0300500
4537 +#define RALINK_PIO_BASE 0xA0300600
4538 +#define RALINK_I2C_BASE 0xA0300900
4539 +#define RALINK_SPI_BASE 0xA0300B00
4540 +#define RALINK_UART_LITE_BASE 0x00300C00
4541 +#define RALINK_FRAME_ENGINE_BASE 0xA0400000
4542 +#define RALINK_EMBEDD_ROM_BASE 0xA0410000
4543 +#define RALINK_PCI_BASE 0xA0440000
4544 +#define RALINK_11N_MAC_BASE 0xA0480000
4545 +
4546 +//Interrupt Controller
4547 +#define RALINK_INTCTL_TIMER0 (1<<0)
4548 +#define RALINK_INTCTL_WDTIMER (1<<1)
4549 +#define RALINK_INTCTL_UART (1<<2)
4550 +#define RALINK_INTCTL_PIO (1<<3)
4551 +#define RALINK_INTCTL_PCM (1<<4)
4552 +#define RALINK_INTCTL_UARTLITE (1<<8)
4553 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
4554 +
4555 +//Reset Control Register
4556 +#define RALINK_TIMER_RST (1<<1)
4557 +#define RALINK_INTC_RST (1<<2)
4558 +#define RALINK_MC_RST (1<<3)
4559 +#define RALINK_CPU_RST (1<<4)
4560 +#define RALINK_UART_RST (1<<5)
4561 +#define RALINK_PIO_RST (1<<6)
4562 +#define RALINK_I2C_RST (1<<9)
4563 +#define RALINK_SPI_RST (1<<11)
4564 +#define RALINK_UART2_RST (1<<12)
4565 +#define RALINK_PCI_RST (1<<16)
4566 +#define RALINK_2860_RST (1<<17)
4567 +#define RALINK_FE_RST (1<<18)
4568 +#define RALINK_PCM_RST (1<<19)
4569 +
4570 +#elif defined (CONFIG_RALINK_RT3052)
4571 +
4572 +#define RALINK_SYSCTL_BASE 0xB0000000
4573 +#define RALINK_TIMER_BASE 0xB0000100
4574 +#define RALINK_INTCL_BASE 0xB0000200
4575 +#define RALINK_MEMCTRL_BASE 0xB0000300
4576 +#define RALINK_PCM_BASE 0xB0000400
4577 +#define RALINK_UART_BASE 0x10000500
4578 +#define RALINK_PIO_BASE 0xB0000600
4579 +#define RALINK_GDMA_BASE 0xB0000700
4580 +#define RALINK_NAND_CTRL_BASE 0xB0000800
4581 +#define RALINK_I2C_BASE 0xB0000900
4582 +#define RALINK_I2S_BASE 0xB0000A00
4583 +#define RALINK_SPI_BASE 0xB0000B00
4584 +#define RALINK_UART_LITE_BASE 0x10000C00
4585 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4586 +#define RALINK_ETH_SW_BASE 0xB0110000
4587 +#define RALINK_11N_MAC_BASE 0xB0180000
4588 +#define RALINK_USB_OTG_BASE 0x101C0000
4589 +
4590 +//Interrupt Controller
4591 +#define RALINK_INTCTL_SYSCTL (1<<0)
4592 +#define RALINK_INTCTL_TIMER0 (1<<1)
4593 +#define RALINK_INTCTL_WDTIMER (1<<2)
4594 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4595 +#define RALINK_INTCTL_PCM (1<<4)
4596 +#define RALINK_INTCTL_UART (1<<5)
4597 +#define RALINK_INTCTL_PIO (1<<6)
4598 +#define RALINK_INTCTL_DMA (1<<7)
4599 +#define RALINK_INTCTL_NAND (1<<8)
4600 +#define RALINK_INTCTL_PC (1<<9)
4601 +#define RALINK_INTCTL_I2S (1<<10)
4602 +#define RALINK_INTCTL_UARTLITE (1<<12)
4603 +#define RALINK_INTCTL_ESW (1<<17)
4604 +#define RALINK_INTCTL_OTG (1<<18)
4605 +#define RALINK_INTCTL_OTG_IRQN 18
4606 +#define RALINK_INTCTL_GLOBAL (1<<31)
4607 +
4608 +//Reset Control Register
4609 +#define RALINK_SYS_RST (1<<0)
4610 +#define RALINK_CPU_RST (1<<1)
4611 +#define RALINK_TIMER_RST (1<<8)
4612 +#define RALINK_INTC_RST (1<<9)
4613 +#define RALINK_MC_RST (1<<10)
4614 +#define RALINK_PCM_RST (1<<11)
4615 +#define RALINK_UART_RST (1<<12)
4616 +#define RALINK_PIO_RST (1<<13)
4617 +#define RALINK_DMA_RST (1<<14)
4618 +#define RALINK_I2C_RST (1<<16)
4619 +#define RALINK_I2S_RST (1<<17)
4620 +#define RALINK_SPI_RST (1<<18)
4621 +#define RALINK_UARTL_RST (1<<19)
4622 +#define RALINK_RT2872_RST (1<<20)
4623 +#define RALINK_FE_RST (1<<21)
4624 +#define RALINK_OTG_RST (1<<22)
4625 +#define RALINK_SW_RST (1<<23)
4626 +#define RALINK_EPHY_RST (1<<24)
4627 +
4628 +#elif defined (CONFIG_RALINK_RT3352)
4629 +
4630 +#define RALINK_SYSCTL_BASE 0xB0000000
4631 +#define RALINK_TIMER_BASE 0xB0000100
4632 +#define RALINK_INTCL_BASE 0xB0000200
4633 +#define RALINK_MEMCTRL_BASE 0xB0000300
4634 +#define RALINK_UART_BASE 0x10000500
4635 +#define RALINK_PIO_BASE 0xB0000600
4636 +#define RALINK_I2C_BASE 0xB0000900
4637 +#define RALINK_I2S_BASE 0xB0000A00
4638 +#define RALINK_SPI_BASE 0xB0000B00
4639 +#define RALINK_NAND_CTRL_BASE 0xB0000800
4640 +#define RALINK_UART_LITE_BASE 0x10000C00
4641 +#define RALINK_PCM_BASE 0xB0002000
4642 +#define RALINK_GDMA_BASE 0xB0002800
4643 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4644 +#define RALINK_ETH_SW_BASE 0xB0110000
4645 +#define RALINK_USB_DEV_BASE 0x10120000
4646 +#define RALINK_11N_MAC_BASE 0xB0180000
4647 +#define RALINK_USB_HOST_BASE 0x101C0000
4648 +
4649 +#define RALINK_MCNT_CFG 0xB0000D00
4650 +#define RALINK_COMPARE 0xB0000D04
4651 +#define RALINK_COUNT 0xB0000D08
4652 +
4653 +//Interrupt Controller
4654 +#define RALINK_INTCTL_SYSCTL (1<<0)
4655 +#define RALINK_INTCTL_TIMER0 (1<<1)
4656 +#define RALINK_INTCTL_WDTIMER (1<<2)
4657 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4658 +#define RALINK_INTCTL_PCM (1<<4)
4659 +#define RALINK_INTCTL_UART (1<<5)
4660 +#define RALINK_INTCTL_PIO (1<<6)
4661 +#define RALINK_INTCTL_DMA (1<<7)
4662 +#define RALINK_INTCTL_PC (1<<9)
4663 +#define RALINK_INTCTL_I2S (1<<10)
4664 +#define RALINK_INTCTL_UARTLITE (1<<12)
4665 +#define RALINK_INTCTL_ESW (1<<17)
4666 +#define RALINK_INTCTL_OTG (1<<18)
4667 +#define RALINK_INTCTL_GLOBAL (1<<31)
4668 +
4669 +//Reset Control Register
4670 +#define RALINK_SYS_RST (1<<0)
4671 +#define RALINK_TIMER_RST (1<<8)
4672 +#define RALINK_INTC_RST (1<<9)
4673 +#define RALINK_MC_RST (1<<10)
4674 +#define RALINK_PCM_RST (1<<11)
4675 +#define RALINK_UART_RST (1<<12)
4676 +#define RALINK_PIO_RST (1<<13)
4677 +#define RALINK_DMA_RST (1<<14)
4678 +#define RALINK_I2C_RST (1<<16)
4679 +#define RALINK_I2S_RST (1<<17)
4680 +#define RALINK_SPI_RST (1<<18)
4681 +#define RALINK_UARTL_RST (1<<19)
4682 +#define RALINK_WLAN_RST (1<<20)
4683 +#define RALINK_FE_RST (1<<21)
4684 +#define RALINK_UHST_RST (1<<22)
4685 +#define RALINK_ESW_RST (1<<23)
4686 +#define RALINK_EPHY_RST (1<<24)
4687 +#define RALINK_UDEV_RST (1<<25)
4688 +
4689 +
4690 +//Clock Conf Register
4691 +#define RALINK_UPHY1_CLK_EN (1<<20)
4692 +#define RALINK_UPHY0_CLK_EN (1<<18)
4693 +#define RALINK_GE1_CLK_EN (1<<16)
4694 +
4695 +
4696 +#elif defined (CONFIG_RALINK_RT5350)
4697 +
4698 +#define RALINK_SYSCTL_BASE 0xB0000000
4699 +#define RALINK_TIMER_BASE 0xB0000100
4700 +#define RALINK_INTCL_BASE 0xB0000200
4701 +#define RALINK_MEMCTRL_BASE 0xB0000300
4702 +#define RALINK_UART_BASE 0x10000500
4703 +#define RALINK_PIO_BASE 0xB0000600
4704 +#define RALINK_I2C_BASE 0xB0000900
4705 +#define RALINK_I2S_BASE 0xB0000A00
4706 +#define RALINK_SPI_BASE 0xB0000B00
4707 +#define RALINK_UART_LITE_BASE 0x10000C00
4708 +#define RALINK_PCM_BASE 0xB0002000
4709 +#define RALINK_GDMA_BASE 0xB0002800
4710 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4711 +#define RALINK_ETH_SW_BASE 0xB0110000
4712 +#define RALINK_USB_DEV_BASE 0x10120000
4713 +#define RALINK_11N_MAC_BASE 0xB0180000
4714 +#define RALINK_USB_HOST_BASE 0x101C0000
4715 +
4716 +#define RALINK_MCNT_CFG 0xB0000D00
4717 +#define RALINK_COMPARE 0xB0000D04
4718 +#define RALINK_COUNT 0xB0000D08
4719 +
4720 +//Interrupt Controller
4721 +#define RALINK_INTCTL_SYSCTL (1<<0)
4722 +#define RALINK_INTCTL_TIMER0 (1<<1)
4723 +#define RALINK_INTCTL_WDTIMER (1<<2)
4724 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4725 +#define RALINK_INTCTL_PCM (1<<4)
4726 +#define RALINK_INTCTL_UART (1<<5)
4727 +#define RALINK_INTCTL_PIO (1<<6)
4728 +#define RALINK_INTCTL_DMA (1<<7)
4729 +#define RALINK_INTCTL_PC (1<<9)
4730 +#define RALINK_INTCTL_I2S (1<<10)
4731 +#define RALINK_INTCTL_UARTLITE (1<<12)
4732 +#define RALINK_INTCTL_ESW (1<<17)
4733 +#define RALINK_INTCTL_USB_HOST (1<<18)
4734 +#define RALINK_INTCTL_USB_DEV (1<<19)
4735 +#define RALINK_INTCTL_GLOBAL (1<<31)
4736 +
4737 +//Reset Control Register
4738 +#define RALINK_SYS_RST (1<<0)
4739 +#define RALINK_TIMER_RST (1<<8)
4740 +#define RALINK_INTC_RST (1<<9)
4741 +#define RALINK_MC_RST (1<<10)
4742 +#define RALINK_PCM_RST (1<<11)
4743 +#define RALINK_UART_RST (1<<12)
4744 +#define RALINK_PIO_RST (1<<13)
4745 +#define RALINK_DMA_RST (1<<14)
4746 +#define RALINK_I2C_RST (1<<16)
4747 +#define RALINK_I2S_RST (1<<17)
4748 +#define RALINK_SPI_RST (1<<18)
4749 +#define RALINK_UARTL_RST (1<<19)
4750 +#define RALINK_WLAN_RST (1<<20)
4751 +#define RALINK_FE_RST (1<<21)
4752 +#define RALINK_UHST_RST (1<<22)
4753 +#define RALINK_ESW_RST (1<<23)
4754 +#define RALINK_EPHY_RST (1<<24)
4755 +#define RALINK_UDEV_RST (1<<25)
4756 +#define RALINK_MIPSC_RST (1<<28)
4757 +
4758 +//Clock Conf Register
4759 +#define RALINK_UPHY0_CLK_EN (1<<18)
4760 +#define RALINK_GE1_CLK_EN (1<<16)
4761 +
4762 +#elif defined (CONFIG_RALINK_RT2883)
4763 +
4764 +#define RALINK_SYSCTL_BASE 0xB0000000
4765 +#define RALINK_TIMER_BASE 0xB0000100
4766 +#define RALINK_INTCL_BASE 0xB0000200
4767 +#define RALINK_MEMCTRL_BASE 0xB0000300
4768 +#define RALINK_PCM_BASE 0xB0000400
4769 +#define RALINK_UART_BASE 0x10000500
4770 +#define RALINK_PIO_BASE 0xB0000600
4771 +#define RALINK_GDMA_BASE 0xB0000700
4772 +#define RALINK_NAND_CTRL_BASE 0xB0000800
4773 +#define RALINK_I2C_BASE 0xB0000900
4774 +#define RALINK_I2S_BASE 0xB0000A00
4775 +#define RALINK_SPI_BASE 0xB0000B00
4776 +#define RALINK_UART_LITE_BASE 0x10000C00
4777 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4778 +#define RALINK_PCI_BASE 0xB0140000
4779 +#define RALINK_11N_MAC_BASE 0xB0180000
4780 +#define RALINK_USB_OTG_BASE 0x101C0000
4781 +
4782 +//Interrupt Controller
4783 +#define RALINK_INTCTL_SYSCTL (1<<0)
4784 +#define RALINK_INTCTL_TIMER0 (1<<1)
4785 +#define RALINK_INTCTL_WDTIMER (1<<2)
4786 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4787 +#define RALINK_INTCTL_PCM (1<<4)
4788 +#define RALINK_INTCTL_UART (1<<5)
4789 +#define RALINK_INTCTL_PIO (1<<6)
4790 +#define RALINK_INTCTL_DMA (1<<7)
4791 +#define RALINK_INTCTL_NAND (1<<8)
4792 +#define RALINK_INTCTL_PC (1<<9)
4793 +#define RALINK_INTCTL_I2S (1<<10)
4794 +#define RALINK_INTCTL_UARTLITE (1<<12)
4795 +#define RALINK_INTCTL_OTG (1<<18)
4796 +#define RALINK_INTCTL_OTG_IRQN 18
4797 +#define RALINK_INTCTL_GLOBAL (1<<31)
4798 +
4799 +//Reset Control Register
4800 +#define RALINK_SYS_RST (1<<0)
4801 +#define RALINK_CPU_RST (1<<1)
4802 +#define RALINK_TIMER_RST (1<<8)
4803 +#define RALINK_INTC_RST (1<<9)
4804 +#define RALINK_MC_RST (1<<10)
4805 +#define RALINK_PCM_RST (1<<11)
4806 +#define RALINK_UART_RST (1<<12)
4807 +#define RALINK_PIO_RST (1<<13)
4808 +#define RALINK_DMA_RST (1<<14)
4809 +#define RALINK_I2C_RST (1<<16)
4810 +#define RALINK_I2S_RST (1<<17)
4811 +#define RALINK_SPI_RST (1<<18)
4812 +#define RALINK_UARTL_RST (1<<19)
4813 +#define RALINK_WLAN_RST (1<<20)
4814 +#define RALINK_FE_RST (1<<21)
4815 +#define RALINK_OTG_RST (1<<22)
4816 +#define RALINK_PCIE_RST (1<<23)
4817 +
4818 +#elif defined (CONFIG_RALINK_RT3883)
4819 +
4820 +#define RALINK_SYSCTL_BASE 0xB0000000
4821 +#define RALINK_TIMER_BASE 0xB0000100
4822 +#define RALINK_INTCL_BASE 0xB0000200
4823 +#define RALINK_MEMCTRL_BASE 0xB0000300
4824 +#define RALINK_UART_BASE 0x10000500
4825 +#define RALINK_PIO_BASE 0xB0000600
4826 +#define RALINK_NOR_CTRL_BASE 0xB0000700
4827 +#define RALINK_NAND_CTRL_BASE 0xB0000810
4828 +#define RALINK_I2C_BASE 0xB0000900
4829 +#define RALINK_I2S_BASE 0xB0000A00
4830 +#define RALINK_SPI_BASE 0xB0000B00
4831 +#define RALINK_UART_LITE_BASE 0x10000C00
4832 +#define RALINK_PCM_BASE 0xB0002000
4833 +#define RALINK_GDMA_BASE 0xB0002800
4834 +#define RALINK_CODEC1_BASE 0xB0003000
4835 +#define RALINK_CODEC2_BASE 0xB0003800
4836 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4837 +#define RALINK_USB_DEV_BASE 0x10120000
4838 +#define RALINK_PCI_BASE 0xB0140000
4839 +#define RALINK_11N_MAC_BASE 0xB0180000
4840 +#define RALINK_USB_HOST_BASE 0x101C0000
4841 +#define RALINK_PCIE_BASE 0xB0200000
4842 +
4843 +//Interrupt Controller
4844 +#define RALINK_INTCTL_SYSCTL (1<<0)
4845 +#define RALINK_INTCTL_TIMER0 (1<<1)
4846 +#define RALINK_INTCTL_WDTIMER (1<<2)
4847 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4848 +#define RALINK_INTCTL_PCM (1<<4)
4849 +#define RALINK_INTCTL_UART (1<<5)
4850 +#define RALINK_INTCTL_PIO (1<<6)
4851 +#define RALINK_INTCTL_DMA (1<<7)
4852 +#define RALINK_INTCTL_NAND (1<<8)
4853 +#define RALINK_INTCTL_PC (1<<9)
4854 +#define RALINK_INTCTL_I2S (1<<10)
4855 +#define RALINK_INTCTL_UARTLITE (1<<12)
4856 +#define RALINK_INTCTL_UHST (1<<18)
4857 +#define RALINK_INTCTL_UDEV (1<<19)
4858 +
4859 +//Reset Control Register
4860 +#define RALINK_SYS_RST (1<<0)
4861 +#define RALINK_TIMER_RST (1<<8)
4862 +#define RALINK_INTC_RST (1<<9)
4863 +#define RALINK_MC_RST (1<<10)
4864 +#define RALINK_PCM_RST (1<<11)
4865 +#define RALINK_UART_RST (1<<12)
4866 +#define RALINK_PIO_RST (1<<13)
4867 +#define RALINK_DMA_RST (1<<14)
4868 +#define RALINK_NAND_RST (1<<15)
4869 +#define RALINK_I2C_RST (1<<16)
4870 +#define RALINK_I2S_RST (1<<17)
4871 +#define RALINK_SPI_RST (1<<18)
4872 +#define RALINK_UARTL_RST (1<<19)
4873 +#define RALINK_WLAN_RST (1<<20)
4874 +#define RALINK_FE_RST (1<<21)
4875 +#define RALINK_UHST_RST (1<<22)
4876 +#define RALINK_PCIE_RST (1<<23)
4877 +#define RALINK_PCI_RST (1<<24)
4878 +#define RALINK_UDEV_RST (1<<25)
4879 +#define RALINK_FLASH_RST (1<<26)
4880 +
4881 +//Clock Conf Register
4882 +#define RALINK_UPHY1_CLK_EN (1<<20)
4883 +#define RALINK_UPHY0_CLK_EN (1<<18)
4884 +#define RALINK_GE1_CLK_EN (1<<16)
4885 +
4886 +#elif defined (CONFIG_RALINK_RT6855)
4887 +
4888 +#define RALINK_SYSCTL_BASE 0xB0000000
4889 +#define RALINK_TIMER_BASE 0xB0000100
4890 +#define RALINK_INTCL_BASE 0xB0000200
4891 +#define RALINK_MEMCTRL_BASE 0xB0000300
4892 +#define RALINK_UART_BASE 0x10000500
4893 +#define RALINK_PIO_BASE 0xB0000600
4894 +#define RALINK_I2C_BASE 0xB0000900
4895 +#define RALINK_I2S_BASE 0xB0000A00
4896 +#define RALINK_SPI_BASE 0xB0000B00
4897 +#define RALINK_NAND_CTRL_BASE 0xB0000800
4898 +#define RALINK_UART_LITE_BASE 0x10000C00
4899 +#define RALINK_PCM_BASE 0xB0002000
4900 +#define RALINK_GDMA_BASE 0xB0002800
4901 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4902 +#define RALINK_ETH_SW_BASE 0xB0110000
4903 +#define RALINK_PCI_BASE 0xB0140000
4904 +#define RALINK_USB_DEV_BASE 0x10120000
4905 +#define RALINK_11N_MAC_BASE 0xB0180000
4906 +#define RALINK_USB_HOST_BASE 0x101C0000
4907 +
4908 +#define RALINK_MCNT_CFG 0xB0000D00
4909 +#define RALINK_COMPARE 0xB0000D04
4910 +#define RALINK_COUNT 0xB0000D08
4911 +
4912 +//Interrupt Controller
4913 +#define RALINK_INTCTL_SYSCTL (1<<0)
4914 +#define RALINK_INTCTL_TIMER0 (1<<1)
4915 +#define RALINK_INTCTL_WDTIMER (1<<2)
4916 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4917 +#define RALINK_INTCTL_PCM (1<<4)
4918 +#define RALINK_INTCTL_UART (1<<5)
4919 +#define RALINK_INTCTL_PIO (1<<6)
4920 +#define RALINK_INTCTL_DMA (1<<7)
4921 +#define RALINK_INTCTL_PC (1<<9)
4922 +#define RALINK_INTCTL_I2S (1<<10)
4923 +#define RALINK_INTCTL_UARTLITE (1<<12)
4924 +#define RALINK_INTCTL_ESW (1<<17)
4925 +#define RALINK_INTCTL_OTG (1<<18)
4926 +#define RALINK_INTCTL_GLOBAL (1<<31)
4927 +
4928 +//Reset Control Register
4929 +#define RALINK_SYS_RST (1<<0)
4930 +#define RALINK_TIMER_RST (1<<8)
4931 +#define RALINK_INTC_RST (1<<9)
4932 +#define RALINK_MC_RST (1<<10)
4933 +#define RALINK_PCM_RST (1<<11)
4934 +#define RALINK_UART_RST (1<<12)
4935 +#define RALINK_PIO_RST (1<<13)
4936 +#define RALINK_DMA_RST (1<<14)
4937 +#define RALINK_I2C_RST (1<<16)
4938 +#define RALINK_I2S_RST (1<<17)
4939 +#define RALINK_SPI_RST (1<<18)
4940 +#define RALINK_UARTL_RST (1<<19)
4941 +#define RALINK_FE_RST (1<<21)
4942 +#define RALINK_UHST_RST (1<<22)
4943 +#define RALINK_ESW_RST (1<<23)
4944 +#define RALINK_EPHY_RST (1<<24)
4945 +#define RALINK_UDEV_RST (1<<25)
4946 +#define RALINK_PCIE0_RST (1<<26)
4947 +#define RALINK_PCIE1_RST (1<<27)
4948 +
4949 +//Clock Conf Register
4950 +#define RALINK_UPHY0_CLK_EN (1<<25)
4951 +#define RALINK_PCIE0_CLK_EN (1<<26)
4952 +#define RALINK_PCIE1_CLK_EN (1<<27)
4953 +
4954 +
4955 +#elif defined (CONFIG_RALINK_MT7620)
4956 +
4957 +#define RALINK_SYSCTL_BASE 0xB0000000
4958 +#define RALINK_TIMER_BASE 0xB0000100
4959 +#define RALINK_INTCL_BASE 0xB0000200
4960 +#define RALINK_MEMCTRL_BASE 0xB0000300
4961 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
4962 +#define RALINK_UART_BASE 0x10000500
4963 +#define RALINK_PIO_BASE 0xB0000600
4964 +#define RALINK_NAND_CTRL_BASE 0xB0000810
4965 +#define RALINK_I2C_BASE 0xB0000900
4966 +#define RALINK_I2S_BASE 0xB0000A00
4967 +#define RALINK_SPI_BASE 0xB0000B00
4968 +#define RALINK_UART_LITE_BASE 0x10000C00
4969 +#define RALINK_MIPS_CNT_BASE 0x10000D00
4970 +#define RALINK_PCM_BASE 0xB0002000
4971 +#define RALINK_GDMA_BASE 0xB0002800
4972 +#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
4973 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
4974 +#define RALINK_PPE_BASE 0xB0100C00
4975 +#define RALINK_ETH_SW_BASE 0xB0110000
4976 +#define RALINK_USB_DEV_BASE 0x10120000
4977 +#define RALINK_MSDC_BASE 0xB0130000
4978 +#define RALINK_PCI_BASE 0xB0140000
4979 +#define RALINK_11N_MAC_BASE 0xB0180000
4980 +#define RALINK_USB_HOST_BASE 0x101C0000
4981 +
4982 +#define RALINK_MCNT_CFG 0xB0000D00
4983 +#define RALINK_COMPARE 0xB0000D04
4984 +#define RALINK_COUNT 0xB0000D08
4985 +
4986 +//Interrupt Controller
4987 +#define RALINK_INTCTL_SYSCTL (1<<0)
4988 +#define RALINK_INTCTL_TIMER0 (1<<1)
4989 +#define RALINK_INTCTL_WDTIMER (1<<2)
4990 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
4991 +#define RALINK_INTCTL_PCM (1<<4)
4992 +#define RALINK_INTCTL_UART (1<<5)
4993 +#define RALINK_INTCTL_PIO (1<<6)
4994 +#define RALINK_INTCTL_DMA (1<<7)
4995 +#define RALINK_INTCTL_PC (1<<9)
4996 +#define RALINK_INTCTL_I2S (1<<10)
4997 +#define RALINK_INTCTL_SPI (1<<11)
4998 +#define RALINK_INTCTL_UARTLITE (1<<12)
4999 +#define RALINK_INTCTL_CRYPTO (1<<13)
5000 +#define RALINK_INTCTL_ESW (1<<17)
5001 +#define RALINK_INTCTL_UHST (1<<18)
5002 +#define RALINK_INTCTL_UDEV (1<<19)
5003 +#define RALINK_INTCTL_GLOBAL (1<<31)
5004 +
5005 +//Reset Control Register
5006 +#define RALINK_SYS_RST (1<<0)
5007 +#define RALINK_TIMER_RST (1<<8)
5008 +#define RALINK_INTC_RST (1<<9)
5009 +#define RALINK_MC_RST (1<<10)
5010 +#define RALINK_PCM_RST (1<<11)
5011 +#define RALINK_UART_RST (1<<12)
5012 +#define RALINK_PIO_RST (1<<13)
5013 +#define RALINK_DMA_RST (1<<14)
5014 +#define RALINK_I2C_RST (1<<16)
5015 +#define RALINK_I2S_RST (1<<17)
5016 +#define RALINK_SPI_RST (1<<18)
5017 +#define RALINK_UARTL_RST (1<<19)
5018 +#define RALINK_FE_RST (1<<21)
5019 +#define RALINK_UHST_RST (1<<22)
5020 +#define RALINK_ESW_RST (1<<23)
5021 +#define RALINK_EPHY_RST (1<<24)
5022 +#define RALINK_UDEV_RST (1<<25)
5023 +#define RALINK_PCIE0_RST (1<<26)
5024 +#define RALINK_PCIE1_RST (1<<27)
5025 +#define RALINK_MIPS_CNT_RST (1<<28)
5026 +#define RALINK_CRYPTO_RST (1<<29)
5027 +
5028 +//Clock Conf Register
5029 +#define RALINK_UPHY0_CLK_EN (1<<25)
5030 +#define RALINK_UPHY1_CLK_EN (1<<22)
5031 +#define RALINK_PCIE0_CLK_EN (1<<26)
5032 +#define RALINK_PCIE1_CLK_EN (1<<27)
5033 +
5034 +//CPU PLL CFG Register
5035 +#define CPLL_SW_CONFIG (0x1UL << 31)
5036 +#define CPLL_MULT_RATIO_SHIFT 16
5037 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
5038 +#define CPLL_DIV_RATIO_SHIFT 10
5039 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
5040 +#define BASE_CLOCK 40 /* Mhz */
5041 +
5042 +#elif defined (CONFIG_RALINK_MT7621)
5043 +
5044 +#define RALINK_SYSCTL_BASE 0xBE000000
5045 +#define RALINK_TIMER_BASE 0xBE000100
5046 +#define RALINK_INTCL_BASE 0xBE000200
5047 +#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
5048 +#define RALINK_MIPS_CNT_BASE 0x1E000500
5049 +#define RALINK_PIO_BASE 0xBE000600
5050 +#define RALINK_SPDIF_BASE 0xBE000700
5051 +#define RALINK_I2C_BASE 0xBE000900
5052 +#define RALINK_I2S_BASE 0xBE000A00
5053 +#define RALINK_SPI_BASE 0xBE000B00
5054 +#define RALINK_UART_LITE1_BASE 0x1E000C00
5055 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
5056 +#define RALINK_UART_LITE2_BASE 0x1E000D00
5057 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
5058 +#define RALINK_UART_LITE3_BASE 0x1E000E00
5059 +#define RALINK_ANA_CTRL_BASE 0xBE000F00
5060 +#define RALINK_PCM_BASE 0xBE002000
5061 +#define RALINK_GDMA_BASE 0xBE002800
5062 +#define RALINK_NAND_CTRL_BASE 0xBE003000
5063 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
5064 +#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
5065 +#define RALINK_MEMCTRL_BASE 0xBE005000
5066 +#define RALINK_EXT_MC_ARB_BASE 0xBE006000
5067 +#define RALINK_HS_DMA_BASE 0xBE007000
5068 +#define RALINK_FRAME_ENGINE_BASE 0xBE100000
5069 +#define RALINK_PPE_BASE 0xBE100C00
5070 +#define RALINK_ETH_SW_BASE 0xBE110000
5071 +#define RALINK_ROM_BASE 0xBE118000
5072 +#define RALINK_MSDC_BASE 0xBE130000
5073 +#define RALINK_PCI_BASE 0xBE140000
5074 +#define RALINK_USB_HOST_BASE 0x1E1C0000
5075 +#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
5076 +
5077 +#define RALINK_MCNT_CFG 0xBE000500
5078 +#define RALINK_COMPARE 0xBE000504
5079 +#define RALINK_COUNT 0xBE000508
5080 +
5081 +//Interrupt Controller
5082 +#define RALINK_INTCTL_FE (1<<3)
5083 +#define RALINK_INTCTL_PCIE0 (1<<4)
5084 +#define RALINK_INTCTL_SYSCTL (1<<6)
5085 +#define RALINK_INTCTL_I2C (1<<8)
5086 +#define RALINK_INTCTL_DRAMC (1<<9)
5087 +#define RALINK_INTCTL_PCM (1<<10)
5088 +#define RALINK_INTCTL_HSDMA (1<<11)
5089 +#define RALINK_INTCTL_PIO (1<<12)
5090 +#define RALINK_INTCTL_DMA (1<<13)
5091 +#define RALINK_INTCTL_NFI (1<<14)
5092 +#define RALINK_INTCTL_NFIECC (1<<15)
5093 +#define RALINK_INTCTL_I2S (1<<16)
5094 +#define RALINK_INTCTL_SPI (1<<17)
5095 +#define RALINK_INTCTL_SPDIF (1<<18)
5096 +#define RALINK_INTCTL_CRYPTO (1<<19)
5097 +#define RALINK_INTCTL_SDXC (1<<20)
5098 +#define RALINK_INTCTL_PCTRL (1<<21)
5099 +#define RALINK_INTCTL_USB (1<<22)
5100 +#define RALINK_INTCTL_SWITCH (1<<23)
5101 +#define RALINK_INTCTL_PCIE1 (1<<24)
5102 +#define RALINK_INTCTL_PCIE2 (1<<25)
5103 +#define RALINK_INTCTL_UART1 (1<<26)
5104 +#define RALINK_INTCTL_UART2 (1<<27)
5105 +#define RALINK_INTCTL_UART3 (1<<28)
5106 +#define RALINK_INTCTL_WDTIMER (1<<29)
5107 +#define RALINK_INTCTL_TIMER0 (1<<30)
5108 +#define RALINK_INTCTL_TIMER1 (1<<31)
5109 +
5110 +
5111 +//Reset Control Register
5112 +#define RALINK_SYS_RST (1<<0)
5113 +#define RALINK_MCM_RST (1<<1)
5114 +#define RALINK_HSDMA_RST (1<<2)
5115 +#define RALINK_FE_RST (1<<6)
5116 +#define RALINK_SPDIF_RST (1<<7)
5117 +#define RALINK_TIMER_RST (1<<8)
5118 +#define RALINK_INTC_RST (1<<9)
5119 +#define RALINK_MC_RST (1<<10)
5120 +#define RALINK_PCM_RST (1<<11)
5121 +#define RALINK_PIO_RST (1<<13)
5122 +#define RALINK_DMA_RST (1<<14)
5123 +#define RALINK_NAND_RST (1<<15)
5124 +#define RALINK_I2C_RST (1<<16)
5125 +#define RALINK_I2S_RST (1<<17)
5126 +#define RALINK_SPI_RST (1<<18)
5127 +#define RALINK_UART1_RST (1<<19)
5128 +#define RALINK_UART2_RST (1<<20)
5129 +#define RALINK_UART3_RST (1<<21)
5130 +#define RALINK_ETH_RST (1<<23)
5131 +#define RALINK_PCIE0_RST (1<<24)
5132 +#define RALINK_PCIE1_RST (1<<25)
5133 +#define RALINK_PCIE2_RST (1<<26)
5134 +#define RALINK_AUX_STCK_RST (1<<28)
5135 +#define RALINK_CRYPTO_RST (1<<29)
5136 +#define RALINK_SDXC_RST (1<<30)
5137 +#define RALINK_PPE_RST (1<<31)
5138 +
5139 +//Clock Conf Register
5140 +#define RALINK_PCIE0_CLK_EN (1<<24)
5141 +#define RALINK_PCIE1_CLK_EN (1<<25)
5142 +#define RALINK_PCIE2_CLK_EN (1<<26)
5143 +//#define RALINK_UPHY0_CLK_EN (1<<27)
5144 +//#define RALINK_UPHY1_CLK_EN (1<<28)
5145 +
5146 +//CPU PLL CFG Register
5147 +#define CPLL_SW_CONFIG (0x1UL << 31)
5148 +#define CPLL_MULT_RATIO_SHIFT 16
5149 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
5150 +#define CPLL_DIV_RATIO_SHIFT 10
5151 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
5152 +#define BASE_CLOCK 40 /* Mhz */
5153 +
5154 +#define RALINK_TESTSTAT 0xBE000018
5155 +#define RALINK_TESTSTAT2 0xBE00001C
5156 +
5157 +#elif defined (CONFIG_RALINK_MT7628)
5158 +
5159 +#define RALINK_SYSCTL_BASE 0xB0000000
5160 +#define RALINK_TIMER_BASE 0xB0000100
5161 +#define RALINK_INTCL_BASE 0xB0000200
5162 +#define RALINK_MEMCTRL_BASE 0xB0000300
5163 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
5164 +#define RALINK_MIPS_CNT_BASE 0x10000500
5165 +#define RALINK_PIO_BASE 0xB0000600
5166 +#define RALINK_SPI_SLAVE_BASE 0xB0000700
5167 +#define RALINK_I2C_BASE 0xB0000900
5168 +#define RALINK_I2S_BASE 0xB0000A00
5169 +#define RALINK_SPI_BASE 0xB0000B00
5170 +#define RALINK_UART_LITE1_BASE 0x10000C00
5171 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
5172 +#define RALINK_UART_LITE2_BASE 0x10000D00
5173 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
5174 +#define RALINK_UART_LITE3_BASE 0x10000E00
5175 +#define RALINK_PCM_BASE 0xB0002000
5176 +#define RALINK_GDMA_BASE 0xB0002800
5177 +#define RALINK_AES_ENGINE_BASE 0xB0004000
5178 +#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
5179 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
5180 +#define RALINK_PPE_BASE 0xB0100C00
5181 +#define RALINK_ETH_SW_BASE 0xB0110000
5182 +#define RALINK_USB_DEV_BASE 0xB0120000
5183 +#define RALINK_MSDC_BASE 0xB0130000
5184 +#define RALINK_PCI_BASE 0xB0140000
5185 +#define RALINK_11N_MAC_BASE 0xB0180000
5186 +#define RALINK_USB_HOST_BASE 0x101C0000
5187 +
5188 +#define RALINK_MCNT_CFG 0xB0000500
5189 +#define RALINK_COMPARE 0xB0000504
5190 +#define RALINK_COUNT 0xB0000508
5191 +
5192 +
5193 +//Interrupt Controller
5194 +#define RALINK_INTCTL_SYSCTL (1<<0)
5195 +#define RALINK_INTCTL_TIMER0 (1<<1)
5196 +#define RALINK_INTCTL_WDTIMER (1<<2)
5197 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
5198 +#define RALINK_INTCTL_PCM (1<<4)
5199 +#define RALINK_INTCTL_UART (1<<5)
5200 +#define RALINK_INTCTL_PIO (1<<6)
5201 +#define RALINK_INTCTL_DMA (1<<7)
5202 +#define RALINK_INTCTL_PC (1<<9)
5203 +#define RALINK_INTCTL_I2S (1<<10)
5204 +#define RALINK_INTCTL_SPI (1<<11)
5205 +#define RALINK_INTCTL_UARTLITE (1<<12)
5206 +#define RALINK_INTCTL_CRYPTO (1<<13)
5207 +#define RALINK_INTCTL_ESW (1<<17)
5208 +#define RALINK_INTCTL_UHST (1<<18)
5209 +#define RALINK_INTCTL_UDEV (1<<19)
5210 +#define RALINK_INTCTL_GLOBAL (1<<31)
5211 +
5212 +//Reset Control Register
5213 +#define RALINK_SYS_RST (1<<0)
5214 +#define RALINK_TIMER_RST (1<<8)
5215 +#define RALINK_INTC_RST (1<<9)
5216 +#define RALINK_MC_RST (1<<10)
5217 +#define RALINK_PCM_RST (1<<11)
5218 +#define RALINK_UART_RST (1<<12)
5219 +#define RALINK_PIO_RST (1<<13)
5220 +#define RALINK_DMA_RST (1<<14)
5221 +#define RALINK_I2C_RST (1<<16)
5222 +#define RALINK_I2S_RST (1<<17)
5223 +#define RALINK_SPI_RST (1<<18)
5224 +#define RALINK_UARTL_RST (1<<19)
5225 +#define RALINK_FE_RST (1<<21)
5226 +#define RALINK_UHST_RST (1<<22)
5227 +#define RALINK_ESW_RST (1<<23)
5228 +#define RALINK_EPHY_RST (1<<24)
5229 +#define RALINK_UDEV_RST (1<<25)
5230 +#define RALINK_PCIE0_RST (1<<26)
5231 +#define RALINK_PCIE1_RST (1<<27)
5232 +#define RALINK_MIPS_CNT_RST (1<<28)
5233 +#define RALINK_CRYPTO_RST (1<<29)
5234 +
5235 +//Clock Conf Register
5236 +#define RALINK_UPHY0_CLK_EN (1<<25)
5237 +#define RALINK_UPHY1_CLK_EN (1<<22)
5238 +#define RALINK_PCIE0_CLK_EN (1<<26)
5239 +#define RALINK_PCIE1_CLK_EN (1<<27)
5240 +
5241 +//CPU PLL CFG Register
5242 +#define CPLL_SW_CONFIG (0x1UL << 31)
5243 +#define CPLL_MULT_RATIO_SHIFT 16
5244 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
5245 +#define CPLL_DIV_RATIO_SHIFT 10
5246 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
5247 +#define BASE_CLOCK 40 /* Mhz */
5248 +
5249 +#endif
5250 +#endif
5251 --- /dev/null
5252 +++ b/arch/mips/include/asm/rt2880/serial_rt2880.h
5253 @@ -0,0 +1,443 @@
5254 +/**************************************************************************
5255 + *
5256 + * BRIEF MODULE DESCRIPTION
5257 + * serial port definition for Ralink RT2880 solution
5258 + *
5259 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
5260 + *
5261 + * This program is free software; you can redistribute it and/or modify it
5262 + * under the terms of the GNU General Public License as published by the
5263 + * Free Software Foundation; either version 2 of the License, or (at your
5264 + * option) any later version.
5265 + *
5266 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5267 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5268 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5269 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5270 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5271 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5272 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5273 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5274 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5275 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5276 + *
5277 + * You should have received a copy of the GNU General Public License along
5278 + * with this program; if not, write to the Free Software Foundation, Inc.,
5279 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5280 + *
5281 + *
5282 + **************************************************************************
5283 + * May 2007 Bruce Chang
5284 + *
5285 + * Initial Release
5286 + *
5287 + *
5288 + *
5289 + **************************************************************************
5290 + */
5291 +
5292 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
5293 +#define RT2880_UART_RBR_OFFSET 0x00
5294 +#define RT2880_UART_TBR_OFFSET 0x00
5295 +#define RT2880_UART_IER_OFFSET 0x04
5296 +#define RT2880_UART_IIR_OFFSET 0x08
5297 +#define RT2880_UART_FCR_OFFSET 0x08
5298 +#define RT2880_UART_LCR_OFFSET 0x0C
5299 +#define RT2880_UART_MCR_OFFSET 0x10
5300 +#define RT2880_UART_LSR_OFFSET 0x14
5301 +#define RT2880_UART_DLL_OFFSET 0x00
5302 +#define RT2880_UART_DLM_OFFSET 0x04
5303 +#else
5304 +#define RT2880_UART_RBR_OFFSET 0x00
5305 +#define RT2880_UART_TBR_OFFSET 0x04
5306 +#define RT2880_UART_IER_OFFSET 0x08
5307 +#define RT2880_UART_IIR_OFFSET 0x0C
5308 +#define RT2880_UART_FCR_OFFSET 0x10
5309 +#define RT2880_UART_LCR_OFFSET 0x14
5310 +#define RT2880_UART_MCR_OFFSET 0x18
5311 +#define RT2880_UART_LSR_OFFSET 0x1C
5312 +#define RT2880_UART_DLL_OFFSET 0x2C
5313 +#define RT2880_UART_DLM_OFFSET 0x30
5314 +#endif
5315 +
5316 +#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
5317 +#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
5318 +#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
5319 +#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
5320 +#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
5321 +#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
5322 +#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
5323 +#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
5324 +#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
5325 +#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
5326 +
5327 +
5328 +#if defined (CONFIG_RALINK_RT2880) || \
5329 + defined (CONFIG_RALINK_RT2883) || \
5330 + defined (CONFIG_RALINK_RT3883) || \
5331 + defined (CONFIG_RALINK_RT3352) || \
5332 + defined (CONFIG_RALINK_RT5350) || \
5333 + defined (CONFIG_RALINK_RT6855) || \
5334 + defined (CONFIG_RALINK_MT7620) || \
5335 + defined (CONFIG_RALINK_RT3052)
5336 +
5337 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
5338 +
5339 +#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
5340 +#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
5341 + * In: Fifo count
5342 + * Out: Fifo custom trigger levels
5343 + * XR16C85x only
5344 + */
5345 +
5346 +#define UART_IER 8 /* Out: Interrupt Enable Register */
5347 +#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
5348 + * XR16C85x only
5349 + */
5350 +
5351 +#define UART_IIR 12 /* In: Interrupt ID Register */
5352 +#define UART_EFR 12 /* I/O: Extended Features Register */
5353 + /* (DLAB=1, 16C660 only) */
5354 +
5355 +#define UART_FCR 16 /* Out: FIFO Control Register */
5356 +#define UART_LCR 20 /* Out: Line Control Register */
5357 +#define UART_MCR 24 /* Out: Modem Control Register */
5358 +#define UART_LSR 28 /* In: Line Status Register */
5359 +#define UART_MSR 32 /* In: Modem Status Register */
5360 +#define UART_SCR 36 /* I/O: Scratch Register */
5361 +#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
5362 +/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
5363 + * unpredictable values to be written to the Divisor Latch
5364 + */
5365 +#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
5366 +
5367 +#else
5368 +
5369 +#define UART_RX 0 /* In: Receive buffer */
5370 +#define UART_TX 0 /* Out: Transmit buffer */
5371 +#define UART_DLL 0 /* Out: Divisor Latch Low */
5372 +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
5373 + * In: Fifo count
5374 + * Out: Fifo custom trigger levels */
5375 +
5376 +#define UART_DLM 4 /* Out: Divisor Latch High */
5377 +#define UART_IER 4 /* Out: Interrupt Enable Register */
5378 +#define UART_FCTR 4 /* Feature Control Register */
5379 +
5380 +#define UART_IIR 8 /* In: Interrupt ID Register */
5381 +#define UART_FCR 8 /* Out: FIFO Control Register */
5382 +#define UART_EFR 8 /* I/O: Extended Features Register */
5383 +
5384 +#define UART_LCR 12 /* Out: Line Control Register */
5385 +#define UART_MCR 16 /* Out: Modem Control Register */
5386 +#define UART_LSR 20 /* In: Line Status Register */
5387 +#define UART_MSR 24 /* In: Modem Status Register */
5388 +#define UART_SCR 28 /* I/O: Scratch Register */
5389 +#define UART_EMSR 28 /* Extended Mode Select Register */
5390 +
5391 +#endif
5392 +/*
5393 + * DLAB=0
5394 + */
5395 +//#define UART_IER 1 /* Out: Interrupt Enable Register */
5396 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
5397 +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
5398 +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
5399 +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
5400 +/*
5401 + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
5402 + */
5403 +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
5404 +
5405 +//#define UART_IIR 2 /* In: Interrupt ID Register */
5406 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
5407 +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
5408 +#define UART_IIR_MSI 0x00 /* Modem status interrupt */
5409 +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
5410 +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
5411 +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
5412 +
5413 +//#define UART_FCR 2 /* Out: FIFO Control Register */
5414 +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
5415 +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
5416 +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
5417 +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
5418 +/*
5419 + * Note: The FIFO trigger levels are chip specific:
5420 + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
5421 + * PC16550D: 1 4 8 14 xx xx xx xx
5422 + * TI16C550A: 1 4 8 14 xx xx xx xx
5423 + * TI16C550C: 1 4 8 14 xx xx xx xx
5424 + * ST16C550: 1 4 8 14 xx xx xx xx
5425 + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
5426 + * NS16C552: 1 4 8 14 xx xx xx xx
5427 + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
5428 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
5429 + * TI16C752: 8 16 56 60 8 16 32 56
5430 + */
5431 +#define UART_FCR_R_TRIG_00 0x00
5432 +#define UART_FCR_R_TRIG_01 0x40
5433 +#define UART_FCR_R_TRIG_10 0x80
5434 +#define UART_FCR_R_TRIG_11 0xc0
5435 +#define UART_FCR_T_TRIG_00 0x00
5436 +#define UART_FCR_T_TRIG_01 0x10
5437 +#define UART_FCR_T_TRIG_10 0x20
5438 +#define UART_FCR_T_TRIG_11 0x30
5439 +
5440 +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
5441 +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
5442 +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
5443 +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
5444 +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
5445 +/* 16650 definitions */
5446 +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
5447 +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
5448 +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
5449 +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
5450 +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
5451 +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
5452 +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
5453 +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
5454 +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
5455 +
5456 +//#define UART_LCR 3 /* Out: Line Control Register */
5457 +/*
5458 + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
5459 + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
5460 + */
5461 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
5462 +#define UART_LCR_SBC 0x40 /* Set break control */
5463 +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
5464 +#define UART_LCR_EPAR 0x10 /* Even parity select */
5465 +#define UART_LCR_PARITY 0x08 /* Parity Enable */
5466 +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
5467 +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
5468 +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
5469 +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
5470 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
5471 +
5472 +//#define UART_MCR 4 /* Out: Modem Control Register */
5473 +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
5474 +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
5475 +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
5476 +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
5477 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
5478 +#define UART_MCR_OUT2 0x08 /* Out2 complement */
5479 +#define UART_MCR_OUT1 0x04 /* Out1 complement */
5480 +#define UART_MCR_RTS 0x02 /* RTS complement */
5481 +#define UART_MCR_DTR 0x01 /* DTR complement */
5482 +
5483 +//#define UART_LSR 5 /* In: Line Status Register */
5484 +#define UART_LSR_TEMT 0x40 /* Transmitter empty */
5485 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
5486 +#define UART_LSR_BI 0x10 /* Break interrupt indicator */
5487 +#define UART_LSR_FE 0x08 /* Frame error indicator */
5488 +#define UART_LSR_PE 0x04 /* Parity error indicator */
5489 +#define UART_LSR_OE 0x02 /* Overrun error indicator */
5490 +#define UART_LSR_DR 0x01 /* Receiver data ready */
5491 +
5492 +//#define UART_MSR 6 /* In: Modem Status Register */
5493 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
5494 +#define UART_MSR_RI 0x40 /* Ring Indicator */
5495 +#define UART_MSR_DSR 0x20 /* Data Set Ready */
5496 +#define UART_MSR_CTS 0x10 /* Clear to Send */
5497 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
5498 +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
5499 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
5500 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
5501 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
5502 +
5503 +//#define UART_SCR 7 /* I/O: Scratch Register */
5504 +
5505 +/*
5506 + * DLAB=1
5507 + */
5508 +//#define UART_DLL 0 /* Out: Divisor Latch Low */
5509 +//#define UART_DLM 1 /* Out: Divisor Latch High */
5510 +
5511 +/*
5512 + * LCR=0xBF (or DLAB=1 for 16C660)
5513 + */
5514 +//#define UART_EFR 2 /* I/O: Extended Features Register */
5515 +#define UART_EFR_CTS 0x80 /* CTS flow control */
5516 +#define UART_EFR_RTS 0x40 /* RTS flow control */
5517 +#define UART_EFR_SCD 0x20 /* Special character detect */
5518 +#define UART_EFR_ECB 0x10 /* Enhanced control bit */
5519 +/*
5520 + * the low four bits control software flow control
5521 + */
5522 +
5523 +/*
5524 + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
5525 + */
5526 +#define UART_XON1 4 /* I/O: Xon character 1 */
5527 +#define UART_XON2 5 /* I/O: Xon character 2 */
5528 +#define UART_XOFF1 6 /* I/O: Xoff character 1 */
5529 +#define UART_XOFF2 7 /* I/O: Xoff character 2 */
5530 +
5531 +/*
5532 + * EFR[4]=1 MCR[6]=1, TI16C752
5533 + */
5534 +#define UART_TI752_TCR 6 /* I/O: transmission control register */
5535 +#define UART_TI752_TLR 7 /* I/O: trigger level register */
5536 +
5537 +/*
5538 + * LCR=0xBF, XR16C85x
5539 + */
5540 +//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
5541 +// * In: Fifo count
5542 +// * Out: Fifo custom trigger levels */
5543 +/*
5544 + * These are the definitions for the Programmable Trigger Register
5545 + */
5546 +#define UART_TRG_1 0x01
5547 +#define UART_TRG_4 0x04
5548 +#define UART_TRG_8 0x08
5549 +#define UART_TRG_16 0x10
5550 +#define UART_TRG_32 0x20
5551 +#define UART_TRG_64 0x40
5552 +#define UART_TRG_96 0x60
5553 +#define UART_TRG_120 0x78
5554 +#define UART_TRG_128 0x80
5555 +
5556 +//#define UART_FCTR 1 /* Feature Control Register */
5557 +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
5558 +#define UART_FCTR_RTS_4DELAY 0x01
5559 +#define UART_FCTR_RTS_6DELAY 0x02
5560 +#define UART_FCTR_RTS_8DELAY 0x03
5561 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
5562 +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
5563 +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
5564 +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
5565 +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
5566 +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
5567 +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
5568 +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
5569 +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
5570 +
5571 +/*
5572 + * LCR=0xBF, FCTR[6]=1
5573 + */
5574 +//#define UART_EMSR 7 /* Extended Mode Select Register */
5575 +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
5576 +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
5577 +
5578 +/*
5579 + * The Intel XScale on-chip UARTs define these bits
5580 + */
5581 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
5582 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
5583 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
5584 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
5585 +
5586 +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
5587 +
5588 +#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
5589 +#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
5590 +#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
5591 +#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
5592 +
5593 +
5594 +
5595 +
5596 +/*
5597 + * These register definitions are for the 16C950
5598 + */
5599 +#define UART_ASR 0x01 /* Additional Status Register */
5600 +#define UART_RFL 0x03 /* Receiver FIFO level */
5601 +#define UART_TFL 0x04 /* Transmitter FIFO level */
5602 +#define UART_ICR 0x05 /* Index Control Register */
5603 +
5604 +/* The 16950 ICR registers */
5605 +#define UART_ACR 0x00 /* Additional Control Register */
5606 +#define UART_CPR 0x01 /* Clock Prescalar Register */
5607 +#define UART_TCR 0x02 /* Times Clock Register */
5608 +#define UART_CKS 0x03 /* Clock Select Register */
5609 +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
5610 +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
5611 +#define UART_FCL 0x06 /* Flow Control Level Lower */
5612 +#define UART_FCH 0x07 /* Flow Control Level Higher */
5613 +#define UART_ID1 0x08 /* ID #1 */
5614 +#define UART_ID2 0x09 /* ID #2 */
5615 +#define UART_ID3 0x0A /* ID #3 */
5616 +#define UART_REV 0x0B /* Revision */
5617 +#define UART_CSR 0x0C /* Channel Software Reset */
5618 +#define UART_NMR 0x0D /* Nine-bit Mode Register */
5619 +#define UART_CTR 0xFF
5620 +
5621 +/*
5622 + * The 16C950 Additional Control Reigster
5623 + */
5624 +#define UART_ACR_RXDIS 0x01 /* Receiver disable */
5625 +#define UART_ACR_TXDIS 0x02 /* Receiver disable */
5626 +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
5627 +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
5628 +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
5629 +#define UART_ACR_ASREN 0x80 /* Additional status enable */
5630 +
5631 +
5632 +
5633 +/*
5634 + * These definitions are for the RSA-DV II/S card, from
5635 + *
5636 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
5637 + */
5638 +
5639 +#define UART_RSA_BASE (-8)
5640 +
5641 +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
5642 +
5643 +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
5644 +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
5645 +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
5646 +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
5647 +
5648 +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
5649 +
5650 +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
5651 +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
5652 +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
5653 +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
5654 +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
5655 +
5656 +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
5657 +
5658 +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
5659 +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
5660 +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
5661 +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
5662 +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
5663 +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
5664 +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
5665 +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
5666 +
5667 +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
5668 +
5669 +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
5670 +
5671 +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
5672 +
5673 +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
5674 +
5675 +/*
5676 + * The RSA DSV/II board has two fixed clock frequencies. One is the
5677 + * standard rate, and the other is 8 times faster.
5678 + */
5679 +#define SERIAL_RSA_BAUD_BASE (921600)
5680 +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
5681 +
5682 +/*
5683 + * Extra serial register definitions for the internal UARTs
5684 + * in TI OMAP processors.
5685 + */
5686 +#define UART_OMAP_MDR1 0x08 /* Mode definition register */
5687 +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
5688 +#define UART_OMAP_SCR 0x10 /* Supplementary control register */
5689 +#define UART_OMAP_SSR 0x11 /* Supplementary status register */
5690 +#define UART_OMAP_EBLR 0x12 /* BOF length register */
5691 +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
5692 +#define UART_OMAP_MVER 0x14 /* Module version register */
5693 +#define UART_OMAP_SYSC 0x15 /* System configuration register */
5694 +#define UART_OMAP_SYSS 0x16 /* System status register */
5695 +
5696 +
5697 --- /dev/null
5698 +++ b/arch/mips/include/asm/rt2880/sizes.h
5699 @@ -0,0 +1,52 @@
5700 +/*
5701 + * This program is free software; you can redistribute it and/or modify
5702 + * it under the terms of the GNU General Public License as published by
5703 + * the Free Software Foundation; either version 2 of the License, or
5704 + * (at your option) any later version.
5705 + *
5706 + * This program is distributed in the hope that it will be useful,
5707 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5708 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5709 + * GNU General Public License for more details.
5710 + *
5711 + * You should have received a copy of the GNU General Public License
5712 + * along with this program; if not, write to the Free Software
5713 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5714 + */
5715 +/* DO NOT EDIT!! - this file automatically generated
5716 + * from .s file by awk -f s2h.awk
5717 + */
5718 +/* Size definitions
5719 + * Copyright (C) ARM Limited 1998. All rights reserved.
5720 + */
5721 +
5722 +#ifndef __sizes_h
5723 +#define __sizes_h 1
5724 +
5725 +/* handy sizes */
5726 +#define SZ_1K 0x00000400
5727 +#define SZ_4K 0x00001000
5728 +#define SZ_8K 0x00002000
5729 +#define SZ_16K 0x00004000
5730 +#define SZ_64K 0x00010000
5731 +#define SZ_128K 0x00020000
5732 +#define SZ_256K 0x00040000
5733 +#define SZ_512K 0x00080000
5734 +
5735 +#define SZ_1M 0x00100000
5736 +#define SZ_2M 0x00200000
5737 +#define SZ_4M 0x00400000
5738 +#define SZ_8M 0x00800000
5739 +#define SZ_16M 0x01000000
5740 +#define SZ_32M 0x02000000
5741 +#define SZ_64M 0x04000000
5742 +#define SZ_128M 0x08000000
5743 +#define SZ_256M 0x10000000
5744 +#define SZ_512M 0x20000000
5745 +
5746 +#define SZ_1G 0x40000000
5747 +#define SZ_2G 0x80000000
5748 +
5749 +#endif
5750 +
5751 +/* END */
5752 --- /dev/null
5753 +++ b/arch/mips/include/asm/rt2880/surfboard.h
5754 @@ -0,0 +1,70 @@
5755 +/*
5756 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
5757 + *
5758 + * ########################################################################
5759 + *
5760 + * This program is free software; you can distribute it and/or modify it
5761 + * under the terms of the GNU General Public License (Version 2) as
5762 + * published by the Free Software Foundation.
5763 + *
5764 + * This program is distributed in the hope it will be useful, but WITHOUT
5765 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5766 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
5767 + * for more details.
5768 + *
5769 + * You should have received a copy of the GNU General Public License along
5770 + * with this program; if not, write to the Free Software Foundation, Inc.,
5771 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
5772 + *
5773 + * ########################################################################
5774 + *
5775 + */
5776 +#ifndef _SURFBOARD_H
5777 +#define _SURFBOARD_H
5778 +
5779 +#include <asm/addrspace.h>
5780 +
5781 +
5782 +
5783 +/*
5784 + * Surfboard system clock.
5785 + * This is the default value and maybe overidden by System Clock passed on the
5786 + * command line (sysclk=).
5787 + */
5788 +#define SURFBOARD_SYSTEM_CLOCK (125000000)
5789 +
5790 +/*
5791 + * Surfboard UART base baud rate = System Clock / 16.
5792 + * Ex. (14.7456 MHZ / 16) = 921600
5793 + * (32.0000 MHZ / 16) = 2000000
5794 + */
5795 +#define SURFBOARD_BAUD_DIV (16)
5796 +#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
5797 +
5798 +/*
5799 + * Maximum number of IDE Controllers
5800 + * Surfboard only has one ide (ide0), so only 2 drives are
5801 + * possible. (no need to check for more hwifs.)
5802 + */
5803 +//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
5804 +#define MAX_IDE_HWIFS (2) /* Graphite board */
5805 +
5806 +#define GCMP_BASE_ADDR 0x1fbf8000
5807 +#define GCMP_ADDRSPACE_SZ (256 * 1024)
5808 +
5809 +/*
5810 + * * GIC Specific definitions
5811 + * */
5812 +#define GIC_BASE_ADDR 0x1fbc0000
5813 +#define GIC_ADDRSPACE_SZ (128 * 1024)
5814 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
5815 +
5816 +/* GIC's Nomenclature for Core Interrupt Pins */
5817 +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
5818 +#define GIC_CPU_INT1 1 /* . */
5819 +#define GIC_CPU_INT2 2 /* . */
5820 +#define GIC_CPU_INT3 3 /* . */
5821 +#define GIC_CPU_INT4 4 /* . */
5822 +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
5823 +
5824 +#endif /* !(_SURFBOARD_H) */
5825 --- /dev/null
5826 +++ b/arch/mips/include/asm/rt2880/surfboardint.h
5827 @@ -0,0 +1,190 @@
5828 +/*
5829 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
5830 + *
5831 + * ########################################################################
5832 + *
5833 + * This program is free software; you can distribute it and/or modify it
5834 + * under the terms of the GNU General Public License (Version 2) as
5835 + * published by the Free Software Foundation.
5836 + *
5837 + * This program is distributed in the hope it will be useful, but WITHOUT
5838 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5839 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
5840 + * for more details.
5841 + *
5842 + * You should have received a copy of the GNU General Public License along
5843 + * with this program; if not, write to the Free Software Foundation, Inc.,
5844 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
5845 + *
5846 + * ########################################################################
5847 + *
5848 + * Defines for the Surfboard interrupt controller.
5849 + *
5850 + */
5851 +#ifndef _SURFBOARDINT_H
5852 +#define _SURFBOARDINT_H
5853 +
5854 +/* Number of IRQ supported on hw interrupt 0. */
5855 +#if defined (CONFIG_RALINK_RT2880)
5856 +#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
5857 +#define SURFBOARDINT_GPIO 7 /* GPIO */
5858 +#define SURFBOARDINT_UART1 8 /* UART Lite */
5859 +#define SURFBOARDINT_UART 9 /* UART */
5860 +#define SURFBOARDINT_TIMER0 10 /* timer0 */
5861 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
5862 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
5863 +#define SURFBOARDINT_GPIO 6 /* GPIO */
5864 +#define SURFBOARDINT_DMA 7 /* DMA */
5865 +#define SURFBOARDINT_NAND 8 /* NAND */
5866 +#define SURFBOARDINT_PC 9 /* Performance counter */
5867 +#define SURFBOARDINT_I2S 10 /* I2S */
5868 +#define SURFBOARDINT_SDXC 14 /* SDXC */
5869 +#define SURFBOARDINT_ESW 17 /* ESW */
5870 +#define SURFBOARDINT_UART1 12 /* UART Lite */
5871 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
5872 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
5873 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
5874 +#define SURFBOARDINT_WDG 34 /* watch dog */
5875 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
5876 +#define SURFBOARDINT_PCM 36 /* PCM */
5877 +#define SURFBOARDINT_UART 37 /* UART */
5878 +#define RALINK_INT_PCIE0 13 /* PCIE0 */
5879 +#define RALINK_INT_PCIE1 14 /* PCIE1 */
5880 +
5881 +
5882 +#elif defined (CONFIG_RALINK_MT7628)
5883 +#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
5884 +#define SURFBOARDINT_PCM 4 /* PCM */
5885 +#define SURFBOARDINT_GPIO 6 /* GPIO */
5886 +#define SURFBOARDINT_DMA 7 /* DMA */
5887 +#define SURFBOARDINT_PC 9 /* Performance counter */
5888 +#define SURFBOARDINT_I2S 10 /* I2S */
5889 +#define SURFBOARDINT_SPI 11 /* SPI */
5890 +#define SURFBOARDINT_AES 13 /* AES */
5891 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
5892 +#define SURFBOARDINT_SDXC 14 /* SDXC */
5893 +#define SURFBOARDINT_ESW 17 /* ESW */
5894 +#define SURFBOARDINT_USB 18 /* USB */
5895 +#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
5896 +#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
5897 +#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
5898 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
5899 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
5900 +#define SURFBOARDINT_WDG 23 /* WDG timer */
5901 +#define SURFBOARDINT_TIMER0 24 /* Timer0 */
5902 +#define SURFBOARDINT_TIMER1 25 /* Timer1 */
5903 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
5904 +#define RALINK_INT_PCIE0 2 /* PCIE0 */
5905 +
5906 +
5907 +#elif defined (CONFIG_RALINK_MT7621)
5908 +
5909 +#define SURFBOARDINT_FE 3 /* FE */
5910 +#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
5911 +#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
5912 +#define SURFBOARDINT_I2C 8 /* I2C */
5913 +#define SURFBOARDINT_DRAMC 9 /* DRAMC */
5914 +#define SURFBOARDINT_PCM 10 /* PCM */
5915 +#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
5916 +#define SURFBOARDINT_GPIO 12 /* GPIO */
5917 +#define SURFBOARDINT_DMA 13 /* GDMA */
5918 +#define SURFBOARDINT_NAND 14 /* NAND */
5919 +#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
5920 +#define SURFBOARDINT_I2S 16 /* I2S */
5921 +#define SURFBOARDINT_SPI 17 /* SPI */
5922 +#define SURFBOARDINT_SPDIF 18 /* SPDIF */
5923 +#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
5924 +#define SURFBOARDINT_SDXC 20 /* SDXC */
5925 +#define SURFBOARDINT_PCTRL 21 /* Performance counter */
5926 +#define SURFBOARDINT_USB 22 /* USB */
5927 +#define SURFBOARDINT_ESW 31 /* Switch */
5928 +#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
5929 +#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
5930 +#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
5931 +#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
5932 +#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
5933 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
5934 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
5935 +
5936 +#define SURFBOARDINT_WDG 29 /* WDG timer */
5937 +#define SURFBOARDINT_TIMER0 30 /* Timer0 */
5938 +#define SURFBOARDINT_TIMER1 31 /* Timer1 */
5939 +
5940 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
5941 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
5942 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
5943 +
5944 +#elif defined (CONFIG_RALINK_RT3883)
5945 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
5946 +#define SURFBOARDINT_GPIO 6 /* GPIO */
5947 +#define SURFBOARDINT_DMA 7 /* DMA */
5948 +#define SURFBOARDINT_NAND 8 /* NAND */
5949 +#define SURFBOARDINT_PC 9 /* Performance counter */
5950 +#define SURFBOARDINT_I2S 10 /* I2S */
5951 +#define SURFBOARDINT_UART1 12 /* UART Lite */
5952 +#define SURFBOARDINT_PCI 18 /* PCI */
5953 +#define SURFBOARDINT_UDEV 19 /* USB Device */
5954 +#define SURFBOARDINT_UHST 20 /* USB Host */
5955 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
5956 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
5957 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
5958 +#define SURFBOARDINT_PCM 36 /* PCM */
5959 +#define SURFBOARDINT_UART 37 /* UART */
5960 +#endif
5961 +
5962 +#define SURFBOARDINT_END 64
5963 +#define RT2880_INTERINT_START 40
5964 +
5965 +/* Global interrupt bit definitions */
5966 +#define C_SURFBOARD_GLOBAL_INT 31
5967 +#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
5968 +
5969 +/* added ??? */
5970 +#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
5971 +#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
5972 +/* end of added, bobtseng */
5973 +
5974 +/*
5975 + * Surfboard registers are memory mapped on 32-bit aligned boundaries and
5976 + * only word access are allowed.
5977 + */
5978 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
5979 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
5980 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
5981 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
5982 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
5983 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
5984 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
5985 +#else
5986 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
5987 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
5988 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
5989 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
5990 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
5991 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
5992 +#endif
5993 +
5994 +/* bobtseng added ++, 2006.3.6. */
5995 +#define read_32bit_cp0_register(source) \
5996 +({ int __res; \
5997 + __asm__ __volatile__( \
5998 + ".set\tpush\n\t" \
5999 + ".set\treorder\n\t" \
6000 + "mfc0\t%0,"STR(source)"\n\t" \
6001 + ".set\tpop" \
6002 + : "=r" (__res)); \
6003 + __res;})
6004 +
6005 +#define write_32bit_cp0_register(register,value) \
6006 + __asm__ __volatile__( \
6007 + "mtc0\t%0,"STR(register)"\n\t" \
6008 + "nop" \
6009 + : : "r" (value));
6010 +
6011 +/* bobtseng added --, 2006.3.6. */
6012 +
6013 +void surfboardint_init(void);
6014 +u32 get_surfboard_sysclk(void);
6015 +
6016 +
6017 +#endif /* !(_SURFBOARDINT_H) */
6018 --- /dev/null
6019 +++ b/arch/mips/include/asm/rt2880/war.h
6020 @@ -0,0 +1,25 @@
6021 +/*
6022 + * This file is subject to the terms and conditions of the GNU General Public
6023 + * License. See the file "COPYING" in the main directory of this archive
6024 + * for more details.
6025 + *
6026 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
6027 + */
6028 +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
6029 +#define __ASM_MIPS_MACH_MIPS_WAR_H
6030 +
6031 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
6032 +#define R4600_V1_HIT_CACHEOP_WAR 0
6033 +#define R4600_V2_HIT_CACHEOP_WAR 0
6034 +#define R5432_CP0_INTERRUPT_WAR 0
6035 +#define BCM1250_M3_WAR 0
6036 +#define SIBYTE_1956_WAR 0
6037 +#define MIPS4K_ICACHE_REFILL_WAR 1
6038 +#define MIPS_CACHE_SYNC_WAR 1
6039 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
6040 +#define RM9000_CDEX_SMP_WAR 0
6041 +#define ICACHE_REFILLS_WORKAROUND_WAR 1
6042 +#define R10000_LLSC_WAR 0
6043 +#define MIPS34K_MISSED_ITLB_WAR 0
6044 +
6045 +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
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