ramips: second spi device on rt5350
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.10 / 0222-rt5350-spi-second-device.patch
1 --- a/drivers/spi/spi-rt2880.c
2 +++ b/drivers/spi/spi-rt2880.c
3 @@ -29,16 +29,17 @@
4 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
5
6 #define DRIVER_NAME "spi-rt2880"
7 -/* only one slave is supported*/
8 -#define RALINK_NUM_CHIPSELECTS 1
9 /* in usec */
10 #define RALINK_SPI_WAIT_MAX_LOOP 2000
11
12 -#define RAMIPS_SPI_STAT 0x00
13 -#define RAMIPS_SPI_CFG 0x10
14 -#define RAMIPS_SPI_CTL 0x14
15 -#define RAMIPS_SPI_DATA 0x20
16 -#define RAMIPS_SPI_FIFO_STAT 0x38
17 +#define RAMIPS_SPI_DEV_OFFSET 0x40
18 +
19 +#define RAMIPS_SPI_STAT(cs) (0x00 + (cs * RAMIPS_SPI_DEV_OFFSET))
20 +#define RAMIPS_SPI_CFG(cs) (0x10 + (cs * RAMIPS_SPI_DEV_OFFSET))
21 +#define RAMIPS_SPI_CTL(cs) (0x14 + (cs * RAMIPS_SPI_DEV_OFFSET))
22 +#define RAMIPS_SPI_DATA(cs) (0x20 + (cs * RAMIPS_SPI_DEV_OFFSET))
23 +#define RAMIPS_SPI_FIFO_STAT(cs) (0x38 + (cs * RAMIPS_SPI_DEV_OFFSET))
24 +#define RAMIPS_SPI_ARBITER 0xF0
25
26 /* SPISTAT register bit field */
27 #define SPISTAT_BUSY BIT(0)
28 @@ -68,6 +69,10 @@
29 /* SPIFIFOSTAT register bit field */
30 #define SPIFIFOSTAT_TXFULL BIT(17)
31
32 +#define SPICTL_ARB_EN BIT(31)
33 +#define SPI1_POR BIT(1)
34 +#define SPI0_POR BIT(0)
35 +
36 #define MT7621_SPI_TRANS 0x00
37 #define SPITRANS_BUSY BIT(16)
38 #define MT7621_SPI_OPCODE 0x04
39 @@ -78,13 +83,16 @@
40 #define MT7621_SPI_MASTER 0x28
41 #define MT7621_SPI_SPACE 0x3c
42
43 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
44 +
45 struct rt2880_spi;
46
47 struct rt2880_spi_ops {
48 void (*init_hw)(struct rt2880_spi *rs);
49 - void (*set_cs)(struct rt2880_spi *rs, int enable);
50 + void (*set_cs)(struct spi_device *spi, int enable);
51 int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
52 unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
53 + int num_cs;
54 };
55
56 struct rt2880_spi {
57 @@ -141,6 +149,7 @@ static inline void rt2880_spi_clrbits(st
58
59 static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
60 {
61 + int cs = spi->chip_select;
62 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
63 u32 rate;
64 u32 prescale;
65 @@ -168,9 +177,9 @@ static int rt2880_spi_baudrate_set(struc
66 prescale = ilog2(rate / 2);
67 dev_dbg(&spi->dev, "prescale:%u\n", prescale);
68
69 - reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
70 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
71 reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
72 - rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
73 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
74 rs->speed = speed;
75 return 0;
76 }
77 @@ -194,7 +203,8 @@ rt2880_spi_setup_transfer(struct spi_dev
78 {
79 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
80 unsigned int speed = spi->max_speed_hz;
81 - int rc;
82 + int rc, cs = spi->chip_select;
83 + u32 reg;
84
85 if ((t != NULL) && t->speed_hz)
86 speed = t->speed_hz;
87 @@ -206,19 +216,61 @@ rt2880_spi_setup_transfer(struct spi_dev
88 return rc;
89 }
90
91 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
92 +
93 + reg = (reg & ~SPICFG_MSBFIRST);
94 + if (!(spi->mode & SPI_LSB_FIRST))
95 + reg |= SPICFG_MSBFIRST;
96 +
97 + reg = (reg & ~(SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING |SPICFG_TXCLKEDGE_FALLING));
98 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
99 + case SPI_MODE_0:
100 + reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
101 + break;
102 + case SPI_MODE_1:
103 + reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
104 + break;
105 + case SPI_MODE_2:
106 + reg |= SPICFG_RXCLKEDGE_FALLING;
107 + break;
108 + case SPI_MODE_3:
109 + reg |= SPICFG_TXCLKEDGE_FALLING;
110 + break;
111 + }
112 +
113 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
114 +
115 + reg = SPICTL_ARB_EN;
116 + if (spi->mode & SPI_CS_HIGH) {
117 + switch(cs) {
118 + case 0:
119 + reg |= SPI0_POR;
120 + break;
121 + case 1:
122 + reg |= SPI1_POR;
123 + break;
124 + }
125 + }
126 +
127 + rt2880_spi_write(rs, RAMIPS_SPI_ARBITER, reg);
128 +
129 return 0;
130 }
131
132 -static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
133 +static void rt2880_spi_set_cs(struct spi_device *spi, int enable)
134 {
135 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
136 + int cs = spi->chip_select;
137 +
138 if (enable)
139 - rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
140 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
141 else
142 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
143 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
144 }
145
146 -static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
147 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
148 {
149 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
150 u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
151
152 if (enable)
153 @@ -228,14 +280,16 @@ static void mt7621_spi_set_cs(struct rt2
154 rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
155 }
156
157 -static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
158 +static inline int rt2880_spi_wait_till_ready(struct spi_device *spi)
159 {
160 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
161 + int cs = spi->chip_select;
162 int i;
163
164 for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
165 u32 status;
166
167 - status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
168 + status = rt2880_spi_read(rs, RAMIPS_SPI_STAT(cs));
169 if ((status & SPISTAT_BUSY) == 0)
170 return 0;
171
172 @@ -246,8 +300,9 @@ static inline int rt2880_spi_wait_till_r
173 return -ETIMEDOUT;
174 }
175
176 -static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
177 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
178 {
179 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
180 int i;
181
182 for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
183 @@ -268,6 +323,7 @@ static unsigned int
184 rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
185 {
186 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
187 + int cs = spi->chip_select;
188 unsigned count = 0;
189 u8 *rx = xfer->rx_buf;
190 const u8 *tx = xfer->tx_buf;
191 @@ -279,9 +335,9 @@ rt2880_spi_write_read(struct spi_device
192
193 if (tx) {
194 for (count = 0; count < xfer->len; count++) {
195 - rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
196 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
197 - err = rt2880_spi_wait_till_ready(rs);
198 + rt2880_spi_write(rs, RAMIPS_SPI_DATA(cs), tx[count]);
199 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTWR);
200 + err = rt2880_spi_wait_till_ready(spi);
201 if (err) {
202 dev_err(&spi->dev, "TX failed, err=%d\n", err);
203 goto out;
204 @@ -291,13 +347,13 @@ rt2880_spi_write_read(struct spi_device
205
206 if (rx) {
207 for (count = 0; count < xfer->len; count++) {
208 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
209 - err = rt2880_spi_wait_till_ready(rs);
210 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTRD);
211 + err = rt2880_spi_wait_till_ready(spi);
212 if (err) {
213 dev_err(&spi->dev, "RX failed, err=%d\n", err);
214 goto out;
215 }
216 - rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
217 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA(cs));
218 }
219 }
220
221 @@ -364,7 +420,7 @@ mt7621_spi_write_read(struct spi_device
222 trans |= SPI_CTL_START;
223 rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
224
225 - mt7621_spi_wait_till_ready(rs);
226 + mt7621_spi_wait_till_ready(spi);
227
228 if (rx) {
229 u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
230 @@ -440,7 +496,7 @@ static int rt2880_spi_transfer_one_messa
231 }
232
233 if (!cs_active) {
234 - rs->ops->set_cs(rs, 1);
235 + rs->ops->set_cs(spi, 1);
236 cs_active = 1;
237 }
238
239 @@ -451,14 +507,14 @@ static int rt2880_spi_transfer_one_messa
240 udelay(t->delay_usecs);
241
242 if (t->cs_change) {
243 - rs->ops->set_cs(rs, 0);
244 + rs->ops->set_cs(spi, 0);
245 cs_active = 0;
246 }
247 }
248
249 msg_done:
250 if (cs_active)
251 - rs->ops->set_cs(rs, 0);
252 + rs->ops->set_cs(spi, 0);
253
254 m->status = status;
255 spi_finalize_current_message(master);
256 @@ -471,7 +527,7 @@ static int rt2880_spi_setup(struct spi_d
257 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
258
259 if ((spi->max_speed_hz == 0) ||
260 - (spi->max_speed_hz > (rs->sys_freq / 2)))
261 + (spi->max_speed_hz > (rs->sys_freq / 2)))
262 spi->max_speed_hz = (rs->sys_freq / 2);
263
264 if (spi->max_speed_hz < (rs->sys_freq / 128)) {
265 @@ -488,10 +544,25 @@ static int rt2880_spi_setup(struct spi_d
266
267 static void rt2880_spi_reset(struct rt2880_spi *rs)
268 {
269 - rt2880_spi_write(rs, RAMIPS_SPI_CFG,
270 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(0),
271 SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
272 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
273 - rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
274 + rt2880_spi_write(rs, RAMIPS_SPI_CTL(0), SPICTL_HIZSDO | SPICTL_SPIENA);
275 +}
276 +
277 +static void rt5350_spi_reset(struct rt2880_spi *rs)
278 +{
279 + int cs;
280 +
281 + rt2880_spi_write(rs, RAMIPS_SPI_ARBITER,
282 + SPICTL_ARB_EN);
283 +
284 + for (cs = 0; cs < rs->ops->num_cs; cs++) {
285 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs),
286 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
287 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
288 + rt2880_spi_write(rs, RAMIPS_SPI_CTL(cs), SPICTL_HIZSDO | SPICTL_SPIENA);
289 + }
290 }
291
292 static void mt7621_spi_reset(struct rt2880_spi *rs)
293 @@ -511,24 +582,33 @@ static struct rt2880_spi_ops spi_ops[] =
294 .set_cs = rt2880_spi_set_cs,
295 .baudrate_set = rt2880_spi_baudrate_set,
296 .write_read = rt2880_spi_write_read,
297 + .num_cs = 1,
298 + }, {
299 + .init_hw = rt5350_spi_reset,
300 + .set_cs = rt2880_spi_set_cs,
301 + .baudrate_set = rt2880_spi_baudrate_set,
302 + .write_read = rt2880_spi_write_read,
303 + .num_cs = 2,
304 }, {
305 .init_hw = mt7621_spi_reset,
306 .set_cs = mt7621_spi_set_cs,
307 .baudrate_set = mt7621_spi_baudrate_set,
308 .write_read = mt7621_spi_write_read,
309 + .num_cs = 1,
310 },
311 };
312
313 static const struct of_device_id rt2880_spi_match[] = {
314 { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
315 - { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
316 + { .compatible = "ralink,rt5350-spi", .data = &spi_ops[1]},
317 + { .compatible = "ralink,mt7621-spi", .data = &spi_ops[2] },
318 {},
319 };
320 MODULE_DEVICE_TABLE(of, rt2880_spi_match);
321
322 static int rt2880_spi_probe(struct platform_device *pdev)
323 {
324 - const struct of_device_id *match;
325 + const struct of_device_id *match;
326 struct spi_master *master;
327 struct rt2880_spi *rs;
328 unsigned long flags;
329 @@ -536,10 +616,12 @@ static int rt2880_spi_probe(struct platf
330 struct resource *r;
331 int status = 0;
332 struct clk *clk;
333 + struct rt2880_spi_ops *ops;
334
335 - match = of_match_device(rt2880_spi_match, &pdev->dev);
336 + match = of_match_device(rt2880_spi_match, &pdev->dev);
337 if (!match)
338 return -EINVAL;
339 + ops = (struct rt2880_spi_ops *)match->data;
340
341 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342 base = devm_ioremap_resource(&pdev->dev, r);
343 @@ -563,14 +645,13 @@ static int rt2880_spi_probe(struct platf
344 return -ENOMEM;
345 }
346
347 - /* we support only mode 0, and no options */
348 - master->mode_bits = 0;
349 + master->mode_bits = RT2880_SPI_MODE_BITS;
350
351 master->setup = rt2880_spi_setup;
352 master->transfer_one_message = rt2880_spi_transfer_one_message;
353 - master->num_chipselect = RALINK_NUM_CHIPSELECTS;
354 master->bits_per_word_mask = SPI_BPW_MASK(8);
355 master->dev.of_node = pdev->dev.of_node;
356 + master->num_chipselect = ops->num_cs;
357
358 dev_set_drvdata(&pdev->dev, master);
359
360 @@ -579,7 +660,7 @@ static int rt2880_spi_probe(struct platf
361 rs->clk = clk;
362 rs->master = master;
363 rs->sys_freq = clk_get_rate(rs->clk);
364 - rs->ops = (struct rt2880_spi_ops *) match->data;
365 + rs->ops = ops;
366 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
367 spin_lock_irqsave(&rs->lock, flags);
368