target/linux/ramips/patches-3.10/0500-spi-mt7621.patch

   1 --- a/drivers/spi/spi-rt2880.c
   2 +++ b/drivers/spi/spi-rt2880.c
   3 @@ -21,8 +21,11 @@
   4  #include <linux/io.h>
   5  #include <linux/reset.h>
   6  #include <linux/spi/spi.h>
   7 +#include <linux/of_device.h>
   8  #include <linux/platform_device.h>
   9
  10 +#include <ralink_regs.h>
  11 +
  12  #define DRIVER_NAME                    "spi-rt2880"
  13  /* only one slave is supported*/
  14  #define RALINK_NUM_CHIPSELECTS         1
  15 @@ -63,6 +66,25 @@
  16  /* SPIFIFOSTAT register bit field */
  17  #define SPIFIFOSTAT_TXFULL             BIT(17)
  18
  19 +#define MT7621_SPI_TRANS       0x00
  20 +#define SPITRANS_BUSY          BIT(16)
  21 +#define MT7621_SPI_OPCODE      0x04
  22 +#define MT7621_SPI_DATA0       0x08
  23 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  24 +#define SPI_CTL_START          BIT(8)
  25 +#define MT7621_SPI_POLAR       0x38
  26 +#define MT7621_SPI_MASTER      0x28
  27 +#define MT7621_SPI_SPACE       0x3c
  28 +
  29 +struct rt2880_spi;
  30 +
  31 +struct rt2880_spi_ops {
  32 +       void (*init_hw)(struct rt2880_spi *rs);
  33 +       void (*set_cs)(struct rt2880_spi *rs, int enable);
  34 +       int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
  35 +       unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
  36 +};
  37 +
  38  struct rt2880_spi {
  39         struct spi_master       *master;
  40         void __iomem            *base;
  41 @@ -70,6 +92,8 @@ struct rt2880_spi {
  42         unsigned int            speed;
  43         struct clk              *clk;
  44         spinlock_t              lock;
  45 +
  46 +       struct rt2880_spi_ops   *ops;
  47  };
  48
  49  static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
  50 @@ -149,6 +173,17 @@ static int rt2880_spi_baudrate_set(struc
  51         return 0;
  52  }
  53
  54 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  55 +{
  56 +/*     u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
  57 +
  58 +       // set default clock to hclk/5
  59 +       master &= ~(0xfff << 16);
  60 +       master |= 0x3 << 16;
  61 +*/
  62 +       return 0;
  63 +}
  64 +
  65  /*
  66   * called only when no transfer is active on the bus
  67   */
  68 @@ -164,7 +199,7 @@ rt2880_spi_setup_transfer(struct spi_dev
  69
  70         if (rs->speed != speed) {
  71                 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
  72 -               rc = rt2880_spi_baudrate_set(spi, speed);
  73 +               rc = rs->ops->baudrate_set(spi, speed);
  74                 if (rc)
  75                         return rc;
  76         }
  77 @@ -180,6 +215,17 @@ static void rt2880_spi_set_cs(struct rt2
  78                 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
  79  }
  80
  81 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
  82 +{
  83 +       u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
  84 +
  85 +       if (enable)
  86 +               polar |= 1;
  87 +       else
  88 +               polar &= ~1;
  89 +       rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
  90 +}
  91 +
  92  static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
  93  {
  94         int i;
  95 @@ -198,8 +244,26 @@ static inline int rt2880_spi_wait_till_r
  96         return -ETIMEDOUT;
  97  }
  98
  99 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
 100 +{
 101 +       int i;
 102 +
 103 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 104 +               u32 status;
 105 +
 106 +               status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 107 +               if ((status & SPITRANS_BUSY) == 0) {
 108 +                       return 0;
 109 +               }
 110 +               cpu_relax();
 111 +               udelay(1);
 112 +       }
 113 +
 114 +       return -ETIMEDOUT;
 115 +}
 116 +
 117  static unsigned int
 118 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 119 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 120  {
 121         struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 122         unsigned count = 0;
 123 @@ -239,6 +303,100 @@ out:
 124         return count;
 125  }
 126
 127 +static unsigned int
 128 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 129 +{
 130 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 131 +       struct spi_transfer *next = NULL;
 132 +       const u8 *tx = xfer->tx_buf;
 133 +       u8 *rx = NULL;
 134 +       u32 trans;
 135 +       int len = xfer->len;
 136 +
 137 +       if (!tx)
 138 +               return 0;
 139 +
 140 +       if (!list_is_last(&xfer->transfer_list, list)) {
 141 +               next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
 142 +               rx = next->rx_buf;
 143 +       }
 144 +
 145 +       trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 146 +       trans &= ~SPI_CTL_TX_RX_CNT_MASK;
 147 +
 148 +       if (tx) {
 149 +               u32 data0 = 0, opcode = 0;
 150 +
 151 +               switch (xfer->len) {
 152 +               case 8:
 153 +                       data0 |= tx[7] << 24;
 154 +               case 7:
 155 +                       data0 |= tx[6] << 16;
 156 +               case 6:
 157 +                       data0 |= tx[5] << 8;
 158 +               case 5:
 159 +                       data0 |= tx[4];
 160 +               case 4:
 161 +                       opcode |= tx[3] << 8;
 162 +               case 3:
 163 +                       opcode |= tx[2] << 16;
 164 +               case 2:
 165 +                       opcode |= tx[1] << 24;
 166 +               case 1:
 167 +                       opcode |= tx[0];
 168 +                       break;
 169 +
 170 +               default:
 171 +                       dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
 172 +                       return -EINVAL;
 173 +               }
 174 +
 175 +               rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
 176 +               rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
 177 +               trans |= xfer->len;
 178 +       }
 179 +
 180 +       if (rx)
 181 +               trans |= (next->len << 4);
 182 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 183 +       trans |= SPI_CTL_START;
 184 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 185 +
 186 +       mt7621_spi_wait_till_ready(rs);
 187 +
 188 +       if (rx) {
 189 +               u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
 190 +               u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
 191 +
 192 +               switch (next->len) {
 193 +               case 8:
 194 +                       rx[7] = (opcode >> 24) & 0xff;
 195 +               case 7:
 196 +                       rx[6] = (opcode >> 16) & 0xff;
 197 +               case 6:
 198 +                       rx[5] = (opcode >> 8) & 0xff;
 199 +               case 5:
 200 +                       rx[4] = opcode & 0xff;
 201 +               case 4:
 202 +                       rx[3] = (data0 >> 24) & 0xff;
 203 +               case 3:
 204 +                       rx[2] = (data0 >> 16) & 0xff;
 205 +               case 2:
 206 +                       rx[1] = (data0 >> 8) & 0xff;
 207 +               case 1:
 208 +                       rx[0] = data0 & 0xff;
 209 +                       break;
 210 +
 211 +               default:
 212 +                       dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
 213 +                       return -EINVAL;
 214 +               }
 215 +               len += next->len;
 216 +       }
 217 +
 218 +       return len;
 219 +}
 220 +
 221  static int rt2880_spi_transfer_one_message(struct spi_master *master,
 222                                            struct spi_message *m)
 223  {
 224 @@ -280,25 +438,25 @@ static int rt2880_spi_transfer_one_messa
 225                 }
 226
 227                 if (!cs_active) {
 228 -                       rt2880_spi_set_cs(rs, 1);
 229 +                       rs->ops->set_cs(rs, 1);
 230                         cs_active = 1;
 231                 }
 232
 233                 if (t->len)
 234 -                       m->actual_length += rt2880_spi_write_read(spi, t);
 235 +                       m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
 236
 237                 if (t->delay_usecs)
 238                         udelay(t->delay_usecs);
 239
 240                 if (t->cs_change) {
 241 -                       rt2880_spi_set_cs(rs, 0);
 242 +                       rs->ops->set_cs(rs, 0);
 243                         cs_active = 0;
 244                 }
 245         }
 246
 247  msg_done:
 248         if (cs_active)
 249 -               rt2880_spi_set_cs(rs, 0);
 250 +               rs->ops->set_cs(rs, 0);
 251
 252         m->status = status;
 253         spi_finalize_current_message(master);
 254 @@ -334,8 +492,41 @@ static void rt2880_spi_reset(struct rt28
 255         rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 256  }
 257
 258 +static void mt7621_spi_reset(struct rt2880_spi *rs)
 259 +{
 260 +       u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
 261 +
 262 +       master &= ~(0xfff << 16);
 263 +       master |= 3 << 16;
 264 +
 265 +       master |= 7 << 29;
 266 +       rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
 267 +}
 268 +
 269 +static struct rt2880_spi_ops spi_ops[] = {
 270 +       {
 271 +               .init_hw = rt2880_spi_reset,
 272 +               .set_cs = rt2880_spi_set_cs,
 273 +               .baudrate_set = rt2880_spi_baudrate_set,
 274 +               .write_read = rt2880_spi_write_read,
 275 +       }, {
 276 +               .init_hw = mt7621_spi_reset,
 277 +               .set_cs = mt7621_spi_set_cs,
 278 +               .baudrate_set = mt7621_spi_baudrate_set,
 279 +               .write_read = mt7621_spi_write_read,
 280 +       },
 281 +};
 282 +
 283 +static const struct of_device_id rt2880_spi_match[] = {
 284 +       { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
 285 +       { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
 286 +       {},
 287 +};
 288 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 289 +
 290  static int rt2880_spi_probe(struct platform_device *pdev)
 291  {
 292 +        const struct of_device_id *match;
 293         struct spi_master *master;
 294         struct rt2880_spi *rs;
 295         unsigned long flags;
 296 @@ -344,6 +535,10 @@ static int rt2880_spi_probe(struct platf
 297         int status = 0;
 298         struct clk *clk;
 299
 300 +        match = of_match_device(rt2880_spi_match, &pdev->dev);
 301 +       if (!match)
 302 +               return -EINVAL;
 303 +
 304         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 305         base = devm_ioremap_resource(&pdev->dev, r);
 306         if (IS_ERR(base))
 307 @@ -382,12 +577,13 @@ static int rt2880_spi_probe(struct platf
 308         rs->clk = clk;
 309         rs->master = master;
 310         rs->sys_freq = clk_get_rate(rs->clk);
 311 +       rs->ops = (struct rt2880_spi_ops *) match->data;
 312         dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 313         spin_lock_irqsave(&rs->lock, flags);
 314
 315         device_reset(&pdev->dev);
 316
 317 -       rt2880_spi_reset(rs);
 318 +       rs->ops->init_hw(rs);
 319
 320         return spi_register_master(master);
 321  }
 322 @@ -408,12 +604,6 @@ static int rt2880_spi_remove(struct plat
 323
 324  MODULE_ALIAS("platform:" DRIVER_NAME);
 325
 326 -static const struct of_device_id rt2880_spi_match[] = {
 327 -       { .compatible = "ralink,rt2880-spi" },
 328 -       {},
 329 -};
 330 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 331 -
 332  static struct platform_driver rt2880_spi_driver = {
 333         .driver = {
 334                 .name = DRIVER_NAME,