ramips: enable second SPI for VoCore
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.14 / 0001-MIPS-ralink-add-verbose-pmu-info.patch
1 From 453850d315070678245f61202ae343153589e5a6 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:16:50 +0100
4 Subject: [PATCH 01/57] MIPS: ralink: add verbose pmu info
5
6 Print the PMU and LDO settings on boot.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
11 1 file changed, 26 insertions(+)
12
13 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
14 index a3ad56c..5846817 100644
15 --- a/arch/mips/ralink/mt7620.c
16 +++ b/arch/mips/ralink/mt7620.c
17 @@ -20,6 +20,22 @@
18
19 #include "common.h"
20
21 +/* analog */
22 +#define PMU0_CFG 0x88
23 +#define PMU_SW_SET BIT(28)
24 +#define A_DCDC_EN BIT(24)
25 +#define A_SSC_PERI BIT(19)
26 +#define A_SSC_GEN BIT(18)
27 +#define A_SSC_M 0x3
28 +#define A_SSC_S 16
29 +#define A_DLY_M 0x7
30 +#define A_DLY_S 8
31 +#define A_VTUNE_M 0xff
32 +
33 +/* digital */
34 +#define PMU1_CFG 0x8C
35 +#define DIG_SW_SEL BIT(25)
36 +
37 /* does the board have sdram or ddram */
38 static int dram_type;
39
40 @@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
41 u32 n1;
42 u32 rev;
43 u32 cfg0;
44 + u32 pmu0;
45 + u32 pmu1;
46
47 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
48 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
49 @@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
50 BUG();
51 }
52 soc_info->mem_base = MT7620_DRAM_BASE;
53 +
54 + pmu0 = __raw_readl(sysc + PMU0_CFG);
55 + pmu1 = __raw_readl(sysc + PMU1_CFG);
56 +
57 + pr_info("Analog PMU set to %s control\n",
58 + (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
59 + pr_info("Digital PMU set to %s control\n",
60 + (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
61 }
62 --
63 1.7.10.4
64