ramips: enable second SPI for VoCore
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.14 / 0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch
1 From 1f1c12e85defba9459b41ec95b86f23b4791f1ab Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 4 Aug 2014 20:43:25 +0200
4 Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency
5 scaling
6
7 If the USB HCD is running and the cpu is scaled too low, then the USB stops
8 working. Increase the idle speed of the core to fix this if the kernel is
9 built with USB support.
10
11 The values are taken from the Ralink SDK Kernel.
12
13 Signed-off-by: John Crispin <blogic@openwrt.org>
14 ---
15 arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
16 1 file changed, 19 insertions(+)
17
18 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
19 index c883973..d68b8ff 100644
20 --- a/arch/mips/ralink/mt7620.c
21 +++ b/arch/mips/ralink/mt7620.c
22 @@ -36,6 +36,12 @@
23 #define PMU1_CFG 0x8C
24 #define DIG_SW_SEL BIT(25)
25
26 +/* clock scaling */
27 +#define CLKCFG_FDIV_MASK 0x1f00
28 +#define CLKCFG_FDIV_USB_VAL 0x0300
29 +#define CLKCFG_FFRAC_MASK 0x001f
30 +#define CLKCFG_FFRAC_USB_VAL 0x0003
31 +
32 /* does the board have sdram or ddram */
33 static int dram_type;
34
35 @@ -337,6 +343,19 @@ void __init ralink_clk_init(void)
36 ralink_clk_add("10000b00.spi", sys_rate);
37 ralink_clk_add("10000c00.uartlite", periph_rate);
38 ralink_clk_add("10180000.wmac", xtal_rate);
39 +
40 + if (IS_ENABLED(CONFIG_USB)) {
41 + /*
42 + * When the CPU goes into sleep mode, the BUS clock will be too low for
43 + * USB to function properly
44 + */
45 + u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
46 +
47 + val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
48 + val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
49 +
50 + rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
51 + }
52 }
53
54 void __init ralink_of_remap(void)
55 --
56 1.7.10.4
57