target/linux/ramips/patches-3.14/0031-PCI-MIPS-adds-rt2880-pci-support.patch

   1 From 5b0bcc314005dd14eeae190948165a81eef7da1f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:36:02 +0100
   4 Subject: [PATCH 31/57] PCI: MIPS: adds rt2880 pci support
   5
   6 Add support for the pci found on the rt2880 SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/pci/Makefile     |    1 +
  11  arch/mips/pci/pci-rt2880.c |  281 ++++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ralink/Kconfig   |    1 +
  13  3 files changed, 283 insertions(+)
  14  create mode 100644 arch/mips/pci/pci-rt2880.c
  15
  16 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
  17 index d054bc8..6a0f453 100644
  18 --- a/arch/mips/pci/Makefile
  19 +++ b/arch/mips/pci/Makefile
  20 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops-sni.o
  21  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  22  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  23  obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  24 +obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  25  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  26  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  27  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  28 diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
  29 new file mode 100644
  30 index 0000000..e2c4730
  31 --- /dev/null
  32 +++ b/arch/mips/pci/pci-rt2880.c
  33 @@ -0,0 +1,281 @@
  34 +/*
  35 + *  Ralink RT288x SoC PCI register definitions
  36 + *
  37 + *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
  38 + *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  39 + *
  40 + *  Parts of this file are based on Ralink's 2.6.21 BSP
  41 + *
  42 + *  This program is free software; you can redistribute it and/or modify it
  43 + *  under the terms of the GNU General Public License version 2 as published
  44 + *  by the Free Software Foundation.
  45 + */
  46 +
  47 +#include <linux/types.h>
  48 +#include <linux/pci.h>
  49 +#include <linux/io.h>
  50 +#include <linux/init.h>
  51 +#include <linux/module.h>
  52 +#include <linux/of_platform.h>
  53 +#include <linux/of_irq.h>
  54 +#include <linux/of_pci.h>
  55 +
  56 +#include <asm/mach-ralink/rt288x.h>
  57 +
  58 +#define RT2880_PCI_BASE                0x00440000
  59 +#define RT288X_CPU_IRQ_PCI     4
  60 +
  61 +#define RT2880_PCI_MEM_BASE    0x20000000
  62 +#define RT2880_PCI_MEM_SIZE    0x10000000
  63 +#define RT2880_PCI_IO_BASE     0x00460000
  64 +#define RT2880_PCI_IO_SIZE     0x00010000
  65 +
  66 +#define RT2880_PCI_REG_PCICFG_ADDR     0x00
  67 +#define RT2880_PCI_REG_PCIMSK_ADDR     0x0c
  68 +#define RT2880_PCI_REG_BAR0SETUP_ADDR  0x10
  69 +#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
  70 +#define RT2880_PCI_REG_CONFIG_ADDR     0x20
  71 +#define RT2880_PCI_REG_CONFIG_DATA     0x24
  72 +#define RT2880_PCI_REG_MEMBASE         0x28
  73 +#define RT2880_PCI_REG_IOBASE          0x2c
  74 +#define RT2880_PCI_REG_ID              0x30
  75 +#define RT2880_PCI_REG_CLASS           0x34
  76 +#define RT2880_PCI_REG_SUBID           0x38
  77 +#define RT2880_PCI_REG_ARBCTL          0x80
  78 +
  79 +static void __iomem *rt2880_pci_base;
  80 +static DEFINE_SPINLOCK(rt2880_pci_lock);
  81 +
  82 +static u32 rt2880_pci_reg_read(u32 reg)
  83 +{
  84 +       return readl(rt2880_pci_base + reg);
  85 +}
  86 +
  87 +static void rt2880_pci_reg_write(u32 val, u32 reg)
  88 +{
  89 +       writel(val, rt2880_pci_base + reg);
  90 +}
  91 +
  92 +static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  93 +                                        unsigned int func, unsigned int where)
  94 +{
  95 +       return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  96 +               0x80000000);
  97 +}
  98 +
  99 +static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 100 +                                 int where, int size, u32 *val)
 101 +{
 102 +       unsigned long flags;
 103 +       u32 address;
 104 +       u32 data;
 105 +
 106 +       address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 107 +                                        PCI_FUNC(devfn), where);
 108 +
 109 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 110 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 111 +       data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 112 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 113 +
 114 +       switch (size) {
 115 +       case 1:
 116 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 117 +               break;
 118 +       case 2:
 119 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 120 +               break;
 121 +       case 4:
 122 +               *val = data;
 123 +               break;
 124 +       }
 125 +
 126 +       return PCIBIOS_SUCCESSFUL;
 127 +}
 128 +
 129 +static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 130 +                                  int where, int size, u32 val)
 131 +{
 132 +       unsigned long flags;
 133 +       u32 address;
 134 +       u32 data;
 135 +
 136 +       address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 137 +                                        PCI_FUNC(devfn), where);
 138 +
 139 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 140 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 141 +       data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 142 +
 143 +       switch (size) {
 144 +       case 1:
 145 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 146 +                      (val << ((where & 3) << 3));
 147 +               break;
 148 +       case 2:
 149 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 150 +                      (val << ((where & 3) << 3));
 151 +               break;
 152 +       case 4:
 153 +               data = val;
 154 +               break;
 155 +       }
 156 +
 157 +       rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
 158 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 159 +
 160 +       return PCIBIOS_SUCCESSFUL;
 161 +}
 162 +
 163 +static struct pci_ops rt2880_pci_ops = {
 164 +       .read   = rt2880_pci_config_read,
 165 +       .write  = rt2880_pci_config_write,
 166 +};
 167 +
 168 +static struct resource rt2880_pci_mem_resource = {
 169 +       .name   = "PCI MEM space",
 170 +       .start  = RT2880_PCI_MEM_BASE,
 171 +       .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
 172 +       .flags  = IORESOURCE_MEM,
 173 +};
 174 +
 175 +static struct resource rt2880_pci_io_resource = {
 176 +       .name   = "PCI IO space",
 177 +       .start  = RT2880_PCI_IO_BASE,
 178 +       .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
 179 +       .flags  = IORESOURCE_IO,
 180 +};
 181 +
 182 +static struct pci_controller rt2880_pci_controller = {
 183 +       .pci_ops        = &rt2880_pci_ops,
 184 +       .mem_resource   = &rt2880_pci_mem_resource,
 185 +       .io_resource    = &rt2880_pci_io_resource,
 186 +};
 187 +
 188 +static inline u32 rt2880_pci_read_u32(unsigned long reg)
 189 +{
 190 +       unsigned long flags;
 191 +       u32 address;
 192 +       u32 ret;
 193 +
 194 +       address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 195 +
 196 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 197 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 198 +       ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 199 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 200 +
 201 +       return ret;
 202 +}
 203 +
 204 +static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
 205 +{
 206 +       unsigned long flags;
 207 +       u32 address;
 208 +
 209 +       address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 210 +
 211 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 212 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 213 +       rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
 214 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 215 +}
 216 +
 217 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 218 +{
 219 +       u16 cmd;
 220 +       int irq = -1;
 221 +
 222 +       if (dev->bus->number != 0)
 223 +               return irq;
 224 +
 225 +       switch (PCI_SLOT(dev->devfn)) {
 226 +       case 0x00:
 227 +               rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
 228 +               (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 229 +               break;
 230 +       case 0x11:
 231 +               irq = RT288X_CPU_IRQ_PCI;
 232 +               break;
 233 +       default:
 234 +               printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 235 +                      __FILE__, __func__, __LINE__);
 236 +               BUG();
 237 +               break;
 238 +       }
 239 +
 240 +       pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 241 +       pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 242 +       pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 243 +       cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 244 +              PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 245 +              PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 246 +       pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 247 +       pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 248 +                             dev->irq);
 249 +       return irq;
 250 +}
 251 +
 252 +static int rt288x_pci_probe(struct platform_device *pdev)
 253 +{
 254 +       void __iomem *io_map_base;
 255 +       int i;
 256 +
 257 +       rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
 258 +
 259 +       io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
 260 +       rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
 261 +       set_io_port_base((unsigned long) io_map_base);
 262 +
 263 +       ioport_resource.start = RT2880_PCI_IO_BASE;
 264 +       ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
 265 +
 266 +       rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
 267 +       for(i = 0; i < 0xfffff; i++) {}
 268 +
 269 +       rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
 270 +       rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 271 +       rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
 272 +       rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
 273 +       rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
 274 +       rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
 275 +       rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 276 +       rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 277 +       rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
 278 +
 279 +       rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
 280 +       (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 281 +
 282 +       register_pci_controller(&rt2880_pci_controller);
 283 +       return 0;
 284 +}
 285 +
 286 +int pcibios_plat_dev_init(struct pci_dev *dev)
 287 +{
 288 +       return 0;
 289 +}
 290 +
 291 +static const struct of_device_id rt288x_pci_match[] = {
 292 +       { .compatible = "ralink,rt288x-pci" },
 293 +       {},
 294 +};
 295 +MODULE_DEVICE_TABLE(of, rt288x_pci_match);
 296 +
 297 +static struct platform_driver rt288x_pci_driver = {
 298 +       .probe = rt288x_pci_probe,
 299 +       .driver = {
 300 +               .name = "rt288x-pci",
 301 +               .owner = THIS_MODULE,
 302 +               .of_match_table = rt288x_pci_match,
 303 +       },
 304 +};
 305 +
 306 +int __init pcibios_init(void)
 307 +{
 308 +       int ret = platform_driver_register(&rt288x_pci_driver);
 309 +       if (ret)
 310 +               pr_info("rt288x-pci: Error registering platform driver!");
 311 +       return ret;
 312 +}
 313 +
 314 +arch_initcall(pcibios_init);
 315 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 316 index f93835f..eb2b2cd 100644
 317 --- a/arch/mips/ralink/Kconfig
 318 +++ b/arch/mips/ralink/Kconfig
 319 @@ -21,6 +21,7 @@ choice
 320         config SOC_RT288X
 321                 bool "RT288x"
 322                 select MIPS_L1_CACHE_SHIFT_4
 323 +               select HW_HAS_PCI
 324
 325         config SOC_RT305X
 326                 bool "RT305x"
 327 --
 328 1.7.10.4
 329