ralink: add 3.14 support
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.14 / 0036-NET-add-mt7621-ethernet-driver.patch
1 From 810c2afe0c7e1be9352ad512b337110b100bfe3a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 08:51:14 +0000
4 Subject: [PATCH 36/57] NET: add mt7621 ethernet driver
5
6 ---
7 arch/mips/include/asm/rt2880/board-custom.h | 153 +++
8 arch/mips/include/asm/rt2880/eureka_ep430.h | 204 ++++
9 arch/mips/include/asm/rt2880/generic.h | 42 +
10 arch/mips/include/asm/rt2880/lm.h | 32 +
11 arch/mips/include/asm/rt2880/prom.h | 50 +
12 arch/mips/include/asm/rt2880/rt_mmap.h | 796 ++++++++++++++++
13 arch/mips/include/asm/rt2880/serial_rt2880.h | 443 +++++++++
14 arch/mips/include/asm/rt2880/sizes.h | 52 +
15 arch/mips/include/asm/rt2880/surfboard.h | 70 ++
16 arch/mips/include/asm/rt2880/surfboardint.h | 190 ++++
17 arch/mips/include/asm/rt2880/war.h | 25 +
18 drivers/net/ethernet/Kconfig | 1 +
19 drivers/net/ethernet/Makefile | 1 +
20 drivers/net/ethernet/raeth/Kconfig | 344 +++++++
21 drivers/net/ethernet/raeth/Makefile | 7 +
22 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
23 drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
24 drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
25 drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
26 drivers/net/ethernet/raeth/ra_mac.c | 98 ++
27 drivers/net/ethernet/raeth/ra_mac.h | 35 +
28 drivers/net/ethernet/raeth/raether.c | 693 ++++++++++++++
29 drivers/net/ethernet/raeth/raether.h | 92 ++
30 drivers/net/ethernet/raeth/raether_pdma.c | 212 +++++
31 drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
32 25 files changed, 5915 insertions(+)
33 create mode 100644 arch/mips/include/asm/rt2880/board-custom.h
34 create mode 100644 arch/mips/include/asm/rt2880/eureka_ep430.h
35 create mode 100644 arch/mips/include/asm/rt2880/generic.h
36 create mode 100644 arch/mips/include/asm/rt2880/lm.h
37 create mode 100644 arch/mips/include/asm/rt2880/prom.h
38 create mode 100644 arch/mips/include/asm/rt2880/rt_mmap.h
39 create mode 100644 arch/mips/include/asm/rt2880/serial_rt2880.h
40 create mode 100644 arch/mips/include/asm/rt2880/sizes.h
41 create mode 100644 arch/mips/include/asm/rt2880/surfboard.h
42 create mode 100644 arch/mips/include/asm/rt2880/surfboardint.h
43 create mode 100644 arch/mips/include/asm/rt2880/war.h
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
47 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
48 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
49 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
50 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
51 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
52 create mode 100644 drivers/net/ethernet/raeth/raether.c
53 create mode 100644 drivers/net/ethernet/raeth/raether.h
54 create mode 100644 drivers/net/ethernet/raeth/raether_pdma.c
55 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
56
57 diff --git a/arch/mips/include/asm/rt2880/board-custom.h b/arch/mips/include/asm/rt2880/board-custom.h
58 new file mode 100644
59 index 0000000..120e846
60 --- /dev/null
61 +++ b/arch/mips/include/asm/rt2880/board-custom.h
62 @@ -0,0 +1,153 @@
63 +/* Copyright Statement:
64 + *
65 + * This software/firmware and related documentation ("MediaTek Software") are
66 + * protected under relevant copyright laws. The information contained herein
67 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
68 + * Without the prior written permission of MediaTek inc. and/or its licensors,
69 + * any reproduction, modification, use or disclosure of MediaTek Software,
70 + * and information contained herein, in whole or in part, shall be strictly prohibited.
71 + */
72 +/* MediaTek Inc. (C) 2010. All rights reserved.
73 + *
74 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
75 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
76 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
77 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
78 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
79 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
80 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
81 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
82 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
83 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
84 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
85 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
86 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
87 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
88 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
89 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
90 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
91 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
92 + *
93 + * The following software/firmware and/or related documentation ("MediaTek Software")
94 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
95 + * applicable license agreements with MediaTek Inc.
96 + */
97 +
98 +#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
99 +#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
100 +
101 +#include <linux/autoconf.h>
102 +
103 +/*=======================================================================*/
104 +/* MT6575 SD */
105 +/*=======================================================================*/
106 +#ifdef MTK_EMMC_SUPPORT
107 +#define CFG_DEV_MSDC0
108 +#endif
109 +#define CFG_DEV_MSDC1
110 +#define CFG_DEV_MSDC2
111 +#define CFG_DEV_MSDC3
112 +#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
113 +/*
114 +SDIO slot index number used by connectivity combo chip:
115 +0: invalid (used by memory card)
116 +1: MSDC1
117 +2: MSDC2
118 +*/
119 +#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
120 +#else
121 +#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
122 +#endif
123 +
124 +#if 0 /* FIXME. */
125 +/*=======================================================================*/
126 +/* MT6575 UART */
127 +/*=======================================================================*/
128 +#define CFG_DEV_UART1
129 +#define CFG_DEV_UART2
130 +#define CFG_DEV_UART3
131 +#define CFG_DEV_UART4
132 +
133 +#define CFG_UART_PORTS (4)
134 +
135 +/*=======================================================================*/
136 +/* MT6575 I2C */
137 +/*=======================================================================*/
138 +#define CFG_DEV_I2C
139 +//#define CFG_I2C_HIGH_SPEED_MODE
140 +//#define CFG_I2C_DMA_MODE
141 +
142 +/*=======================================================================*/
143 +/* MT6575 ADB */
144 +/*=======================================================================*/
145 +#define ADB_SERIAL "E1K"
146 +
147 +#endif
148 +
149 +/*=======================================================================*/
150 +/* MT6575 NAND FLASH */
151 +/*=======================================================================*/
152 +#if 0
153 +#define RAMDOM_READ 1<<0
154 +#define CACHE_READ 1<<1
155 +/*******************************************************************************
156 + * NFI & ECC Configuration
157 + *******************************************************************************/
158 +typedef struct
159 +{
160 + u16 id; //deviceid+menuid
161 + u8 addr_cycle;
162 + u8 iowidth;
163 + u16 totalsize;
164 + u16 blocksize;
165 + u16 pagesize;
166 + u32 timmingsetting;
167 + char devciename[14];
168 + u32 advancedmode; //
169 +}flashdev_info,*pflashdev_info;
170 +
171 +static const flashdev_info g_FlashTable[]={
172 + //micro
173 + {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
174 + {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
175 + {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
176 + {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
177 + {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
178 + //samsung
179 + {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
180 + {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
181 + {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
182 + {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
183 + {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
184 + //hynix
185 + {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
186 + {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
187 + {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
188 + {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
189 + //toshiba
190 + {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
191 + {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
192 + {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
193 + {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
194 + //st-micro
195 + {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
196 +
197 + // elpida
198 + {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
199 + {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
200 +};
201 +#endif
202 +
203 +
204 +#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
205 +
206 +//uboot only support 1 cs
207 +#define NFI_CS_NUM (2)
208 +#define NFI_DEFAULT_CS (0)
209 +
210 +#define USE_AHB_MODE (1)
211 +
212 +#define PLATFORM_EVB (1)
213 +
214 +#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
215 +
216 diff --git a/arch/mips/include/asm/rt2880/eureka_ep430.h b/arch/mips/include/asm/rt2880/eureka_ep430.h
217 new file mode 100644
218 index 0000000..e42a992
219 --- /dev/null
220 +++ b/arch/mips/include/asm/rt2880/eureka_ep430.h
221 @@ -0,0 +1,204 @@
222 +/**************************************************************************
223 + *
224 + * This program is free software; you can redistribute it and/or modify it
225 + * under the terms of the GNU General Public License as published by the
226 + * Free Software Foundation; either version 2 of the License, or (at your
227 + * option) any later version.
228 + *
229 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
230 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
231 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
232 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
233 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
234 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
235 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
236 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
237 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
238 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
239 + *
240 + * You should have received a copy of the GNU General Public License along
241 + * with this program; if not, write to the Free Software Foundation, Inc.,
242 + * 675 Mass Ave, Cambridge, MA 02139, USA.
243 + *
244 + *
245 + **************************************************************************
246 + */
247 +
248 +#ifndef _EUREKA_EP430_H
249 +#define _EUREKA_EP430_H
250 +
251 +
252 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
253 +#include <asm/byteorder.h> /* for cpu_to_le32() */
254 +#include <asm/mach-ralink/rt_mmap.h>
255 +
256 +
257 +/*
258 + * Because of an error/peculiarity in the Galileo chip, we need to swap the
259 + * bytes when running bigendian.
260 + */
261 +
262 +#define MV_WRITE(ofs, data) \
263 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
264 +#define MV_READ(ofs, data) \
265 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
266 +#define MV_READ_DATA(ofs) \
267 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
268 +
269 +#define MV_WRITE_16(ofs, data) \
270 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
271 +#define MV_READ_16(ofs, data) \
272 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
273 +
274 +#define MV_WRITE_8(ofs, data) \
275 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
276 +#define MV_READ_8(ofs, data) \
277 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
278 +
279 +#define MV_SET_REG_BITS(ofs,bits) \
280 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
281 +#define MV_RESET_REG_BITS(ofs,bits) \
282 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
283 +
284 +#define RALINK_PCI_CONFIG_ADDR 0x20
285 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
286 +
287 +#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
288 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
289 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
290 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
291 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
292 +#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
293 +#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
294 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
295 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
296 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
297 +#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
298 +#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
299 +#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
300 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
301 +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
302 +
303 +#elif defined(CONFIG_RALINK_RT3883)
304 +
305 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
306 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
307 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
308 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
309 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
310 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
311 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
312 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
313 +
314 +/*
315 +PCI0 --> PCI
316 +PCI1 --> PCIe
317 +*/
318 +#define RT3883_PCI_OFFSET 0x1000
319 +#define RT3883_PCIE_OFFSET 0x2000
320 +
321 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
322 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
323 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
324 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
325 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
326 +
327 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
328 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
329 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
330 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
331 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
332 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
333 +
334 +#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
335 +
336 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
337 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
338 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
339 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
340 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
341 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
342 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
343 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
344 +
345 +/*
346 +PCI0 --> PCIe 0
347 +PCI1 --> PCIe 1
348 +*/
349 +#define RT6855_PCIE0_OFFSET 0x2000
350 +#define RT6855_PCIE1_OFFSET 0x3000
351 +
352 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
353 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
354 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
355 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
356 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
357 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
358 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
359 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
360 +
361 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
362 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
363 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
364 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
365 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
366 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
367 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
368 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
369 +
370 +#elif defined (CONFIG_RALINK_MT7621)
371 +
372 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
373 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
374 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
375 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
376 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
377 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
378 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
379 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
380 +
381 +/*
382 +PCI0 --> PCIe 0
383 +PCI1 --> PCIe 1
384 +PCI2 --> PCIe 2
385 +*/
386 +#define RT6855_PCIE0_OFFSET 0x2000
387 +#define RT6855_PCIE1_OFFSET 0x3000
388 +#define RT6855_PCIE2_OFFSET 0x4000
389 +
390 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
391 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
392 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
393 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
394 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
395 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
396 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
397 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
398 +
399 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
400 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
401 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
402 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
403 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
404 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
405 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
406 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
407 +
408 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
409 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
410 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
411 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
412 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
413 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
414 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
415 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
416 +
417 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
418 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
419 +
420 +#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
421 +#else
422 +#error "undefined in PCI"
423 +#endif
424 +
425 +#endif
426 diff --git a/arch/mips/include/asm/rt2880/generic.h b/arch/mips/include/asm/rt2880/generic.h
427 new file mode 100644
428 index 0000000..4128f91
429 --- /dev/null
430 +++ b/arch/mips/include/asm/rt2880/generic.h
431 @@ -0,0 +1,42 @@
432 +/*
433 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
434 + *
435 + * This program is free software; you can distribute it and/or modify it
436 + * under the terms of the GNU General Public License (Version 2) as
437 + * published by the Free Software Foundation.
438 + *
439 + * This program is distributed in the hope it will be useful, but WITHOUT
440 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
441 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
442 + * for more details.
443 + *
444 + * You should have received a copy of the GNU General Public License along
445 + * with this program; if not, write to the Free Software Foundation, Inc.,
446 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
447 + *
448 + * Defines of the Palmchip boards specific address-MAP, registers, etc.
449 + */
450 +#ifndef __ASM_SURFBOARD_GENERIC_H
451 +#define __ASM_SURFBOARD_GENERIC_H
452 +
453 +#include <asm/addrspace.h>
454 +#include <asm/byteorder.h>
455 +#include <asm/mach-ralink/rt_mmap.h>
456 +
457 +/*
458 + * Reset register.
459 + */
460 +#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
461 +#define GORESET (0x1)
462 +
463 +/*
464 + * Power-off register
465 + */
466 +#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
467 +#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
468 +#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
469 +#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
470 +#define POWEROFF (0x0) /* drive low */
471 +
472 +
473 +#endif /* __ASM_SURFBOARD_GENERIC_H */
474 diff --git a/arch/mips/include/asm/rt2880/lm.h b/arch/mips/include/asm/rt2880/lm.h
475 new file mode 100644
476 index 0000000..25e2930
477 --- /dev/null
478 +++ b/arch/mips/include/asm/rt2880/lm.h
479 @@ -0,0 +1,32 @@
480 +#include <linux/version.h>
481 +
482 +struct lm_device {
483 + struct device dev;
484 + struct resource resource;
485 + unsigned int irq;
486 + unsigned int id;
487 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
488 + void *lm_drvdata;
489 +#endif
490 +};
491 +
492 +struct lm_driver {
493 + struct device_driver drv;
494 + int (*probe)(struct lm_device *);
495 + void (*remove)(struct lm_device *);
496 + int (*suspend)(struct lm_device *, u32);
497 + int (*resume)(struct lm_device *);
498 +};
499 +
500 +int lm_driver_register(struct lm_driver *drv);
501 +void lm_driver_unregister(struct lm_driver *drv);
502 +
503 +int lm_device_register(struct lm_device *dev);
504 +
505 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
506 +# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
507 +# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
508 +#else
509 +# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
510 +# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
511 +#endif
512 diff --git a/arch/mips/include/asm/rt2880/prom.h b/arch/mips/include/asm/rt2880/prom.h
513 new file mode 100644
514 index 0000000..51be9b0
515 --- /dev/null
516 +++ b/arch/mips/include/asm/rt2880/prom.h
517 @@ -0,0 +1,50 @@
518 +/*
519 + * Carsten Langgaard, carstenl@mips.com
520 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
521 + *
522 + * ########################################################################
523 + *
524 + * This program is free software; you can distribute it and/or modify it
525 + * under the terms of the GNU General Public License (Version 2) as
526 + * published by the Free Software Foundation.
527 + *
528 + * This program is distributed in the hope it will be useful, but WITHOUT
529 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
530 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
531 + * for more details.
532 + *
533 + * You should have received a copy of the GNU General Public License along
534 + * with this program; if not, write to the Free Software Foundation, Inc.,
535 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
536 + *
537 + * ########################################################################
538 + *
539 + * MIPS boards bootprom interface for the Linux kernel.
540 + *
541 + */
542 +
543 +#ifndef _MIPS_PROM_H
544 +#define _MIPS_PROM_H
545 +
546 +extern char *prom_getcmdline(void);
547 +extern char *prom_getenv(char *name);
548 +extern void setup_prom_printf(int tty_no);
549 +extern void prom_setup_printf(int tty_no);
550 +extern void prom_printf(char *fmt, ...);
551 +extern void prom_init_cmdline(void);
552 +extern void prom_meminit(void);
553 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
554 +extern void prom_free_prom_memory (void);
555 +extern void mips_display_message(const char *str);
556 +extern void mips_display_word(unsigned int num);
557 +extern int get_ethernet_addr(char *ethernet_addr);
558 +
559 +/* Memory descriptor management. */
560 +#define PROM_MAX_PMEMBLOCKS 32
561 +struct prom_pmemblock {
562 + unsigned long base; /* Within KSEG0. */
563 + unsigned int size; /* In bytes. */
564 + unsigned int type; /* free or prom memory */
565 +};
566 +
567 +#endif /* !(_MIPS_PROM_H) */
568 diff --git a/arch/mips/include/asm/rt2880/rt_mmap.h b/arch/mips/include/asm/rt2880/rt_mmap.h
569 new file mode 100644
570 index 0000000..0e8f051
571 --- /dev/null
572 +++ b/arch/mips/include/asm/rt2880/rt_mmap.h
573 @@ -0,0 +1,796 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * register definition for Ralink RT-series SoC
578 + *
579 + * Copyright 2007 Ralink Inc.
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + */
604 +
605 +#ifndef __RALINK_MMAP__
606 +#define __RALINK_MMAP__
607 +
608 +#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
609 +
610 +#define RALINK_SYSCTL_BASE 0xA0300000
611 +#define RALINK_TIMER_BASE 0xA0300100
612 +#define RALINK_INTCL_BASE 0xA0300200
613 +#define RALINK_MEMCTRL_BASE 0xA0300300
614 +#define RALINK_UART_BASE 0xA0300500
615 +#define RALINK_PIO_BASE 0xA0300600
616 +#define RALINK_I2C_BASE 0xA0300900
617 +#define RALINK_SPI_BASE 0xA0300B00
618 +#define RALINK_UART_LITE_BASE 0xA0300C00
619 +#define RALINK_FRAME_ENGINE_BASE 0xA0310000
620 +#define RALINK_EMBEDD_ROM_BASE 0xA0400000
621 +#define RALINK_PCI_BASE 0xA0500000
622 +#define RALINK_11N_MAC_BASE 0xA0600000
623 +
624 +//Interrupt Controller
625 +#define RALINK_INTCTL_TIMER0 (1<<0)
626 +#define RALINK_INTCTL_WDTIMER (1<<1)
627 +#define RALINK_INTCTL_UART (1<<2)
628 +#define RALINK_INTCTL_PIO (1<<3)
629 +#define RALINK_INTCTL_PCM (1<<4)
630 +#define RALINK_INTCTL_UARTLITE (1<<8)
631 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
632 +
633 +//Reset Control Register
634 +#define RALINK_TIMER_RST (1<<1)
635 +#define RALINK_INTC_RST (1<<2)
636 +#define RALINK_MC_RST (1<<3)
637 +#define RALINK_CPU_RST (1<<4)
638 +#define RALINK_UART_RST (1<<5)
639 +#define RALINK_PIO_RST (1<<6)
640 +#define RALINK_I2C_RST (1<<9)
641 +#define RALINK_SPI_RST (1<<11)
642 +#define RALINK_UART2_RST (1<<12)
643 +#define RALINK_PCI_RST (1<<16)
644 +#define RALINK_2860_RST (1<<17)
645 +#define RALINK_FE_RST (1<<18)
646 +#define RALINK_PCM_RST (1<<19)
647 +
648 +
649 +#elif defined (CONFIG_RALINK_RT2880_MP)
650 +
651 +#define RALINK_SYSCTL_BASE 0xA0300000
652 +#define RALINK_TIMER_BASE 0xA0300100
653 +#define RALINK_INTCL_BASE 0xA0300200
654 +#define RALINK_MEMCTRL_BASE 0xA0300300
655 +#define RALINK_UART_BASE 0xA0300500
656 +#define RALINK_PIO_BASE 0xA0300600
657 +#define RALINK_I2C_BASE 0xA0300900
658 +#define RALINK_SPI_BASE 0xA0300B00
659 +#define RALINK_UART_LITE_BASE 0x00300C00
660 +#define RALINK_FRAME_ENGINE_BASE 0xA0400000
661 +#define RALINK_EMBEDD_ROM_BASE 0xA0410000
662 +#define RALINK_PCI_BASE 0xA0440000
663 +#define RALINK_11N_MAC_BASE 0xA0480000
664 +
665 +//Interrupt Controller
666 +#define RALINK_INTCTL_TIMER0 (1<<0)
667 +#define RALINK_INTCTL_WDTIMER (1<<1)
668 +#define RALINK_INTCTL_UART (1<<2)
669 +#define RALINK_INTCTL_PIO (1<<3)
670 +#define RALINK_INTCTL_PCM (1<<4)
671 +#define RALINK_INTCTL_UARTLITE (1<<8)
672 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
673 +
674 +//Reset Control Register
675 +#define RALINK_TIMER_RST (1<<1)
676 +#define RALINK_INTC_RST (1<<2)
677 +#define RALINK_MC_RST (1<<3)
678 +#define RALINK_CPU_RST (1<<4)
679 +#define RALINK_UART_RST (1<<5)
680 +#define RALINK_PIO_RST (1<<6)
681 +#define RALINK_I2C_RST (1<<9)
682 +#define RALINK_SPI_RST (1<<11)
683 +#define RALINK_UART2_RST (1<<12)
684 +#define RALINK_PCI_RST (1<<16)
685 +#define RALINK_2860_RST (1<<17)
686 +#define RALINK_FE_RST (1<<18)
687 +#define RALINK_PCM_RST (1<<19)
688 +
689 +#elif defined (CONFIG_RALINK_RT3052)
690 +
691 +#define RALINK_SYSCTL_BASE 0xB0000000
692 +#define RALINK_TIMER_BASE 0xB0000100
693 +#define RALINK_INTCL_BASE 0xB0000200
694 +#define RALINK_MEMCTRL_BASE 0xB0000300
695 +#define RALINK_PCM_BASE 0xB0000400
696 +#define RALINK_UART_BASE 0x10000500
697 +#define RALINK_PIO_BASE 0xB0000600
698 +#define RALINK_GDMA_BASE 0xB0000700
699 +#define RALINK_NAND_CTRL_BASE 0xB0000800
700 +#define RALINK_I2C_BASE 0xB0000900
701 +#define RALINK_I2S_BASE 0xB0000A00
702 +#define RALINK_SPI_BASE 0xB0000B00
703 +#define RALINK_UART_LITE_BASE 0x10000C00
704 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
705 +#define RALINK_ETH_SW_BASE 0xB0110000
706 +#define RALINK_11N_MAC_BASE 0xB0180000
707 +#define RALINK_USB_OTG_BASE 0x101C0000
708 +
709 +//Interrupt Controller
710 +#define RALINK_INTCTL_SYSCTL (1<<0)
711 +#define RALINK_INTCTL_TIMER0 (1<<1)
712 +#define RALINK_INTCTL_WDTIMER (1<<2)
713 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
714 +#define RALINK_INTCTL_PCM (1<<4)
715 +#define RALINK_INTCTL_UART (1<<5)
716 +#define RALINK_INTCTL_PIO (1<<6)
717 +#define RALINK_INTCTL_DMA (1<<7)
718 +#define RALINK_INTCTL_NAND (1<<8)
719 +#define RALINK_INTCTL_PC (1<<9)
720 +#define RALINK_INTCTL_I2S (1<<10)
721 +#define RALINK_INTCTL_UARTLITE (1<<12)
722 +#define RALINK_INTCTL_ESW (1<<17)
723 +#define RALINK_INTCTL_OTG (1<<18)
724 +#define RALINK_INTCTL_OTG_IRQN 18
725 +#define RALINK_INTCTL_GLOBAL (1<<31)
726 +
727 +//Reset Control Register
728 +#define RALINK_SYS_RST (1<<0)
729 +#define RALINK_CPU_RST (1<<1)
730 +#define RALINK_TIMER_RST (1<<8)
731 +#define RALINK_INTC_RST (1<<9)
732 +#define RALINK_MC_RST (1<<10)
733 +#define RALINK_PCM_RST (1<<11)
734 +#define RALINK_UART_RST (1<<12)
735 +#define RALINK_PIO_RST (1<<13)
736 +#define RALINK_DMA_RST (1<<14)
737 +#define RALINK_I2C_RST (1<<16)
738 +#define RALINK_I2S_RST (1<<17)
739 +#define RALINK_SPI_RST (1<<18)
740 +#define RALINK_UARTL_RST (1<<19)
741 +#define RALINK_RT2872_RST (1<<20)
742 +#define RALINK_FE_RST (1<<21)
743 +#define RALINK_OTG_RST (1<<22)
744 +#define RALINK_SW_RST (1<<23)
745 +#define RALINK_EPHY_RST (1<<24)
746 +
747 +#elif defined (CONFIG_RALINK_RT3352)
748 +
749 +#define RALINK_SYSCTL_BASE 0xB0000000
750 +#define RALINK_TIMER_BASE 0xB0000100
751 +#define RALINK_INTCL_BASE 0xB0000200
752 +#define RALINK_MEMCTRL_BASE 0xB0000300
753 +#define RALINK_UART_BASE 0x10000500
754 +#define RALINK_PIO_BASE 0xB0000600
755 +#define RALINK_I2C_BASE 0xB0000900
756 +#define RALINK_I2S_BASE 0xB0000A00
757 +#define RALINK_SPI_BASE 0xB0000B00
758 +#define RALINK_NAND_CTRL_BASE 0xB0000800
759 +#define RALINK_UART_LITE_BASE 0x10000C00
760 +#define RALINK_PCM_BASE 0xB0002000
761 +#define RALINK_GDMA_BASE 0xB0002800
762 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
763 +#define RALINK_ETH_SW_BASE 0xB0110000
764 +#define RALINK_USB_DEV_BASE 0x10120000
765 +#define RALINK_11N_MAC_BASE 0xB0180000
766 +#define RALINK_USB_HOST_BASE 0x101C0000
767 +
768 +#define RALINK_MCNT_CFG 0xB0000D00
769 +#define RALINK_COMPARE 0xB0000D04
770 +#define RALINK_COUNT 0xB0000D08
771 +
772 +//Interrupt Controller
773 +#define RALINK_INTCTL_SYSCTL (1<<0)
774 +#define RALINK_INTCTL_TIMER0 (1<<1)
775 +#define RALINK_INTCTL_WDTIMER (1<<2)
776 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
777 +#define RALINK_INTCTL_PCM (1<<4)
778 +#define RALINK_INTCTL_UART (1<<5)
779 +#define RALINK_INTCTL_PIO (1<<6)
780 +#define RALINK_INTCTL_DMA (1<<7)
781 +#define RALINK_INTCTL_PC (1<<9)
782 +#define RALINK_INTCTL_I2S (1<<10)
783 +#define RALINK_INTCTL_UARTLITE (1<<12)
784 +#define RALINK_INTCTL_ESW (1<<17)
785 +#define RALINK_INTCTL_OTG (1<<18)
786 +#define RALINK_INTCTL_GLOBAL (1<<31)
787 +
788 +//Reset Control Register
789 +#define RALINK_SYS_RST (1<<0)
790 +#define RALINK_TIMER_RST (1<<8)
791 +#define RALINK_INTC_RST (1<<9)
792 +#define RALINK_MC_RST (1<<10)
793 +#define RALINK_PCM_RST (1<<11)
794 +#define RALINK_UART_RST (1<<12)
795 +#define RALINK_PIO_RST (1<<13)
796 +#define RALINK_DMA_RST (1<<14)
797 +#define RALINK_I2C_RST (1<<16)
798 +#define RALINK_I2S_RST (1<<17)
799 +#define RALINK_SPI_RST (1<<18)
800 +#define RALINK_UARTL_RST (1<<19)
801 +#define RALINK_WLAN_RST (1<<20)
802 +#define RALINK_FE_RST (1<<21)
803 +#define RALINK_UHST_RST (1<<22)
804 +#define RALINK_ESW_RST (1<<23)
805 +#define RALINK_EPHY_RST (1<<24)
806 +#define RALINK_UDEV_RST (1<<25)
807 +
808 +
809 +//Clock Conf Register
810 +#define RALINK_UPHY1_CLK_EN (1<<20)
811 +#define RALINK_UPHY0_CLK_EN (1<<18)
812 +#define RALINK_GE1_CLK_EN (1<<16)
813 +
814 +
815 +#elif defined (CONFIG_RALINK_RT5350)
816 +
817 +#define RALINK_SYSCTL_BASE 0xB0000000
818 +#define RALINK_TIMER_BASE 0xB0000100
819 +#define RALINK_INTCL_BASE 0xB0000200
820 +#define RALINK_MEMCTRL_BASE 0xB0000300
821 +#define RALINK_UART_BASE 0x10000500
822 +#define RALINK_PIO_BASE 0xB0000600
823 +#define RALINK_I2C_BASE 0xB0000900
824 +#define RALINK_I2S_BASE 0xB0000A00
825 +#define RALINK_SPI_BASE 0xB0000B00
826 +#define RALINK_UART_LITE_BASE 0x10000C00
827 +#define RALINK_PCM_BASE 0xB0002000
828 +#define RALINK_GDMA_BASE 0xB0002800
829 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
830 +#define RALINK_ETH_SW_BASE 0xB0110000
831 +#define RALINK_USB_DEV_BASE 0x10120000
832 +#define RALINK_11N_MAC_BASE 0xB0180000
833 +#define RALINK_USB_HOST_BASE 0x101C0000
834 +
835 +#define RALINK_MCNT_CFG 0xB0000D00
836 +#define RALINK_COMPARE 0xB0000D04
837 +#define RALINK_COUNT 0xB0000D08
838 +
839 +//Interrupt Controller
840 +#define RALINK_INTCTL_SYSCTL (1<<0)
841 +#define RALINK_INTCTL_TIMER0 (1<<1)
842 +#define RALINK_INTCTL_WDTIMER (1<<2)
843 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
844 +#define RALINK_INTCTL_PCM (1<<4)
845 +#define RALINK_INTCTL_UART (1<<5)
846 +#define RALINK_INTCTL_PIO (1<<6)
847 +#define RALINK_INTCTL_DMA (1<<7)
848 +#define RALINK_INTCTL_PC (1<<9)
849 +#define RALINK_INTCTL_I2S (1<<10)
850 +#define RALINK_INTCTL_UARTLITE (1<<12)
851 +#define RALINK_INTCTL_ESW (1<<17)
852 +#define RALINK_INTCTL_USB_HOST (1<<18)
853 +#define RALINK_INTCTL_USB_DEV (1<<19)
854 +#define RALINK_INTCTL_GLOBAL (1<<31)
855 +
856 +//Reset Control Register
857 +#define RALINK_SYS_RST (1<<0)
858 +#define RALINK_TIMER_RST (1<<8)
859 +#define RALINK_INTC_RST (1<<9)
860 +#define RALINK_MC_RST (1<<10)
861 +#define RALINK_PCM_RST (1<<11)
862 +#define RALINK_UART_RST (1<<12)
863 +#define RALINK_PIO_RST (1<<13)
864 +#define RALINK_DMA_RST (1<<14)
865 +#define RALINK_I2C_RST (1<<16)
866 +#define RALINK_I2S_RST (1<<17)
867 +#define RALINK_SPI_RST (1<<18)
868 +#define RALINK_UARTL_RST (1<<19)
869 +#define RALINK_WLAN_RST (1<<20)
870 +#define RALINK_FE_RST (1<<21)
871 +#define RALINK_UHST_RST (1<<22)
872 +#define RALINK_ESW_RST (1<<23)
873 +#define RALINK_EPHY_RST (1<<24)
874 +#define RALINK_UDEV_RST (1<<25)
875 +#define RALINK_MIPSC_RST (1<<28)
876 +
877 +//Clock Conf Register
878 +#define RALINK_UPHY0_CLK_EN (1<<18)
879 +#define RALINK_GE1_CLK_EN (1<<16)
880 +
881 +#elif defined (CONFIG_RALINK_RT2883)
882 +
883 +#define RALINK_SYSCTL_BASE 0xB0000000
884 +#define RALINK_TIMER_BASE 0xB0000100
885 +#define RALINK_INTCL_BASE 0xB0000200
886 +#define RALINK_MEMCTRL_BASE 0xB0000300
887 +#define RALINK_PCM_BASE 0xB0000400
888 +#define RALINK_UART_BASE 0x10000500
889 +#define RALINK_PIO_BASE 0xB0000600
890 +#define RALINK_GDMA_BASE 0xB0000700
891 +#define RALINK_NAND_CTRL_BASE 0xB0000800
892 +#define RALINK_I2C_BASE 0xB0000900
893 +#define RALINK_I2S_BASE 0xB0000A00
894 +#define RALINK_SPI_BASE 0xB0000B00
895 +#define RALINK_UART_LITE_BASE 0x10000C00
896 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
897 +#define RALINK_PCI_BASE 0xB0140000
898 +#define RALINK_11N_MAC_BASE 0xB0180000
899 +#define RALINK_USB_OTG_BASE 0x101C0000
900 +
901 +//Interrupt Controller
902 +#define RALINK_INTCTL_SYSCTL (1<<0)
903 +#define RALINK_INTCTL_TIMER0 (1<<1)
904 +#define RALINK_INTCTL_WDTIMER (1<<2)
905 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
906 +#define RALINK_INTCTL_PCM (1<<4)
907 +#define RALINK_INTCTL_UART (1<<5)
908 +#define RALINK_INTCTL_PIO (1<<6)
909 +#define RALINK_INTCTL_DMA (1<<7)
910 +#define RALINK_INTCTL_NAND (1<<8)
911 +#define RALINK_INTCTL_PC (1<<9)
912 +#define RALINK_INTCTL_I2S (1<<10)
913 +#define RALINK_INTCTL_UARTLITE (1<<12)
914 +#define RALINK_INTCTL_OTG (1<<18)
915 +#define RALINK_INTCTL_OTG_IRQN 18
916 +#define RALINK_INTCTL_GLOBAL (1<<31)
917 +
918 +//Reset Control Register
919 +#define RALINK_SYS_RST (1<<0)
920 +#define RALINK_CPU_RST (1<<1)
921 +#define RALINK_TIMER_RST (1<<8)
922 +#define RALINK_INTC_RST (1<<9)
923 +#define RALINK_MC_RST (1<<10)
924 +#define RALINK_PCM_RST (1<<11)
925 +#define RALINK_UART_RST (1<<12)
926 +#define RALINK_PIO_RST (1<<13)
927 +#define RALINK_DMA_RST (1<<14)
928 +#define RALINK_I2C_RST (1<<16)
929 +#define RALINK_I2S_RST (1<<17)
930 +#define RALINK_SPI_RST (1<<18)
931 +#define RALINK_UARTL_RST (1<<19)
932 +#define RALINK_WLAN_RST (1<<20)
933 +#define RALINK_FE_RST (1<<21)
934 +#define RALINK_OTG_RST (1<<22)
935 +#define RALINK_PCIE_RST (1<<23)
936 +
937 +#elif defined (CONFIG_RALINK_RT3883)
938 +
939 +#define RALINK_SYSCTL_BASE 0xB0000000
940 +#define RALINK_TIMER_BASE 0xB0000100
941 +#define RALINK_INTCL_BASE 0xB0000200
942 +#define RALINK_MEMCTRL_BASE 0xB0000300
943 +#define RALINK_UART_BASE 0x10000500
944 +#define RALINK_PIO_BASE 0xB0000600
945 +#define RALINK_NOR_CTRL_BASE 0xB0000700
946 +#define RALINK_NAND_CTRL_BASE 0xB0000810
947 +#define RALINK_I2C_BASE 0xB0000900
948 +#define RALINK_I2S_BASE 0xB0000A00
949 +#define RALINK_SPI_BASE 0xB0000B00
950 +#define RALINK_UART_LITE_BASE 0x10000C00
951 +#define RALINK_PCM_BASE 0xB0002000
952 +#define RALINK_GDMA_BASE 0xB0002800
953 +#define RALINK_CODEC1_BASE 0xB0003000
954 +#define RALINK_CODEC2_BASE 0xB0003800
955 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
956 +#define RALINK_USB_DEV_BASE 0x10120000
957 +#define RALINK_PCI_BASE 0xB0140000
958 +#define RALINK_11N_MAC_BASE 0xB0180000
959 +#define RALINK_USB_HOST_BASE 0x101C0000
960 +#define RALINK_PCIE_BASE 0xB0200000
961 +
962 +//Interrupt Controller
963 +#define RALINK_INTCTL_SYSCTL (1<<0)
964 +#define RALINK_INTCTL_TIMER0 (1<<1)
965 +#define RALINK_INTCTL_WDTIMER (1<<2)
966 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
967 +#define RALINK_INTCTL_PCM (1<<4)
968 +#define RALINK_INTCTL_UART (1<<5)
969 +#define RALINK_INTCTL_PIO (1<<6)
970 +#define RALINK_INTCTL_DMA (1<<7)
971 +#define RALINK_INTCTL_NAND (1<<8)
972 +#define RALINK_INTCTL_PC (1<<9)
973 +#define RALINK_INTCTL_I2S (1<<10)
974 +#define RALINK_INTCTL_UARTLITE (1<<12)
975 +#define RALINK_INTCTL_UHST (1<<18)
976 +#define RALINK_INTCTL_UDEV (1<<19)
977 +
978 +//Reset Control Register
979 +#define RALINK_SYS_RST (1<<0)
980 +#define RALINK_TIMER_RST (1<<8)
981 +#define RALINK_INTC_RST (1<<9)
982 +#define RALINK_MC_RST (1<<10)
983 +#define RALINK_PCM_RST (1<<11)
984 +#define RALINK_UART_RST (1<<12)
985 +#define RALINK_PIO_RST (1<<13)
986 +#define RALINK_DMA_RST (1<<14)
987 +#define RALINK_NAND_RST (1<<15)
988 +#define RALINK_I2C_RST (1<<16)
989 +#define RALINK_I2S_RST (1<<17)
990 +#define RALINK_SPI_RST (1<<18)
991 +#define RALINK_UARTL_RST (1<<19)
992 +#define RALINK_WLAN_RST (1<<20)
993 +#define RALINK_FE_RST (1<<21)
994 +#define RALINK_UHST_RST (1<<22)
995 +#define RALINK_PCIE_RST (1<<23)
996 +#define RALINK_PCI_RST (1<<24)
997 +#define RALINK_UDEV_RST (1<<25)
998 +#define RALINK_FLASH_RST (1<<26)
999 +
1000 +//Clock Conf Register
1001 +#define RALINK_UPHY1_CLK_EN (1<<20)
1002 +#define RALINK_UPHY0_CLK_EN (1<<18)
1003 +#define RALINK_GE1_CLK_EN (1<<16)
1004 +
1005 +#elif defined (CONFIG_RALINK_RT6855)
1006 +
1007 +#define RALINK_SYSCTL_BASE 0xB0000000
1008 +#define RALINK_TIMER_BASE 0xB0000100
1009 +#define RALINK_INTCL_BASE 0xB0000200
1010 +#define RALINK_MEMCTRL_BASE 0xB0000300
1011 +#define RALINK_UART_BASE 0x10000500
1012 +#define RALINK_PIO_BASE 0xB0000600
1013 +#define RALINK_I2C_BASE 0xB0000900
1014 +#define RALINK_I2S_BASE 0xB0000A00
1015 +#define RALINK_SPI_BASE 0xB0000B00
1016 +#define RALINK_NAND_CTRL_BASE 0xB0000800
1017 +#define RALINK_UART_LITE_BASE 0x10000C00
1018 +#define RALINK_PCM_BASE 0xB0002000
1019 +#define RALINK_GDMA_BASE 0xB0002800
1020 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1021 +#define RALINK_ETH_SW_BASE 0xB0110000
1022 +#define RALINK_PCI_BASE 0xB0140000
1023 +#define RALINK_USB_DEV_BASE 0x10120000
1024 +#define RALINK_11N_MAC_BASE 0xB0180000
1025 +#define RALINK_USB_HOST_BASE 0x101C0000
1026 +
1027 +#define RALINK_MCNT_CFG 0xB0000D00
1028 +#define RALINK_COMPARE 0xB0000D04
1029 +#define RALINK_COUNT 0xB0000D08
1030 +
1031 +//Interrupt Controller
1032 +#define RALINK_INTCTL_SYSCTL (1<<0)
1033 +#define RALINK_INTCTL_TIMER0 (1<<1)
1034 +#define RALINK_INTCTL_WDTIMER (1<<2)
1035 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1036 +#define RALINK_INTCTL_PCM (1<<4)
1037 +#define RALINK_INTCTL_UART (1<<5)
1038 +#define RALINK_INTCTL_PIO (1<<6)
1039 +#define RALINK_INTCTL_DMA (1<<7)
1040 +#define RALINK_INTCTL_PC (1<<9)
1041 +#define RALINK_INTCTL_I2S (1<<10)
1042 +#define RALINK_INTCTL_UARTLITE (1<<12)
1043 +#define RALINK_INTCTL_ESW (1<<17)
1044 +#define RALINK_INTCTL_OTG (1<<18)
1045 +#define RALINK_INTCTL_GLOBAL (1<<31)
1046 +
1047 +//Reset Control Register
1048 +#define RALINK_SYS_RST (1<<0)
1049 +#define RALINK_TIMER_RST (1<<8)
1050 +#define RALINK_INTC_RST (1<<9)
1051 +#define RALINK_MC_RST (1<<10)
1052 +#define RALINK_PCM_RST (1<<11)
1053 +#define RALINK_UART_RST (1<<12)
1054 +#define RALINK_PIO_RST (1<<13)
1055 +#define RALINK_DMA_RST (1<<14)
1056 +#define RALINK_I2C_RST (1<<16)
1057 +#define RALINK_I2S_RST (1<<17)
1058 +#define RALINK_SPI_RST (1<<18)
1059 +#define RALINK_UARTL_RST (1<<19)
1060 +#define RALINK_FE_RST (1<<21)
1061 +#define RALINK_UHST_RST (1<<22)
1062 +#define RALINK_ESW_RST (1<<23)
1063 +#define RALINK_EPHY_RST (1<<24)
1064 +#define RALINK_UDEV_RST (1<<25)
1065 +#define RALINK_PCIE0_RST (1<<26)
1066 +#define RALINK_PCIE1_RST (1<<27)
1067 +
1068 +//Clock Conf Register
1069 +#define RALINK_UPHY0_CLK_EN (1<<25)
1070 +#define RALINK_PCIE0_CLK_EN (1<<26)
1071 +#define RALINK_PCIE1_CLK_EN (1<<27)
1072 +
1073 +
1074 +#elif defined (CONFIG_RALINK_MT7620)
1075 +
1076 +#define RALINK_SYSCTL_BASE 0xB0000000
1077 +#define RALINK_TIMER_BASE 0xB0000100
1078 +#define RALINK_INTCL_BASE 0xB0000200
1079 +#define RALINK_MEMCTRL_BASE 0xB0000300
1080 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1081 +#define RALINK_UART_BASE 0x10000500
1082 +#define RALINK_PIO_BASE 0xB0000600
1083 +#define RALINK_NAND_CTRL_BASE 0xB0000810
1084 +#define RALINK_I2C_BASE 0xB0000900
1085 +#define RALINK_I2S_BASE 0xB0000A00
1086 +#define RALINK_SPI_BASE 0xB0000B00
1087 +#define RALINK_UART_LITE_BASE 0x10000C00
1088 +#define RALINK_MIPS_CNT_BASE 0x10000D00
1089 +#define RALINK_PCM_BASE 0xB0002000
1090 +#define RALINK_GDMA_BASE 0xB0002800
1091 +#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
1092 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1093 +#define RALINK_PPE_BASE 0xB0100C00
1094 +#define RALINK_ETH_SW_BASE 0xB0110000
1095 +#define RALINK_USB_DEV_BASE 0x10120000
1096 +#define RALINK_MSDC_BASE 0xB0130000
1097 +#define RALINK_PCI_BASE 0xB0140000
1098 +#define RALINK_11N_MAC_BASE 0xB0180000
1099 +#define RALINK_USB_HOST_BASE 0x101C0000
1100 +
1101 +#define RALINK_MCNT_CFG 0xB0000D00
1102 +#define RALINK_COMPARE 0xB0000D04
1103 +#define RALINK_COUNT 0xB0000D08
1104 +
1105 +//Interrupt Controller
1106 +#define RALINK_INTCTL_SYSCTL (1<<0)
1107 +#define RALINK_INTCTL_TIMER0 (1<<1)
1108 +#define RALINK_INTCTL_WDTIMER (1<<2)
1109 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1110 +#define RALINK_INTCTL_PCM (1<<4)
1111 +#define RALINK_INTCTL_UART (1<<5)
1112 +#define RALINK_INTCTL_PIO (1<<6)
1113 +#define RALINK_INTCTL_DMA (1<<7)
1114 +#define RALINK_INTCTL_PC (1<<9)
1115 +#define RALINK_INTCTL_I2S (1<<10)
1116 +#define RALINK_INTCTL_SPI (1<<11)
1117 +#define RALINK_INTCTL_UARTLITE (1<<12)
1118 +#define RALINK_INTCTL_CRYPTO (1<<13)
1119 +#define RALINK_INTCTL_ESW (1<<17)
1120 +#define RALINK_INTCTL_UHST (1<<18)
1121 +#define RALINK_INTCTL_UDEV (1<<19)
1122 +#define RALINK_INTCTL_GLOBAL (1<<31)
1123 +
1124 +//Reset Control Register
1125 +#define RALINK_SYS_RST (1<<0)
1126 +#define RALINK_TIMER_RST (1<<8)
1127 +#define RALINK_INTC_RST (1<<9)
1128 +#define RALINK_MC_RST (1<<10)
1129 +#define RALINK_PCM_RST (1<<11)
1130 +#define RALINK_UART_RST (1<<12)
1131 +#define RALINK_PIO_RST (1<<13)
1132 +#define RALINK_DMA_RST (1<<14)
1133 +#define RALINK_I2C_RST (1<<16)
1134 +#define RALINK_I2S_RST (1<<17)
1135 +#define RALINK_SPI_RST (1<<18)
1136 +#define RALINK_UARTL_RST (1<<19)
1137 +#define RALINK_FE_RST (1<<21)
1138 +#define RALINK_UHST_RST (1<<22)
1139 +#define RALINK_ESW_RST (1<<23)
1140 +#define RALINK_EPHY_RST (1<<24)
1141 +#define RALINK_UDEV_RST (1<<25)
1142 +#define RALINK_PCIE0_RST (1<<26)
1143 +#define RALINK_PCIE1_RST (1<<27)
1144 +#define RALINK_MIPS_CNT_RST (1<<28)
1145 +#define RALINK_CRYPTO_RST (1<<29)
1146 +
1147 +//Clock Conf Register
1148 +#define RALINK_UPHY0_CLK_EN (1<<25)
1149 +#define RALINK_UPHY1_CLK_EN (1<<22)
1150 +#define RALINK_PCIE0_CLK_EN (1<<26)
1151 +#define RALINK_PCIE1_CLK_EN (1<<27)
1152 +
1153 +//CPU PLL CFG Register
1154 +#define CPLL_SW_CONFIG (0x1UL << 31)
1155 +#define CPLL_MULT_RATIO_SHIFT 16
1156 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1157 +#define CPLL_DIV_RATIO_SHIFT 10
1158 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1159 +#define BASE_CLOCK 40 /* Mhz */
1160 +
1161 +#elif defined (CONFIG_RALINK_MT7621)
1162 +
1163 +#define RALINK_SYSCTL_BASE 0xBE000000
1164 +#define RALINK_TIMER_BASE 0xBE000100
1165 +#define RALINK_INTCL_BASE 0xBE000200
1166 +#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
1167 +#define RALINK_MIPS_CNT_BASE 0x1E000500
1168 +#define RALINK_PIO_BASE 0xBE000600
1169 +#define RALINK_SPDIF_BASE 0xBE000700
1170 +#define RALINK_I2C_BASE 0xBE000900
1171 +#define RALINK_I2S_BASE 0xBE000A00
1172 +#define RALINK_SPI_BASE 0xBE000B00
1173 +#define RALINK_UART_LITE1_BASE 0x1E000C00
1174 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1175 +#define RALINK_UART_LITE2_BASE 0x1E000D00
1176 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1177 +#define RALINK_UART_LITE3_BASE 0x1E000E00
1178 +#define RALINK_ANA_CTRL_BASE 0xBE000F00
1179 +#define RALINK_PCM_BASE 0xBE002000
1180 +#define RALINK_GDMA_BASE 0xBE002800
1181 +#define RALINK_NAND_CTRL_BASE 0xBE003000
1182 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
1183 +#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
1184 +#define RALINK_MEMCTRL_BASE 0xBE005000
1185 +#define RALINK_EXT_MC_ARB_BASE 0xBE006000
1186 +#define RALINK_HS_DMA_BASE 0xBE007000
1187 +#define RALINK_FRAME_ENGINE_BASE 0xBE100000
1188 +#define RALINK_PPE_BASE 0xBE100C00
1189 +#define RALINK_ETH_SW_BASE 0xBE110000
1190 +#define RALINK_ROM_BASE 0xBE118000
1191 +#define RALINK_MSDC_BASE 0xBE130000
1192 +#define RALINK_PCI_BASE 0xBE140000
1193 +#define RALINK_USB_HOST_BASE 0x1E1C0000
1194 +#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
1195 +
1196 +#define RALINK_MCNT_CFG 0xBE000500
1197 +#define RALINK_COMPARE 0xBE000504
1198 +#define RALINK_COUNT 0xBE000508
1199 +
1200 +//Interrupt Controller
1201 +#define RALINK_INTCTL_FE (1<<3)
1202 +#define RALINK_INTCTL_PCIE0 (1<<4)
1203 +#define RALINK_INTCTL_SYSCTL (1<<6)
1204 +#define RALINK_INTCTL_I2C (1<<8)
1205 +#define RALINK_INTCTL_DRAMC (1<<9)
1206 +#define RALINK_INTCTL_PCM (1<<10)
1207 +#define RALINK_INTCTL_HSDMA (1<<11)
1208 +#define RALINK_INTCTL_PIO (1<<12)
1209 +#define RALINK_INTCTL_DMA (1<<13)
1210 +#define RALINK_INTCTL_NFI (1<<14)
1211 +#define RALINK_INTCTL_NFIECC (1<<15)
1212 +#define RALINK_INTCTL_I2S (1<<16)
1213 +#define RALINK_INTCTL_SPI (1<<17)
1214 +#define RALINK_INTCTL_SPDIF (1<<18)
1215 +#define RALINK_INTCTL_CRYPTO (1<<19)
1216 +#define RALINK_INTCTL_SDXC (1<<20)
1217 +#define RALINK_INTCTL_PCTRL (1<<21)
1218 +#define RALINK_INTCTL_USB (1<<22)
1219 +#define RALINK_INTCTL_SWITCH (1<<23)
1220 +#define RALINK_INTCTL_PCIE1 (1<<24)
1221 +#define RALINK_INTCTL_PCIE2 (1<<25)
1222 +#define RALINK_INTCTL_UART1 (1<<26)
1223 +#define RALINK_INTCTL_UART2 (1<<27)
1224 +#define RALINK_INTCTL_UART3 (1<<28)
1225 +#define RALINK_INTCTL_WDTIMER (1<<29)
1226 +#define RALINK_INTCTL_TIMER0 (1<<30)
1227 +#define RALINK_INTCTL_TIMER1 (1<<31)
1228 +
1229 +
1230 +//Reset Control Register
1231 +#define RALINK_SYS_RST (1<<0)
1232 +#define RALINK_MCM_RST (1<<1)
1233 +#define RALINK_HSDMA_RST (1<<2)
1234 +#define RALINK_FE_RST (1<<6)
1235 +#define RALINK_SPDIF_RST (1<<7)
1236 +#define RALINK_TIMER_RST (1<<8)
1237 +#define RALINK_INTC_RST (1<<9)
1238 +#define RALINK_MC_RST (1<<10)
1239 +#define RALINK_PCM_RST (1<<11)
1240 +#define RALINK_PIO_RST (1<<13)
1241 +#define RALINK_DMA_RST (1<<14)
1242 +#define RALINK_NAND_RST (1<<15)
1243 +#define RALINK_I2C_RST (1<<16)
1244 +#define RALINK_I2S_RST (1<<17)
1245 +#define RALINK_SPI_RST (1<<18)
1246 +#define RALINK_UART1_RST (1<<19)
1247 +#define RALINK_UART2_RST (1<<20)
1248 +#define RALINK_UART3_RST (1<<21)
1249 +#define RALINK_ETH_RST (1<<23)
1250 +#define RALINK_PCIE0_RST (1<<24)
1251 +#define RALINK_PCIE1_RST (1<<25)
1252 +#define RALINK_PCIE2_RST (1<<26)
1253 +#define RALINK_AUX_STCK_RST (1<<28)
1254 +#define RALINK_CRYPTO_RST (1<<29)
1255 +#define RALINK_SDXC_RST (1<<30)
1256 +#define RALINK_PPE_RST (1<<31)
1257 +
1258 +//Clock Conf Register
1259 +#define RALINK_PCIE0_CLK_EN (1<<24)
1260 +#define RALINK_PCIE1_CLK_EN (1<<25)
1261 +#define RALINK_PCIE2_CLK_EN (1<<26)
1262 +//#define RALINK_UPHY0_CLK_EN (1<<27)
1263 +//#define RALINK_UPHY1_CLK_EN (1<<28)
1264 +
1265 +//CPU PLL CFG Register
1266 +#define CPLL_SW_CONFIG (0x1UL << 31)
1267 +#define CPLL_MULT_RATIO_SHIFT 16
1268 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1269 +#define CPLL_DIV_RATIO_SHIFT 10
1270 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1271 +#define BASE_CLOCK 40 /* Mhz */
1272 +
1273 +#define RALINK_TESTSTAT 0xBE000018
1274 +#define RALINK_TESTSTAT2 0xBE00001C
1275 +
1276 +#elif defined (CONFIG_RALINK_MT7628)
1277 +
1278 +#define RALINK_SYSCTL_BASE 0xB0000000
1279 +#define RALINK_TIMER_BASE 0xB0000100
1280 +#define RALINK_INTCL_BASE 0xB0000200
1281 +#define RALINK_MEMCTRL_BASE 0xB0000300
1282 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1283 +#define RALINK_MIPS_CNT_BASE 0x10000500
1284 +#define RALINK_PIO_BASE 0xB0000600
1285 +#define RALINK_SPI_SLAVE_BASE 0xB0000700
1286 +#define RALINK_I2C_BASE 0xB0000900
1287 +#define RALINK_I2S_BASE 0xB0000A00
1288 +#define RALINK_SPI_BASE 0xB0000B00
1289 +#define RALINK_UART_LITE1_BASE 0x10000C00
1290 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1291 +#define RALINK_UART_LITE2_BASE 0x10000D00
1292 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1293 +#define RALINK_UART_LITE3_BASE 0x10000E00
1294 +#define RALINK_PCM_BASE 0xB0002000
1295 +#define RALINK_GDMA_BASE 0xB0002800
1296 +#define RALINK_AES_ENGINE_BASE 0xB0004000
1297 +#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
1298 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1299 +#define RALINK_PPE_BASE 0xB0100C00
1300 +#define RALINK_ETH_SW_BASE 0xB0110000
1301 +#define RALINK_USB_DEV_BASE 0xB0120000
1302 +#define RALINK_MSDC_BASE 0xB0130000
1303 +#define RALINK_PCI_BASE 0xB0140000
1304 +#define RALINK_11N_MAC_BASE 0xB0180000
1305 +#define RALINK_USB_HOST_BASE 0x101C0000
1306 +
1307 +#define RALINK_MCNT_CFG 0xB0000500
1308 +#define RALINK_COMPARE 0xB0000504
1309 +#define RALINK_COUNT 0xB0000508
1310 +
1311 +
1312 +//Interrupt Controller
1313 +#define RALINK_INTCTL_SYSCTL (1<<0)
1314 +#define RALINK_INTCTL_TIMER0 (1<<1)
1315 +#define RALINK_INTCTL_WDTIMER (1<<2)
1316 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1317 +#define RALINK_INTCTL_PCM (1<<4)
1318 +#define RALINK_INTCTL_UART (1<<5)
1319 +#define RALINK_INTCTL_PIO (1<<6)
1320 +#define RALINK_INTCTL_DMA (1<<7)
1321 +#define RALINK_INTCTL_PC (1<<9)
1322 +#define RALINK_INTCTL_I2S (1<<10)
1323 +#define RALINK_INTCTL_SPI (1<<11)
1324 +#define RALINK_INTCTL_UARTLITE (1<<12)
1325 +#define RALINK_INTCTL_CRYPTO (1<<13)
1326 +#define RALINK_INTCTL_ESW (1<<17)
1327 +#define RALINK_INTCTL_UHST (1<<18)
1328 +#define RALINK_INTCTL_UDEV (1<<19)
1329 +#define RALINK_INTCTL_GLOBAL (1<<31)
1330 +
1331 +//Reset Control Register
1332 +#define RALINK_SYS_RST (1<<0)
1333 +#define RALINK_TIMER_RST (1<<8)
1334 +#define RALINK_INTC_RST (1<<9)
1335 +#define RALINK_MC_RST (1<<10)
1336 +#define RALINK_PCM_RST (1<<11)
1337 +#define RALINK_UART_RST (1<<12)
1338 +#define RALINK_PIO_RST (1<<13)
1339 +#define RALINK_DMA_RST (1<<14)
1340 +#define RALINK_I2C_RST (1<<16)
1341 +#define RALINK_I2S_RST (1<<17)
1342 +#define RALINK_SPI_RST (1<<18)
1343 +#define RALINK_UARTL_RST (1<<19)
1344 +#define RALINK_FE_RST (1<<21)
1345 +#define RALINK_UHST_RST (1<<22)
1346 +#define RALINK_ESW_RST (1<<23)
1347 +#define RALINK_EPHY_RST (1<<24)
1348 +#define RALINK_UDEV_RST (1<<25)
1349 +#define RALINK_PCIE0_RST (1<<26)
1350 +#define RALINK_PCIE1_RST (1<<27)
1351 +#define RALINK_MIPS_CNT_RST (1<<28)
1352 +#define RALINK_CRYPTO_RST (1<<29)
1353 +
1354 +//Clock Conf Register
1355 +#define RALINK_UPHY0_CLK_EN (1<<25)
1356 +#define RALINK_UPHY1_CLK_EN (1<<22)
1357 +#define RALINK_PCIE0_CLK_EN (1<<26)
1358 +#define RALINK_PCIE1_CLK_EN (1<<27)
1359 +
1360 +//CPU PLL CFG Register
1361 +#define CPLL_SW_CONFIG (0x1UL << 31)
1362 +#define CPLL_MULT_RATIO_SHIFT 16
1363 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1364 +#define CPLL_DIV_RATIO_SHIFT 10
1365 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1366 +#define BASE_CLOCK 40 /* Mhz */
1367 +
1368 +#endif
1369 +#endif
1370 diff --git a/arch/mips/include/asm/rt2880/serial_rt2880.h b/arch/mips/include/asm/rt2880/serial_rt2880.h
1371 new file mode 100644
1372 index 0000000..74f024f
1373 --- /dev/null
1374 +++ b/arch/mips/include/asm/rt2880/serial_rt2880.h
1375 @@ -0,0 +1,443 @@
1376 +/**************************************************************************
1377 + *
1378 + * BRIEF MODULE DESCRIPTION
1379 + * serial port definition for Ralink RT2880 solution
1380 + *
1381 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
1382 + *
1383 + * This program is free software; you can redistribute it and/or modify it
1384 + * under the terms of the GNU General Public License as published by the
1385 + * Free Software Foundation; either version 2 of the License, or (at your
1386 + * option) any later version.
1387 + *
1388 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1389 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1390 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1391 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1392 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1393 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1394 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1395 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1396 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1397 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1398 + *
1399 + * You should have received a copy of the GNU General Public License along
1400 + * with this program; if not, write to the Free Software Foundation, Inc.,
1401 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1402 + *
1403 + *
1404 + **************************************************************************
1405 + * May 2007 Bruce Chang
1406 + *
1407 + * Initial Release
1408 + *
1409 + *
1410 + *
1411 + **************************************************************************
1412 + */
1413 +
1414 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1415 +#define RT2880_UART_RBR_OFFSET 0x00
1416 +#define RT2880_UART_TBR_OFFSET 0x00
1417 +#define RT2880_UART_IER_OFFSET 0x04
1418 +#define RT2880_UART_IIR_OFFSET 0x08
1419 +#define RT2880_UART_FCR_OFFSET 0x08
1420 +#define RT2880_UART_LCR_OFFSET 0x0C
1421 +#define RT2880_UART_MCR_OFFSET 0x10
1422 +#define RT2880_UART_LSR_OFFSET 0x14
1423 +#define RT2880_UART_DLL_OFFSET 0x00
1424 +#define RT2880_UART_DLM_OFFSET 0x04
1425 +#else
1426 +#define RT2880_UART_RBR_OFFSET 0x00
1427 +#define RT2880_UART_TBR_OFFSET 0x04
1428 +#define RT2880_UART_IER_OFFSET 0x08
1429 +#define RT2880_UART_IIR_OFFSET 0x0C
1430 +#define RT2880_UART_FCR_OFFSET 0x10
1431 +#define RT2880_UART_LCR_OFFSET 0x14
1432 +#define RT2880_UART_MCR_OFFSET 0x18
1433 +#define RT2880_UART_LSR_OFFSET 0x1C
1434 +#define RT2880_UART_DLL_OFFSET 0x2C
1435 +#define RT2880_UART_DLM_OFFSET 0x30
1436 +#endif
1437 +
1438 +#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
1439 +#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
1440 +#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
1441 +#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
1442 +#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
1443 +#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
1444 +#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
1445 +#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
1446 +#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
1447 +#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
1448 +
1449 +
1450 +#if defined (CONFIG_RALINK_RT2880) || \
1451 + defined (CONFIG_RALINK_RT2883) || \
1452 + defined (CONFIG_RALINK_RT3883) || \
1453 + defined (CONFIG_RALINK_RT3352) || \
1454 + defined (CONFIG_RALINK_RT5350) || \
1455 + defined (CONFIG_RALINK_RT6855) || \
1456 + defined (CONFIG_RALINK_MT7620) || \
1457 + defined (CONFIG_RALINK_RT3052)
1458 +
1459 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1460 +
1461 +#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
1462 +#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
1463 + * In: Fifo count
1464 + * Out: Fifo custom trigger levels
1465 + * XR16C85x only
1466 + */
1467 +
1468 +#define UART_IER 8 /* Out: Interrupt Enable Register */
1469 +#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
1470 + * XR16C85x only
1471 + */
1472 +
1473 +#define UART_IIR 12 /* In: Interrupt ID Register */
1474 +#define UART_EFR 12 /* I/O: Extended Features Register */
1475 + /* (DLAB=1, 16C660 only) */
1476 +
1477 +#define UART_FCR 16 /* Out: FIFO Control Register */
1478 +#define UART_LCR 20 /* Out: Line Control Register */
1479 +#define UART_MCR 24 /* Out: Modem Control Register */
1480 +#define UART_LSR 28 /* In: Line Status Register */
1481 +#define UART_MSR 32 /* In: Modem Status Register */
1482 +#define UART_SCR 36 /* I/O: Scratch Register */
1483 +#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
1484 +/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
1485 + * unpredictable values to be written to the Divisor Latch
1486 + */
1487 +#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
1488 +
1489 +#else
1490 +
1491 +#define UART_RX 0 /* In: Receive buffer */
1492 +#define UART_TX 0 /* Out: Transmit buffer */
1493 +#define UART_DLL 0 /* Out: Divisor Latch Low */
1494 +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1495 + * In: Fifo count
1496 + * Out: Fifo custom trigger levels */
1497 +
1498 +#define UART_DLM 4 /* Out: Divisor Latch High */
1499 +#define UART_IER 4 /* Out: Interrupt Enable Register */
1500 +#define UART_FCTR 4 /* Feature Control Register */
1501 +
1502 +#define UART_IIR 8 /* In: Interrupt ID Register */
1503 +#define UART_FCR 8 /* Out: FIFO Control Register */
1504 +#define UART_EFR 8 /* I/O: Extended Features Register */
1505 +
1506 +#define UART_LCR 12 /* Out: Line Control Register */
1507 +#define UART_MCR 16 /* Out: Modem Control Register */
1508 +#define UART_LSR 20 /* In: Line Status Register */
1509 +#define UART_MSR 24 /* In: Modem Status Register */
1510 +#define UART_SCR 28 /* I/O: Scratch Register */
1511 +#define UART_EMSR 28 /* Extended Mode Select Register */
1512 +
1513 +#endif
1514 +/*
1515 + * DLAB=0
1516 + */
1517 +//#define UART_IER 1 /* Out: Interrupt Enable Register */
1518 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1519 +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1520 +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1521 +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1522 +/*
1523 + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
1524 + */
1525 +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
1526 +
1527 +//#define UART_IIR 2 /* In: Interrupt ID Register */
1528 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1529 +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1530 +#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1531 +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1532 +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1533 +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1534 +
1535 +//#define UART_FCR 2 /* Out: FIFO Control Register */
1536 +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1537 +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1538 +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1539 +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1540 +/*
1541 + * Note: The FIFO trigger levels are chip specific:
1542 + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
1543 + * PC16550D: 1 4 8 14 xx xx xx xx
1544 + * TI16C550A: 1 4 8 14 xx xx xx xx
1545 + * TI16C550C: 1 4 8 14 xx xx xx xx
1546 + * ST16C550: 1 4 8 14 xx xx xx xx
1547 + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
1548 + * NS16C552: 1 4 8 14 xx xx xx xx
1549 + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
1550 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
1551 + * TI16C752: 8 16 56 60 8 16 32 56
1552 + */
1553 +#define UART_FCR_R_TRIG_00 0x00
1554 +#define UART_FCR_R_TRIG_01 0x40
1555 +#define UART_FCR_R_TRIG_10 0x80
1556 +#define UART_FCR_R_TRIG_11 0xc0
1557 +#define UART_FCR_T_TRIG_00 0x00
1558 +#define UART_FCR_T_TRIG_01 0x10
1559 +#define UART_FCR_T_TRIG_10 0x20
1560 +#define UART_FCR_T_TRIG_11 0x30
1561 +
1562 +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
1563 +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
1564 +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
1565 +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
1566 +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
1567 +/* 16650 definitions */
1568 +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
1569 +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
1570 +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
1571 +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
1572 +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
1573 +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
1574 +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
1575 +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
1576 +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
1577 +
1578 +//#define UART_LCR 3 /* Out: Line Control Register */
1579 +/*
1580 + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
1581 + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
1582 + */
1583 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1584 +#define UART_LCR_SBC 0x40 /* Set break control */
1585 +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1586 +#define UART_LCR_EPAR 0x10 /* Even parity select */
1587 +#define UART_LCR_PARITY 0x08 /* Parity Enable */
1588 +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
1589 +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1590 +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1591 +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1592 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1593 +
1594 +//#define UART_MCR 4 /* Out: Modem Control Register */
1595 +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
1596 +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
1597 +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
1598 +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
1599 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1600 +#define UART_MCR_OUT2 0x08 /* Out2 complement */
1601 +#define UART_MCR_OUT1 0x04 /* Out1 complement */
1602 +#define UART_MCR_RTS 0x02 /* RTS complement */
1603 +#define UART_MCR_DTR 0x01 /* DTR complement */
1604 +
1605 +//#define UART_LSR 5 /* In: Line Status Register */
1606 +#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1607 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1608 +#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1609 +#define UART_LSR_FE 0x08 /* Frame error indicator */
1610 +#define UART_LSR_PE 0x04 /* Parity error indicator */
1611 +#define UART_LSR_OE 0x02 /* Overrun error indicator */
1612 +#define UART_LSR_DR 0x01 /* Receiver data ready */
1613 +
1614 +//#define UART_MSR 6 /* In: Modem Status Register */
1615 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1616 +#define UART_MSR_RI 0x40 /* Ring Indicator */
1617 +#define UART_MSR_DSR 0x20 /* Data Set Ready */
1618 +#define UART_MSR_CTS 0x10 /* Clear to Send */
1619 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
1620 +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1621 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
1622 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
1623 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1624 +
1625 +//#define UART_SCR 7 /* I/O: Scratch Register */
1626 +
1627 +/*
1628 + * DLAB=1
1629 + */
1630 +//#define UART_DLL 0 /* Out: Divisor Latch Low */
1631 +//#define UART_DLM 1 /* Out: Divisor Latch High */
1632 +
1633 +/*
1634 + * LCR=0xBF (or DLAB=1 for 16C660)
1635 + */
1636 +//#define UART_EFR 2 /* I/O: Extended Features Register */
1637 +#define UART_EFR_CTS 0x80 /* CTS flow control */
1638 +#define UART_EFR_RTS 0x40 /* RTS flow control */
1639 +#define UART_EFR_SCD 0x20 /* Special character detect */
1640 +#define UART_EFR_ECB 0x10 /* Enhanced control bit */
1641 +/*
1642 + * the low four bits control software flow control
1643 + */
1644 +
1645 +/*
1646 + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
1647 + */
1648 +#define UART_XON1 4 /* I/O: Xon character 1 */
1649 +#define UART_XON2 5 /* I/O: Xon character 2 */
1650 +#define UART_XOFF1 6 /* I/O: Xoff character 1 */
1651 +#define UART_XOFF2 7 /* I/O: Xoff character 2 */
1652 +
1653 +/*
1654 + * EFR[4]=1 MCR[6]=1, TI16C752
1655 + */
1656 +#define UART_TI752_TCR 6 /* I/O: transmission control register */
1657 +#define UART_TI752_TLR 7 /* I/O: trigger level register */
1658 +
1659 +/*
1660 + * LCR=0xBF, XR16C85x
1661 + */
1662 +//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1663 +// * In: Fifo count
1664 +// * Out: Fifo custom trigger levels */
1665 +/*
1666 + * These are the definitions for the Programmable Trigger Register
1667 + */
1668 +#define UART_TRG_1 0x01
1669 +#define UART_TRG_4 0x04
1670 +#define UART_TRG_8 0x08
1671 +#define UART_TRG_16 0x10
1672 +#define UART_TRG_32 0x20
1673 +#define UART_TRG_64 0x40
1674 +#define UART_TRG_96 0x60
1675 +#define UART_TRG_120 0x78
1676 +#define UART_TRG_128 0x80
1677 +
1678 +//#define UART_FCTR 1 /* Feature Control Register */
1679 +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
1680 +#define UART_FCTR_RTS_4DELAY 0x01
1681 +#define UART_FCTR_RTS_6DELAY 0x02
1682 +#define UART_FCTR_RTS_8DELAY 0x03
1683 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
1684 +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
1685 +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
1686 +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
1687 +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
1688 +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
1689 +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
1690 +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
1691 +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
1692 +
1693 +/*
1694 + * LCR=0xBF, FCTR[6]=1
1695 + */
1696 +//#define UART_EMSR 7 /* Extended Mode Select Register */
1697 +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
1698 +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
1699 +
1700 +/*
1701 + * The Intel XScale on-chip UARTs define these bits
1702 + */
1703 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
1704 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
1705 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
1706 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
1707 +
1708 +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
1709 +
1710 +#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
1711 +#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
1712 +#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
1713 +#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
1714 +
1715 +
1716 +
1717 +
1718 +/*
1719 + * These register definitions are for the 16C950
1720 + */
1721 +#define UART_ASR 0x01 /* Additional Status Register */
1722 +#define UART_RFL 0x03 /* Receiver FIFO level */
1723 +#define UART_TFL 0x04 /* Transmitter FIFO level */
1724 +#define UART_ICR 0x05 /* Index Control Register */
1725 +
1726 +/* The 16950 ICR registers */
1727 +#define UART_ACR 0x00 /* Additional Control Register */
1728 +#define UART_CPR 0x01 /* Clock Prescalar Register */
1729 +#define UART_TCR 0x02 /* Times Clock Register */
1730 +#define UART_CKS 0x03 /* Clock Select Register */
1731 +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
1732 +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
1733 +#define UART_FCL 0x06 /* Flow Control Level Lower */
1734 +#define UART_FCH 0x07 /* Flow Control Level Higher */
1735 +#define UART_ID1 0x08 /* ID #1 */
1736 +#define UART_ID2 0x09 /* ID #2 */
1737 +#define UART_ID3 0x0A /* ID #3 */
1738 +#define UART_REV 0x0B /* Revision */
1739 +#define UART_CSR 0x0C /* Channel Software Reset */
1740 +#define UART_NMR 0x0D /* Nine-bit Mode Register */
1741 +#define UART_CTR 0xFF
1742 +
1743 +/*
1744 + * The 16C950 Additional Control Reigster
1745 + */
1746 +#define UART_ACR_RXDIS 0x01 /* Receiver disable */
1747 +#define UART_ACR_TXDIS 0x02 /* Receiver disable */
1748 +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
1749 +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
1750 +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
1751 +#define UART_ACR_ASREN 0x80 /* Additional status enable */
1752 +
1753 +
1754 +
1755 +/*
1756 + * These definitions are for the RSA-DV II/S card, from
1757 + *
1758 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
1759 + */
1760 +
1761 +#define UART_RSA_BASE (-8)
1762 +
1763 +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
1764 +
1765 +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
1766 +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
1767 +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
1768 +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
1769 +
1770 +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
1771 +
1772 +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
1773 +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
1774 +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
1775 +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
1776 +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
1777 +
1778 +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
1779 +
1780 +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
1781 +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
1782 +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
1783 +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
1784 +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
1785 +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
1786 +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
1787 +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
1788 +
1789 +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
1790 +
1791 +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
1792 +
1793 +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
1794 +
1795 +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
1796 +
1797 +/*
1798 + * The RSA DSV/II board has two fixed clock frequencies. One is the
1799 + * standard rate, and the other is 8 times faster.
1800 + */
1801 +#define SERIAL_RSA_BAUD_BASE (921600)
1802 +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
1803 +
1804 +/*
1805 + * Extra serial register definitions for the internal UARTs
1806 + * in TI OMAP processors.
1807 + */
1808 +#define UART_OMAP_MDR1 0x08 /* Mode definition register */
1809 +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
1810 +#define UART_OMAP_SCR 0x10 /* Supplementary control register */
1811 +#define UART_OMAP_SSR 0x11 /* Supplementary status register */
1812 +#define UART_OMAP_EBLR 0x12 /* BOF length register */
1813 +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
1814 +#define UART_OMAP_MVER 0x14 /* Module version register */
1815 +#define UART_OMAP_SYSC 0x15 /* System configuration register */
1816 +#define UART_OMAP_SYSS 0x16 /* System status register */
1817 +
1818 +
1819 diff --git a/arch/mips/include/asm/rt2880/sizes.h b/arch/mips/include/asm/rt2880/sizes.h
1820 new file mode 100644
1821 index 0000000..7f50ae0
1822 --- /dev/null
1823 +++ b/arch/mips/include/asm/rt2880/sizes.h
1824 @@ -0,0 +1,52 @@
1825 +/*
1826 + * This program is free software; you can redistribute it and/or modify
1827 + * it under the terms of the GNU General Public License as published by
1828 + * the Free Software Foundation; either version 2 of the License, or
1829 + * (at your option) any later version.
1830 + *
1831 + * This program is distributed in the hope that it will be useful,
1832 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1833 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1834 + * GNU General Public License for more details.
1835 + *
1836 + * You should have received a copy of the GNU General Public License
1837 + * along with this program; if not, write to the Free Software
1838 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1839 + */
1840 +/* DO NOT EDIT!! - this file automatically generated
1841 + * from .s file by awk -f s2h.awk
1842 + */
1843 +/* Size definitions
1844 + * Copyright (C) ARM Limited 1998. All rights reserved.
1845 + */
1846 +
1847 +#ifndef __sizes_h
1848 +#define __sizes_h 1
1849 +
1850 +/* handy sizes */
1851 +#define SZ_1K 0x00000400
1852 +#define SZ_4K 0x00001000
1853 +#define SZ_8K 0x00002000
1854 +#define SZ_16K 0x00004000
1855 +#define SZ_64K 0x00010000
1856 +#define SZ_128K 0x00020000
1857 +#define SZ_256K 0x00040000
1858 +#define SZ_512K 0x00080000
1859 +
1860 +#define SZ_1M 0x00100000
1861 +#define SZ_2M 0x00200000
1862 +#define SZ_4M 0x00400000
1863 +#define SZ_8M 0x00800000
1864 +#define SZ_16M 0x01000000
1865 +#define SZ_32M 0x02000000
1866 +#define SZ_64M 0x04000000
1867 +#define SZ_128M 0x08000000
1868 +#define SZ_256M 0x10000000
1869 +#define SZ_512M 0x20000000
1870 +
1871 +#define SZ_1G 0x40000000
1872 +#define SZ_2G 0x80000000
1873 +
1874 +#endif
1875 +
1876 +/* END */
1877 diff --git a/arch/mips/include/asm/rt2880/surfboard.h b/arch/mips/include/asm/rt2880/surfboard.h
1878 new file mode 100644
1879 index 0000000..373da34
1880 --- /dev/null
1881 +++ b/arch/mips/include/asm/rt2880/surfboard.h
1882 @@ -0,0 +1,70 @@
1883 +/*
1884 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1885 + *
1886 + * ########################################################################
1887 + *
1888 + * This program is free software; you can distribute it and/or modify it
1889 + * under the terms of the GNU General Public License (Version 2) as
1890 + * published by the Free Software Foundation.
1891 + *
1892 + * This program is distributed in the hope it will be useful, but WITHOUT
1893 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1894 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1895 + * for more details.
1896 + *
1897 + * You should have received a copy of the GNU General Public License along
1898 + * with this program; if not, write to the Free Software Foundation, Inc.,
1899 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1900 + *
1901 + * ########################################################################
1902 + *
1903 + */
1904 +#ifndef _SURFBOARD_H
1905 +#define _SURFBOARD_H
1906 +
1907 +#include <asm/addrspace.h>
1908 +
1909 +
1910 +
1911 +/*
1912 + * Surfboard system clock.
1913 + * This is the default value and maybe overidden by System Clock passed on the
1914 + * command line (sysclk=).
1915 + */
1916 +#define SURFBOARD_SYSTEM_CLOCK (125000000)
1917 +
1918 +/*
1919 + * Surfboard UART base baud rate = System Clock / 16.
1920 + * Ex. (14.7456 MHZ / 16) = 921600
1921 + * (32.0000 MHZ / 16) = 2000000
1922 + */
1923 +#define SURFBOARD_BAUD_DIV (16)
1924 +#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
1925 +
1926 +/*
1927 + * Maximum number of IDE Controllers
1928 + * Surfboard only has one ide (ide0), so only 2 drives are
1929 + * possible. (no need to check for more hwifs.)
1930 + */
1931 +//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
1932 +#define MAX_IDE_HWIFS (2) /* Graphite board */
1933 +
1934 +#define GCMP_BASE_ADDR 0x1fbf8000
1935 +#define GCMP_ADDRSPACE_SZ (256 * 1024)
1936 +
1937 +/*
1938 + * * GIC Specific definitions
1939 + * */
1940 +#define GIC_BASE_ADDR 0x1fbc0000
1941 +#define GIC_ADDRSPACE_SZ (128 * 1024)
1942 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
1943 +
1944 +/* GIC's Nomenclature for Core Interrupt Pins */
1945 +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
1946 +#define GIC_CPU_INT1 1 /* . */
1947 +#define GIC_CPU_INT2 2 /* . */
1948 +#define GIC_CPU_INT3 3 /* . */
1949 +#define GIC_CPU_INT4 4 /* . */
1950 +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
1951 +
1952 +#endif /* !(_SURFBOARD_H) */
1953 diff --git a/arch/mips/include/asm/rt2880/surfboardint.h b/arch/mips/include/asm/rt2880/surfboardint.h
1954 new file mode 100644
1955 index 0000000..671cca5
1956 --- /dev/null
1957 +++ b/arch/mips/include/asm/rt2880/surfboardint.h
1958 @@ -0,0 +1,190 @@
1959 +/*
1960 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1961 + *
1962 + * ########################################################################
1963 + *
1964 + * This program is free software; you can distribute it and/or modify it
1965 + * under the terms of the GNU General Public License (Version 2) as
1966 + * published by the Free Software Foundation.
1967 + *
1968 + * This program is distributed in the hope it will be useful, but WITHOUT
1969 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1970 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1971 + * for more details.
1972 + *
1973 + * You should have received a copy of the GNU General Public License along
1974 + * with this program; if not, write to the Free Software Foundation, Inc.,
1975 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1976 + *
1977 + * ########################################################################
1978 + *
1979 + * Defines for the Surfboard interrupt controller.
1980 + *
1981 + */
1982 +#ifndef _SURFBOARDINT_H
1983 +#define _SURFBOARDINT_H
1984 +
1985 +/* Number of IRQ supported on hw interrupt 0. */
1986 +#if defined (CONFIG_RALINK_RT2880)
1987 +#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
1988 +#define SURFBOARDINT_GPIO 7 /* GPIO */
1989 +#define SURFBOARDINT_UART1 8 /* UART Lite */
1990 +#define SURFBOARDINT_UART 9 /* UART */
1991 +#define SURFBOARDINT_TIMER0 10 /* timer0 */
1992 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
1993 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
1994 +#define SURFBOARDINT_GPIO 6 /* GPIO */
1995 +#define SURFBOARDINT_DMA 7 /* DMA */
1996 +#define SURFBOARDINT_NAND 8 /* NAND */
1997 +#define SURFBOARDINT_PC 9 /* Performance counter */
1998 +#define SURFBOARDINT_I2S 10 /* I2S */
1999 +#define SURFBOARDINT_SDXC 14 /* SDXC */
2000 +#define SURFBOARDINT_ESW 17 /* ESW */
2001 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2002 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
2003 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2004 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2005 +#define SURFBOARDINT_WDG 34 /* watch dog */
2006 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2007 +#define SURFBOARDINT_PCM 36 /* PCM */
2008 +#define SURFBOARDINT_UART 37 /* UART */
2009 +#define RALINK_INT_PCIE0 13 /* PCIE0 */
2010 +#define RALINK_INT_PCIE1 14 /* PCIE1 */
2011 +
2012 +
2013 +#elif defined (CONFIG_RALINK_MT7628)
2014 +#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
2015 +#define SURFBOARDINT_PCM 4 /* PCM */
2016 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2017 +#define SURFBOARDINT_DMA 7 /* DMA */
2018 +#define SURFBOARDINT_PC 9 /* Performance counter */
2019 +#define SURFBOARDINT_I2S 10 /* I2S */
2020 +#define SURFBOARDINT_SPI 11 /* SPI */
2021 +#define SURFBOARDINT_AES 13 /* AES */
2022 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
2023 +#define SURFBOARDINT_SDXC 14 /* SDXC */
2024 +#define SURFBOARDINT_ESW 17 /* ESW */
2025 +#define SURFBOARDINT_USB 18 /* USB */
2026 +#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
2027 +#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
2028 +#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
2029 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
2030 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
2031 +#define SURFBOARDINT_WDG 23 /* WDG timer */
2032 +#define SURFBOARDINT_TIMER0 24 /* Timer0 */
2033 +#define SURFBOARDINT_TIMER1 25 /* Timer1 */
2034 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2035 +#define RALINK_INT_PCIE0 2 /* PCIE0 */
2036 +
2037 +
2038 +#elif defined (CONFIG_RALINK_MT7621)
2039 +
2040 +#define SURFBOARDINT_FE 3 /* FE */
2041 +#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
2042 +#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
2043 +#define SURFBOARDINT_I2C 8 /* I2C */
2044 +#define SURFBOARDINT_DRAMC 9 /* DRAMC */
2045 +#define SURFBOARDINT_PCM 10 /* PCM */
2046 +#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
2047 +#define SURFBOARDINT_GPIO 12 /* GPIO */
2048 +#define SURFBOARDINT_DMA 13 /* GDMA */
2049 +#define SURFBOARDINT_NAND 14 /* NAND */
2050 +#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
2051 +#define SURFBOARDINT_I2S 16 /* I2S */
2052 +#define SURFBOARDINT_SPI 17 /* SPI */
2053 +#define SURFBOARDINT_SPDIF 18 /* SPDIF */
2054 +#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
2055 +#define SURFBOARDINT_SDXC 20 /* SDXC */
2056 +#define SURFBOARDINT_PCTRL 21 /* Performance counter */
2057 +#define SURFBOARDINT_USB 22 /* USB */
2058 +#define SURFBOARDINT_ESW 31 /* Switch */
2059 +#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
2060 +#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
2061 +#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
2062 +#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
2063 +#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
2064 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
2065 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
2066 +
2067 +#define SURFBOARDINT_WDG 29 /* WDG timer */
2068 +#define SURFBOARDINT_TIMER0 30 /* Timer0 */
2069 +#define SURFBOARDINT_TIMER1 31 /* Timer1 */
2070 +
2071 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
2072 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
2073 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
2074 +
2075 +#elif defined (CONFIG_RALINK_RT3883)
2076 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
2077 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2078 +#define SURFBOARDINT_DMA 7 /* DMA */
2079 +#define SURFBOARDINT_NAND 8 /* NAND */
2080 +#define SURFBOARDINT_PC 9 /* Performance counter */
2081 +#define SURFBOARDINT_I2S 10 /* I2S */
2082 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2083 +#define SURFBOARDINT_PCI 18 /* PCI */
2084 +#define SURFBOARDINT_UDEV 19 /* USB Device */
2085 +#define SURFBOARDINT_UHST 20 /* USB Host */
2086 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2087 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2088 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2089 +#define SURFBOARDINT_PCM 36 /* PCM */
2090 +#define SURFBOARDINT_UART 37 /* UART */
2091 +#endif
2092 +
2093 +#define SURFBOARDINT_END 64
2094 +#define RT2880_INTERINT_START 40
2095 +
2096 +/* Global interrupt bit definitions */
2097 +#define C_SURFBOARD_GLOBAL_INT 31
2098 +#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
2099 +
2100 +/* added ??? */
2101 +#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
2102 +#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
2103 +/* end of added, bobtseng */
2104 +
2105 +/*
2106 + * Surfboard registers are memory mapped on 32-bit aligned boundaries and
2107 + * only word access are allowed.
2108 + */
2109 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2110 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
2111 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
2112 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
2113 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
2114 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
2115 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
2116 +#else
2117 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
2118 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
2119 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
2120 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
2121 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
2122 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
2123 +#endif
2124 +
2125 +/* bobtseng added ++, 2006.3.6. */
2126 +#define read_32bit_cp0_register(source) \
2127 +({ int __res; \
2128 + __asm__ __volatile__( \
2129 + ".set\tpush\n\t" \
2130 + ".set\treorder\n\t" \
2131 + "mfc0\t%0,"STR(source)"\n\t" \
2132 + ".set\tpop" \
2133 + : "=r" (__res)); \
2134 + __res;})
2135 +
2136 +#define write_32bit_cp0_register(register,value) \
2137 + __asm__ __volatile__( \
2138 + "mtc0\t%0,"STR(register)"\n\t" \
2139 + "nop" \
2140 + : : "r" (value));
2141 +
2142 +/* bobtseng added --, 2006.3.6. */
2143 +
2144 +void surfboardint_init(void);
2145 +u32 get_surfboard_sysclk(void);
2146 +
2147 +
2148 +#endif /* !(_SURFBOARDINT_H) */
2149 diff --git a/arch/mips/include/asm/rt2880/war.h b/arch/mips/include/asm/rt2880/war.h
2150 new file mode 100644
2151 index 0000000..7c6931d
2152 --- /dev/null
2153 +++ b/arch/mips/include/asm/rt2880/war.h
2154 @@ -0,0 +1,25 @@
2155 +/*
2156 + * This file is subject to the terms and conditions of the GNU General Public
2157 + * License. See the file "COPYING" in the main directory of this archive
2158 + * for more details.
2159 + *
2160 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2161 + */
2162 +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
2163 +#define __ASM_MIPS_MACH_MIPS_WAR_H
2164 +
2165 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
2166 +#define R4600_V1_HIT_CACHEOP_WAR 0
2167 +#define R4600_V2_HIT_CACHEOP_WAR 0
2168 +#define R5432_CP0_INTERRUPT_WAR 0
2169 +#define BCM1250_M3_WAR 0
2170 +#define SIBYTE_1956_WAR 0
2171 +#define MIPS4K_ICACHE_REFILL_WAR 1
2172 +#define MIPS_CACHE_SYNC_WAR 1
2173 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
2174 +#define RM9000_CDEX_SMP_WAR 0
2175 +#define ICACHE_REFILLS_WORKAROUND_WAR 1
2176 +#define R10000_LLSC_WAR 0
2177 +#define MIPS34K_MISSED_ITLB_WAR 0
2178 +
2179 +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
2180 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
2181 index ef6a274..1b9b3b2 100644
2182 --- a/drivers/net/ethernet/Kconfig
2183 +++ b/drivers/net/ethernet/Kconfig
2184 @@ -135,6 +135,7 @@ source "drivers/net/ethernet/packetengines/Kconfig"
2185 source "drivers/net/ethernet/pasemi/Kconfig"
2186 source "drivers/net/ethernet/qlogic/Kconfig"
2187 source "drivers/net/ethernet/ralink/Kconfig"
2188 +source "drivers/net/ethernet/raeth/Kconfig"
2189 source "drivers/net/ethernet/realtek/Kconfig"
2190 source "drivers/net/ethernet/renesas/Kconfig"
2191 source "drivers/net/ethernet/rdc/Kconfig"
2192 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
2193 index 7c3eb7b..e66b3bb 100644
2194 --- a/drivers/net/ethernet/Makefile
2195 +++ b/drivers/net/ethernet/Makefile
2196 @@ -57,6 +57,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
2197 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
2198 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
2199 obj-$(CONFIG_NET_RALINK) += ralink/
2200 +obj-$(CONFIG_RAETH) += raeth/
2201 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
2202 obj-$(CONFIG_SH_ETH) += renesas/
2203 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
2204 diff --git a/drivers/net/ethernet/raeth/Kconfig b/drivers/net/ethernet/raeth/Kconfig
2205 new file mode 100644
2206 index 0000000..e24b52c
2207 --- /dev/null
2208 +++ b/drivers/net/ethernet/raeth/Kconfig
2209 @@ -0,0 +1,344 @@
2210 +
2211 +config RA_NAT_NONE
2212 + bool
2213 + default y
2214 + depends on RALINK
2215 +
2216 +config MT7621_ASIC
2217 + bool
2218 + default y
2219 + depends on SOC_MT7621
2220 +
2221 +config RALINK_MT7621
2222 + bool
2223 + default y
2224 + depends on SOC_MT7621
2225 +
2226 +config RAETH
2227 + tristate "Ralink GMAC"
2228 + depends on SOC_MT7621
2229 + ---help---
2230 + This driver supports Ralink gigabit ethernet family of
2231 + adapters.
2232 +
2233 +config PDMA_NEW
2234 + bool
2235 + default y if (RALINK_MT7620 || RALINK_MT7621)
2236 + depends on RAETH
2237 +
2238 +config RAETH_SCATTER_GATHER_RX_DMA
2239 + bool
2240 + default y if (RALINK_MT7620 || RALINK_MT7621)
2241 + depends on RAETH
2242 +
2243 +
2244 +choice
2245 + prompt "Network BottomHalves"
2246 + depends on RAETH
2247 + default RA_NETWORK_WORKQUEUE_BH
2248 +
2249 + config RA_NETWORK_TASKLET_BH
2250 + bool "Tasklet"
2251 +
2252 + config RA_NETWORK_WORKQUEUE_BH
2253 + bool "Work Queue"
2254 +
2255 + config RAETH_NAPI
2256 + bool "NAPI"
2257 +
2258 +endchoice
2259 +
2260 +#config TASKLET_WORKQUEUE_SW
2261 +# bool "Tasklet and Workqueue switch"
2262 +# depends on RA_NETWORK_TASKLET_BH
2263 +
2264 +config RAETH_SKB_RECYCLE_2K
2265 + bool "SKB Recycling"
2266 + depends on RAETH
2267 +
2268 +config RAETH_SPECIAL_TAG
2269 + bool "Ralink Special Tag (0x810x)"
2270 + depends on RAETH && RT_3052_ESW
2271 +
2272 +#config RAETH_JUMBOFRAME
2273 +# bool "Jumbo Frame up to 4K bytes"
2274 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
2275 +
2276 +config RAETH_CHECKSUM_OFFLOAD
2277 + bool "TCP/UDP/IP checksum offload"
2278 + default y
2279 + depends on RAETH && !RALINK_RT2880
2280 +
2281 +#config RAETH_SW_FC
2282 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
2283 +# default n
2284 +# depends on RAETH
2285 +
2286 +config 32B_DESC
2287 + bool "32bytes TX/RX description"
2288 + default n
2289 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
2290 + ---help---
2291 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
2292 +
2293 +config RAETH_LRO
2294 + bool "LRO (Large Receive Offload )"
2295 + select INET_LRO
2296 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
2297 +
2298 +config RAETH_HW_VLAN_TX
2299 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
2300 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
2301 + ---help---
2302 + Please disable HW_VLAN_TX if you need double vlan
2303 +
2304 +config RAETH_HW_VLAN_RX
2305 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
2306 + depends on RAETH && RALINK_MT7621
2307 + ---help---
2308 + Please disable HW_VLAN_RX if you need double vlan
2309 +
2310 +config RAETH_TSO
2311 + bool "TSOV4 (Tcp Segmentaton Offload)"
2312 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
2313 +
2314 +config RAETH_TSOV6
2315 + bool "TSOV6 (Tcp Segmentaton Offload)"
2316 + depends on RAETH_TSO
2317 +
2318 +config RAETH_RW_PDMAPTR_FROM_VAR
2319 + bool
2320 + default y if RALINK_RT6855A || RALINK_MT7620
2321 + depends on RAETH
2322 +
2323 +#config RAETH_QOS
2324 +# bool "QoS Feature"
2325 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
2326 +
2327 +choice
2328 + prompt "QoS Type"
2329 + depends on RAETH_QOS
2330 + default DSCP_QOS_DSCP
2331 +
2332 +config RAETH_QOS_DSCP_BASED
2333 + bool "DSCP-based"
2334 + depends on RAETH_QOS
2335 +
2336 +config RAETH_QOS_VPRI_BASED
2337 + bool "VPRI-based"
2338 + depends on RAETH_QOS
2339 +
2340 +endchoice
2341 +
2342 +config RAETH_QDMA
2343 + bool "Choose QDMA instead PDMA"
2344 + default n
2345 + depends on RAETH && RALINK_MT7621
2346 +
2347 +choice
2348 + prompt "GMAC is connected to"
2349 + depends on RAETH
2350 + default GE1_RGMII_FORCE_1000
2351 +
2352 +config GE1_MII_FORCE_100
2353 + bool "MII_FORCE_100 (10/100M Switch)"
2354 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2355 +
2356 +config GE1_MII_AN
2357 + bool "MII_AN (100Phy)"
2358 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2359 +
2360 +config GE1_RVMII_FORCE_100
2361 + bool "RvMII_FORCE_100 (CPU)"
2362 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2363 +
2364 +config GE1_RGMII_FORCE_1000
2365 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2366 + depends on (RALINK_RT2880 || RALINK_RT3883)
2367 + select RALINK_SPI
2368 +
2369 +config GE1_RGMII_FORCE_1000
2370 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2371 + depends on (RALINK_MT7621)
2372 + select RT_3052_ESW
2373 +
2374 +config GE1_TRGMII_FORCE_1200
2375 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
2376 + depends on (RALINK_MT7621)
2377 + select RT_3052_ESW
2378 +
2379 +config GE1_RGMII_AN
2380 + bool "RGMII_AN (GigaPhy)"
2381 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2382 +
2383 +config GE1_RGMII_NONE
2384 + bool "NONE (NO CONNECT)"
2385 + depends on (RALINK_MT7621)
2386 +
2387 +endchoice
2388 +
2389 +config RT_3052_ESW
2390 + bool "Ralink Embedded Switch"
2391 + default y
2392 + depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
2393 +
2394 +config LAN_WAN_SUPPORT
2395 + bool "LAN/WAN Partition"
2396 + depends on RAETH_ROUTER || RT_3052_ESW
2397 +
2398 +choice
2399 + prompt "Switch Board Layout Type"
2400 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
2401 + default WAN_AT_P0
2402 +
2403 + config WAN_AT_P4
2404 + bool "LLLL/W"
2405 +
2406 + config WAN_AT_P0
2407 + bool "W/LLLL"
2408 +endchoice
2409 +
2410 +config RALINK_VISTA_BASIC
2411 + bool 'Vista Basic Logo for IC+ 175C'
2412 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
2413 +
2414 +config ESW_DOUBLE_VLAN_TAG
2415 + bool
2416 + default y if RT_3052_ESW
2417 +
2418 +config RAETH_HAS_PORT4
2419 + bool "Port 4 Support"
2420 + depends on RAETH && RALINK_MT7620
2421 +choice
2422 + prompt "Target Mode"
2423 + depends on RAETH_HAS_PORT4
2424 + default P4_RGMII_TO_MAC_MODE
2425 +
2426 + config P4_MAC_TO_PHY_MODE
2427 + bool "Giga_Phy (RGMII)"
2428 + config GE_RGMII_MT7530_P0_AN
2429 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
2430 + config GE_RGMII_MT7530_P4_AN
2431 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
2432 + config P4_RGMII_TO_MAC_MODE
2433 + bool "Giga_SW/iNIC (RGMII)"
2434 + config P4_MII_TO_MAC_MODE
2435 + bool "External_CPU (MII_RvMII)"
2436 + config P4_RMII_TO_MAC_MODE
2437 + bool "External_CPU (RvMII_MII)"
2438 +endchoice
2439 +
2440 +config MAC_TO_GIGAPHY_MODE_ADDR2
2441 + hex "Port4 Phy Address"
2442 + default 0x4
2443 + depends on P4_MAC_TO_PHY_MODE
2444 +
2445 +config RAETH_HAS_PORT5
2446 + bool "Port 5 Support"
2447 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
2448 +choice
2449 + prompt "Target Mode"
2450 + depends on RAETH_HAS_PORT5
2451 + default P5_RGMII_TO_MAC_MODE
2452 +
2453 + config P5_MAC_TO_PHY_MODE
2454 + bool "Giga_Phy (RGMII)"
2455 + config P5_RGMII_TO_MAC_MODE
2456 + bool "Giga_SW/iNIC (RGMII)"
2457 + config P5_RGMII_TO_MT7530_MODE
2458 + bool "MT7530 Giga_SW (RGMII)"
2459 + depends on RALINK_MT7620
2460 + config P5_MII_TO_MAC_MODE
2461 + bool "External_CPU (MII_RvMII)"
2462 + config P5_RMII_TO_MAC_MODE
2463 + bool "External_CPU (RvMII_MII)"
2464 +endchoice
2465 +
2466 +config MAC_TO_GIGAPHY_MODE_ADDR
2467 + hex "GE1 Phy Address"
2468 + default 0x1F
2469 + depends on GE1_MII_AN || GE1_RGMII_AN
2470 +
2471 +config MAC_TO_GIGAPHY_MODE_ADDR
2472 + hex "Port5 Phy Address"
2473 + default 0x5
2474 + depends on P5_MAC_TO_PHY_MODE
2475 +
2476 +config RAETH_GMAC2
2477 + bool "GMAC2 Support"
2478 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
2479 +
2480 +choice
2481 + prompt "GMAC2 is connected to"
2482 + depends on RAETH_GMAC2
2483 + default GE2_RGMII_AN
2484 +
2485 +config GE2_MII_FORCE_100
2486 + bool "MII_FORCE_100 (10/100M Switch)"
2487 + depends on RAETH_GMAC2
2488 +
2489 +config GE2_MII_AN
2490 + bool "MII_AN (100Phy)"
2491 + depends on RAETH_GMAC2
2492 +
2493 +config GE2_RVMII_FORCE_100
2494 + bool "RvMII_FORCE_100 (CPU)"
2495 + depends on RAETH_GMAC2
2496 +
2497 +config GE2_RGMII_FORCE_1000
2498 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2499 + depends on RAETH_GMAC2
2500 + select RALINK_SPI
2501 +
2502 +config GE2_RGMII_AN
2503 + bool "RGMII_AN (GigaPhy)"
2504 + depends on RAETH_GMAC2
2505 +
2506 +config GE2_INTERNAL_GPHY
2507 + bool "Internal GigaPHY"
2508 + depends on RAETH_GMAC2
2509 + select LAN_WAN_SUPPORT
2510 +
2511 +endchoice
2512 +
2513 +config GE_RGMII_INTERNAL_P0_AN
2514 + bool
2515 + depends on GE2_INTERNAL_GPHY
2516 + default y if WAN_AT_P0
2517 +
2518 +config GE_RGMII_INTERNAL_P4_AN
2519 + bool
2520 + depends on GE2_INTERNAL_GPHY
2521 + default y if WAN_AT_P4
2522 +
2523 +config MAC_TO_GIGAPHY_MODE_ADDR2
2524 + hex
2525 + default 0 if GE_RGMII_INTERNAL_P0_AN
2526 + default 4 if GE_RGMII_INTERNAL_P4_AN
2527 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
2528 +
2529 +config MAC_TO_GIGAPHY_MODE_ADDR2
2530 + hex "GE2 Phy Address"
2531 + default 0x1E
2532 + depends on GE2_MII_AN || GE2_RGMII_AN
2533 +
2534 +#force 100M
2535 +config RAETH_ROUTER
2536 +bool
2537 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
2538 +
2539 +#force 1000M
2540 +config MAC_TO_MAC_MODE
2541 +bool
2542 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
2543 +depends on (RALINK_RT2880 || RALINK_RT3883)
2544 +
2545 +#AN
2546 +config GIGAPHY
2547 +bool
2548 +default y if GE1_RGMII_AN || GE2_RGMII_AN
2549 +
2550 +#AN
2551 +config 100PHY
2552 +bool
2553 +default y if GE1_MII_AN || GE2_MII_AN
2554 diff --git a/drivers/net/ethernet/raeth/Makefile b/drivers/net/ethernet/raeth/Makefile
2555 new file mode 100644
2556 index 0000000..94c19bd
2557 --- /dev/null
2558 +++ b/drivers/net/ethernet/raeth/Makefile
2559 @@ -0,0 +1,7 @@
2560 +obj-$(CONFIG_RAETH) += raeth.o
2561 +raeth-objs := ra_mac.o mii_mgr.o
2562 +raeth-objs += raether_pdma.o
2563 +EXTRA_CFLAGS += -DWORKQUEUE_BH
2564 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
2565 +
2566 +raeth-objs += raether.o
2567 diff --git a/drivers/net/ethernet/raeth/ethtool_readme.txt b/drivers/net/ethernet/raeth/ethtool_readme.txt
2568 new file mode 100644
2569 index 0000000..10e918b
2570 --- /dev/null
2571 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
2572 @@ -0,0 +1,44 @@
2573 +
2574 +Ethtool readme for selecting different PHY address.
2575 +
2576 +Before doing any ethtool command you should make sure the current PHY
2577 +address is expected. The default PHY address is 1(port 1).
2578 +
2579 +You can change current PHY address to X(0~4) by doing follow command:
2580 +# echo X > /proc/rt2880/gmac
2581 +
2582 +Ethtool command also would show the current PHY address as following.
2583 +
2584 +# ethtool eth2
2585 +Settings for eth2:
2586 + Supported ports: [ TP MII ]
2587 + Supported link modes: 10baseT/Half 10baseT/Full
2588 + 100baseT/Half 100baseT/Full
2589 + Supports auto-negotiation: Yes
2590 + Advertised link modes: 10baseT/Half 10baseT/Full
2591 + 100baseT/Half 100baseT/Full
2592 + Advertised auto-negotiation: No
2593 + Speed: 10Mb/s
2594 + Duplex: Full
2595 + Port: MII
2596 + PHYAD: 1
2597 + Transceiver: internal
2598 + Auto-negotiation: off
2599 + Current message level: 0x00000000 (0)
2600 + Link detected: no
2601 +
2602 +
2603 +The "PHYAD" field shows the current PHY address.
2604 +
2605 +
2606 +
2607 +Usage example
2608 +1) show port1 info
2609 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2610 +# ethtool eth2
2611 +
2612 +2) show port0 info
2613 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2614 +# ethtool eth2
2615 +
2616 +
2617 diff --git a/drivers/net/ethernet/raeth/mii_mgr.c b/drivers/net/ethernet/raeth/mii_mgr.c
2618 new file mode 100644
2619 index 0000000..3de0a74
2620 --- /dev/null
2621 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
2622 @@ -0,0 +1,166 @@
2623 +#include <linux/module.h>
2624 +#include <linux/version.h>
2625 +#include <linux/netdevice.h>
2626 +
2627 +#include <linux/kernel.h>
2628 +#include <linux/sched.h>
2629 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2630 +#include <asm/rt2880/rt_mmap.h>
2631 +#endif
2632 +
2633 +#include "ra2882ethreg.h"
2634 +#include "raether.h"
2635 +
2636 +
2637 +#define PHY_CONTROL_0 0x0004
2638 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2639 +#define enable_mdio(x)
2640 +
2641 +
2642 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2643 +{
2644 + u32 volatile status = 0;
2645 + u32 rc = 0;
2646 + unsigned long volatile t_start = jiffies;
2647 + u32 volatile data = 0;
2648 +
2649 + /* We enable mdio gpio purpose register, and disable it when exit. */
2650 + enable_mdio(1);
2651 +
2652 + // make sure previous read operation is complete
2653 + while (1) {
2654 + // 0 : Read/write operation complete
2655 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2656 + {
2657 + break;
2658 + }
2659 + else if (time_after(jiffies, t_start + 5*HZ)) {
2660 + enable_mdio(0);
2661 + printk("\n MDIO Read operation is ongoing !!\n");
2662 + return rc;
2663 + }
2664 + }
2665 +
2666 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
2667 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2668 + data |= (1<<31);
2669 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2670 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2671 +
2672 +
2673 + // make sure read operation is complete
2674 + t_start = jiffies;
2675 + while (1) {
2676 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
2677 + status = sysRegRead(MDIO_PHY_CONTROL_0);
2678 + *read_data = (u32)(status & 0x0000FFFF);
2679 +
2680 + enable_mdio(0);
2681 + return 1;
2682 + }
2683 + else if (time_after(jiffies, t_start+5*HZ)) {
2684 + enable_mdio(0);
2685 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
2686 + return 0;
2687 + }
2688 + }
2689 +}
2690 +
2691 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2692 +{
2693 + unsigned long volatile t_start=jiffies;
2694 + u32 volatile data;
2695 +
2696 + enable_mdio(1);
2697 +
2698 + // make sure previous write operation is complete
2699 + while(1) {
2700 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2701 + {
2702 + break;
2703 + }
2704 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2705 + enable_mdio(0);
2706 + printk("\n MDIO Write operation ongoing\n");
2707 + return 0;
2708 + }
2709 + }
2710 + /*add 1 us delay to make sequencial write more robus*/
2711 + udelay(1);
2712 +
2713 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
2714 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2715 + data |= (1<<31);
2716 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
2717 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2718 +
2719 + t_start = jiffies;
2720 +
2721 + // make sure write operation is complete
2722 + while (1) {
2723 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
2724 + {
2725 + enable_mdio(0);
2726 + return 1;
2727 + }
2728 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2729 + enable_mdio(0);
2730 + printk("\n MDIO Write operation Time Out\n");
2731 + return 0;
2732 + }
2733 + }
2734 +}
2735 +
2736 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2737 +{
2738 + u32 low_word;
2739 + u32 high_word;
2740 + if(phy_addr==31)
2741 + {
2742 + //phase1: write page address phase
2743 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
2744 + //phase2: write address & read low word phase
2745 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
2746 + //phase3: write address & read high word phase
2747 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
2748 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
2749 + return 1;
2750 + }
2751 + }
2752 + }
2753 + } else
2754 + {
2755 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
2756 + return 1;
2757 + }
2758 + }
2759 +
2760 + return 0;
2761 +}
2762 +
2763 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2764 +{
2765 + if(phy_addr == 31)
2766 + {
2767 + //phase1: write page address phase
2768 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
2769 + //phase2: write address & read low word phase
2770 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
2771 + //phase3: write address & read high word phase
2772 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
2773 + return 1;
2774 + }
2775 + }
2776 + }
2777 + } else
2778 + {
2779 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
2780 + return 1;
2781 + }
2782 + }
2783 +
2784 + return 0;
2785 +}
2786 +
2787 +EXPORT_SYMBOL(mii_mgr_write);
2788 +EXPORT_SYMBOL(mii_mgr_read);
2789 diff --git a/drivers/net/ethernet/raeth/ra2882ethreg.h b/drivers/net/ethernet/raeth/ra2882ethreg.h
2790 new file mode 100644
2791 index 0000000..05b789e
2792 --- /dev/null
2793 +++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
2794 @@ -0,0 +1,1268 @@
2795 +#ifndef RA2882ETHREG_H
2796 +#define RA2882ETHREG_H
2797 +
2798 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
2799 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
2800 +
2801 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2802 +#include <asm/rt2880/rt_mmap.h>
2803 +#endif
2804 +#include "raether.h"
2805 +
2806 +#ifdef WORKQUEUE_BH
2807 +#include <linux/workqueue.h>
2808 +#endif // WORKQUEUE_BH //
2809 +#ifdef CONFIG_RAETH_LRO
2810 +#include <linux/inet_lro.h>
2811 +#endif
2812 +
2813 +#define MAX_PACKET_SIZE 1514
2814 +#define MIN_PACKET_SIZE 60
2815 +
2816 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
2817 +
2818 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
2819 +#define BIT(x) ((1 << x))
2820 +#endif
2821 +#define ETHER_ADDR_LEN 6
2822 +
2823 +/* Phy Vender ID list */
2824 +
2825 +#define EV_ICPLUS_PHY_ID0 0x0243
2826 +#define EV_ICPLUS_PHY_ID1 0x0D90
2827 +#define EV_MARVELL_PHY_ID0 0x0141
2828 +#define EV_MARVELL_PHY_ID1 0x0CC2
2829 +#define EV_VTSS_PHY_ID0 0x0007
2830 +#define EV_VTSS_PHY_ID1 0x0421
2831 +
2832 +/*
2833 + FE_INT_STATUS
2834 +*/
2835 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2836 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2837 +
2838 +#define RX_COHERENT BIT(31)
2839 +#define RX_DLY_INT BIT(30)
2840 +#define TX_COHERENT BIT(29)
2841 +#define TX_DLY_INT BIT(28)
2842 +
2843 +#define RX_DONE_INT1 BIT(17)
2844 +#define RX_DONE_INT0 BIT(16)
2845 +
2846 +#define TX_DONE_INT3 BIT(3)
2847 +#define TX_DONE_INT2 BIT(2)
2848 +#define TX_DONE_INT1 BIT(1)
2849 +#define TX_DONE_INT0 BIT(0)
2850 +
2851 +#if defined (CONFIG_RALINK_MT7621)
2852 +#define RLS_COHERENT BIT(29)
2853 +#define RLS_DLY_INT BIT(28)
2854 +#define RLS_DONE_INT BIT(0)
2855 +#endif
2856 +
2857 +#else
2858 +//#define CNT_PPE_AF BIT(31)
2859 +//#define CNT_GDM_AF BIT(29)
2860 +#define PSE_P2_FC BIT(26)
2861 +#define GDM_CRC_DROP BIT(25)
2862 +#define PSE_BUF_DROP BIT(24)
2863 +#define GDM_OTHER_DROP BIT(23)
2864 +#define PSE_P1_FC BIT(22)
2865 +#define PSE_P0_FC BIT(21)
2866 +#define PSE_FQ_EMPTY BIT(20)
2867 +#define GE1_STA_CHG BIT(18)
2868 +#define TX_COHERENT BIT(17)
2869 +#define RX_COHERENT BIT(16)
2870 +
2871 +#define TX_DONE_INT3 BIT(11)
2872 +#define TX_DONE_INT2 BIT(10)
2873 +#define TX_DONE_INT1 BIT(9)
2874 +#define TX_DONE_INT0 BIT(8)
2875 +#define RX_DONE_INT1 RX_DONE_INT0
2876 +#define RX_DONE_INT0 BIT(2)
2877 +#define TX_DLY_INT BIT(1)
2878 +#define RX_DLY_INT BIT(0)
2879 +#endif
2880 +
2881 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
2882 + TX_DONE_INT1 | TX_DONE_INT0 | \
2883 + RX_DONE_INT0 )
2884 +
2885 +#if defined (CONFIG_RALINK_MT7621)
2886 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
2887 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
2888 +
2889 +#define NUM_QDMA_PAGE 256
2890 +#define QDMA_PAGE_SIZE 2048
2891 +#endif
2892 +/*
2893 + * SW_INT_STATUS
2894 + */
2895 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2896 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
2897 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
2898 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
2899 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
2900 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
2901 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
2902 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
2903 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
2904 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
2905 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
2906 +#define PORT_ST_CHG BIT(26) //Port status change
2907 +#define UNSECURED_ALERT BIT(27) //Intruder alert
2908 +#define ABNORMAL_ALERT BIT(28) //Abnormal
2909 +
2910 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
2911 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
2912 +#define ESW_INT_ALL (PORT_ST_CHG)
2913 +
2914 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2915 + defined (CONFIG_RALINK_MT7620)
2916 +#define MIB_INT BIT(25)
2917 +#define ACL_INT BIT(24)
2918 +#define P5_LINK_CH BIT(5)
2919 +#define P4_LINK_CH BIT(4)
2920 +#define P3_LINK_CH BIT(3)
2921 +#define P2_LINK_CH BIT(2)
2922 +#define P1_LINK_CH BIT(1)
2923 +#define P0_LINK_CH BIT(0)
2924 +
2925 +#define RX_GOCT_CNT BIT(4)
2926 +#define RX_GOOD_CNT BIT(6)
2927 +#define TX_GOCT_CNT BIT(17)
2928 +#define TX_GOOD_CNT BIT(19)
2929 +
2930 +#define MSK_RX_GOCT_CNT BIT(4)
2931 +#define MSK_RX_GOOD_CNT BIT(6)
2932 +#define MSK_TX_GOCT_CNT BIT(17)
2933 +#define MSK_TX_GOOD_CNT BIT(19)
2934 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
2935 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
2936 +
2937 +
2938 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
2939 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
2940 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
2941 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
2942 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
2943 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
2944 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
2945 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
2946 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
2947 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
2948 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
2949 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
2950 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
2951 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
2952 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
2953 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
2954 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
2955 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
2956 +
2957 +#if defined (CONFIG_RALINK_MT7620)
2958 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
2959 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
2960 +#endif
2961 +
2962 +
2963 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
2964 +
2965 +#elif defined (CONFIG_RALINK_MT7621)
2966 +
2967 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
2968 +
2969 +#define P5_LINK_CH BIT(5)
2970 +#define P4_LINK_CH BIT(4)
2971 +#define P3_LINK_CH BIT(3)
2972 +#define P2_LINK_CH BIT(2)
2973 +#define P1_LINK_CH BIT(1)
2974 +#define P0_LINK_CH BIT(0)
2975 +
2976 +
2977 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
2978 +
2979 +#define RX_BUF_ALLOC_SIZE 2000
2980 +#define FASTPATH_HEADROOM 64
2981 +
2982 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
2983 +
2984 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
2985 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
2986 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
2987 +
2988 +#ifdef CONFIG_PSEUDO_SUPPORT
2989 +typedef struct _PSEUDO_ADAPTER {
2990 + struct net_device *RaethDev;
2991 + struct net_device *PseudoDev;
2992 + struct net_device_stats stat;
2993 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
2994 + struct mii_if_info mii_info;
2995 +#endif
2996 +
2997 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
2998 +
2999 +#define MAX_PSEUDO_ENTRY 1
3000 +#endif
3001 +
3002 +
3003 +
3004 +/* Register Categories Definition */
3005 +#define RAFRAMEENGINE_OFFSET 0x0000
3006 +#define RAGDMA_OFFSET 0x0020
3007 +#define RAPSE_OFFSET 0x0040
3008 +#define RAGDMA2_OFFSET 0x0060
3009 +#define RACDMA_OFFSET 0x0080
3010 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3011 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3012 +
3013 +#define RAPDMA_OFFSET 0x0800
3014 +#define SDM_OFFSET 0x0C00
3015 +#else
3016 +#define RAPDMA_OFFSET 0x0100
3017 +#endif
3018 +#define RAPPE_OFFSET 0x0200
3019 +#define RACMTABLE_OFFSET 0x0400
3020 +#define RAPOLICYTABLE_OFFSET 0x1000
3021 +
3022 +
3023 +/* Register Map Detail */
3024 +/* RT3883 */
3025 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
3026 +
3027 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3028 +
3029 +/* 1. PDMA */
3030 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
3031 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
3032 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
3033 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
3034 +
3035 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
3036 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
3037 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
3038 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
3039 +
3040 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
3041 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
3042 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
3043 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
3044 +
3045 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
3046 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
3047 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
3048 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
3049 +
3050 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
3051 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3052 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3053 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3054 +
3055 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3056 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3057 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3058 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3059 +
3060 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3061 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3062 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3063 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3064 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3065 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3066 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3067 +#define FE_INT_STATUS (INT_STATUS)
3068 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3069 +#define FE_INT_ENABLE (INT_MASK)
3070 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3071 +#define PDMA_SCH_CFG (PDMA_WRR)
3072 +
3073 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
3074 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
3075 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
3076 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
3077 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
3078 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3079 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3080 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3081 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3082 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3083 +
3084 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3085 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3086 +
3087 +/* Old FE with New PDMA */
3088 +#define PDMA_RELATED 0x0800
3089 +/* 1. PDMA */
3090 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3091 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3092 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3093 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3094 +
3095 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3096 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3097 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3098 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3099 +
3100 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3101 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3102 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3103 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3104 +
3105 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3106 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3107 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3108 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3109 +
3110 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3111 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3112 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3113 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3114 +
3115 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3116 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3117 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3118 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3119 +
3120 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3121 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3122 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3123 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3124 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3125 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3126 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3127 +#define FE_INT_STATUS (INT_STATUS)
3128 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3129 +#define FE_INT_ENABLE (INT_MASK)
3130 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3131 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3132 +
3133 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
3134 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
3135 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
3136 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
3137 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
3138 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
3139 +
3140 +#if defined (CONFIG_RALINK_MT7620)
3141 +#define GDMA1_RELATED 0x0600
3142 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3143 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3144 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3145 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3146 +#elif defined (CONFIG_RALINK_MT7621)
3147 +#define GDMA1_RELATED 0x0500
3148 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3149 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3150 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3151 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3152 +
3153 +#define GDMA2_RELATED 0x1500
3154 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3155 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3156 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3157 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3158 +#else
3159 +#define GDMA1_RELATED 0x0020
3160 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3161 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3162 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3163 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3164 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
3165 +
3166 +#define GDMA2_RELATED 0x0060
3167 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3168 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3169 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3170 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3171 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
3172 +#endif
3173 +
3174 +#if defined (CONFIG_RALINK_MT7620)
3175 +#define PSE_RELATED 0x0500
3176 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3177 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3178 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3179 +#else
3180 +#define PSE_RELATED 0x0040
3181 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3182 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3183 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3184 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
3185 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
3186 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
3187 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
3188 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
3189 +#endif
3190 +
3191 +
3192 +#if defined (CONFIG_RALINK_MT7620)
3193 +#define CDMA_RELATED 0x0400
3194 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3195 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
3196 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
3197 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
3198 +#elif defined (CONFIG_RALINK_MT7621)
3199 +#define CDMA_RELATED 0x0400
3200 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
3201 +#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3202 +#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3203 +#else
3204 +#define CDMA_RELATED 0x0080
3205 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3206 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3207 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
3208 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
3209 +#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
3210 +#endif
3211 +
3212 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
3213 +
3214 +
3215 +#if defined (CONFIG_RALINK_MT7621)
3216 +/*kurtis: add QDMA define*/
3217 +
3218 +#define CLK_CFG_0