ralink: a few 3.14 related fixes
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.14 / 0036-NET-add-mt7621-ethernet-driver.patch
1 From 810c2afe0c7e1be9352ad512b337110b100bfe3a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 08:51:14 +0000
4 Subject: [PATCH 36/57] NET: add mt7621 ethernet driver
5
6 ---
7 arch/mips/include/asm/rt2880/board-custom.h | 153 +++
8 arch/mips/include/asm/rt2880/eureka_ep430.h | 204 ++++
9 arch/mips/include/asm/rt2880/generic.h | 42 +
10 arch/mips/include/asm/rt2880/lm.h | 32 +
11 arch/mips/include/asm/rt2880/prom.h | 50 +
12 arch/mips/include/asm/rt2880/rt_mmap.h | 796 ++++++++++++++++
13 arch/mips/include/asm/rt2880/serial_rt2880.h | 443 +++++++++
14 arch/mips/include/asm/rt2880/sizes.h | 52 +
15 arch/mips/include/asm/rt2880/surfboard.h | 70 ++
16 arch/mips/include/asm/rt2880/surfboardint.h | 190 ++++
17 arch/mips/include/asm/rt2880/war.h | 25 +
18 drivers/net/ethernet/Kconfig | 1 +
19 drivers/net/ethernet/Makefile | 1 +
20 drivers/net/ethernet/raeth/Kconfig | 344 +++++++
21 drivers/net/ethernet/raeth/Makefile | 7 +
22 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
23 drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
24 drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
25 drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
26 drivers/net/ethernet/raeth/ra_mac.c | 98 ++
27 drivers/net/ethernet/raeth/ra_mac.h | 35 +
28 drivers/net/ethernet/raeth/raether.c | 693 ++++++++++++++
29 drivers/net/ethernet/raeth/raether.h | 92 ++
30 drivers/net/ethernet/raeth/raether_pdma.c | 212 +++++
31 drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
32 25 files changed, 5915 insertions(+)
33 create mode 100644 arch/mips/include/asm/rt2880/board-custom.h
34 create mode 100644 arch/mips/include/asm/rt2880/eureka_ep430.h
35 create mode 100644 arch/mips/include/asm/rt2880/generic.h
36 create mode 100644 arch/mips/include/asm/rt2880/lm.h
37 create mode 100644 arch/mips/include/asm/rt2880/prom.h
38 create mode 100644 arch/mips/include/asm/rt2880/rt_mmap.h
39 create mode 100644 arch/mips/include/asm/rt2880/serial_rt2880.h
40 create mode 100644 arch/mips/include/asm/rt2880/sizes.h
41 create mode 100644 arch/mips/include/asm/rt2880/surfboard.h
42 create mode 100644 arch/mips/include/asm/rt2880/surfboardint.h
43 create mode 100644 arch/mips/include/asm/rt2880/war.h
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
47 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
48 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
49 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
50 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
51 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
52 create mode 100644 drivers/net/ethernet/raeth/raether.c
53 create mode 100644 drivers/net/ethernet/raeth/raether.h
54 create mode 100644 drivers/net/ethernet/raeth/raether_pdma.c
55 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
56
57 Index: linux-3.14.16/arch/mips/include/asm/rt2880/board-custom.h
58 ===================================================================
59 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
60 +++ linux-3.14.16/arch/mips/include/asm/rt2880/board-custom.h 2014-08-24 15:51:48.530654066 +0200
61 @@ -0,0 +1,153 @@
62 +/* Copyright Statement:
63 + *
64 + * This software/firmware and related documentation ("MediaTek Software") are
65 + * protected under relevant copyright laws. The information contained herein
66 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
67 + * Without the prior written permission of MediaTek inc. and/or its licensors,
68 + * any reproduction, modification, use or disclosure of MediaTek Software,
69 + * and information contained herein, in whole or in part, shall be strictly prohibited.
70 + */
71 +/* MediaTek Inc. (C) 2010. All rights reserved.
72 + *
73 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
74 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
75 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
76 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
77 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
78 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
79 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
80 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
81 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
82 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
83 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
84 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
85 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
86 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
87 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
88 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
89 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
90 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
91 + *
92 + * The following software/firmware and/or related documentation ("MediaTek Software")
93 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
94 + * applicable license agreements with MediaTek Inc.
95 + */
96 +
97 +#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
98 +#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
99 +
100 +#include <linux/autoconf.h>
101 +
102 +/*=======================================================================*/
103 +/* MT6575 SD */
104 +/*=======================================================================*/
105 +#ifdef MTK_EMMC_SUPPORT
106 +#define CFG_DEV_MSDC0
107 +#endif
108 +#define CFG_DEV_MSDC1
109 +#define CFG_DEV_MSDC2
110 +#define CFG_DEV_MSDC3
111 +#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
112 +/*
113 +SDIO slot index number used by connectivity combo chip:
114 +0: invalid (used by memory card)
115 +1: MSDC1
116 +2: MSDC2
117 +*/
118 +#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
119 +#else
120 +#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
121 +#endif
122 +
123 +#if 0 /* FIXME. */
124 +/*=======================================================================*/
125 +/* MT6575 UART */
126 +/*=======================================================================*/
127 +#define CFG_DEV_UART1
128 +#define CFG_DEV_UART2
129 +#define CFG_DEV_UART3
130 +#define CFG_DEV_UART4
131 +
132 +#define CFG_UART_PORTS (4)
133 +
134 +/*=======================================================================*/
135 +/* MT6575 I2C */
136 +/*=======================================================================*/
137 +#define CFG_DEV_I2C
138 +//#define CFG_I2C_HIGH_SPEED_MODE
139 +//#define CFG_I2C_DMA_MODE
140 +
141 +/*=======================================================================*/
142 +/* MT6575 ADB */
143 +/*=======================================================================*/
144 +#define ADB_SERIAL "E1K"
145 +
146 +#endif
147 +
148 +/*=======================================================================*/
149 +/* MT6575 NAND FLASH */
150 +/*=======================================================================*/
151 +#if 0
152 +#define RAMDOM_READ 1<<0
153 +#define CACHE_READ 1<<1
154 +/*******************************************************************************
155 + * NFI & ECC Configuration
156 + *******************************************************************************/
157 +typedef struct
158 +{
159 + u16 id; //deviceid+menuid
160 + u8 addr_cycle;
161 + u8 iowidth;
162 + u16 totalsize;
163 + u16 blocksize;
164 + u16 pagesize;
165 + u32 timmingsetting;
166 + char devciename[14];
167 + u32 advancedmode; //
168 +}flashdev_info,*pflashdev_info;
169 +
170 +static const flashdev_info g_FlashTable[]={
171 + //micro
172 + {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
173 + {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
174 + {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
175 + {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
176 + {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
177 + //samsung
178 + {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
179 + {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
180 + {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
181 + {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
182 + {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
183 + //hynix
184 + {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
185 + {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
186 + {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
187 + {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
188 + //toshiba
189 + {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
190 + {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
191 + {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
192 + {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
193 + //st-micro
194 + {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
195 +
196 + // elpida
197 + {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
198 + {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
199 +};
200 +#endif
201 +
202 +
203 +#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
204 +
205 +//uboot only support 1 cs
206 +#define NFI_CS_NUM (2)
207 +#define NFI_DEFAULT_CS (0)
208 +
209 +#define USE_AHB_MODE (1)
210 +
211 +#define PLATFORM_EVB (1)
212 +
213 +#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
214 +
215 Index: linux-3.14.16/arch/mips/include/asm/rt2880/eureka_ep430.h
216 ===================================================================
217 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
218 +++ linux-3.14.16/arch/mips/include/asm/rt2880/eureka_ep430.h 2014-08-24 15:51:48.530654066 +0200
219 @@ -0,0 +1,204 @@
220 +/**************************************************************************
221 + *
222 + * This program is free software; you can redistribute it and/or modify it
223 + * under the terms of the GNU General Public License as published by the
224 + * Free Software Foundation; either version 2 of the License, or (at your
225 + * option) any later version.
226 + *
227 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
228 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
229 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
230 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
231 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
232 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
233 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
234 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
235 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
236 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
237 + *
238 + * You should have received a copy of the GNU General Public License along
239 + * with this program; if not, write to the Free Software Foundation, Inc.,
240 + * 675 Mass Ave, Cambridge, MA 02139, USA.
241 + *
242 + *
243 + **************************************************************************
244 + */
245 +
246 +#ifndef _EUREKA_EP430_H
247 +#define _EUREKA_EP430_H
248 +
249 +
250 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
251 +#include <asm/byteorder.h> /* for cpu_to_le32() */
252 +#include <asm/mach-ralink/rt_mmap.h>
253 +
254 +
255 +/*
256 + * Because of an error/peculiarity in the Galileo chip, we need to swap the
257 + * bytes when running bigendian.
258 + */
259 +
260 +#define MV_WRITE(ofs, data) \
261 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
262 +#define MV_READ(ofs, data) \
263 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
264 +#define MV_READ_DATA(ofs) \
265 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
266 +
267 +#define MV_WRITE_16(ofs, data) \
268 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
269 +#define MV_READ_16(ofs, data) \
270 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
271 +
272 +#define MV_WRITE_8(ofs, data) \
273 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
274 +#define MV_READ_8(ofs, data) \
275 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
276 +
277 +#define MV_SET_REG_BITS(ofs,bits) \
278 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
279 +#define MV_RESET_REG_BITS(ofs,bits) \
280 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
281 +
282 +#define RALINK_PCI_CONFIG_ADDR 0x20
283 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
284 +
285 +#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
286 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
287 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
288 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
289 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
290 +#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
291 +#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
292 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
293 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
294 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
295 +#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
296 +#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
297 +#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
298 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
299 +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
300 +
301 +#elif defined(CONFIG_RALINK_RT3883)
302 +
303 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
304 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
305 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
306 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
307 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
308 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
309 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
310 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
311 +
312 +/*
313 +PCI0 --> PCI
314 +PCI1 --> PCIe
315 +*/
316 +#define RT3883_PCI_OFFSET 0x1000
317 +#define RT3883_PCIE_OFFSET 0x2000
318 +
319 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
320 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
321 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
322 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
323 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
324 +
325 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
326 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
327 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
328 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
329 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
330 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
331 +
332 +#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
333 +
334 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
335 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
336 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
337 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
338 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
339 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
340 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
341 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
342 +
343 +/*
344 +PCI0 --> PCIe 0
345 +PCI1 --> PCIe 1
346 +*/
347 +#define RT6855_PCIE0_OFFSET 0x2000
348 +#define RT6855_PCIE1_OFFSET 0x3000
349 +
350 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
351 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
352 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
353 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
354 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
355 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
356 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
357 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
358 +
359 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
360 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
361 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
362 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
363 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
364 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
365 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
366 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
367 +
368 +#elif defined (CONFIG_RALINK_MT7621)
369 +
370 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
371 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
372 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
373 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
374 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
375 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
376 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
377 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
378 +
379 +/*
380 +PCI0 --> PCIe 0
381 +PCI1 --> PCIe 1
382 +PCI2 --> PCIe 2
383 +*/
384 +#define RT6855_PCIE0_OFFSET 0x2000
385 +#define RT6855_PCIE1_OFFSET 0x3000
386 +#define RT6855_PCIE2_OFFSET 0x4000
387 +
388 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
389 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
390 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
391 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
392 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
393 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
394 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
395 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
396 +
397 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
398 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
399 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
400 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
401 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
402 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
403 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
404 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
405 +
406 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
407 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
408 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
409 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
410 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
411 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
412 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
413 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
414 +
415 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
416 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
417 +
418 +#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
419 +#else
420 +#error "undefined in PCI"
421 +#endif
422 +
423 +#endif
424 Index: linux-3.14.16/arch/mips/include/asm/rt2880/generic.h
425 ===================================================================
426 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
427 +++ linux-3.14.16/arch/mips/include/asm/rt2880/generic.h 2014-08-24 15:51:48.530654066 +0200
428 @@ -0,0 +1,42 @@
429 +/*
430 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
431 + *
432 + * This program is free software; you can distribute it and/or modify it
433 + * under the terms of the GNU General Public License (Version 2) as
434 + * published by the Free Software Foundation.
435 + *
436 + * This program is distributed in the hope it will be useful, but WITHOUT
437 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
438 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
439 + * for more details.
440 + *
441 + * You should have received a copy of the GNU General Public License along
442 + * with this program; if not, write to the Free Software Foundation, Inc.,
443 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
444 + *
445 + * Defines of the Palmchip boards specific address-MAP, registers, etc.
446 + */
447 +#ifndef __ASM_SURFBOARD_GENERIC_H
448 +#define __ASM_SURFBOARD_GENERIC_H
449 +
450 +#include <asm/addrspace.h>
451 +#include <asm/byteorder.h>
452 +#include <asm/mach-ralink/rt_mmap.h>
453 +
454 +/*
455 + * Reset register.
456 + */
457 +#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
458 +#define GORESET (0x1)
459 +
460 +/*
461 + * Power-off register
462 + */
463 +#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
464 +#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
465 +#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
466 +#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
467 +#define POWEROFF (0x0) /* drive low */
468 +
469 +
470 +#endif /* __ASM_SURFBOARD_GENERIC_H */
471 Index: linux-3.14.16/arch/mips/include/asm/rt2880/lm.h
472 ===================================================================
473 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
474 +++ linux-3.14.16/arch/mips/include/asm/rt2880/lm.h 2014-08-24 15:51:48.530654066 +0200
475 @@ -0,0 +1,32 @@
476 +#include <linux/version.h>
477 +
478 +struct lm_device {
479 + struct device dev;
480 + struct resource resource;
481 + unsigned int irq;
482 + unsigned int id;
483 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
484 + void *lm_drvdata;
485 +#endif
486 +};
487 +
488 +struct lm_driver {
489 + struct device_driver drv;
490 + int (*probe)(struct lm_device *);
491 + void (*remove)(struct lm_device *);
492 + int (*suspend)(struct lm_device *, u32);
493 + int (*resume)(struct lm_device *);
494 +};
495 +
496 +int lm_driver_register(struct lm_driver *drv);
497 +void lm_driver_unregister(struct lm_driver *drv);
498 +
499 +int lm_device_register(struct lm_device *dev);
500 +
501 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
502 +# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
503 +# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
504 +#else
505 +# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
506 +# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
507 +#endif
508 Index: linux-3.14.16/arch/mips/include/asm/rt2880/prom.h
509 ===================================================================
510 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
511 +++ linux-3.14.16/arch/mips/include/asm/rt2880/prom.h 2014-08-24 15:51:48.530654066 +0200
512 @@ -0,0 +1,50 @@
513 +/*
514 + * Carsten Langgaard, carstenl@mips.com
515 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
516 + *
517 + * ########################################################################
518 + *
519 + * This program is free software; you can distribute it and/or modify it
520 + * under the terms of the GNU General Public License (Version 2) as
521 + * published by the Free Software Foundation.
522 + *
523 + * This program is distributed in the hope it will be useful, but WITHOUT
524 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
525 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
526 + * for more details.
527 + *
528 + * You should have received a copy of the GNU General Public License along
529 + * with this program; if not, write to the Free Software Foundation, Inc.,
530 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
531 + *
532 + * ########################################################################
533 + *
534 + * MIPS boards bootprom interface for the Linux kernel.
535 + *
536 + */
537 +
538 +#ifndef _MIPS_PROM_H
539 +#define _MIPS_PROM_H
540 +
541 +extern char *prom_getcmdline(void);
542 +extern char *prom_getenv(char *name);
543 +extern void setup_prom_printf(int tty_no);
544 +extern void prom_setup_printf(int tty_no);
545 +extern void prom_printf(char *fmt, ...);
546 +extern void prom_init_cmdline(void);
547 +extern void prom_meminit(void);
548 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
549 +extern void prom_free_prom_memory (void);
550 +extern void mips_display_message(const char *str);
551 +extern void mips_display_word(unsigned int num);
552 +extern int get_ethernet_addr(char *ethernet_addr);
553 +
554 +/* Memory descriptor management. */
555 +#define PROM_MAX_PMEMBLOCKS 32
556 +struct prom_pmemblock {
557 + unsigned long base; /* Within KSEG0. */
558 + unsigned int size; /* In bytes. */
559 + unsigned int type; /* free or prom memory */
560 +};
561 +
562 +#endif /* !(_MIPS_PROM_H) */
563 Index: linux-3.14.16/arch/mips/include/asm/rt2880/rt_mmap.h
564 ===================================================================
565 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
566 +++ linux-3.14.16/arch/mips/include/asm/rt2880/rt_mmap.h 2014-08-24 15:51:48.530654066 +0200
567 @@ -0,0 +1,796 @@
568 +/**************************************************************************
569 + *
570 + * BRIEF MODULE DESCRIPTION
571 + * register definition for Ralink RT-series SoC
572 + *
573 + * Copyright 2007 Ralink Inc.
574 + *
575 + * This program is free software; you can redistribute it and/or modify it
576 + * under the terms of the GNU General Public License as published by the
577 + * Free Software Foundation; either version 2 of the License, or (at your
578 + * option) any later version.
579 + *
580 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
581 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
582 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
583 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
584 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
585 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
586 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
587 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
588 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
589 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
590 + *
591 + * You should have received a copy of the GNU General Public License along
592 + * with this program; if not, write to the Free Software Foundation, Inc.,
593 + * 675 Mass Ave, Cambridge, MA 02139, USA.
594 + *
595 + *
596 + **************************************************************************
597 + */
598 +
599 +#ifndef __RALINK_MMAP__
600 +#define __RALINK_MMAP__
601 +
602 +#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
603 +
604 +#define RALINK_SYSCTL_BASE 0xA0300000
605 +#define RALINK_TIMER_BASE 0xA0300100
606 +#define RALINK_INTCL_BASE 0xA0300200
607 +#define RALINK_MEMCTRL_BASE 0xA0300300
608 +#define RALINK_UART_BASE 0xA0300500
609 +#define RALINK_PIO_BASE 0xA0300600
610 +#define RALINK_I2C_BASE 0xA0300900
611 +#define RALINK_SPI_BASE 0xA0300B00
612 +#define RALINK_UART_LITE_BASE 0xA0300C00
613 +#define RALINK_FRAME_ENGINE_BASE 0xA0310000
614 +#define RALINK_EMBEDD_ROM_BASE 0xA0400000
615 +#define RALINK_PCI_BASE 0xA0500000
616 +#define RALINK_11N_MAC_BASE 0xA0600000
617 +
618 +//Interrupt Controller
619 +#define RALINK_INTCTL_TIMER0 (1<<0)
620 +#define RALINK_INTCTL_WDTIMER (1<<1)
621 +#define RALINK_INTCTL_UART (1<<2)
622 +#define RALINK_INTCTL_PIO (1<<3)
623 +#define RALINK_INTCTL_PCM (1<<4)
624 +#define RALINK_INTCTL_UARTLITE (1<<8)
625 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
626 +
627 +//Reset Control Register
628 +#define RALINK_TIMER_RST (1<<1)
629 +#define RALINK_INTC_RST (1<<2)
630 +#define RALINK_MC_RST (1<<3)
631 +#define RALINK_CPU_RST (1<<4)
632 +#define RALINK_UART_RST (1<<5)
633 +#define RALINK_PIO_RST (1<<6)
634 +#define RALINK_I2C_RST (1<<9)
635 +#define RALINK_SPI_RST (1<<11)
636 +#define RALINK_UART2_RST (1<<12)
637 +#define RALINK_PCI_RST (1<<16)
638 +#define RALINK_2860_RST (1<<17)
639 +#define RALINK_FE_RST (1<<18)
640 +#define RALINK_PCM_RST (1<<19)
641 +
642 +
643 +#elif defined (CONFIG_RALINK_RT2880_MP)
644 +
645 +#define RALINK_SYSCTL_BASE 0xA0300000
646 +#define RALINK_TIMER_BASE 0xA0300100
647 +#define RALINK_INTCL_BASE 0xA0300200
648 +#define RALINK_MEMCTRL_BASE 0xA0300300
649 +#define RALINK_UART_BASE 0xA0300500
650 +#define RALINK_PIO_BASE 0xA0300600
651 +#define RALINK_I2C_BASE 0xA0300900
652 +#define RALINK_SPI_BASE 0xA0300B00
653 +#define RALINK_UART_LITE_BASE 0x00300C00
654 +#define RALINK_FRAME_ENGINE_BASE 0xA0400000
655 +#define RALINK_EMBEDD_ROM_BASE 0xA0410000
656 +#define RALINK_PCI_BASE 0xA0440000
657 +#define RALINK_11N_MAC_BASE 0xA0480000
658 +
659 +//Interrupt Controller
660 +#define RALINK_INTCTL_TIMER0 (1<<0)
661 +#define RALINK_INTCTL_WDTIMER (1<<1)
662 +#define RALINK_INTCTL_UART (1<<2)
663 +#define RALINK_INTCTL_PIO (1<<3)
664 +#define RALINK_INTCTL_PCM (1<<4)
665 +#define RALINK_INTCTL_UARTLITE (1<<8)
666 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
667 +
668 +//Reset Control Register
669 +#define RALINK_TIMER_RST (1<<1)
670 +#define RALINK_INTC_RST (1<<2)
671 +#define RALINK_MC_RST (1<<3)
672 +#define RALINK_CPU_RST (1<<4)
673 +#define RALINK_UART_RST (1<<5)
674 +#define RALINK_PIO_RST (1<<6)
675 +#define RALINK_I2C_RST (1<<9)
676 +#define RALINK_SPI_RST (1<<11)
677 +#define RALINK_UART2_RST (1<<12)
678 +#define RALINK_PCI_RST (1<<16)
679 +#define RALINK_2860_RST (1<<17)
680 +#define RALINK_FE_RST (1<<18)
681 +#define RALINK_PCM_RST (1<<19)
682 +
683 +#elif defined (CONFIG_RALINK_RT3052)
684 +
685 +#define RALINK_SYSCTL_BASE 0xB0000000
686 +#define RALINK_TIMER_BASE 0xB0000100
687 +#define RALINK_INTCL_BASE 0xB0000200
688 +#define RALINK_MEMCTRL_BASE 0xB0000300
689 +#define RALINK_PCM_BASE 0xB0000400
690 +#define RALINK_UART_BASE 0x10000500
691 +#define RALINK_PIO_BASE 0xB0000600
692 +#define RALINK_GDMA_BASE 0xB0000700
693 +#define RALINK_NAND_CTRL_BASE 0xB0000800
694 +#define RALINK_I2C_BASE 0xB0000900
695 +#define RALINK_I2S_BASE 0xB0000A00
696 +#define RALINK_SPI_BASE 0xB0000B00
697 +#define RALINK_UART_LITE_BASE 0x10000C00
698 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
699 +#define RALINK_ETH_SW_BASE 0xB0110000
700 +#define RALINK_11N_MAC_BASE 0xB0180000
701 +#define RALINK_USB_OTG_BASE 0x101C0000
702 +
703 +//Interrupt Controller
704 +#define RALINK_INTCTL_SYSCTL (1<<0)
705 +#define RALINK_INTCTL_TIMER0 (1<<1)
706 +#define RALINK_INTCTL_WDTIMER (1<<2)
707 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
708 +#define RALINK_INTCTL_PCM (1<<4)
709 +#define RALINK_INTCTL_UART (1<<5)
710 +#define RALINK_INTCTL_PIO (1<<6)
711 +#define RALINK_INTCTL_DMA (1<<7)
712 +#define RALINK_INTCTL_NAND (1<<8)
713 +#define RALINK_INTCTL_PC (1<<9)
714 +#define RALINK_INTCTL_I2S (1<<10)
715 +#define RALINK_INTCTL_UARTLITE (1<<12)
716 +#define RALINK_INTCTL_ESW (1<<17)
717 +#define RALINK_INTCTL_OTG (1<<18)
718 +#define RALINK_INTCTL_OTG_IRQN 18
719 +#define RALINK_INTCTL_GLOBAL (1<<31)
720 +
721 +//Reset Control Register
722 +#define RALINK_SYS_RST (1<<0)
723 +#define RALINK_CPU_RST (1<<1)
724 +#define RALINK_TIMER_RST (1<<8)
725 +#define RALINK_INTC_RST (1<<9)
726 +#define RALINK_MC_RST (1<<10)
727 +#define RALINK_PCM_RST (1<<11)
728 +#define RALINK_UART_RST (1<<12)
729 +#define RALINK_PIO_RST (1<<13)
730 +#define RALINK_DMA_RST (1<<14)
731 +#define RALINK_I2C_RST (1<<16)
732 +#define RALINK_I2S_RST (1<<17)
733 +#define RALINK_SPI_RST (1<<18)
734 +#define RALINK_UARTL_RST (1<<19)
735 +#define RALINK_RT2872_RST (1<<20)
736 +#define RALINK_FE_RST (1<<21)
737 +#define RALINK_OTG_RST (1<<22)
738 +#define RALINK_SW_RST (1<<23)
739 +#define RALINK_EPHY_RST (1<<24)
740 +
741 +#elif defined (CONFIG_RALINK_RT3352)
742 +
743 +#define RALINK_SYSCTL_BASE 0xB0000000
744 +#define RALINK_TIMER_BASE 0xB0000100
745 +#define RALINK_INTCL_BASE 0xB0000200
746 +#define RALINK_MEMCTRL_BASE 0xB0000300
747 +#define RALINK_UART_BASE 0x10000500
748 +#define RALINK_PIO_BASE 0xB0000600
749 +#define RALINK_I2C_BASE 0xB0000900
750 +#define RALINK_I2S_BASE 0xB0000A00
751 +#define RALINK_SPI_BASE 0xB0000B00
752 +#define RALINK_NAND_CTRL_BASE 0xB0000800
753 +#define RALINK_UART_LITE_BASE 0x10000C00
754 +#define RALINK_PCM_BASE 0xB0002000
755 +#define RALINK_GDMA_BASE 0xB0002800
756 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
757 +#define RALINK_ETH_SW_BASE 0xB0110000
758 +#define RALINK_USB_DEV_BASE 0x10120000
759 +#define RALINK_11N_MAC_BASE 0xB0180000
760 +#define RALINK_USB_HOST_BASE 0x101C0000
761 +
762 +#define RALINK_MCNT_CFG 0xB0000D00
763 +#define RALINK_COMPARE 0xB0000D04
764 +#define RALINK_COUNT 0xB0000D08
765 +
766 +//Interrupt Controller
767 +#define RALINK_INTCTL_SYSCTL (1<<0)
768 +#define RALINK_INTCTL_TIMER0 (1<<1)
769 +#define RALINK_INTCTL_WDTIMER (1<<2)
770 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
771 +#define RALINK_INTCTL_PCM (1<<4)
772 +#define RALINK_INTCTL_UART (1<<5)
773 +#define RALINK_INTCTL_PIO (1<<6)
774 +#define RALINK_INTCTL_DMA (1<<7)
775 +#define RALINK_INTCTL_PC (1<<9)
776 +#define RALINK_INTCTL_I2S (1<<10)
777 +#define RALINK_INTCTL_UARTLITE (1<<12)
778 +#define RALINK_INTCTL_ESW (1<<17)
779 +#define RALINK_INTCTL_OTG (1<<18)
780 +#define RALINK_INTCTL_GLOBAL (1<<31)
781 +
782 +//Reset Control Register
783 +#define RALINK_SYS_RST (1<<0)
784 +#define RALINK_TIMER_RST (1<<8)
785 +#define RALINK_INTC_RST (1<<9)
786 +#define RALINK_MC_RST (1<<10)
787 +#define RALINK_PCM_RST (1<<11)
788 +#define RALINK_UART_RST (1<<12)
789 +#define RALINK_PIO_RST (1<<13)
790 +#define RALINK_DMA_RST (1<<14)
791 +#define RALINK_I2C_RST (1<<16)
792 +#define RALINK_I2S_RST (1<<17)
793 +#define RALINK_SPI_RST (1<<18)
794 +#define RALINK_UARTL_RST (1<<19)
795 +#define RALINK_WLAN_RST (1<<20)
796 +#define RALINK_FE_RST (1<<21)
797 +#define RALINK_UHST_RST (1<<22)
798 +#define RALINK_ESW_RST (1<<23)
799 +#define RALINK_EPHY_RST (1<<24)
800 +#define RALINK_UDEV_RST (1<<25)
801 +
802 +
803 +//Clock Conf Register
804 +#define RALINK_UPHY1_CLK_EN (1<<20)
805 +#define RALINK_UPHY0_CLK_EN (1<<18)
806 +#define RALINK_GE1_CLK_EN (1<<16)
807 +
808 +
809 +#elif defined (CONFIG_RALINK_RT5350)
810 +
811 +#define RALINK_SYSCTL_BASE 0xB0000000
812 +#define RALINK_TIMER_BASE 0xB0000100
813 +#define RALINK_INTCL_BASE 0xB0000200
814 +#define RALINK_MEMCTRL_BASE 0xB0000300
815 +#define RALINK_UART_BASE 0x10000500
816 +#define RALINK_PIO_BASE 0xB0000600
817 +#define RALINK_I2C_BASE 0xB0000900
818 +#define RALINK_I2S_BASE 0xB0000A00
819 +#define RALINK_SPI_BASE 0xB0000B00
820 +#define RALINK_UART_LITE_BASE 0x10000C00
821 +#define RALINK_PCM_BASE 0xB0002000
822 +#define RALINK_GDMA_BASE 0xB0002800
823 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
824 +#define RALINK_ETH_SW_BASE 0xB0110000
825 +#define RALINK_USB_DEV_BASE 0x10120000
826 +#define RALINK_11N_MAC_BASE 0xB0180000
827 +#define RALINK_USB_HOST_BASE 0x101C0000
828 +
829 +#define RALINK_MCNT_CFG 0xB0000D00
830 +#define RALINK_COMPARE 0xB0000D04
831 +#define RALINK_COUNT 0xB0000D08
832 +
833 +//Interrupt Controller
834 +#define RALINK_INTCTL_SYSCTL (1<<0)
835 +#define RALINK_INTCTL_TIMER0 (1<<1)
836 +#define RALINK_INTCTL_WDTIMER (1<<2)
837 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
838 +#define RALINK_INTCTL_PCM (1<<4)
839 +#define RALINK_INTCTL_UART (1<<5)
840 +#define RALINK_INTCTL_PIO (1<<6)
841 +#define RALINK_INTCTL_DMA (1<<7)
842 +#define RALINK_INTCTL_PC (1<<9)
843 +#define RALINK_INTCTL_I2S (1<<10)
844 +#define RALINK_INTCTL_UARTLITE (1<<12)
845 +#define RALINK_INTCTL_ESW (1<<17)
846 +#define RALINK_INTCTL_USB_HOST (1<<18)
847 +#define RALINK_INTCTL_USB_DEV (1<<19)
848 +#define RALINK_INTCTL_GLOBAL (1<<31)
849 +
850 +//Reset Control Register
851 +#define RALINK_SYS_RST (1<<0)
852 +#define RALINK_TIMER_RST (1<<8)
853 +#define RALINK_INTC_RST (1<<9)
854 +#define RALINK_MC_RST (1<<10)
855 +#define RALINK_PCM_RST (1<<11)
856 +#define RALINK_UART_RST (1<<12)
857 +#define RALINK_PIO_RST (1<<13)
858 +#define RALINK_DMA_RST (1<<14)
859 +#define RALINK_I2C_RST (1<<16)
860 +#define RALINK_I2S_RST (1<<17)
861 +#define RALINK_SPI_RST (1<<18)
862 +#define RALINK_UARTL_RST (1<<19)
863 +#define RALINK_WLAN_RST (1<<20)
864 +#define RALINK_FE_RST (1<<21)
865 +#define RALINK_UHST_RST (1<<22)
866 +#define RALINK_ESW_RST (1<<23)
867 +#define RALINK_EPHY_RST (1<<24)
868 +#define RALINK_UDEV_RST (1<<25)
869 +#define RALINK_MIPSC_RST (1<<28)
870 +
871 +//Clock Conf Register
872 +#define RALINK_UPHY0_CLK_EN (1<<18)
873 +#define RALINK_GE1_CLK_EN (1<<16)
874 +
875 +#elif defined (CONFIG_RALINK_RT2883)
876 +
877 +#define RALINK_SYSCTL_BASE 0xB0000000
878 +#define RALINK_TIMER_BASE 0xB0000100
879 +#define RALINK_INTCL_BASE 0xB0000200
880 +#define RALINK_MEMCTRL_BASE 0xB0000300
881 +#define RALINK_PCM_BASE 0xB0000400
882 +#define RALINK_UART_BASE 0x10000500
883 +#define RALINK_PIO_BASE 0xB0000600
884 +#define RALINK_GDMA_BASE 0xB0000700
885 +#define RALINK_NAND_CTRL_BASE 0xB0000800
886 +#define RALINK_I2C_BASE 0xB0000900
887 +#define RALINK_I2S_BASE 0xB0000A00
888 +#define RALINK_SPI_BASE 0xB0000B00
889 +#define RALINK_UART_LITE_BASE 0x10000C00
890 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
891 +#define RALINK_PCI_BASE 0xB0140000
892 +#define RALINK_11N_MAC_BASE 0xB0180000
893 +#define RALINK_USB_OTG_BASE 0x101C0000
894 +
895 +//Interrupt Controller
896 +#define RALINK_INTCTL_SYSCTL (1<<0)
897 +#define RALINK_INTCTL_TIMER0 (1<<1)
898 +#define RALINK_INTCTL_WDTIMER (1<<2)
899 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
900 +#define RALINK_INTCTL_PCM (1<<4)
901 +#define RALINK_INTCTL_UART (1<<5)
902 +#define RALINK_INTCTL_PIO (1<<6)
903 +#define RALINK_INTCTL_DMA (1<<7)
904 +#define RALINK_INTCTL_NAND (1<<8)
905 +#define RALINK_INTCTL_PC (1<<9)
906 +#define RALINK_INTCTL_I2S (1<<10)
907 +#define RALINK_INTCTL_UARTLITE (1<<12)
908 +#define RALINK_INTCTL_OTG (1<<18)
909 +#define RALINK_INTCTL_OTG_IRQN 18
910 +#define RALINK_INTCTL_GLOBAL (1<<31)
911 +
912 +//Reset Control Register
913 +#define RALINK_SYS_RST (1<<0)
914 +#define RALINK_CPU_RST (1<<1)
915 +#define RALINK_TIMER_RST (1<<8)
916 +#define RALINK_INTC_RST (1<<9)
917 +#define RALINK_MC_RST (1<<10)
918 +#define RALINK_PCM_RST (1<<11)
919 +#define RALINK_UART_RST (1<<12)
920 +#define RALINK_PIO_RST (1<<13)
921 +#define RALINK_DMA_RST (1<<14)
922 +#define RALINK_I2C_RST (1<<16)
923 +#define RALINK_I2S_RST (1<<17)
924 +#define RALINK_SPI_RST (1<<18)
925 +#define RALINK_UARTL_RST (1<<19)
926 +#define RALINK_WLAN_RST (1<<20)
927 +#define RALINK_FE_RST (1<<21)
928 +#define RALINK_OTG_RST (1<<22)
929 +#define RALINK_PCIE_RST (1<<23)
930 +
931 +#elif defined (CONFIG_RALINK_RT3883)
932 +
933 +#define RALINK_SYSCTL_BASE 0xB0000000
934 +#define RALINK_TIMER_BASE 0xB0000100
935 +#define RALINK_INTCL_BASE 0xB0000200
936 +#define RALINK_MEMCTRL_BASE 0xB0000300
937 +#define RALINK_UART_BASE 0x10000500
938 +#define RALINK_PIO_BASE 0xB0000600
939 +#define RALINK_NOR_CTRL_BASE 0xB0000700
940 +#define RALINK_NAND_CTRL_BASE 0xB0000810
941 +#define RALINK_I2C_BASE 0xB0000900
942 +#define RALINK_I2S_BASE 0xB0000A00
943 +#define RALINK_SPI_BASE 0xB0000B00
944 +#define RALINK_UART_LITE_BASE 0x10000C00
945 +#define RALINK_PCM_BASE 0xB0002000
946 +#define RALINK_GDMA_BASE 0xB0002800
947 +#define RALINK_CODEC1_BASE 0xB0003000
948 +#define RALINK_CODEC2_BASE 0xB0003800
949 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
950 +#define RALINK_USB_DEV_BASE 0x10120000
951 +#define RALINK_PCI_BASE 0xB0140000
952 +#define RALINK_11N_MAC_BASE 0xB0180000
953 +#define RALINK_USB_HOST_BASE 0x101C0000
954 +#define RALINK_PCIE_BASE 0xB0200000
955 +
956 +//Interrupt Controller
957 +#define RALINK_INTCTL_SYSCTL (1<<0)
958 +#define RALINK_INTCTL_TIMER0 (1<<1)
959 +#define RALINK_INTCTL_WDTIMER (1<<2)
960 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
961 +#define RALINK_INTCTL_PCM (1<<4)
962 +#define RALINK_INTCTL_UART (1<<5)
963 +#define RALINK_INTCTL_PIO (1<<6)
964 +#define RALINK_INTCTL_DMA (1<<7)
965 +#define RALINK_INTCTL_NAND (1<<8)
966 +#define RALINK_INTCTL_PC (1<<9)
967 +#define RALINK_INTCTL_I2S (1<<10)
968 +#define RALINK_INTCTL_UARTLITE (1<<12)
969 +#define RALINK_INTCTL_UHST (1<<18)
970 +#define RALINK_INTCTL_UDEV (1<<19)
971 +
972 +//Reset Control Register
973 +#define RALINK_SYS_RST (1<<0)
974 +#define RALINK_TIMER_RST (1<<8)
975 +#define RALINK_INTC_RST (1<<9)
976 +#define RALINK_MC_RST (1<<10)
977 +#define RALINK_PCM_RST (1<<11)
978 +#define RALINK_UART_RST (1<<12)
979 +#define RALINK_PIO_RST (1<<13)
980 +#define RALINK_DMA_RST (1<<14)
981 +#define RALINK_NAND_RST (1<<15)
982 +#define RALINK_I2C_RST (1<<16)
983 +#define RALINK_I2S_RST (1<<17)
984 +#define RALINK_SPI_RST (1<<18)
985 +#define RALINK_UARTL_RST (1<<19)
986 +#define RALINK_WLAN_RST (1<<20)
987 +#define RALINK_FE_RST (1<<21)
988 +#define RALINK_UHST_RST (1<<22)
989 +#define RALINK_PCIE_RST (1<<23)
990 +#define RALINK_PCI_RST (1<<24)
991 +#define RALINK_UDEV_RST (1<<25)
992 +#define RALINK_FLASH_RST (1<<26)
993 +
994 +//Clock Conf Register
995 +#define RALINK_UPHY1_CLK_EN (1<<20)
996 +#define RALINK_UPHY0_CLK_EN (1<<18)
997 +#define RALINK_GE1_CLK_EN (1<<16)
998 +
999 +#elif defined (CONFIG_RALINK_RT6855)
1000 +
1001 +#define RALINK_SYSCTL_BASE 0xB0000000
1002 +#define RALINK_TIMER_BASE 0xB0000100
1003 +#define RALINK_INTCL_BASE 0xB0000200
1004 +#define RALINK_MEMCTRL_BASE 0xB0000300
1005 +#define RALINK_UART_BASE 0x10000500
1006 +#define RALINK_PIO_BASE 0xB0000600
1007 +#define RALINK_I2C_BASE 0xB0000900
1008 +#define RALINK_I2S_BASE 0xB0000A00
1009 +#define RALINK_SPI_BASE 0xB0000B00
1010 +#define RALINK_NAND_CTRL_BASE 0xB0000800
1011 +#define RALINK_UART_LITE_BASE 0x10000C00
1012 +#define RALINK_PCM_BASE 0xB0002000
1013 +#define RALINK_GDMA_BASE 0xB0002800
1014 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1015 +#define RALINK_ETH_SW_BASE 0xB0110000
1016 +#define RALINK_PCI_BASE 0xB0140000
1017 +#define RALINK_USB_DEV_BASE 0x10120000
1018 +#define RALINK_11N_MAC_BASE 0xB0180000
1019 +#define RALINK_USB_HOST_BASE 0x101C0000
1020 +
1021 +#define RALINK_MCNT_CFG 0xB0000D00
1022 +#define RALINK_COMPARE 0xB0000D04
1023 +#define RALINK_COUNT 0xB0000D08
1024 +
1025 +//Interrupt Controller
1026 +#define RALINK_INTCTL_SYSCTL (1<<0)
1027 +#define RALINK_INTCTL_TIMER0 (1<<1)
1028 +#define RALINK_INTCTL_WDTIMER (1<<2)
1029 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1030 +#define RALINK_INTCTL_PCM (1<<4)
1031 +#define RALINK_INTCTL_UART (1<<5)
1032 +#define RALINK_INTCTL_PIO (1<<6)
1033 +#define RALINK_INTCTL_DMA (1<<7)
1034 +#define RALINK_INTCTL_PC (1<<9)
1035 +#define RALINK_INTCTL_I2S (1<<10)
1036 +#define RALINK_INTCTL_UARTLITE (1<<12)
1037 +#define RALINK_INTCTL_ESW (1<<17)
1038 +#define RALINK_INTCTL_OTG (1<<18)
1039 +#define RALINK_INTCTL_GLOBAL (1<<31)
1040 +
1041 +//Reset Control Register
1042 +#define RALINK_SYS_RST (1<<0)
1043 +#define RALINK_TIMER_RST (1<<8)
1044 +#define RALINK_INTC_RST (1<<9)
1045 +#define RALINK_MC_RST (1<<10)
1046 +#define RALINK_PCM_RST (1<<11)
1047 +#define RALINK_UART_RST (1<<12)
1048 +#define RALINK_PIO_RST (1<<13)
1049 +#define RALINK_DMA_RST (1<<14)
1050 +#define RALINK_I2C_RST (1<<16)
1051 +#define RALINK_I2S_RST (1<<17)
1052 +#define RALINK_SPI_RST (1<<18)
1053 +#define RALINK_UARTL_RST (1<<19)
1054 +#define RALINK_FE_RST (1<<21)
1055 +#define RALINK_UHST_RST (1<<22)
1056 +#define RALINK_ESW_RST (1<<23)
1057 +#define RALINK_EPHY_RST (1<<24)
1058 +#define RALINK_UDEV_RST (1<<25)
1059 +#define RALINK_PCIE0_RST (1<<26)
1060 +#define RALINK_PCIE1_RST (1<<27)
1061 +
1062 +//Clock Conf Register
1063 +#define RALINK_UPHY0_CLK_EN (1<<25)
1064 +#define RALINK_PCIE0_CLK_EN (1<<26)
1065 +#define RALINK_PCIE1_CLK_EN (1<<27)
1066 +
1067 +
1068 +#elif defined (CONFIG_RALINK_MT7620)
1069 +
1070 +#define RALINK_SYSCTL_BASE 0xB0000000
1071 +#define RALINK_TIMER_BASE 0xB0000100
1072 +#define RALINK_INTCL_BASE 0xB0000200
1073 +#define RALINK_MEMCTRL_BASE 0xB0000300
1074 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1075 +#define RALINK_UART_BASE 0x10000500
1076 +#define RALINK_PIO_BASE 0xB0000600
1077 +#define RALINK_NAND_CTRL_BASE 0xB0000810
1078 +#define RALINK_I2C_BASE 0xB0000900
1079 +#define RALINK_I2S_BASE 0xB0000A00
1080 +#define RALINK_SPI_BASE 0xB0000B00
1081 +#define RALINK_UART_LITE_BASE 0x10000C00
1082 +#define RALINK_MIPS_CNT_BASE 0x10000D00
1083 +#define RALINK_PCM_BASE 0xB0002000
1084 +#define RALINK_GDMA_BASE 0xB0002800
1085 +#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
1086 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1087 +#define RALINK_PPE_BASE 0xB0100C00
1088 +#define RALINK_ETH_SW_BASE 0xB0110000
1089 +#define RALINK_USB_DEV_BASE 0x10120000
1090 +#define RALINK_MSDC_BASE 0xB0130000
1091 +#define RALINK_PCI_BASE 0xB0140000
1092 +#define RALINK_11N_MAC_BASE 0xB0180000
1093 +#define RALINK_USB_HOST_BASE 0x101C0000
1094 +
1095 +#define RALINK_MCNT_CFG 0xB0000D00
1096 +#define RALINK_COMPARE 0xB0000D04
1097 +#define RALINK_COUNT 0xB0000D08
1098 +
1099 +//Interrupt Controller
1100 +#define RALINK_INTCTL_SYSCTL (1<<0)
1101 +#define RALINK_INTCTL_TIMER0 (1<<1)
1102 +#define RALINK_INTCTL_WDTIMER (1<<2)
1103 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1104 +#define RALINK_INTCTL_PCM (1<<4)
1105 +#define RALINK_INTCTL_UART (1<<5)
1106 +#define RALINK_INTCTL_PIO (1<<6)
1107 +#define RALINK_INTCTL_DMA (1<<7)
1108 +#define RALINK_INTCTL_PC (1<<9)
1109 +#define RALINK_INTCTL_I2S (1<<10)
1110 +#define RALINK_INTCTL_SPI (1<<11)
1111 +#define RALINK_INTCTL_UARTLITE (1<<12)
1112 +#define RALINK_INTCTL_CRYPTO (1<<13)
1113 +#define RALINK_INTCTL_ESW (1<<17)
1114 +#define RALINK_INTCTL_UHST (1<<18)
1115 +#define RALINK_INTCTL_UDEV (1<<19)
1116 +#define RALINK_INTCTL_GLOBAL (1<<31)
1117 +
1118 +//Reset Control Register
1119 +#define RALINK_SYS_RST (1<<0)
1120 +#define RALINK_TIMER_RST (1<<8)
1121 +#define RALINK_INTC_RST (1<<9)
1122 +#define RALINK_MC_RST (1<<10)
1123 +#define RALINK_PCM_RST (1<<11)
1124 +#define RALINK_UART_RST (1<<12)
1125 +#define RALINK_PIO_RST (1<<13)
1126 +#define RALINK_DMA_RST (1<<14)
1127 +#define RALINK_I2C_RST (1<<16)
1128 +#define RALINK_I2S_RST (1<<17)
1129 +#define RALINK_SPI_RST (1<<18)
1130 +#define RALINK_UARTL_RST (1<<19)
1131 +#define RALINK_FE_RST (1<<21)
1132 +#define RALINK_UHST_RST (1<<22)
1133 +#define RALINK_ESW_RST (1<<23)
1134 +#define RALINK_EPHY_RST (1<<24)
1135 +#define RALINK_UDEV_RST (1<<25)
1136 +#define RALINK_PCIE0_RST (1<<26)
1137 +#define RALINK_PCIE1_RST (1<<27)
1138 +#define RALINK_MIPS_CNT_RST (1<<28)
1139 +#define RALINK_CRYPTO_RST (1<<29)
1140 +
1141 +//Clock Conf Register
1142 +#define RALINK_UPHY0_CLK_EN (1<<25)
1143 +#define RALINK_UPHY1_CLK_EN (1<<22)
1144 +#define RALINK_PCIE0_CLK_EN (1<<26)
1145 +#define RALINK_PCIE1_CLK_EN (1<<27)
1146 +
1147 +//CPU PLL CFG Register
1148 +#define CPLL_SW_CONFIG (0x1UL << 31)
1149 +#define CPLL_MULT_RATIO_SHIFT 16
1150 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1151 +#define CPLL_DIV_RATIO_SHIFT 10
1152 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1153 +#define BASE_CLOCK 40 /* Mhz */
1154 +
1155 +#elif defined (CONFIG_RALINK_MT7621)
1156 +
1157 +#define RALINK_SYSCTL_BASE 0xBE000000
1158 +#define RALINK_TIMER_BASE 0xBE000100
1159 +#define RALINK_INTCL_BASE 0xBE000200
1160 +#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
1161 +#define RALINK_MIPS_CNT_BASE 0x1E000500
1162 +#define RALINK_PIO_BASE 0xBE000600
1163 +#define RALINK_SPDIF_BASE 0xBE000700
1164 +#define RALINK_I2C_BASE 0xBE000900
1165 +#define RALINK_I2S_BASE 0xBE000A00
1166 +#define RALINK_SPI_BASE 0xBE000B00
1167 +#define RALINK_UART_LITE1_BASE 0x1E000C00
1168 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1169 +#define RALINK_UART_LITE2_BASE 0x1E000D00
1170 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1171 +#define RALINK_UART_LITE3_BASE 0x1E000E00
1172 +#define RALINK_ANA_CTRL_BASE 0xBE000F00
1173 +#define RALINK_PCM_BASE 0xBE002000
1174 +#define RALINK_GDMA_BASE 0xBE002800
1175 +#define RALINK_NAND_CTRL_BASE 0xBE003000
1176 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
1177 +#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
1178 +#define RALINK_MEMCTRL_BASE 0xBE005000
1179 +#define RALINK_EXT_MC_ARB_BASE 0xBE006000
1180 +#define RALINK_HS_DMA_BASE 0xBE007000
1181 +#define RALINK_FRAME_ENGINE_BASE 0xBE100000
1182 +#define RALINK_PPE_BASE 0xBE100C00
1183 +#define RALINK_ETH_SW_BASE 0xBE110000
1184 +#define RALINK_ROM_BASE 0xBE118000
1185 +#define RALINK_MSDC_BASE 0xBE130000
1186 +#define RALINK_PCI_BASE 0xBE140000
1187 +#define RALINK_USB_HOST_BASE 0x1E1C0000
1188 +#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
1189 +
1190 +#define RALINK_MCNT_CFG 0xBE000500
1191 +#define RALINK_COMPARE 0xBE000504
1192 +#define RALINK_COUNT 0xBE000508
1193 +
1194 +//Interrupt Controller
1195 +#define RALINK_INTCTL_FE (1<<3)
1196 +#define RALINK_INTCTL_PCIE0 (1<<4)
1197 +#define RALINK_INTCTL_SYSCTL (1<<6)
1198 +#define RALINK_INTCTL_I2C (1<<8)
1199 +#define RALINK_INTCTL_DRAMC (1<<9)
1200 +#define RALINK_INTCTL_PCM (1<<10)
1201 +#define RALINK_INTCTL_HSDMA (1<<11)
1202 +#define RALINK_INTCTL_PIO (1<<12)
1203 +#define RALINK_INTCTL_DMA (1<<13)
1204 +#define RALINK_INTCTL_NFI (1<<14)
1205 +#define RALINK_INTCTL_NFIECC (1<<15)
1206 +#define RALINK_INTCTL_I2S (1<<16)
1207 +#define RALINK_INTCTL_SPI (1<<17)
1208 +#define RALINK_INTCTL_SPDIF (1<<18)
1209 +#define RALINK_INTCTL_CRYPTO (1<<19)
1210 +#define RALINK_INTCTL_SDXC (1<<20)
1211 +#define RALINK_INTCTL_PCTRL (1<<21)
1212 +#define RALINK_INTCTL_USB (1<<22)
1213 +#define RALINK_INTCTL_SWITCH (1<<23)
1214 +#define RALINK_INTCTL_PCIE1 (1<<24)
1215 +#define RALINK_INTCTL_PCIE2 (1<<25)
1216 +#define RALINK_INTCTL_UART1 (1<<26)
1217 +#define RALINK_INTCTL_UART2 (1<<27)
1218 +#define RALINK_INTCTL_UART3 (1<<28)
1219 +#define RALINK_INTCTL_WDTIMER (1<<29)
1220 +#define RALINK_INTCTL_TIMER0 (1<<30)
1221 +#define RALINK_INTCTL_TIMER1 (1<<31)
1222 +
1223 +
1224 +//Reset Control Register
1225 +#define RALINK_SYS_RST (1<<0)
1226 +#define RALINK_MCM_RST (1<<1)
1227 +#define RALINK_HSDMA_RST (1<<2)
1228 +#define RALINK_FE_RST (1<<6)
1229 +#define RALINK_SPDIF_RST (1<<7)
1230 +#define RALINK_TIMER_RST (1<<8)
1231 +#define RALINK_INTC_RST (1<<9)
1232 +#define RALINK_MC_RST (1<<10)
1233 +#define RALINK_PCM_RST (1<<11)
1234 +#define RALINK_PIO_RST (1<<13)
1235 +#define RALINK_DMA_RST (1<<14)
1236 +#define RALINK_NAND_RST (1<<15)
1237 +#define RALINK_I2C_RST (1<<16)
1238 +#define RALINK_I2S_RST (1<<17)
1239 +#define RALINK_SPI_RST (1<<18)
1240 +#define RALINK_UART1_RST (1<<19)
1241 +#define RALINK_UART2_RST (1<<20)
1242 +#define RALINK_UART3_RST (1<<21)
1243 +#define RALINK_ETH_RST (1<<23)
1244 +#define RALINK_PCIE0_RST (1<<24)
1245 +#define RALINK_PCIE1_RST (1<<25)
1246 +#define RALINK_PCIE2_RST (1<<26)
1247 +#define RALINK_AUX_STCK_RST (1<<28)
1248 +#define RALINK_CRYPTO_RST (1<<29)
1249 +#define RALINK_SDXC_RST (1<<30)
1250 +#define RALINK_PPE_RST (1<<31)
1251 +
1252 +//Clock Conf Register
1253 +#define RALINK_PCIE0_CLK_EN (1<<24)
1254 +#define RALINK_PCIE1_CLK_EN (1<<25)
1255 +#define RALINK_PCIE2_CLK_EN (1<<26)
1256 +//#define RALINK_UPHY0_CLK_EN (1<<27)
1257 +//#define RALINK_UPHY1_CLK_EN (1<<28)
1258 +
1259 +//CPU PLL CFG Register
1260 +#define CPLL_SW_CONFIG (0x1UL << 31)
1261 +#define CPLL_MULT_RATIO_SHIFT 16
1262 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1263 +#define CPLL_DIV_RATIO_SHIFT 10
1264 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1265 +#define BASE_CLOCK 40 /* Mhz */
1266 +
1267 +#define RALINK_TESTSTAT 0xBE000018
1268 +#define RALINK_TESTSTAT2 0xBE00001C
1269 +
1270 +#elif defined (CONFIG_RALINK_MT7628)
1271 +
1272 +#define RALINK_SYSCTL_BASE 0xB0000000
1273 +#define RALINK_TIMER_BASE 0xB0000100
1274 +#define RALINK_INTCL_BASE 0xB0000200
1275 +#define RALINK_MEMCTRL_BASE 0xB0000300
1276 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1277 +#define RALINK_MIPS_CNT_BASE 0x10000500
1278 +#define RALINK_PIO_BASE 0xB0000600
1279 +#define RALINK_SPI_SLAVE_BASE 0xB0000700
1280 +#define RALINK_I2C_BASE 0xB0000900
1281 +#define RALINK_I2S_BASE 0xB0000A00
1282 +#define RALINK_SPI_BASE 0xB0000B00
1283 +#define RALINK_UART_LITE1_BASE 0x10000C00
1284 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1285 +#define RALINK_UART_LITE2_BASE 0x10000D00
1286 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1287 +#define RALINK_UART_LITE3_BASE 0x10000E00
1288 +#define RALINK_PCM_BASE 0xB0002000
1289 +#define RALINK_GDMA_BASE 0xB0002800
1290 +#define RALINK_AES_ENGINE_BASE 0xB0004000
1291 +#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
1292 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1293 +#define RALINK_PPE_BASE 0xB0100C00
1294 +#define RALINK_ETH_SW_BASE 0xB0110000
1295 +#define RALINK_USB_DEV_BASE 0xB0120000
1296 +#define RALINK_MSDC_BASE 0xB0130000
1297 +#define RALINK_PCI_BASE 0xB0140000
1298 +#define RALINK_11N_MAC_BASE 0xB0180000
1299 +#define RALINK_USB_HOST_BASE 0x101C0000
1300 +
1301 +#define RALINK_MCNT_CFG 0xB0000500
1302 +#define RALINK_COMPARE 0xB0000504
1303 +#define RALINK_COUNT 0xB0000508
1304 +
1305 +
1306 +//Interrupt Controller
1307 +#define RALINK_INTCTL_SYSCTL (1<<0)
1308 +#define RALINK_INTCTL_TIMER0 (1<<1)
1309 +#define RALINK_INTCTL_WDTIMER (1<<2)
1310 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1311 +#define RALINK_INTCTL_PCM (1<<4)
1312 +#define RALINK_INTCTL_UART (1<<5)
1313 +#define RALINK_INTCTL_PIO (1<<6)
1314 +#define RALINK_INTCTL_DMA (1<<7)
1315 +#define RALINK_INTCTL_PC (1<<9)
1316 +#define RALINK_INTCTL_I2S (1<<10)
1317 +#define RALINK_INTCTL_SPI (1<<11)
1318 +#define RALINK_INTCTL_UARTLITE (1<<12)
1319 +#define RALINK_INTCTL_CRYPTO (1<<13)
1320 +#define RALINK_INTCTL_ESW (1<<17)
1321 +#define RALINK_INTCTL_UHST (1<<18)
1322 +#define RALINK_INTCTL_UDEV (1<<19)
1323 +#define RALINK_INTCTL_GLOBAL (1<<31)
1324 +
1325 +//Reset Control Register
1326 +#define RALINK_SYS_RST (1<<0)
1327 +#define RALINK_TIMER_RST (1<<8)
1328 +#define RALINK_INTC_RST (1<<9)
1329 +#define RALINK_MC_RST (1<<10)
1330 +#define RALINK_PCM_RST (1<<11)
1331 +#define RALINK_UART_RST (1<<12)
1332 +#define RALINK_PIO_RST (1<<13)
1333 +#define RALINK_DMA_RST (1<<14)
1334 +#define RALINK_I2C_RST (1<<16)
1335 +#define RALINK_I2S_RST (1<<17)
1336 +#define RALINK_SPI_RST (1<<18)
1337 +#define RALINK_UARTL_RST (1<<19)
1338 +#define RALINK_FE_RST (1<<21)
1339 +#define RALINK_UHST_RST (1<<22)
1340 +#define RALINK_ESW_RST (1<<23)
1341 +#define RALINK_EPHY_RST (1<<24)
1342 +#define RALINK_UDEV_RST (1<<25)
1343 +#define RALINK_PCIE0_RST (1<<26)
1344 +#define RALINK_PCIE1_RST (1<<27)
1345 +#define RALINK_MIPS_CNT_RST (1<<28)
1346 +#define RALINK_CRYPTO_RST (1<<29)
1347 +
1348 +//Clock Conf Register
1349 +#define RALINK_UPHY0_CLK_EN (1<<25)
1350 +#define RALINK_UPHY1_CLK_EN (1<<22)
1351 +#define RALINK_PCIE0_CLK_EN (1<<26)
1352 +#define RALINK_PCIE1_CLK_EN (1<<27)
1353 +
1354 +//CPU PLL CFG Register
1355 +#define CPLL_SW_CONFIG (0x1UL << 31)
1356 +#define CPLL_MULT_RATIO_SHIFT 16
1357 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1358 +#define CPLL_DIV_RATIO_SHIFT 10
1359 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1360 +#define BASE_CLOCK 40 /* Mhz */
1361 +
1362 +#endif
1363 +#endif
1364 Index: linux-3.14.16/arch/mips/include/asm/rt2880/serial_rt2880.h
1365 ===================================================================
1366 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1367 +++ linux-3.14.16/arch/mips/include/asm/rt2880/serial_rt2880.h 2014-08-24 15:51:48.530654066 +0200
1368 @@ -0,0 +1,443 @@
1369 +/**************************************************************************
1370 + *
1371 + * BRIEF MODULE DESCRIPTION
1372 + * serial port definition for Ralink RT2880 solution
1373 + *
1374 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
1375 + *
1376 + * This program is free software; you can redistribute it and/or modify it
1377 + * under the terms of the GNU General Public License as published by the
1378 + * Free Software Foundation; either version 2 of the License, or (at your
1379 + * option) any later version.
1380 + *
1381 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1382 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1383 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1384 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1385 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1386 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1387 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1388 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1389 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1390 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1391 + *
1392 + * You should have received a copy of the GNU General Public License along
1393 + * with this program; if not, write to the Free Software Foundation, Inc.,
1394 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1395 + *
1396 + *
1397 + **************************************************************************
1398 + * May 2007 Bruce Chang
1399 + *
1400 + * Initial Release
1401 + *
1402 + *
1403 + *
1404 + **************************************************************************
1405 + */
1406 +
1407 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1408 +#define RT2880_UART_RBR_OFFSET 0x00
1409 +#define RT2880_UART_TBR_OFFSET 0x00
1410 +#define RT2880_UART_IER_OFFSET 0x04
1411 +#define RT2880_UART_IIR_OFFSET 0x08
1412 +#define RT2880_UART_FCR_OFFSET 0x08
1413 +#define RT2880_UART_LCR_OFFSET 0x0C
1414 +#define RT2880_UART_MCR_OFFSET 0x10
1415 +#define RT2880_UART_LSR_OFFSET 0x14
1416 +#define RT2880_UART_DLL_OFFSET 0x00
1417 +#define RT2880_UART_DLM_OFFSET 0x04
1418 +#else
1419 +#define RT2880_UART_RBR_OFFSET 0x00
1420 +#define RT2880_UART_TBR_OFFSET 0x04
1421 +#define RT2880_UART_IER_OFFSET 0x08
1422 +#define RT2880_UART_IIR_OFFSET 0x0C
1423 +#define RT2880_UART_FCR_OFFSET 0x10
1424 +#define RT2880_UART_LCR_OFFSET 0x14
1425 +#define RT2880_UART_MCR_OFFSET 0x18
1426 +#define RT2880_UART_LSR_OFFSET 0x1C
1427 +#define RT2880_UART_DLL_OFFSET 0x2C
1428 +#define RT2880_UART_DLM_OFFSET 0x30
1429 +#endif
1430 +
1431 +#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
1432 +#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
1433 +#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
1434 +#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
1435 +#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
1436 +#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
1437 +#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
1438 +#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
1439 +#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
1440 +#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
1441 +
1442 +
1443 +#if defined (CONFIG_RALINK_RT2880) || \
1444 + defined (CONFIG_RALINK_RT2883) || \
1445 + defined (CONFIG_RALINK_RT3883) || \
1446 + defined (CONFIG_RALINK_RT3352) || \
1447 + defined (CONFIG_RALINK_RT5350) || \
1448 + defined (CONFIG_RALINK_RT6855) || \
1449 + defined (CONFIG_RALINK_MT7620) || \
1450 + defined (CONFIG_RALINK_RT3052)
1451 +
1452 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1453 +
1454 +#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
1455 +#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
1456 + * In: Fifo count
1457 + * Out: Fifo custom trigger levels
1458 + * XR16C85x only
1459 + */
1460 +
1461 +#define UART_IER 8 /* Out: Interrupt Enable Register */
1462 +#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
1463 + * XR16C85x only
1464 + */
1465 +
1466 +#define UART_IIR 12 /* In: Interrupt ID Register */
1467 +#define UART_EFR 12 /* I/O: Extended Features Register */
1468 + /* (DLAB=1, 16C660 only) */
1469 +
1470 +#define UART_FCR 16 /* Out: FIFO Control Register */
1471 +#define UART_LCR 20 /* Out: Line Control Register */
1472 +#define UART_MCR 24 /* Out: Modem Control Register */
1473 +#define UART_LSR 28 /* In: Line Status Register */
1474 +#define UART_MSR 32 /* In: Modem Status Register */
1475 +#define UART_SCR 36 /* I/O: Scratch Register */
1476 +#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
1477 +/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
1478 + * unpredictable values to be written to the Divisor Latch
1479 + */
1480 +#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
1481 +
1482 +#else
1483 +
1484 +#define UART_RX 0 /* In: Receive buffer */
1485 +#define UART_TX 0 /* Out: Transmit buffer */
1486 +#define UART_DLL 0 /* Out: Divisor Latch Low */
1487 +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1488 + * In: Fifo count
1489 + * Out: Fifo custom trigger levels */
1490 +
1491 +#define UART_DLM 4 /* Out: Divisor Latch High */
1492 +#define UART_IER 4 /* Out: Interrupt Enable Register */
1493 +#define UART_FCTR 4 /* Feature Control Register */
1494 +
1495 +#define UART_IIR 8 /* In: Interrupt ID Register */
1496 +#define UART_FCR 8 /* Out: FIFO Control Register */
1497 +#define UART_EFR 8 /* I/O: Extended Features Register */
1498 +
1499 +#define UART_LCR 12 /* Out: Line Control Register */
1500 +#define UART_MCR 16 /* Out: Modem Control Register */
1501 +#define UART_LSR 20 /* In: Line Status Register */
1502 +#define UART_MSR 24 /* In: Modem Status Register */
1503 +#define UART_SCR 28 /* I/O: Scratch Register */
1504 +#define UART_EMSR 28 /* Extended Mode Select Register */
1505 +
1506 +#endif
1507 +/*
1508 + * DLAB=0
1509 + */
1510 +//#define UART_IER 1 /* Out: Interrupt Enable Register */
1511 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1512 +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1513 +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1514 +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1515 +/*
1516 + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
1517 + */
1518 +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
1519 +
1520 +//#define UART_IIR 2 /* In: Interrupt ID Register */
1521 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1522 +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1523 +#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1524 +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1525 +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1526 +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1527 +
1528 +//#define UART_FCR 2 /* Out: FIFO Control Register */
1529 +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1530 +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1531 +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1532 +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1533 +/*
1534 + * Note: The FIFO trigger levels are chip specific:
1535 + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
1536 + * PC16550D: 1 4 8 14 xx xx xx xx
1537 + * TI16C550A: 1 4 8 14 xx xx xx xx
1538 + * TI16C550C: 1 4 8 14 xx xx xx xx
1539 + * ST16C550: 1 4 8 14 xx xx xx xx
1540 + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
1541 + * NS16C552: 1 4 8 14 xx xx xx xx
1542 + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
1543 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
1544 + * TI16C752: 8 16 56 60 8 16 32 56
1545 + */
1546 +#define UART_FCR_R_TRIG_00 0x00
1547 +#define UART_FCR_R_TRIG_01 0x40
1548 +#define UART_FCR_R_TRIG_10 0x80
1549 +#define UART_FCR_R_TRIG_11 0xc0
1550 +#define UART_FCR_T_TRIG_00 0x00
1551 +#define UART_FCR_T_TRIG_01 0x10
1552 +#define UART_FCR_T_TRIG_10 0x20
1553 +#define UART_FCR_T_TRIG_11 0x30
1554 +
1555 +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
1556 +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
1557 +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
1558 +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
1559 +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
1560 +/* 16650 definitions */
1561 +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
1562 +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
1563 +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
1564 +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
1565 +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
1566 +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
1567 +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
1568 +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
1569 +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
1570 +
1571 +//#define UART_LCR 3 /* Out: Line Control Register */
1572 +/*
1573 + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
1574 + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
1575 + */
1576 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1577 +#define UART_LCR_SBC 0x40 /* Set break control */
1578 +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1579 +#define UART_LCR_EPAR 0x10 /* Even parity select */
1580 +#define UART_LCR_PARITY 0x08 /* Parity Enable */
1581 +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
1582 +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1583 +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1584 +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1585 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1586 +
1587 +//#define UART_MCR 4 /* Out: Modem Control Register */
1588 +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
1589 +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
1590 +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
1591 +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
1592 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1593 +#define UART_MCR_OUT2 0x08 /* Out2 complement */
1594 +#define UART_MCR_OUT1 0x04 /* Out1 complement */
1595 +#define UART_MCR_RTS 0x02 /* RTS complement */
1596 +#define UART_MCR_DTR 0x01 /* DTR complement */
1597 +
1598 +//#define UART_LSR 5 /* In: Line Status Register */
1599 +#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1600 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1601 +#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1602 +#define UART_LSR_FE 0x08 /* Frame error indicator */
1603 +#define UART_LSR_PE 0x04 /* Parity error indicator */
1604 +#define UART_LSR_OE 0x02 /* Overrun error indicator */
1605 +#define UART_LSR_DR 0x01 /* Receiver data ready */
1606 +
1607 +//#define UART_MSR 6 /* In: Modem Status Register */
1608 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1609 +#define UART_MSR_RI 0x40 /* Ring Indicator */
1610 +#define UART_MSR_DSR 0x20 /* Data Set Ready */
1611 +#define UART_MSR_CTS 0x10 /* Clear to Send */
1612 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
1613 +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1614 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
1615 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
1616 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1617 +
1618 +//#define UART_SCR 7 /* I/O: Scratch Register */
1619 +
1620 +/*
1621 + * DLAB=1
1622 + */
1623 +//#define UART_DLL 0 /* Out: Divisor Latch Low */
1624 +//#define UART_DLM 1 /* Out: Divisor Latch High */
1625 +
1626 +/*
1627 + * LCR=0xBF (or DLAB=1 for 16C660)
1628 + */
1629 +//#define UART_EFR 2 /* I/O: Extended Features Register */
1630 +#define UART_EFR_CTS 0x80 /* CTS flow control */
1631 +#define UART_EFR_RTS 0x40 /* RTS flow control */
1632 +#define UART_EFR_SCD 0x20 /* Special character detect */
1633 +#define UART_EFR_ECB 0x10 /* Enhanced control bit */
1634 +/*
1635 + * the low four bits control software flow control
1636 + */
1637 +
1638 +/*
1639 + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
1640 + */
1641 +#define UART_XON1 4 /* I/O: Xon character 1 */
1642 +#define UART_XON2 5 /* I/O: Xon character 2 */
1643 +#define UART_XOFF1 6 /* I/O: Xoff character 1 */
1644 +#define UART_XOFF2 7 /* I/O: Xoff character 2 */
1645 +
1646 +/*
1647 + * EFR[4]=1 MCR[6]=1, TI16C752
1648 + */
1649 +#define UART_TI752_TCR 6 /* I/O: transmission control register */
1650 +#define UART_TI752_TLR 7 /* I/O: trigger level register */
1651 +
1652 +/*
1653 + * LCR=0xBF, XR16C85x
1654 + */
1655 +//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1656 +// * In: Fifo count
1657 +// * Out: Fifo custom trigger levels */
1658 +/*
1659 + * These are the definitions for the Programmable Trigger Register
1660 + */
1661 +#define UART_TRG_1 0x01
1662 +#define UART_TRG_4 0x04
1663 +#define UART_TRG_8 0x08
1664 +#define UART_TRG_16 0x10
1665 +#define UART_TRG_32 0x20
1666 +#define UART_TRG_64 0x40
1667 +#define UART_TRG_96 0x60
1668 +#define UART_TRG_120 0x78
1669 +#define UART_TRG_128 0x80
1670 +
1671 +//#define UART_FCTR 1 /* Feature Control Register */
1672 +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
1673 +#define UART_FCTR_RTS_4DELAY 0x01
1674 +#define UART_FCTR_RTS_6DELAY 0x02
1675 +#define UART_FCTR_RTS_8DELAY 0x03
1676 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
1677 +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
1678 +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
1679 +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
1680 +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
1681 +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
1682 +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
1683 +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
1684 +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
1685 +
1686 +/*
1687 + * LCR=0xBF, FCTR[6]=1
1688 + */
1689 +//#define UART_EMSR 7 /* Extended Mode Select Register */
1690 +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
1691 +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
1692 +
1693 +/*
1694 + * The Intel XScale on-chip UARTs define these bits
1695 + */
1696 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
1697 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
1698 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
1699 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
1700 +
1701 +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
1702 +
1703 +#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
1704 +#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
1705 +#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
1706 +#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
1707 +
1708 +
1709 +
1710 +
1711 +/*
1712 + * These register definitions are for the 16C950
1713 + */
1714 +#define UART_ASR 0x01 /* Additional Status Register */
1715 +#define UART_RFL 0x03 /* Receiver FIFO level */
1716 +#define UART_TFL 0x04 /* Transmitter FIFO level */
1717 +#define UART_ICR 0x05 /* Index Control Register */
1718 +
1719 +/* The 16950 ICR registers */
1720 +#define UART_ACR 0x00 /* Additional Control Register */
1721 +#define UART_CPR 0x01 /* Clock Prescalar Register */
1722 +#define UART_TCR 0x02 /* Times Clock Register */
1723 +#define UART_CKS 0x03 /* Clock Select Register */
1724 +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
1725 +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
1726 +#define UART_FCL 0x06 /* Flow Control Level Lower */
1727 +#define UART_FCH 0x07 /* Flow Control Level Higher */
1728 +#define UART_ID1 0x08 /* ID #1 */
1729 +#define UART_ID2 0x09 /* ID #2 */
1730 +#define UART_ID3 0x0A /* ID #3 */
1731 +#define UART_REV 0x0B /* Revision */
1732 +#define UART_CSR 0x0C /* Channel Software Reset */
1733 +#define UART_NMR 0x0D /* Nine-bit Mode Register */
1734 +#define UART_CTR 0xFF
1735 +
1736 +/*
1737 + * The 16C950 Additional Control Reigster
1738 + */
1739 +#define UART_ACR_RXDIS 0x01 /* Receiver disable */
1740 +#define UART_ACR_TXDIS 0x02 /* Receiver disable */
1741 +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
1742 +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
1743 +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
1744 +#define UART_ACR_ASREN 0x80 /* Additional status enable */
1745 +
1746 +
1747 +
1748 +/*
1749 + * These definitions are for the RSA-DV II/S card, from
1750 + *
1751 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
1752 + */
1753 +
1754 +#define UART_RSA_BASE (-8)
1755 +
1756 +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
1757 +
1758 +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
1759 +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
1760 +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
1761 +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
1762 +
1763 +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
1764 +
1765 +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
1766 +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
1767 +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
1768 +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
1769 +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
1770 +
1771 +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
1772 +
1773 +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
1774 +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
1775 +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
1776 +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
1777 +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
1778 +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
1779 +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
1780 +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
1781 +
1782 +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
1783 +
1784 +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
1785 +
1786 +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
1787 +
1788 +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
1789 +
1790 +/*
1791 + * The RSA DSV/II board has two fixed clock frequencies. One is the
1792 + * standard rate, and the other is 8 times faster.
1793 + */
1794 +#define SERIAL_RSA_BAUD_BASE (921600)
1795 +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
1796 +
1797 +/*
1798 + * Extra serial register definitions for the internal UARTs
1799 + * in TI OMAP processors.
1800 + */
1801 +#define UART_OMAP_MDR1 0x08 /* Mode definition register */
1802 +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
1803 +#define UART_OMAP_SCR 0x10 /* Supplementary control register */
1804 +#define UART_OMAP_SSR 0x11 /* Supplementary status register */
1805 +#define UART_OMAP_EBLR 0x12 /* BOF length register */
1806 +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
1807 +#define UART_OMAP_MVER 0x14 /* Module version register */
1808 +#define UART_OMAP_SYSC 0x15 /* System configuration register */
1809 +#define UART_OMAP_SYSS 0x16 /* System status register */
1810 +
1811 +
1812 Index: linux-3.14.16/arch/mips/include/asm/rt2880/sizes.h
1813 ===================================================================
1814 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1815 +++ linux-3.14.16/arch/mips/include/asm/rt2880/sizes.h 2014-08-24 15:51:48.530654066 +0200
1816 @@ -0,0 +1,52 @@
1817 +/*
1818 + * This program is free software; you can redistribute it and/or modify
1819 + * it under the terms of the GNU General Public License as published by
1820 + * the Free Software Foundation; either version 2 of the License, or
1821 + * (at your option) any later version.
1822 + *
1823 + * This program is distributed in the hope that it will be useful,
1824 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1825 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1826 + * GNU General Public License for more details.
1827 + *
1828 + * You should have received a copy of the GNU General Public License
1829 + * along with this program; if not, write to the Free Software
1830 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1831 + */
1832 +/* DO NOT EDIT!! - this file automatically generated
1833 + * from .s file by awk -f s2h.awk
1834 + */
1835 +/* Size definitions
1836 + * Copyright (C) ARM Limited 1998. All rights reserved.
1837 + */
1838 +
1839 +#ifndef __sizes_h
1840 +#define __sizes_h 1
1841 +
1842 +/* handy sizes */
1843 +#define SZ_1K 0x00000400
1844 +#define SZ_4K 0x00001000
1845 +#define SZ_8K 0x00002000
1846 +#define SZ_16K 0x00004000
1847 +#define SZ_64K 0x00010000
1848 +#define SZ_128K 0x00020000
1849 +#define SZ_256K 0x00040000
1850 +#define SZ_512K 0x00080000
1851 +
1852 +#define SZ_1M 0x00100000
1853 +#define SZ_2M 0x00200000
1854 +#define SZ_4M 0x00400000
1855 +#define SZ_8M 0x00800000
1856 +#define SZ_16M 0x01000000
1857 +#define SZ_32M 0x02000000
1858 +#define SZ_64M 0x04000000
1859 +#define SZ_128M 0x08000000
1860 +#define SZ_256M 0x10000000
1861 +#define SZ_512M 0x20000000
1862 +
1863 +#define SZ_1G 0x40000000
1864 +#define SZ_2G 0x80000000
1865 +
1866 +#endif
1867 +
1868 +/* END */
1869 Index: linux-3.14.16/arch/mips/include/asm/rt2880/surfboard.h
1870 ===================================================================
1871 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1872 +++ linux-3.14.16/arch/mips/include/asm/rt2880/surfboard.h 2014-08-24 15:51:48.530654066 +0200
1873 @@ -0,0 +1,70 @@
1874 +/*
1875 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1876 + *
1877 + * ########################################################################
1878 + *
1879 + * This program is free software; you can distribute it and/or modify it
1880 + * under the terms of the GNU General Public License (Version 2) as
1881 + * published by the Free Software Foundation.
1882 + *
1883 + * This program is distributed in the hope it will be useful, but WITHOUT
1884 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1885 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1886 + * for more details.
1887 + *
1888 + * You should have received a copy of the GNU General Public License along
1889 + * with this program; if not, write to the Free Software Foundation, Inc.,
1890 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1891 + *
1892 + * ########################################################################
1893 + *
1894 + */
1895 +#ifndef _SURFBOARD_H
1896 +#define _SURFBOARD_H
1897 +
1898 +#include <asm/addrspace.h>
1899 +
1900 +
1901 +
1902 +/*
1903 + * Surfboard system clock.
1904 + * This is the default value and maybe overidden by System Clock passed on the
1905 + * command line (sysclk=).
1906 + */
1907 +#define SURFBOARD_SYSTEM_CLOCK (125000000)
1908 +
1909 +/*
1910 + * Surfboard UART base baud rate = System Clock / 16.
1911 + * Ex. (14.7456 MHZ / 16) = 921600
1912 + * (32.0000 MHZ / 16) = 2000000
1913 + */
1914 +#define SURFBOARD_BAUD_DIV (16)
1915 +#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
1916 +
1917 +/*
1918 + * Maximum number of IDE Controllers
1919 + * Surfboard only has one ide (ide0), so only 2 drives are
1920 + * possible. (no need to check for more hwifs.)
1921 + */
1922 +//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
1923 +#define MAX_IDE_HWIFS (2) /* Graphite board */
1924 +
1925 +#define GCMP_BASE_ADDR 0x1fbf8000
1926 +#define GCMP_ADDRSPACE_SZ (256 * 1024)
1927 +
1928 +/*
1929 + * * GIC Specific definitions
1930 + * */
1931 +#define GIC_BASE_ADDR 0x1fbc0000
1932 +#define GIC_ADDRSPACE_SZ (128 * 1024)
1933 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
1934 +
1935 +/* GIC's Nomenclature for Core Interrupt Pins */
1936 +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
1937 +#define GIC_CPU_INT1 1 /* . */
1938 +#define GIC_CPU_INT2 2 /* . */
1939 +#define GIC_CPU_INT3 3 /* . */
1940 +#define GIC_CPU_INT4 4 /* . */
1941 +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
1942 +
1943 +#endif /* !(_SURFBOARD_H) */
1944 Index: linux-3.14.16/arch/mips/include/asm/rt2880/surfboardint.h
1945 ===================================================================
1946 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1947 +++ linux-3.14.16/arch/mips/include/asm/rt2880/surfboardint.h 2014-08-24 15:51:48.530654066 +0200
1948 @@ -0,0 +1,190 @@
1949 +/*
1950 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1951 + *
1952 + * ########################################################################
1953 + *
1954 + * This program is free software; you can distribute it and/or modify it
1955 + * under the terms of the GNU General Public License (Version 2) as
1956 + * published by the Free Software Foundation.
1957 + *
1958 + * This program is distributed in the hope it will be useful, but WITHOUT
1959 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1960 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1961 + * for more details.
1962 + *
1963 + * You should have received a copy of the GNU General Public License along
1964 + * with this program; if not, write to the Free Software Foundation, Inc.,
1965 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1966 + *
1967 + * ########################################################################
1968 + *
1969 + * Defines for the Surfboard interrupt controller.
1970 + *
1971 + */
1972 +#ifndef _SURFBOARDINT_H
1973 +#define _SURFBOARDINT_H
1974 +
1975 +/* Number of IRQ supported on hw interrupt 0. */
1976 +#if defined (CONFIG_RALINK_RT2880)
1977 +#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
1978 +#define SURFBOARDINT_GPIO 7 /* GPIO */
1979 +#define SURFBOARDINT_UART1 8 /* UART Lite */
1980 +#define SURFBOARDINT_UART 9 /* UART */
1981 +#define SURFBOARDINT_TIMER0 10 /* timer0 */
1982 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
1983 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
1984 +#define SURFBOARDINT_GPIO 6 /* GPIO */
1985 +#define SURFBOARDINT_DMA 7 /* DMA */
1986 +#define SURFBOARDINT_NAND 8 /* NAND */
1987 +#define SURFBOARDINT_PC 9 /* Performance counter */
1988 +#define SURFBOARDINT_I2S 10 /* I2S */
1989 +#define SURFBOARDINT_SDXC 14 /* SDXC */
1990 +#define SURFBOARDINT_ESW 17 /* ESW */
1991 +#define SURFBOARDINT_UART1 12 /* UART Lite */
1992 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
1993 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
1994 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
1995 +#define SURFBOARDINT_WDG 34 /* watch dog */
1996 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
1997 +#define SURFBOARDINT_PCM 36 /* PCM */
1998 +#define SURFBOARDINT_UART 37 /* UART */
1999 +#define RALINK_INT_PCIE0 13 /* PCIE0 */
2000 +#define RALINK_INT_PCIE1 14 /* PCIE1 */
2001 +
2002 +
2003 +#elif defined (CONFIG_RALINK_MT7628)
2004 +#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
2005 +#define SURFBOARDINT_PCM 4 /* PCM */
2006 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2007 +#define SURFBOARDINT_DMA 7 /* DMA */
2008 +#define SURFBOARDINT_PC 9 /* Performance counter */
2009 +#define SURFBOARDINT_I2S 10 /* I2S */
2010 +#define SURFBOARDINT_SPI 11 /* SPI */
2011 +#define SURFBOARDINT_AES 13 /* AES */
2012 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
2013 +#define SURFBOARDINT_SDXC 14 /* SDXC */
2014 +#define SURFBOARDINT_ESW 17 /* ESW */
2015 +#define SURFBOARDINT_USB 18 /* USB */
2016 +#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
2017 +#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
2018 +#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
2019 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
2020 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
2021 +#define SURFBOARDINT_WDG 23 /* WDG timer */
2022 +#define SURFBOARDINT_TIMER0 24 /* Timer0 */
2023 +#define SURFBOARDINT_TIMER1 25 /* Timer1 */
2024 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2025 +#define RALINK_INT_PCIE0 2 /* PCIE0 */
2026 +
2027 +
2028 +#elif defined (CONFIG_RALINK_MT7621)
2029 +
2030 +#define SURFBOARDINT_FE 3 /* FE */
2031 +#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
2032 +#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
2033 +#define SURFBOARDINT_I2C 8 /* I2C */
2034 +#define SURFBOARDINT_DRAMC 9 /* DRAMC */
2035 +#define SURFBOARDINT_PCM 10 /* PCM */
2036 +#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
2037 +#define SURFBOARDINT_GPIO 12 /* GPIO */
2038 +#define SURFBOARDINT_DMA 13 /* GDMA */
2039 +#define SURFBOARDINT_NAND 14 /* NAND */
2040 +#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
2041 +#define SURFBOARDINT_I2S 16 /* I2S */
2042 +#define SURFBOARDINT_SPI 17 /* SPI */
2043 +#define SURFBOARDINT_SPDIF 18 /* SPDIF */
2044 +#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
2045 +#define SURFBOARDINT_SDXC 20 /* SDXC */
2046 +#define SURFBOARDINT_PCTRL 21 /* Performance counter */
2047 +#define SURFBOARDINT_USB 22 /* USB */
2048 +#define SURFBOARDINT_ESW 31 /* Switch */
2049 +#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
2050 +#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
2051 +#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
2052 +#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
2053 +#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
2054 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
2055 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
2056 +
2057 +#define SURFBOARDINT_WDG 29 /* WDG timer */
2058 +#define SURFBOARDINT_TIMER0 30 /* Timer0 */
2059 +#define SURFBOARDINT_TIMER1 31 /* Timer1 */
2060 +
2061 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
2062 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
2063 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
2064 +
2065 +#elif defined (CONFIG_RALINK_RT3883)
2066 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
2067 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2068 +#define SURFBOARDINT_DMA 7 /* DMA */
2069 +#define SURFBOARDINT_NAND 8 /* NAND */
2070 +#define SURFBOARDINT_PC 9 /* Performance counter */
2071 +#define SURFBOARDINT_I2S 10 /* I2S */
2072 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2073 +#define SURFBOARDINT_PCI 18 /* PCI */
2074 +#define SURFBOARDINT_UDEV 19 /* USB Device */
2075 +#define SURFBOARDINT_UHST 20 /* USB Host */
2076 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2077 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2078 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2079 +#define SURFBOARDINT_PCM 36 /* PCM */
2080 +#define SURFBOARDINT_UART 37 /* UART */
2081 +#endif
2082 +
2083 +#define SURFBOARDINT_END 64
2084 +#define RT2880_INTERINT_START 40
2085 +
2086 +/* Global interrupt bit definitions */
2087 +#define C_SURFBOARD_GLOBAL_INT 31
2088 +#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
2089 +
2090 +/* added ??? */
2091 +#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
2092 +#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
2093 +/* end of added, bobtseng */
2094 +
2095 +/*
2096 + * Surfboard registers are memory mapped on 32-bit aligned boundaries and
2097 + * only word access are allowed.
2098 + */
2099 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2100 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
2101 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
2102 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
2103 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
2104 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
2105 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
2106 +#else
2107 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
2108 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
2109 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
2110 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
2111 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
2112 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
2113 +#endif
2114 +
2115 +/* bobtseng added ++, 2006.3.6. */
2116 +#define read_32bit_cp0_register(source) \
2117 +({ int __res; \
2118 + __asm__ __volatile__( \
2119 + ".set\tpush\n\t" \
2120 + ".set\treorder\n\t" \
2121 + "mfc0\t%0,"STR(source)"\n\t" \
2122 + ".set\tpop" \
2123 + : "=r" (__res)); \
2124 + __res;})
2125 +
2126 +#define write_32bit_cp0_register(register,value) \
2127 + __asm__ __volatile__( \
2128 + "mtc0\t%0,"STR(register)"\n\t" \
2129 + "nop" \
2130 + : : "r" (value));
2131 +
2132 +/* bobtseng added --, 2006.3.6. */
2133 +
2134 +void surfboardint_init(void);
2135 +u32 get_surfboard_sysclk(void);
2136 +
2137 +
2138 +#endif /* !(_SURFBOARDINT_H) */
2139 Index: linux-3.14.16/arch/mips/include/asm/rt2880/war.h
2140 ===================================================================
2141 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2142 +++ linux-3.14.16/arch/mips/include/asm/rt2880/war.h 2014-08-24 15:51:48.534654066 +0200
2143 @@ -0,0 +1,25 @@
2144 +/*
2145 + * This file is subject to the terms and conditions of the GNU General Public
2146 + * License. See the file "COPYING" in the main directory of this archive
2147 + * for more details.
2148 + *
2149 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2150 + */
2151 +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
2152 +#define __ASM_MIPS_MACH_MIPS_WAR_H
2153 +
2154 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
2155 +#define R4600_V1_HIT_CACHEOP_WAR 0
2156 +#define R4600_V2_HIT_CACHEOP_WAR 0
2157 +#define R5432_CP0_INTERRUPT_WAR 0
2158 +#define BCM1250_M3_WAR 0
2159 +#define SIBYTE_1956_WAR 0
2160 +#define MIPS4K_ICACHE_REFILL_WAR 1
2161 +#define MIPS_CACHE_SYNC_WAR 1
2162 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
2163 +#define RM9000_CDEX_SMP_WAR 0
2164 +#define ICACHE_REFILLS_WORKAROUND_WAR 1
2165 +#define R10000_LLSC_WAR 0
2166 +#define MIPS34K_MISSED_ITLB_WAR 0
2167 +
2168 +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
2169 Index: linux-3.14.16/drivers/net/ethernet/Kconfig
2170 ===================================================================
2171 --- linux-3.14.16.orig/drivers/net/ethernet/Kconfig 2014-08-24 15:51:48.510654065 +0200
2172 +++ linux-3.14.16/drivers/net/ethernet/Kconfig 2014-08-24 15:51:48.534654066 +0200
2173 @@ -135,6 +135,7 @@
2174 source "drivers/net/ethernet/pasemi/Kconfig"
2175 source "drivers/net/ethernet/qlogic/Kconfig"
2176 source "drivers/net/ethernet/ralink/Kconfig"
2177 +source "drivers/net/ethernet/raeth/Kconfig"
2178 source "drivers/net/ethernet/realtek/Kconfig"
2179 source "drivers/net/ethernet/renesas/Kconfig"
2180 source "drivers/net/ethernet/rdc/Kconfig"
2181 Index: linux-3.14.16/drivers/net/ethernet/Makefile
2182 ===================================================================
2183 --- linux-3.14.16.orig/drivers/net/ethernet/Makefile 2014-08-24 15:51:48.510654065 +0200
2184 +++ linux-3.14.16/drivers/net/ethernet/Makefile 2014-08-24 15:51:48.534654066 +0200
2185 @@ -57,6 +57,7 @@
2186 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
2187 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
2188 obj-$(CONFIG_NET_RALINK) += ralink/
2189 +obj-$(CONFIG_RAETH) += raeth/
2190 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
2191 obj-$(CONFIG_SH_ETH) += renesas/
2192 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
2193 Index: linux-3.14.16/drivers/net/ethernet/raeth/Kconfig
2194 ===================================================================
2195 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2196 +++ linux-3.14.16/drivers/net/ethernet/raeth/Kconfig 2014-08-24 15:51:48.534654066 +0200
2197 @@ -0,0 +1,344 @@
2198 +
2199 +config RA_NAT_NONE
2200 + bool
2201 + default y
2202 + depends on RALINK
2203 +
2204 +config MT7621_ASIC
2205 + bool
2206 + default y
2207 + depends on SOC_MT7621
2208 +
2209 +config RALINK_MT7621
2210 + bool
2211 + default y
2212 + depends on SOC_MT7621
2213 +
2214 +config RAETH
2215 + tristate "Ralink GMAC"
2216 + depends on SOC_MT7621
2217 + ---help---
2218 + This driver supports Ralink gigabit ethernet family of
2219 + adapters.
2220 +
2221 +config PDMA_NEW
2222 + bool
2223 + default y if (RALINK_MT7620 || RALINK_MT7621)
2224 + depends on RAETH
2225 +
2226 +config RAETH_SCATTER_GATHER_RX_DMA
2227 + bool
2228 + default y if (RALINK_MT7620 || RALINK_MT7621)
2229 + depends on RAETH
2230 +
2231 +
2232 +choice
2233 + prompt "Network BottomHalves"
2234 + depends on RAETH
2235 + default RA_NETWORK_WORKQUEUE_BH
2236 +
2237 + config RA_NETWORK_TASKLET_BH
2238 + bool "Tasklet"
2239 +
2240 + config RA_NETWORK_WORKQUEUE_BH
2241 + bool "Work Queue"
2242 +
2243 + config RAETH_NAPI
2244 + bool "NAPI"
2245 +
2246 +endchoice
2247 +
2248 +#config TASKLET_WORKQUEUE_SW
2249 +# bool "Tasklet and Workqueue switch"
2250 +# depends on RA_NETWORK_TASKLET_BH
2251 +
2252 +config RAETH_SKB_RECYCLE_2K
2253 + bool "SKB Recycling"
2254 + depends on RAETH
2255 +
2256 +config RAETH_SPECIAL_TAG
2257 + bool "Ralink Special Tag (0x810x)"
2258 + depends on RAETH && RT_3052_ESW
2259 +
2260 +#config RAETH_JUMBOFRAME
2261 +# bool "Jumbo Frame up to 4K bytes"
2262 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
2263 +
2264 +config RAETH_CHECKSUM_OFFLOAD
2265 + bool "TCP/UDP/IP checksum offload"
2266 + default y
2267 + depends on RAETH && !RALINK_RT2880
2268 +
2269 +#config RAETH_SW_FC
2270 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
2271 +# default n
2272 +# depends on RAETH
2273 +
2274 +config 32B_DESC
2275 + bool "32bytes TX/RX description"
2276 + default n
2277 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
2278 + ---help---
2279 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
2280 +
2281 +config RAETH_LRO
2282 + bool "LRO (Large Receive Offload )"
2283 + select INET_LRO
2284 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
2285 +
2286 +config RAETH_HW_VLAN_TX
2287 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
2288 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
2289 + ---help---
2290 + Please disable HW_VLAN_TX if you need double vlan
2291 +
2292 +config RAETH_HW_VLAN_RX
2293 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
2294 + depends on RAETH && RALINK_MT7621
2295 + ---help---
2296 + Please disable HW_VLAN_RX if you need double vlan
2297 +
2298 +config RAETH_TSO
2299 + bool "TSOV4 (Tcp Segmentaton Offload)"
2300 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
2301 +
2302 +config RAETH_TSOV6
2303 + bool "TSOV6 (Tcp Segmentaton Offload)"
2304 + depends on RAETH_TSO
2305 +
2306 +config RAETH_RW_PDMAPTR_FROM_VAR
2307 + bool
2308 + default y if RALINK_RT6855A || RALINK_MT7620
2309 + depends on RAETH
2310 +
2311 +#config RAETH_QOS
2312 +# bool "QoS Feature"
2313 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
2314 +
2315 +choice
2316 + prompt "QoS Type"
2317 + depends on RAETH_QOS
2318 + default DSCP_QOS_DSCP
2319 +
2320 +config RAETH_QOS_DSCP_BASED
2321 + bool "DSCP-based"
2322 + depends on RAETH_QOS
2323 +
2324 +config RAETH_QOS_VPRI_BASED
2325 + bool "VPRI-based"
2326 + depends on RAETH_QOS
2327 +
2328 +endchoice
2329 +
2330 +config RAETH_QDMA
2331 + bool "Choose QDMA instead PDMA"
2332 + default n
2333 + depends on RAETH && RALINK_MT7621
2334 +
2335 +choice
2336 + prompt "GMAC is connected to"
2337 + depends on RAETH
2338 + default GE1_RGMII_FORCE_1000
2339 +
2340 +config GE1_MII_FORCE_100
2341 + bool "MII_FORCE_100 (10/100M Switch)"
2342 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2343 +
2344 +config GE1_MII_AN
2345 + bool "MII_AN (100Phy)"
2346 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2347 +
2348 +config GE1_RVMII_FORCE_100
2349 + bool "RvMII_FORCE_100 (CPU)"
2350 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2351 +
2352 +config GE1_RGMII_FORCE_1000
2353 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2354 + depends on (RALINK_RT2880 || RALINK_RT3883)
2355 + select RALINK_SPI
2356 +
2357 +config GE1_RGMII_FORCE_1000
2358 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2359 + depends on (RALINK_MT7621)
2360 + select RT_3052_ESW
2361 +
2362 +config GE1_TRGMII_FORCE_1200
2363 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
2364 + depends on (RALINK_MT7621)
2365 + select RT_3052_ESW
2366 +
2367 +config GE1_RGMII_AN
2368 + bool "RGMII_AN (GigaPhy)"
2369 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2370 +
2371 +config GE1_RGMII_NONE
2372 + bool "NONE (NO CONNECT)"
2373 + depends on (RALINK_MT7621)
2374 +
2375 +endchoice
2376 +
2377 +config RT_3052_ESW
2378 + bool "Ralink Embedded Switch"
2379 + default y
2380 + depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
2381 +
2382 +config LAN_WAN_SUPPORT
2383 + bool "LAN/WAN Partition"
2384 + depends on RAETH_ROUTER || RT_3052_ESW
2385 +
2386 +choice
2387 + prompt "Switch Board Layout Type"
2388 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
2389 + default WAN_AT_P0
2390 +
2391 + config WAN_AT_P4
2392 + bool "LLLL/W"
2393 +
2394 + config WAN_AT_P0
2395 + bool "W/LLLL"
2396 +endchoice
2397 +
2398 +config RALINK_VISTA_BASIC
2399 + bool 'Vista Basic Logo for IC+ 175C'
2400 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
2401 +
2402 +config ESW_DOUBLE_VLAN_TAG
2403 + bool
2404 + default y if RT_3052_ESW
2405 +
2406 +config RAETH_HAS_PORT4
2407 + bool "Port 4 Support"
2408 + depends on RAETH && RALINK_MT7620
2409 +choice
2410 + prompt "Target Mode"
2411 + depends on RAETH_HAS_PORT4
2412 + default P4_RGMII_TO_MAC_MODE
2413 +
2414 + config P4_MAC_TO_PHY_MODE
2415 + bool "Giga_Phy (RGMII)"
2416 + config GE_RGMII_MT7530_P0_AN
2417 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
2418 + config GE_RGMII_MT7530_P4_AN
2419 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
2420 + config P4_RGMII_TO_MAC_MODE
2421 + bool "Giga_SW/iNIC (RGMII)"
2422 + config P4_MII_TO_MAC_MODE
2423 + bool "External_CPU (MII_RvMII)"
2424 + config P4_RMII_TO_MAC_MODE
2425 + bool "External_CPU (RvMII_MII)"
2426 +endchoice
2427 +
2428 +config MAC_TO_GIGAPHY_MODE_ADDR2
2429 + hex "Port4 Phy Address"
2430 + default 0x4
2431 + depends on P4_MAC_TO_PHY_MODE
2432 +
2433 +config RAETH_HAS_PORT5
2434 + bool "Port 5 Support"
2435 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
2436 +choice
2437 + prompt "Target Mode"
2438 + depends on RAETH_HAS_PORT5
2439 + default P5_RGMII_TO_MAC_MODE
2440 +
2441 + config P5_MAC_TO_PHY_MODE
2442 + bool "Giga_Phy (RGMII)"
2443 + config P5_RGMII_TO_MAC_MODE
2444 + bool "Giga_SW/iNIC (RGMII)"
2445 + config P5_RGMII_TO_MT7530_MODE
2446 + bool "MT7530 Giga_SW (RGMII)"
2447 + depends on RALINK_MT7620
2448 + config P5_MII_TO_MAC_MODE
2449 + bool "External_CPU (MII_RvMII)"
2450 + config P5_RMII_TO_MAC_MODE
2451 + bool "External_CPU (RvMII_MII)"
2452 +endchoice
2453 +
2454 +config MAC_TO_GIGAPHY_MODE_ADDR
2455 + hex "GE1 Phy Address"
2456 + default 0x1F
2457 + depends on GE1_MII_AN || GE1_RGMII_AN
2458 +
2459 +config MAC_TO_GIGAPHY_MODE_ADDR
2460 + hex "Port5 Phy Address"
2461 + default 0x5
2462 + depends on P5_MAC_TO_PHY_MODE
2463 +
2464 +config RAETH_GMAC2
2465 + bool "GMAC2 Support"
2466 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
2467 +
2468 +choice
2469 + prompt "GMAC2 is connected to"
2470 + depends on RAETH_GMAC2
2471 + default GE2_RGMII_AN
2472 +
2473 +config GE2_MII_FORCE_100
2474 + bool "MII_FORCE_100 (10/100M Switch)"
2475 + depends on RAETH_GMAC2
2476 +
2477 +config GE2_MII_AN
2478 + bool "MII_AN (100Phy)"
2479 + depends on RAETH_GMAC2
2480 +
2481 +config GE2_RVMII_FORCE_100
2482 + bool "RvMII_FORCE_100 (CPU)"
2483 + depends on RAETH_GMAC2
2484 +
2485 +config GE2_RGMII_FORCE_1000
2486 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2487 + depends on RAETH_GMAC2
2488 + select RALINK_SPI
2489 +
2490 +config GE2_RGMII_AN
2491 + bool "RGMII_AN (GigaPhy)"
2492 + depends on RAETH_GMAC2
2493 +
2494 +config GE2_INTERNAL_GPHY
2495 + bool "Internal GigaPHY"
2496 + depends on RAETH_GMAC2
2497 + select LAN_WAN_SUPPORT
2498 +
2499 +endchoice
2500 +
2501 +config GE_RGMII_INTERNAL_P0_AN
2502 + bool
2503 + depends on GE2_INTERNAL_GPHY
2504 + default y if WAN_AT_P0
2505 +
2506 +config GE_RGMII_INTERNAL_P4_AN
2507 + bool
2508 + depends on GE2_INTERNAL_GPHY
2509 + default y if WAN_AT_P4
2510 +
2511 +config MAC_TO_GIGAPHY_MODE_ADDR2
2512 + hex
2513 + default 0 if GE_RGMII_INTERNAL_P0_AN
2514 + default 4 if GE_RGMII_INTERNAL_P4_AN
2515 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
2516 +
2517 +config MAC_TO_GIGAPHY_MODE_ADDR2
2518 + hex "GE2 Phy Address"
2519 + default 0x1E
2520 + depends on GE2_MII_AN || GE2_RGMII_AN
2521 +
2522 +#force 100M
2523 +config RAETH_ROUTER
2524 +bool
2525 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
2526 +
2527 +#force 1000M
2528 +config MAC_TO_MAC_MODE
2529 +bool
2530 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
2531 +depends on (RALINK_RT2880 || RALINK_RT3883)
2532 +
2533 +#AN
2534 +config GIGAPHY
2535 +bool
2536 +default y if GE1_RGMII_AN || GE2_RGMII_AN
2537 +
2538 +#AN
2539 +config 100PHY
2540 +bool
2541 +default y if GE1_MII_AN || GE2_MII_AN
2542 Index: linux-3.14.16/drivers/net/ethernet/raeth/Makefile
2543 ===================================================================
2544 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2545 +++ linux-3.14.16/drivers/net/ethernet/raeth/Makefile 2014-08-24 15:51:48.542654066 +0200
2546 @@ -0,0 +1,7 @@
2547 +obj-$(CONFIG_RAETH) += raeth.o
2548 +raeth-objs := ra_mac.o mii_mgr.o
2549 +raeth-objs += raether_pdma.o
2550 +EXTRA_CFLAGS += -DWORKQUEUE_BH
2551 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
2552 +
2553 +raeth-objs += raether.o
2554 Index: linux-3.14.16/drivers/net/ethernet/raeth/ethtool_readme.txt
2555 ===================================================================
2556 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2557 +++ linux-3.14.16/drivers/net/ethernet/raeth/ethtool_readme.txt 2014-08-24 15:51:48.542654066 +0200
2558 @@ -0,0 +1,44 @@
2559 +
2560 +Ethtool readme for selecting different PHY address.
2561 +
2562 +Before doing any ethtool command you should make sure the current PHY
2563 +address is expected. The default PHY address is 1(port 1).
2564 +
2565 +You can change current PHY address to X(0~4) by doing follow command:
2566 +# echo X > /proc/rt2880/gmac
2567 +
2568 +Ethtool command also would show the current PHY address as following.
2569 +
2570 +# ethtool eth2
2571 +Settings for eth2:
2572 + Supported ports: [ TP MII ]
2573 + Supported link modes: 10baseT/Half 10baseT/Full
2574 + 100baseT/Half 100baseT/Full
2575 + Supports auto-negotiation: Yes
2576 + Advertised link modes: 10baseT/Half 10baseT/Full
2577 + 100baseT/Half 100baseT/Full
2578 + Advertised auto-negotiation: No
2579 + Speed: 10Mb/s
2580 + Duplex: Full
2581 + Port: MII
2582 + PHYAD: 1
2583 + Transceiver: internal
2584 + Auto-negotiation: off
2585 + Current message level: 0x00000000 (0)
2586 + Link detected: no
2587 +
2588 +
2589 +The "PHYAD" field shows the current PHY address.
2590 +
2591 +
2592 +
2593 +Usage example
2594 +1) show port1 info
2595 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2596 +# ethtool eth2
2597 +
2598 +2) show port0 info
2599 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2600 +# ethtool eth2
2601 +
2602 +
2603 Index: linux-3.14.16/drivers/net/ethernet/raeth/mii_mgr.c
2604 ===================================================================
2605 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2606 +++ linux-3.14.16/drivers/net/ethernet/raeth/mii_mgr.c 2014-08-24 15:51:48.542654066 +0200
2607 @@ -0,0 +1,166 @@
2608 +#include <linux/module.h>
2609 +#include <linux/version.h>
2610 +#include <linux/netdevice.h>
2611 +
2612 +#include <linux/kernel.h>
2613 +#include <linux/sched.h>
2614 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2615 +#include <asm/rt2880/rt_mmap.h>
2616 +#endif
2617 +
2618 +#include "ra2882ethreg.h"
2619 +#include "raether.h"
2620 +
2621 +
2622 +#define PHY_CONTROL_0 0x0004
2623 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2624 +#define enable_mdio(x)
2625 +
2626 +
2627 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2628 +{
2629 + u32 volatile status = 0;
2630 + u32 rc = 0;
2631 + unsigned long volatile t_start = jiffies;
2632 + u32 volatile data = 0;
2633 +
2634 + /* We enable mdio gpio purpose register, and disable it when exit. */
2635 + enable_mdio(1);
2636 +
2637 + // make sure previous read operation is complete
2638 + while (1) {
2639 + // 0 : Read/write operation complete
2640 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2641 + {
2642 + break;
2643 + }
2644 + else if (time_after(jiffies, t_start + 5*HZ)) {
2645 + enable_mdio(0);
2646 + printk("\n MDIO Read operation is ongoing !!\n");
2647 + return rc;
2648 + }
2649 + }
2650 +
2651 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
2652 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2653 + data |= (1<<31);
2654 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2655 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2656 +
2657 +
2658 + // make sure read operation is complete
2659 + t_start = jiffies;
2660 + while (1) {
2661 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
2662 + status = sysRegRead(MDIO_PHY_CONTROL_0);
2663 + *read_data = (u32)(status & 0x0000FFFF);
2664 +
2665 + enable_mdio(0);
2666 + return 1;
2667 + }
2668 + else if (time_after(jiffies, t_start+5*HZ)) {
2669 + enable_mdio(0);
2670 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
2671 + return 0;
2672 + }
2673 + }
2674 +}
2675 +
2676 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2677 +{
2678 + unsigned long volatile t_start=jiffies;
2679 + u32 volatile data;
2680 +
2681 + enable_mdio(1);
2682 +
2683 + // make sure previous write operation is complete
2684 + while(1) {
2685 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2686 + {
2687 + break;
2688 + }
2689 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2690 + enable_mdio(0);
2691 + printk("\n MDIO Write operation ongoing\n");
2692 + return 0;
2693 + }
2694 + }
2695 + /*add 1 us delay to make sequencial write more robus*/
2696 + udelay(1);
2697 +
2698 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
2699 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2700 + data |= (1<<31);
2701 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
2702 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2703 +
2704 + t_start = jiffies;
2705 +
2706 + // make sure write operation is complete
2707 + while (1) {
2708 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
2709 + {
2710 + enable_mdio(0);
2711 + return 1;
2712 + }
2713 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2714 + enable_mdio(0);
2715 + printk("\n MDIO Write operation Time Out\n");
2716 + return 0;
2717 + }
2718 + }
2719 +}
2720 +
2721 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2722 +{
2723 + u32 low_word;
2724 + u32 high_word;
2725 + if(phy_addr==31)
2726 + {
2727 + //phase1: write page address phase
2728 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
2729 + //phase2: write address & read low word phase
2730 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
2731 + //phase3: write address & read high word phase
2732 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
2733 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
2734 + return 1;
2735 + }
2736 + }
2737 + }
2738 + } else
2739 + {
2740 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
2741 + return 1;
2742 + }
2743 + }
2744 +
2745 + return 0;
2746 +}
2747 +
2748 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2749 +{
2750 + if(phy_addr == 31)
2751 + {
2752 + //phase1: write page address phase
2753 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
2754 + //phase2: write address & read low word phase
2755 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
2756 + //phase3: write address & read high word phase
2757 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
2758 + return 1;
2759 + }
2760 + }
2761 + }
2762 + } else
2763 + {
2764 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
2765 + return 1;
2766 + }
2767 + }
2768 +
2769 + return 0;
2770 +}
2771 +
2772 +EXPORT_SYMBOL(mii_mgr_write);
2773 +EXPORT_SYMBOL(mii_mgr_read);
2774 Index: linux-3.14.16/drivers/net/ethernet/raeth/ra2882ethreg.h
2775 ===================================================================
2776 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2777 +++ linux-3.14.16/drivers/net/ethernet/raeth/ra2882ethreg.h 2014-08-24 15:51:48.542654066 +0200
2778 @@ -0,0 +1,1268 @@
2779 +#ifndef RA2882ETHREG_H
2780 +#define RA2882ETHREG_H
2781 +
2782 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
2783 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
2784 +
2785 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2786 +#include <asm/rt2880/rt_mmap.h>
2787 +#endif
2788 +#include "raether.h"
2789 +
2790 +#ifdef WORKQUEUE_BH
2791 +#include <linux/workqueue.h>
2792 +#endif // WORKQUEUE_BH //
2793 +#ifdef CONFIG_RAETH_LRO
2794 +#include <linux/inet_lro.h>
2795 +#endif
2796 +
2797 +#define MAX_PACKET_SIZE 1514
2798 +#define MIN_PACKET_SIZE 60
2799 +
2800 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
2801 +
2802 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
2803 +#define BIT(x) ((1 << x))
2804 +#endif
2805 +#define ETHER_ADDR_LEN 6
2806 +
2807 +/* Phy Vender ID list */
2808 +
2809 +#define EV_ICPLUS_PHY_ID0 0x0243
2810 +#define EV_ICPLUS_PHY_ID1 0x0D90
2811 +#define EV_MARVELL_PHY_ID0 0x0141
2812 +#define EV_MARVELL_PHY_ID1 0x0CC2
2813 +#define EV_VTSS_PHY_ID0 0x0007
2814 +#define EV_VTSS_PHY_ID1 0x0421
2815 +
2816 +/*
2817 + FE_INT_STATUS
2818 +*/
2819 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2820 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2821 +
2822 +#define RX_COHERENT BIT(31)
2823 +#define RX_DLY_INT BIT(30)
2824 +#define TX_COHERENT BIT(29)
2825 +#define TX_DLY_INT BIT(28)
2826 +
2827 +#define RX_DONE_INT1 BIT(17)
2828 +#define RX_DONE_INT0 BIT(16)
2829 +
2830 +#define TX_DONE_INT3 BIT(3)
2831 +#define TX_DONE_INT2 BIT(2)
2832 +#define TX_DONE_INT1 BIT(1)
2833 +#define TX_DONE_INT0 BIT(0)
2834 +
2835 +#if defined (CONFIG_RALINK_MT7621)
2836 +#define RLS_COHERENT BIT(29)
2837 +#define RLS_DLY_INT BIT(28)
2838 +#define RLS_DONE_INT BIT(0)
2839 +#endif
2840 +
2841 +#else
2842 +//#define CNT_PPE_AF BIT(31)
2843 +//#define CNT_GDM_AF BIT(29)
2844 +#define PSE_P2_FC BIT(26)
2845 +#define GDM_CRC_DROP BIT(25)
2846 +#define PSE_BUF_DROP BIT(24)
2847 +#define GDM_OTHER_DROP BIT(23)
2848 +#define PSE_P1_FC BIT(22)
2849 +#define PSE_P0_FC BIT(21)
2850 +#define PSE_FQ_EMPTY BIT(20)
2851 +#define GE1_STA_CHG BIT(18)
2852 +#define TX_COHERENT BIT(17)
2853 +#define RX_COHERENT BIT(16)
2854 +
2855 +#define TX_DONE_INT3 BIT(11)
2856 +#define TX_DONE_INT2 BIT(10)
2857 +#define TX_DONE_INT1 BIT(9)
2858 +#define TX_DONE_INT0 BIT(8)
2859 +#define RX_DONE_INT1 RX_DONE_INT0
2860 +#define RX_DONE_INT0 BIT(2)
2861 +#define TX_DLY_INT BIT(1)
2862 +#define RX_DLY_INT BIT(0)
2863 +#endif
2864 +
2865 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
2866 + TX_DONE_INT1 | TX_DONE_INT0 | \
2867 + RX_DONE_INT0 )
2868 +
2869 +#if defined (CONFIG_RALINK_MT7621)
2870 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
2871 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
2872 +
2873 +#define NUM_QDMA_PAGE 256
2874 +#define QDMA_PAGE_SIZE 2048
2875 +#endif
2876 +/*
2877 + * SW_INT_STATUS
2878 + */
2879 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2880 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
2881 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
2882 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
2883 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
2884 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
2885 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
2886 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
2887 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
2888 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
2889 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
2890 +#define PORT_ST_CHG BIT(26) //Port status change
2891 +#define UNSECURED_ALERT BIT(27) //Intruder alert
2892 +#define ABNORMAL_ALERT BIT(28) //Abnormal
2893 +
2894 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
2895 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
2896 +#define ESW_INT_ALL (PORT_ST_CHG)
2897 +
2898 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2899 + defined (CONFIG_RALINK_MT7620)
2900 +#define MIB_INT BIT(25)
2901 +#define ACL_INT BIT(24)
2902 +#define P5_LINK_CH BIT(5)
2903 +#define P4_LINK_CH BIT(4)
2904 +#define P3_LINK_CH BIT(3)
2905 +#define P2_LINK_CH BIT(2)
2906 +#define P1_LINK_CH BIT(1)
2907 +#define P0_LINK_CH BIT(0)
2908 +
2909 +#define RX_GOCT_CNT BIT(4)
2910 +#define RX_GOOD_CNT BIT(6)
2911 +#define TX_GOCT_CNT BIT(17)
2912 +#define TX_GOOD_CNT BIT(19)
2913 +
2914 +#define MSK_RX_GOCT_CNT BIT(4)
2915 +#define MSK_RX_GOOD_CNT BIT(6)
2916 +#define MSK_TX_GOCT_CNT BIT(17)
2917 +#define MSK_TX_GOOD_CNT BIT(19)
2918 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
2919 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
2920 +
2921 +
2922 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
2923 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
2924 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
2925 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
2926 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
2927 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
2928 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
2929 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
2930 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
2931 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
2932 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
2933 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
2934 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
2935 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
2936 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
2937 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
2938 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
2939 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
2940 +
2941 +#if defined (CONFIG_RALINK_MT7620)
2942 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
2943 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
2944 +#endif
2945 +
2946 +
2947 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
2948 +
2949 +#elif defined (CONFIG_RALINK_MT7621)
2950 +
2951 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
2952 +
2953 +#define P5_LINK_CH BIT(5)
2954 +#define P4_LINK_CH BIT(4)
2955 +#define P3_LINK_CH BIT(3)
2956 +#define P2_LINK_CH BIT(2)
2957 +#define P1_LINK_CH BIT(1)
2958 +#define P0_LINK_CH BIT(0)
2959 +
2960 +
2961 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
2962 +
2963 +#define RX_BUF_ALLOC_SIZE 2000
2964 +#define FASTPATH_HEADROOM 64
2965 +
2966 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
2967 +
2968 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
2969 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
2970 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
2971 +
2972 +#ifdef CONFIG_PSEUDO_SUPPORT
2973 +typedef struct _PSEUDO_ADAPTER {
2974 + struct net_device *RaethDev;
2975 + struct net_device *PseudoDev;
2976 + struct net_device_stats stat;
2977 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
2978 + struct mii_if_info mii_info;
2979 +#endif
2980 +
2981 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
2982 +
2983 +#define MAX_PSEUDO_ENTRY 1
2984 +#endif
2985 +
2986 +
2987 +
2988 +/* Register Categories Definition */
2989 +#define RAFRAMEENGINE_OFFSET 0x0000
2990 +#define RAGDMA_OFFSET 0x0020
2991 +#define RAPSE_OFFSET 0x0040
2992 +#define RAGDMA2_OFFSET 0x0060
2993 +#define RACDMA_OFFSET 0x0080
2994 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2995 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2996 +
2997 +#define RAPDMA_OFFSET 0x0800
2998 +#define SDM_OFFSET 0x0C00
2999 +#else
3000 +#define RAPDMA_OFFSET 0x0100
3001 +#endif
3002 +#define RAPPE_OFFSET 0x0200
3003 +#define RACMTABLE_OFFSET 0x0400
3004 +#define RAPOLICYTABLE_OFFSET 0x1000
3005 +
3006 +
3007 +/* Register Map Detail */
3008 +/* RT3883 */
3009 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
3010 +
3011 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3012 +
3013 +/* 1. PDMA */
3014 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
3015 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
3016 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
3017 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
3018 +
3019 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
3020 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
3021 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
3022 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
3023 +
3024 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
3025 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
3026 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
3027 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
3028 +
3029 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
3030 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
3031 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
3032 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
3033 +
3034 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
3035 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3036 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3037 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3038 +
3039 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3040 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3041 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3042 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3043 +
3044 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3045 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3046 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3047 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3048 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3049 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3050 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3051 +#define FE_INT_STATUS (INT_STATUS)
3052 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3053 +#define FE_INT_ENABLE (INT_MASK)
3054 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3055 +#define PDMA_SCH_CFG (PDMA_WRR)
3056 +
3057 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
3058 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
3059 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
3060 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
3061 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
3062 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3063 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3064 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3065 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3066 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3067 +
3068 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3069 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3070 +
3071 +/* Old FE with New PDMA */
3072 +#define PDMA_RELATED 0x0800
3073 +/* 1. PDMA */
3074 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3075 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3076 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3077 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3078 +
3079 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3080 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3081 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3082 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3083 +
3084 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3085 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3086 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3087 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3088 +
3089 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3090 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3091 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3092 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3093 +
3094 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3095 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3096 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3097 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3098 +
3099 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3100 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3101 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3102 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3103 +
3104 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3105 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3106 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3107 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3108 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3109 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3110 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3111 +#define FE_INT_STATUS (INT_STATUS)
3112 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3113 +#define FE_INT_ENABLE (INT_MASK)
3114 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3115 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3116 +
3117 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
3118 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
3119 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
3120 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
3121 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
3122 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
3123 +
3124 +#if defined (CONFIG_RALINK_MT7620)
3125 +#define GDMA1_RELATED 0x0600
3126 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3127 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3128 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3129 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3130 +#elif defined (CONFIG_RALINK_MT7621)
3131 +#define GDMA1_RELATED 0x0500
3132 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3133 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3134 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3135 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3136 +
3137 +#define GDMA2_RELATED 0x1500
3138 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3139 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3140 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3141 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3142 +#else
3143 +#define GDMA1_RELATED 0x0020
3144 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3145 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3146 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3147 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3148 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
3149 +
3150 +#define GDMA2_RELATED 0x0060
3151 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3152 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3153 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3154 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3155 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
3156 +#endif
3157 +
3158 +#if defined (CONFIG_RALINK_MT7620)
3159 +#define PSE_RELATED 0x0500
3160 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3161 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3162 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3163 +#else
3164 +#define PSE_RELATED 0x0040
3165 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3166 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3167 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3168 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
3169 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
3170 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
3171 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
3172 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
3173 +#endif
3174 +
3175 +
3176 +#if defined (CONFIG_RALINK_MT7620)
3177 +#define CDMA_RELATED 0x0400
3178 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3179 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
3180 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
3181 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
3182 +#elif defined (CONFIG_RALINK_MT7621)
3183 +#define CDMA_RELATED 0x0400
3184 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
3185 +#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3186 +#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3187 +#else
3188 +#define CDMA_RELATED 0x0080
3189 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3190 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3191 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
3192 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
3193 +#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
3194 +#endif
3195 +
3196 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
3197 +
3198 +
3199 +#if defined (CONFIG_RALINK_MT7621)
3200 +/*kurtis: add QDMA define*/
3201 +
3202 +#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
3203 +#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
3204 +
3205 +#define QDMA_RELATED 0x1800
3206 +#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
3207 +#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
3208 +#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
3209 +#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
3210 +#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
3211 +#define QTX_SCH_1