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[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.14 / 0040-USB-add-mt7621-xhci-support.patch
1 From 023e31c036fef5daf7711878590e0930544b5ad7 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:10:49 +0100
4 Subject: [PATCH 40/57] USB: add mt7621 xhci support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/usb/core/hcd-pci.c | 6 +-
9 drivers/usb/core/hub.c | 2 +-
10 drivers/usb/core/port.c | 3 +-
11 drivers/usb/host/Kconfig | 8 +-
12 drivers/usb/host/Makefile | 8 +
13 drivers/usb/host/mtk-phy-7621.c | 445 +++++
14 drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
15 drivers/usb/host/mtk-phy-ahb.c | 58 +
16 drivers/usb/host/mtk-phy.c | 102 ++
17 drivers/usb/host/mtk-phy.h | 179 ++
18 drivers/usb/host/pci-quirks.h | 2 +-
19 drivers/usb/host/xhci-dbg.c | 3 +
20 drivers/usb/host/xhci-mem.c | 11 +
21 drivers/usb/host/xhci-mtk-power.c | 115 ++
22 drivers/usb/host/xhci-mtk-power.h | 13 +
23 drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
24 drivers/usb/host/xhci-mtk-scheduler.h | 77 +
25 drivers/usb/host/xhci-mtk.c | 265 +++
26 drivers/usb/host/xhci-mtk.h | 120 ++
27 drivers/usb/host/xhci-plat.c | 18 +
28 drivers/usb/host/xhci-ring.c | 109 +-
29 drivers/usb/host/xhci.c | 201 ++-
30 drivers/usb/host/xhci.h | 23 +-
31 23 files changed, 5234 insertions(+), 13 deletions(-)
32 create mode 100644 drivers/usb/host/mtk-phy-7621.c
33 create mode 100644 drivers/usb/host/mtk-phy-7621.h
34 create mode 100644 drivers/usb/host/mtk-phy-ahb.c
35 create mode 100644 drivers/usb/host/mtk-phy.c
36 create mode 100644 drivers/usb/host/mtk-phy.h
37 create mode 100644 drivers/usb/host/xhci-mtk-power.c
38 create mode 100644 drivers/usb/host/xhci-mtk-power.h
39 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
40 create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
41 create mode 100644 drivers/usb/host/xhci-mtk.c
42 create mode 100644 drivers/usb/host/xhci-mtk.h
43
44 --- a/drivers/usb/core/hcd-pci.c
45 +++ b/drivers/usb/core/hcd-pci.c
46 @@ -215,9 +215,13 @@ int usb_hcd_pci_probe(struct pci_dev *de
47 goto disable_pci;
48 }
49
50 +
51 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
52 + hcd->amd_resume_bug = 0;
53 +#else
54 hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
55 driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
56 -
57 +#endif
58 if (driver->flags & HCD_MEMORY) {
59 /* EHCI, OHCI */
60 hcd->rsrc_start = pci_resource_start(dev, 0);
61 --- a/drivers/usb/core/hub.c
62 +++ b/drivers/usb/core/hub.c
63 @@ -1270,7 +1270,7 @@ static void hub_quiesce(struct usb_hub *
64 if (type != HUB_SUSPEND) {
65 /* Disconnect all the children */
66 for (i = 0; i < hdev->maxchild; ++i) {
67 - if (hub->ports[i]->child)
68 + if (hub->ports[i] && hub->ports[i]->child)
69 usb_disconnect(&hub->ports[i]->child);
70 }
71 }
72 --- a/drivers/usb/core/port.c
73 +++ b/drivers/usb/core/port.c
74 @@ -191,6 +191,7 @@ exit:
75 void usb_hub_remove_port_device(struct usb_hub *hub,
76 int port1)
77 {
78 - device_unregister(&hub->ports[port1 - 1]->dev);
79 + if (hub->ports[port1 - 1])
80 + device_unregister(&hub->ports[port1 - 1]->dev);
81 }
82
83 --- a/drivers/usb/host/Kconfig
84 +++ b/drivers/usb/host/Kconfig
85 @@ -27,7 +27,13 @@ config USB_XHCI_HCD
86 if USB_XHCI_HCD
87
88 config USB_XHCI_PLATFORM
89 - tristate
90 + bool "xHCI platform"
91 + depends on SOC_MT7621
92 +
93 +config USB_MT7621_XHCI_PLATFORM
94 + bool "MTK MT7621 xHCI"
95 + depends on USB_XHCI_PLATFORM
96 + depends on SOC_MT7621
97
98 endif # USB_XHCI_HCD
99
100 --- a/drivers/usb/host/Makefile
101 +++ b/drivers/usb/host/Makefile
102 @@ -15,7 +15,13 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
103 xhci-hcd-y := xhci.o xhci-mem.o
104 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
105 xhci-hcd-y += xhci-trace.o
106 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
107 xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
108 +endif
109 +
110 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
111 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
112 +endif
113
114 ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
115 xhci-hcd-y += xhci-plat.o
116 @@ -23,7 +29,9 @@ endif
117
118 obj-$(CONFIG_USB_WHCI_HCD) += whci/
119
120 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
121 obj-$(CONFIG_PCI) += pci-quirks.o
122 +endif
123
124 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
125 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
126 --- /dev/null
127 +++ b/drivers/usb/host/mtk-phy-7621.c
128 @@ -0,0 +1,445 @@
129 +#include "mtk-phy.h"
130 +
131 +#ifdef CONFIG_PROJECT_7621
132 +#include "mtk-phy-7621.h"
133 +
134 +//not used on SoC
135 +PHY_INT32 phy_init(struct u3phy_info *info){
136 + return PHY_TRUE;
137 +}
138 +
139 +//not used on SoC
140 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
141 + return PHY_TRUE;
142 +}
143 +
144 +//--------------------------------------------------------
145 +// Function : fgEyeScanHelper_CheckPtInRegion()
146 +// Description : Check if the test point is in a rectangle region.
147 +// If it is in the rectangle, also check if this point
148 +// is on the multiple of deltaX and deltaY.
149 +// Parameter : strucScanRegion * prEye - the region
150 +// BYTE bX
151 +// BYTE bY
152 +// Return : BYTE - TRUE : This point needs to be tested
153 +// FALSE: This point will be omitted
154 +// Note : First check within the rectangle.
155 +// Secondly, use modulous to check if the point will be tested.
156 +//--------------------------------------------------------
157 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
158 +{
159 + PHY_INT8 fgValid = true;
160 +
161 +
162 + /// Be careful, the axis origin is on the TOP-LEFT corner.
163 + /// Therefore the top-left point has the minimum X and Y
164 + /// Botton-right point is the maximum X and Y
165 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
166 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
167 + {
168 + // With the region, now check whether or not the input test point is
169 + // on the multiples of X and Y
170 + // Do not have to worry about negative value, because we have already
171 + // check the input bX, and bY is within the region.
172 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
173 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
174 + {
175 + // if the division will have remainder, that means
176 + // the input test point is on the multiples of X and Y
177 + fgValid = false;
178 + }
179 + else
180 + {
181 + }
182 + }
183 + else
184 + {
185 +
186 + fgValid = false;
187 + }
188 + return fgValid;
189 +}
190 +
191 +//--------------------------------------------------------
192 +// Function : EyeScanHelper_RunTest()
193 +// Description : Enable the test, and wait til it is completed
194 +// Parameter : None
195 +// Return : None
196 +// Note : None
197 +//--------------------------------------------------------
198 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
199 +{
200 + DRV_UDELAY(100);
201 + // Disable the test
202 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
203 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
204 + DRV_UDELAY(100);
205 + // Run the test
206 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
207 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
208 + DRV_UDELAY(100);
209 + // Wait til it's done
210 + //RGS_SSUSB_RX_EYE_CNT_RDY
211 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
212 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
213 +}
214 +
215 +//--------------------------------------------------------
216 +// Function : fgEyeScanHelper_CalNextPoint()
217 +// Description : Calcualte the test point for the measurement
218 +// Parameter : None
219 +// Return : BOOL - TRUE : the next point is within the
220 +// boundaryof HW limit
221 +// FALSE: the next point is out of the HW limit
222 +// Note : The next point is obtained by calculating
223 +// from the bottom left of the region rectangle
224 +// and then scanning up until it reaches the upper
225 +// limit. At this time, the x will increment, and
226 +// start scanning downwards until the y hits the
227 +// zero.
228 +//--------------------------------------------------------
229 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
230 +{
231 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
232 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
233 + )
234 + {
235 + /// Reaches the limit of Y axis
236 + /// Increment X
237 + _bXcurr++;
238 + _fgXChged = true;
239 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
240 +
241 + if (_bXcurr > MAX_X)
242 + {
243 + return false;
244 + }
245 + }
246 + else
247 + {
248 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
249 + _fgXChged = false;
250 + }
251 + return PHY_TRUE;
252 +}
253 +
254 +PHY_INT32 eyescan_init(struct u3phy_info *info){
255 + //initial PHY setting
256 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
257 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
258 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
259 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
260 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
261 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
262 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
263 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
264 + return PHY_TRUE;
265 +}
266 +
267 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
268 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
269 + PHY_INT32 cOfst = 0;
270 + PHY_UINT8 bIdxX = 0;
271 + PHY_UINT8 bIdxY = 0;
272 + //PHY_INT8 bCnt = 0;
273 + PHY_UINT8 bIdxCycCnt = 0;
274 + PHY_INT8 fgValid;
275 + PHY_INT8 cX;
276 + PHY_INT8 cY;
277 + PHY_UINT8 bExtendCnt;
278 + PHY_INT8 isContinue;
279 + //PHY_INT8 isBreak;
280 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
281 + //PHY_UINT32 temp;
282 +
283 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
284 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
285 +
286 + _rEye1.bX_tl = x_t1;
287 + _rEye1.bY_tl = y_t1;
288 + _rEye1.bX_br = x_br;
289 + _rEye1.bY_br = y_br;
290 + _rEye1.bDeltaX = delta_x;
291 + _rEye1.bDeltaY = delta_y;
292 +
293 + _rEye2.bX_tl = x_t1;
294 + _rEye2.bY_tl = y_t1;
295 + _rEye2.bX_br = x_br;
296 + _rEye2.bY_br = y_br;
297 + _rEye2.bDeltaX = delta_x;
298 + _rEye2.bDeltaY = delta_y;
299 +
300 + _rTestCycle.wEyeCnt = eye_cnt;
301 + _rTestCycle.bNumOfEyeCnt = num_cnt;
302 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
303 + _rTestCycle.bPICalEn = PI_cal_en;
304 +
305 + _bXcurr = 0;
306 + _bYcurr = 0;
307 + _eScanDir = SCAN_DN;
308 + _fgXChged = false;
309 +
310 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
311 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
312 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
313 +
314 + //force SIGDET to OFF
315 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
316 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
317 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
318 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
319 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
320 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
321 +
322 + // RX_TRI_DET_EN to Disable
323 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
324 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
325 +
326 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
327 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
328 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
329 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
330 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
331 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
332 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
333 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
334 +
335 +
336 + if (PI_cal_en){
337 + // PI Calibration
338 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
339 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
340 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
341 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
342 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
343 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
344 +
345 + DRV_UDELAY(20);
346 +
347 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
348 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
349 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
350 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
351 +
352 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
353 + }
354 + // Read Initial DAC
355 + // Set CYCLE
356 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
357 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
358 +
359 + // Eye Monitor Feature
360 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
361 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
362 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
363 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
364 +
365 + // Move X,Y to the top-left corner
366 + for (cOfst = 0; cOfst >= -64; cOfst--)
367 + {
368 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
369 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
370 + }
371 + for (cOfst = 0; cOfst < 64; cOfst++)
372 + {
373 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
374 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
375 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
376 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
377 + }
378 + //ClearErrorResult
379 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
380 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
381 + {
382 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
383 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
384 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
385 + }
386 + }
387 + }
388 + isContinue = true;
389 + while(isContinue){
390 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
391 + // The point is within the boundary, then let's check if it is within
392 + // the testing region.
393 + // The point is only test-able if one of the eye region
394 + // includes this point.
395 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
396 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
397 + // Translate bX and bY to 2's complement from where the origin was on the
398 + // top left corner.
399 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
400 + cX = (_bXcurr ^ 0x40);
401 + cY = (_bYcurr ^ 0x3F);
402 +
403 + // Set X if necessary
404 + if (_fgXChged == true)
405 + {
406 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
407 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
408 + }
409 + // Set Y
410 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
411 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
412 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
413 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
414 +
415 + /// Test this point!
416 + if (fgValid){
417 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
418 + {
419 + //run test
420 + EyeScanHelper_RunTest(info);
421 + }
422 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
423 + {
424 + EyeScanHelper_RunTest(info);
425 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
426 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
427 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
428 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
429 +
430 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
431 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
432 +
433 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
434 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
435 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
436 + }
437 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
438 + }
439 + else{
440 +
441 + }
442 + if (fgEyeScanHelper_CalNextPoint() == false){
443 +#if 0
444 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
445 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
446 +#endif
447 + printk(KERN_ERR "end of eye scan\n");
448 + isContinue = false;
449 + }
450 + }
451 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
452 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
453 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
454 +
455 + // Move X,Y to the top-left corner
456 + for (cOfst = 63; cOfst >= 0; cOfst--)
457 + {
458 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
459 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
460 + }
461 + for (cOfst = 63; cOfst >= 0; cOfst--)
462 + {
463 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
464 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
465 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
466 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
467 +
468 + }
469 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
470 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
471 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
472 +
473 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
474 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
475 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
476 +
477 + return PHY_TRUE;
478 +}
479 +
480 +//not used on SoC
481 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
482 + return PHY_TRUE;
483 +}
484 +
485 +//not used on SoC
486 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
487 + return PHY_TRUE;
488 +}
489 +
490 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
491 + PHY_INT32 i=0;
492 + //PHY_INT32 j=0;
493 + //PHY_INT8 u1SrCalVal = 0;
494 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
495 + PHY_INT32 fgRet = 0;
496 + PHY_INT32 u4FmOut = 0;
497 + PHY_INT32 u4Tmp = 0;
498 + //PHY_INT32 temp;
499 +
500 + // => RG_USB20_HSTX_SRCAL_EN = 1
501 + // enable HS TX SR calibration
502 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
503 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
504 + DRV_MSLEEP(1);
505 +
506 + // => RG_FRCK_EN = 1
507 + // Enable free run clock
508 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
509 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
510 +
511 + // MT6290 HS signal quality patch
512 + // => RG_CYCLECNT = 400
513 + // Setting cyclecnt =400
514 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
515 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
516 +
517 + // => RG_FREQDET_EN = 1
518 + // Enable frequency meter
519 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
520 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
521 +
522 + // wait for FM detection done, set 10ms timeout
523 + for(i=0; i<10; i++){
524 + // => u4FmOut = USB_FM_OUT
525 + // read FM_OUT
526 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
527 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
528 +
529 + // check if FM detection done
530 + if (u4FmOut != 0)
531 + {
532 + fgRet = 0;
533 + printk("FM detection done! loop = %d\n", i);
534 +
535 + break;
536 + }
537 +
538 + fgRet = 1;
539 + DRV_MSLEEP(1);
540 + }
541 + // => RG_FREQDET_EN = 0
542 + // disable frequency meter
543 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
544 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
545 +
546 + // => RG_FRCK_EN = 0
547 + // disable free run clock
548 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
549 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
550 +
551 + // => RG_USB20_HSTX_SRCAL_EN = 0
552 + // disable HS TX SR calibration
553 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
554 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
555 + DRV_MSLEEP(1);
556 +
557 + if(u4FmOut == 0){
558 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
559 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
560 +
561 + fgRet = 1;
562 + }
563 + else{
564 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
565 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
566 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
567 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
568 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
569 + }
570 + return fgRet;
571 +}
572 +
573 +#endif
574 --- /dev/null
575 +++ b/drivers/usb/host/mtk-phy-7621.h
576 @@ -0,0 +1,2871 @@
577 +#ifdef CONFIG_PROJECT_7621
578 +#ifndef __MTK_PHY_7621_H
579 +#define __MTK_PHY_7621_H
580 +
581 +#define U2_SR_COEF_7621 28
582 +
583 +///////////////////////////////////////////////////////////////////////////////
584 +
585 +struct u2phy_reg {
586 + //0x0
587 + PHY_LE32 u2phyac0;
588 + PHY_LE32 u2phyac1;
589 + PHY_LE32 u2phyac2;
590 + PHY_LE32 reserve0;
591 + //0x10
592 + PHY_LE32 u2phyacr0;
593 + PHY_LE32 u2phyacr1;
594 + PHY_LE32 u2phyacr2;
595 + PHY_LE32 u2phyacr3;
596 + //0x20
597 + PHY_LE32 u2phyacr4;
598 + PHY_LE32 u2phyamon0;
599 + PHY_LE32 reserve1[2];
600 + //0x30~0x50
601 + PHY_LE32 reserve2[12];
602 + //0x60
603 + PHY_LE32 u2phydcr0;
604 + PHY_LE32 u2phydcr1;
605 + PHY_LE32 u2phydtm0;
606 + PHY_LE32 u2phydtm1;
607 + //0x70
608 + PHY_LE32 u2phydmon0;
609 + PHY_LE32 u2phydmon1;
610 + PHY_LE32 u2phydmon2;
611 + PHY_LE32 u2phydmon3;
612 + //0x80
613 + PHY_LE32 u2phybc12c;
614 + PHY_LE32 u2phybc12c1;
615 + PHY_LE32 reserve3[2];
616 + //0x90~0xe0
617 + PHY_LE32 reserve4[24];
618 + //0xf0
619 + PHY_LE32 reserve6[3];
620 + PHY_LE32 regfcom;
621 +};
622 +
623 +//U3D_U2PHYAC0
624 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
625 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
626 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
627 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
628 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
629 +#define RG_USB20_REF_EN (0x1<<15) //15:15
630 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
631 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
632 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
633 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
634 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
635 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
636 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
637 +
638 +//U3D_U2PHYAC1
639 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
640 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
641 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
642 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
643 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
644 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
645 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
646 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
647 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
648 +
649 +//U3D_U2PHYAC2
650 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
651 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
652 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
653 +
654 +//U3D_U2PHYACR0
655 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
656 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
657 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
658 +#define RG_USB20_LS_CR (0x7<<12) //14:12
659 +#define RG_USB20_FS_CR (0x7<<8) //10:8
660 +#define RG_USB20_LS_SR (0x7<<4) //6:4
661 +#define RG_USB20_FS_SR (0x7<<0) //2:0
662 +
663 +//U3D_U2PHYACR1
664 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
665 +#define RG_USB20_SQD (0x3<<24) //25:24
666 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
667 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
668 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
669 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
670 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
671 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
672 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
673 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
674 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
675 +
676 +//U3D_U2PHYACR2
677 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
678 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
679 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
680 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
681 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
682 +#define RG_USB20_DISCD (0x3<<20) //21:20
683 +#define RG_USB20_DISCTH (0xf<<16) //19:16
684 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
685 +#define RG_USB20_SQCAL (0xf<<8) //11:8
686 +#define RG_USB20_SQTH (0xf<<0) //3:0
687 +
688 +//U3D_U2PHYACR3
689 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
690 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
691 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
692 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
693 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
694 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
695 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
696 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
697 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
698 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
699 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
700 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
701 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
702 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
703 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
704 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
705 +
706 +//U3D_U2PHYACR4
707 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
708 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
709 +#define USB20_DP_100K_EN (0x1<<16) //16:16
710 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
711 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
712 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
713 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
714 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
715 +#define USB20_GPIO_MODE (0x1<<8) //8:8
716 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
717 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
718 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
719 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
720 +
721 +//U3D_U2PHYAMON0
722 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
723 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
724 +
725 +//U3D_U2PHYDCR0
726 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
727 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
728 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
729 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
730 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
731 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
732 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
733 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
734 +#define RG_USB20_TX_TST (0x1<<5) //5:5
735 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
736 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
737 +
738 +//U3D_U2PHYDCR1
739 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
740 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
741 +#define RG_DEBUG_EN (0x1<<22) //22:22
742 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
743 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
744 +#define RG_USB20_BERTH (0x3<<16) //17:16
745 +#define RG_USB20_LBMODE (0x3<<13) //14:13
746 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
747 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
748 +
749 +//U3D_U2PHYDTM0
750 +#define RG_UART_MODE (0x3<<30) //31:30
751 +#define FORCE_UART_I (0x1<<29) //29:29
752 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
753 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
754 +#define FORCE_UART_EN (0x1<<26) //26:26
755 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
756 +#define FORCE_DRVVBUS (0x1<<24) //24:24
757 +#define FORCE_DATAIN (0x1<<23) //23:23
758 +#define FORCE_TXVALID (0x1<<22) //22:22
759 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
760 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
761 +#define FORCE_XCVRSEL (0x1<<19) //19:19
762 +#define FORCE_SUSPENDM (0x1<<18) //18:18
763 +#define FORCE_TERMSEL (0x1<<17) //17:17
764 +#define FORCE_OPMODE (0x1<<16) //16:16
765 +#define UTMI_MUXSEL (0x1<<15) //15:15
766 +#define RG_RESET (0x1<<14) //14:14
767 +#define RG_DATAIN (0xf<<10) //13:10
768 +#define RG_TXVALIDH (0x1<<9) //9:9
769 +#define RG_TXVALID (0x1<<8) //8:8
770 +#define RG_DMPULLDOWN (0x1<<7) //7:7
771 +#define RG_DPPULLDOWN (0x1<<6) //6:6
772 +#define RG_XCVRSEL (0x3<<4) //5:4
773 +#define RG_SUSPENDM (0x1<<3) //3:3
774 +#define RG_TERMSEL (0x1<<2) //2:2
775 +#define RG_OPMODE (0x3<<0) //1:0
776 +
777 +//U3D_U2PHYDTM1
778 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
779 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
780 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
781 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
782 +#define RG_UART_I (0x1<<19) //19:19
783 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
784 +#define RG_UART_TX_OE (0x1<<17) //17:17
785 +#define RG_UART_EN (0x1<<16) //16:16
786 +#define FORCE_VBUSVALID (0x1<<13) //13:13
787 +#define FORCE_SESSEND (0x1<<12) //12:12
788 +#define FORCE_BVALID (0x1<<11) //11:11
789 +#define FORCE_AVALID (0x1<<10) //10:10
790 +#define FORCE_IDDIG (0x1<<9) //9:9
791 +#define FORCE_IDPULLUP (0x1<<8) //8:8
792 +#define RG_VBUSVALID (0x1<<5) //5:5
793 +#define RG_SESSEND (0x1<<4) //4:4
794 +#define RG_BVALID (0x1<<3) //3:3
795 +#define RG_AVALID (0x1<<2) //2:2
796 +#define RG_IDDIG (0x1<<1) //1:1
797 +#define RG_IDPULLUP (0x1<<0) //0:0
798 +
799 +//U3D_U2PHYDMON0
800 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
801 +
802 +//U3D_U2PHYDMON1
803 +#define USB20_UART_O (0x1<<31) //31:31
804 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
805 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
806 +#define AD_USB20_BVALID (0x1<<28) //28:28
807 +#define USB20_IDDIG (0x1<<27) //27:27
808 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
809 +#define AD_USB20_SESSEND (0x1<<25) //25:25
810 +#define AD_USB20_AVALID (0x1<<24) //24:24
811 +#define USB20_LINE_STATE (0x3<<22) //23:22
812 +#define USB20_HST_DISCON (0x1<<21) //21:21
813 +#define USB20_TX_READY (0x1<<20) //20:20
814 +#define USB20_RX_ERROR (0x1<<19) //19:19
815 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
816 +#define USB20_RX_VALIDH (0x1<<17) //17:17
817 +#define USB20_RX_VALID (0x1<<16) //16:16
818 +#define USB20_DATA_OUT (0xffff<<0) //15:0
819 +
820 +//U3D_U2PHYDMON2
821 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
822 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
823 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
824 +#define USB20_PROBE_OUT (0xff<<0) //7:0
825 +
826 +//U3D_U2PHYDMON3
827 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
828 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
829 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
830 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
831 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
832 +
833 +//U3D_U2PHYBC12C
834 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
835 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
836 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
837 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
838 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
839 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
840 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
841 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
842 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
843 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
844 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
845 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
846 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
847 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
848 +#define RG_CHGDT_EN (0x1<<0) //0:0
849 +
850 +//U3D_U2PHYBC12C1
851 +#define RG_CHGDT_REV (0xff<<0) //7:0
852 +
853 +//U3D_REGFCOM
854 +#define RG_PAGE (0xff<<24) //31:24
855 +#define I2C_MODE (0x1<<16) //16:16
856 +
857 +
858 +/* OFFSET */
859 +
860 +//U3D_U2PHYAC0
861 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
862 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
863 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
864 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
865 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
866 +#define RG_USB20_REF_EN_OFST (15)
867 +#define RG_USB20_INTR_EN_OFST (14)
868 +#define RG_USB20_BG_TRIM_OFST (8)
869 +#define RG_USB20_BG_RBSEL_OFST (6)
870 +#define RG_USB20_BG_RASEL_OFST (4)
871 +#define RG_USB20_BGR_DIV_OFST (2)
872 +#define RG_SIFSLV_CHP_EN_OFST (1)
873 +#define RG_SIFSLV_BGR_EN_OFST (0)
874 +
875 +//U3D_U2PHYAC1
876 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
877 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
878 +#define RG_USB20_MPX_SEL_OFST (16)
879 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
880 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
881 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
882 +#define RG_USB20_USBPLL_LF_OFST (2)
883 +#define RG_USB20_USBPLL_BR_OFST (1)
884 +#define RG_USB20_USBPLL_BP_OFST (0)
885 +
886 +//U3D_U2PHYAC2
887 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
888 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
889 +#define RG_USB20_CLKREF_REV_OFST (0)
890 +
891 +//U3D_U2PHYACR0
892 +#define RG_USB20_ICUSB_EN_OFST (24)
893 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
894 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
895 +#define RG_USB20_LS_CR_OFST (12)
896 +#define RG_USB20_FS_CR_OFST (8)
897 +#define RG_USB20_LS_SR_OFST (4)
898 +#define RG_USB20_FS_SR_OFST (0)
899 +
900 +//U3D_U2PHYACR1
901 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
902 +#define RG_USB20_SQD_OFST (24)
903 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
904 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
905 +#define RG_USB20_PHYD_MONEN_OFST (18)
906 +#define RG_USB20_INLPBK_EN_OFST (17)
907 +#define RG_USB20_CHIRP_EN_OFST (16)
908 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
909 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
910 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
911 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
912 +
913 +//U3D_U2PHYACR2
914 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
915 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
916 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
917 +#define RG_USB20_OTG_VBUSTH_OFST (24)
918 +#define RG_USB20_DISC_FIT_EN_OFST (22)
919 +#define RG_USB20_DISCD_OFST (20)
920 +#define RG_USB20_DISCTH_OFST (16)
921 +#define RG_USB20_SQCAL_EN_OFST (15)
922 +#define RG_USB20_SQCAL_OFST (8)
923 +#define RG_USB20_SQTH_OFST (0)
924 +
925 +//U3D_U2PHYACR3
926 +#define RG_USB20_HSTX_DBIST_OFST (28)
927 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
928 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
929 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
930 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
931 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
932 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
933 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
934 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
935 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
936 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
937 +#define RG_USB20_EN_PU_DM_OFST (11)
938 +#define RG_USB20_EN_PD_DM_OFST (10)
939 +#define RG_USB20_EN_PU_DP_OFST (9)
940 +#define RG_USB20_EN_PD_DP_OFST (8)
941 +#define RG_USB20_PHY_REV_OFST (0)
942 +
943 +//U3D_U2PHYACR4
944 +#define RG_USB20_DP_100K_MODE_OFST (18)
945 +#define RG_USB20_DM_100K_EN_OFST (17)
946 +#define USB20_DP_100K_EN_OFST (16)
947 +#define USB20_GPIO_DM_I_OFST (15)
948 +#define USB20_GPIO_DP_I_OFST (14)
949 +#define USB20_GPIO_DM_OE_OFST (13)
950 +#define USB20_GPIO_DP_OE_OFST (12)
951 +#define RG_USB20_GPIO_CTL_OFST (9)
952 +#define USB20_GPIO_MODE_OFST (8)
953 +#define RG_USB20_TX_BIAS_EN_OFST (5)
954 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
955 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
956 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
957 +
958 +//U3D_U2PHYAMON0
959 +#define RGO_USB20_GPIO_DM_O_OFST (1)
960 +#define RGO_USB20_GPIO_DP_O_OFST (0)
961 +
962 +//U3D_U2PHYDCR0
963 +#define RG_USB20_CDR_TST_OFST (30)
964 +#define RG_USB20_GATED_ENB_OFST (29)
965 +#define RG_USB20_TESTMODE_OFST (26)
966 +#define RG_USB20_PLL_STABLE_OFST (25)
967 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
968 +#define RG_USB20_PHYD_RESERVE_OFST (8)
969 +#define RG_USB20_EBTHRLD_OFST (7)
970 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
971 +#define RG_USB20_TX_TST_OFST (5)
972 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
973 +#define RG_USB20_CDR_FILT_OFST (0)
974 +
975 +//U3D_U2PHYDCR1
976 +#define RG_USB20_PROBE_SEL_OFST (24)
977 +#define RG_USB20_DRVVBUS_OFST (23)
978 +#define RG_DEBUG_EN_OFST (22)
979 +#define RG_USB20_OTG_PROBE_OFST (20)
980 +#define RG_USB20_SW_PLLMODE_OFST (18)
981 +#define RG_USB20_BERTH_OFST (16)
982 +#define RG_USB20_LBMODE_OFST (13)
983 +#define RG_USB20_FORCE_TAP_OFST (12)
984 +#define RG_USB20_TAPSEL_OFST (0)
985 +
986 +//U3D_U2PHYDTM0
987 +#define RG_UART_MODE_OFST (30)
988 +#define FORCE_UART_I_OFST (29)
989 +#define FORCE_UART_BIAS_EN_OFST (28)
990 +#define FORCE_UART_TX_OE_OFST (27)
991 +#define FORCE_UART_EN_OFST (26)
992 +#define FORCE_USB_CLKEN_OFST (25)
993 +#define FORCE_DRVVBUS_OFST (24)
994 +#define FORCE_DATAIN_OFST (23)
995 +#define FORCE_TXVALID_OFST (22)
996 +#define FORCE_DM_PULLDOWN_OFST (21)
997 +#define FORCE_DP_PULLDOWN_OFST (20)
998 +#define FORCE_XCVRSEL_OFST (19)
999 +#define FORCE_SUSPENDM_OFST (18)
1000 +#define FORCE_TERMSEL_OFST (17)
1001 +#define FORCE_OPMODE_OFST (16)
1002 +#define UTMI_MUXSEL_OFST (15)
1003 +#define RG_RESET_OFST (14)
1004 +#define RG_DATAIN_OFST (10)
1005 +#define RG_TXVALIDH_OFST (9)
1006 +#define RG_TXVALID_OFST (8)
1007 +#define RG_DMPULLDOWN_OFST (7)
1008 +#define RG_DPPULLDOWN_OFST (6)
1009 +#define RG_XCVRSEL_OFST (4)
1010 +#define RG_SUSPENDM_OFST (3)
1011 +#define RG_TERMSEL_OFST (2)
1012 +#define RG_OPMODE_OFST (0)
1013 +
1014 +//U3D_U2PHYDTM1
1015 +#define RG_USB20_PRBS7_EN_OFST (31)
1016 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
1017 +#define RG_USB20_CLK48M_EN_OFST (23)
1018 +#define RG_USB20_CLK60M_EN_OFST (22)
1019 +#define RG_UART_I_OFST (19)
1020 +#define RG_UART_BIAS_EN_OFST (18)
1021 +#define RG_UART_TX_OE_OFST (17)
1022 +#define RG_UART_EN_OFST (16)
1023 +#define FORCE_VBUSVALID_OFST (13)
1024 +#define FORCE_SESSEND_OFST (12)
1025 +#define FORCE_BVALID_OFST (11)
1026 +#define FORCE_AVALID_OFST (10)
1027 +#define FORCE_IDDIG_OFST (9)
1028 +#define FORCE_IDPULLUP_OFST (8)
1029 +#define RG_VBUSVALID_OFST (5)
1030 +#define RG_SESSEND_OFST (4)
1031 +#define RG_BVALID_OFST (3)
1032 +#define RG_AVALID_OFST (2)
1033 +#define RG_IDDIG_OFST (1)
1034 +#define RG_IDPULLUP_OFST (0)
1035 +
1036 +//U3D_U2PHYDMON0
1037 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1038 +
1039 +//U3D_U2PHYDMON1
1040 +#define USB20_UART_O_OFST (31)
1041 +#define RGO_USB20_LB_PASS_OFST (30)
1042 +#define RGO_USB20_LB_DONE_OFST (29)
1043 +#define AD_USB20_BVALID_OFST (28)
1044 +#define USB20_IDDIG_OFST (27)
1045 +#define AD_USB20_VBUSVALID_OFST (26)
1046 +#define AD_USB20_SESSEND_OFST (25)
1047 +#define AD_USB20_AVALID_OFST (24)
1048 +#define USB20_LINE_STATE_OFST (22)
1049 +#define USB20_HST_DISCON_OFST (21)
1050 +#define USB20_TX_READY_OFST (20)
1051 +#define USB20_RX_ERROR_OFST (19)
1052 +#define USB20_RX_ACTIVE_OFST (18)
1053 +#define USB20_RX_VALIDH_OFST (17)
1054 +#define USB20_RX_VALID_OFST (16)
1055 +#define USB20_DATA_OUT_OFST (0)
1056 +
1057 +//U3D_U2PHYDMON2
1058 +#define RGO_TXVALID_CNT_OFST (24)
1059 +#define RGO_RXACTIVE_CNT_OFST (16)
1060 +#define RGO_USB20_LB_BERCNT_OFST (8)
1061 +#define USB20_PROBE_OUT_OFST (0)
1062 +
1063 +//U3D_U2PHYDMON3
1064 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1065 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1066 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1067 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1068 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1069 +
1070 +//U3D_U2PHYBC12C
1071 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1072 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1073 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1074 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1075 +#define RG_CHGDT_VDATSRC_OFST (13)
1076 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1077 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1078 +#define RG_CHGDT_ISRC_DP_OFST (7)
1079 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1080 +#define RG_CHGDT_VDAT_DM_OFST (5)
1081 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1082 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1083 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1084 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1085 +#define RG_CHGDT_EN_OFST (0)
1086 +
1087 +//U3D_U2PHYBC12C1
1088 +#define RG_CHGDT_REV_OFST (0)
1089 +
1090 +//U3D_REGFCOM
1091 +#define RG_PAGE_OFST (24)
1092 +#define I2C_MODE_OFST (16)
1093 +
1094 +
1095 +///////////////////////////////////////////////////////////////////////////////
1096 +
1097 +struct u3phya_reg {
1098 + //0x0
1099 + PHY_LE32 reg0;
1100 + PHY_LE32 reg1;
1101 + PHY_LE32 reg2;
1102 + PHY_LE32 reg3;
1103 + //0x10
1104 + PHY_LE32 reg4;
1105 + PHY_LE32 reg5;
1106 + PHY_LE32 reg6;
1107 + PHY_LE32 reg7;
1108 + //0x20
1109 + PHY_LE32 reg8;
1110 + PHY_LE32 reg9;
1111 + PHY_LE32 rega;
1112 + PHY_LE32 regb;
1113 + //0x30
1114 + PHY_LE32 regc;
1115 + PHY_LE32 regd;
1116 + PHY_LE32 rege;
1117 +};
1118 +
1119 +//U3D_reg0
1120 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1121 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1122 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1123 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1124 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1125 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1126 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1127 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1128 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1129 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1130 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1131 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1132 +
1133 +//U3D_reg1
1134 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1135 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1136 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1137 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1138 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1139 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1140 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1141 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1142 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1143 +
1144 +//U3D_reg2
1145 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1146 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1147 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1148 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1149 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1150 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1151 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1152 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1153 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1154 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1155 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1156 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1157 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1158 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1159 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1160 +
1161 +//U3D_reg3
1162 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1163 +
1164 +//U3D_reg4
1165 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1166 +
1167 +//U3D_reg5
1168 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1169 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1170 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1171 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1172 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1173 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1174 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1175 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1176 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1177 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1178 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1179 +
1180 +//U3D_reg6
1181 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1182 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1183 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1184 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1185 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1186 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1187 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1188 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1189 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1190 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1191 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1192 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1193 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1194 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1195 +
1196 +//U3D_reg7
1197 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1198 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1199 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1200 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1201 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1202 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1203 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1204 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1205 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1206 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1207 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1208 +
1209 +//U3D_reg8
1210 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1211 +
1212 +//U3D_reg9
1213 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1214 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1215 +
1216 +//U3D_regA
1217 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1218 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1219 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1220 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1221 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1222 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1223 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1224 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1225 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1226 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1227 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1228 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1229 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1230 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1231 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1232 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1233 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1234 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1235 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1236 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1237 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1238 +
1239 +//U3D_regB
1240 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1241 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1242 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1243 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1244 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1245 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1246 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1247 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1248 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1249 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1250 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1251 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1252 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1253 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1254 +
1255 +//U3D_regC
1256 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1257 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1258 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1259 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1260 +
1261 +//U3D_redD
1262 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1263 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1264 +
1265 +//U3D_regE
1266 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1267 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1268 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1269 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1270 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1271 +
1272 +
1273 +/* OFFSET */
1274 +
1275 +//U3D_reg0
1276 +#define RG_SSUSB_BGR_EN_OFST (31)
1277 +#define RG_SSUSB_CHPEN_OFST (30)
1278 +#define RG_SSUSB_BG_DIV_OFST (28)
1279 +#define RG_SSUSB_INTR_EN_OFST (26)
1280 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1281 +#define RG_SSUSB_MPX_SEL_OFST (16)
1282 +#define RG_SSUSB_REF_EN_OFST (15)
1283 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1284 +#define RG_SSUSB_BG_RASEL_OFST (9)
1285 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1286 +#define RG_SSUSB_BG_MONEN_OFST (6)
1287 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1288 +
1289 +//U3D_reg1
1290 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1291 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1292 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1293 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1294 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1295 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1296 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1297 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1298 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1299 +
1300 +//U3D_reg2
1301 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1302 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1303 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1304 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1305 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1306 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1307 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1308 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1309 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1310 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1311 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1312 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1313 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1314 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1315 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1316 +
1317 +//U3D_reg3
1318 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1319 +
1320 +//U3D_reg4
1321 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1322 +
1323 +//U3D_reg5
1324 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1325 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1326 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1327 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1328 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1329 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1330 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1331 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1332 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1333 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1334 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1335 +
1336 +//U3D_reg6
1337 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1338 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1339 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1340 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1341 +#define RG_SSUSB_TX_SR_OFST (20)
1342 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1343 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1344 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1345 +#define RG_SSUSB_CKMON_EN_OFST (11)
1346 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1347 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1348 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1349 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1350 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1351 +
1352 +//U3D_reg7
1353 +#define RG_SSUSB_RESERVE_OFST (12)
1354 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1355 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1356 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1357 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1358 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1359 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1360 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1361 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1362 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1363 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1364 +
1365 +//U3D_reg8
1366 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1367 +
1368 +//U3D_reg9
1369 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1370 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1371 +
1372 +//U3D_regA
1373 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1374 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1375 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1376 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1377 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1378 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1379 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1380 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1381 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1382 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1383 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1384 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1385 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1386 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1387 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1388 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1389 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1390 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1391 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1392 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1393 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1394 +
1395 +//U3D_regB
1396 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1397 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1398 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1399 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1400 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1401 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1402 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1403 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1404 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1405 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1406 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1407 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1408 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1409 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1410 +
1411 +//U3D_regC
1412 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1413 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1414 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1415 +#define RG_PCIE_RX_RESERVE_OFST (0)
1416 +
1417 +//U3D_redD
1418 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1419 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1420 +
1421 +//U3D_regE
1422 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1423 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1424 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1425 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1426 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1427 +
1428 +///////////////////////////////////////////////////////////////////////////////
1429 +
1430 +struct u3phya_da_reg {
1431 + //0x0
1432 + PHY_LE32 reg0;
1433 + PHY_LE32 reg1;
1434 + PHY_LE32 reg4;
1435 + PHY_LE32 reg5;
1436 + //0x10
1437 + PHY_LE32 reg6;
1438 + PHY_LE32 reg7;
1439 + PHY_LE32 reg8;
1440 + PHY_LE32 reg9;
1441 + //0x20
1442 + PHY_LE32 reg10;
1443 + PHY_LE32 reg12;
1444 + PHY_LE32 reg13;
1445 + PHY_LE32 reg14;
1446 + //0x30
1447 + PHY_LE32 reg15;
1448 + PHY_LE32 reg16;
1449 + PHY_LE32 reg19;
1450 + PHY_LE32 reg20;
1451 + //0x40
1452 + PHY_LE32 reg21;
1453 + PHY_LE32 reg23;
1454 + PHY_LE32 reg25;
1455 + PHY_LE32 reg26;
1456 + //0x50
1457 + PHY_LE32 reg28;
1458 + PHY_LE32 reg29;
1459 + PHY_LE32 reg30;
1460 + PHY_LE32 reg31;
1461 + //0x60
1462 + PHY_LE32 reg32;
1463 + PHY_LE32 reg33;
1464 +};
1465 +
1466 +//U3D_reg0
1467 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1468 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1469 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1470 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1471 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1472 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1473 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1474 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1475 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1476 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1477 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1478 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1479 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1480 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1481 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1482 +
1483 +//U3D_reg1
1484 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1485 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1486 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1487 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1488 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1489 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1490 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1491 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1492 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1493 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1494 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1495 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1496 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1497 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1498 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1499 +
1500 +//U3D_reg4
1501 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1502 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1503 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1504 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1505 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1506 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1507 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1508 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1509 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1510 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1511 +
1512 +//U3D_reg5
1513 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1514 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1515 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1516 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1517 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1518 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1519 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1520 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1521 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1522 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1523 +
1524 +//U3D_reg6
1525 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1526 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1527 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1528 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1529 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1530 +
1531 +//U3D_reg7
1532 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1533 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1534 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1535 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1536 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1537 +
1538 +//U3D_reg8
1539 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1540 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1541 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1542 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1543 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1544 +
1545 +//U3D_reg9
1546 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1547 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1548 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1549 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1550 +
1551 +//U3D_reg10
1552 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1553 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1554 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1555 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1556 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1557 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1558 +
1559 +//U3D_reg12
1560 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1561 +
1562 +//U3D_reg13
1563 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1564 +
1565 +//U3D_reg14
1566 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1567 +
1568 +//U3D_reg15
1569 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1570 +
1571 +//U3D_reg16
1572 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1573 +
1574 +//U3D_reg19
1575 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1576 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1577 +
1578 +//U3D_reg20
1579 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1580 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1581 +
1582 +//U3D_reg21
1583 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1584 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1585 +
1586 +//U3D_reg23
1587 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1588 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1589 +
1590 +//U3D_reg25
1591 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1592 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1593 +
1594 +//U3D_reg26
1595 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1596 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1597 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1598 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1599 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1600 +
1601 +//U3D_reg28
1602 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1603 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1604 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1605 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1606 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1607 +
1608 +//U3D_reg29
1609 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1610 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1611 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1612 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1613 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1614 +
1615 +//U3D_reg30
1616 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1617 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1618 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1619 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1620 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1621 +
1622 +//U3D_reg31
1623 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1624 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1625 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1626 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1627 +
1628 +//U3D_reg32
1629 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1630 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1631 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1632 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1633 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1634 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1635 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1636 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1637 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1638 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1639 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1640 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1641 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1642 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1643 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1644 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1645 +
1646 +//U3D_reg33
1647 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1648 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1649 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1650 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1651 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1652 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1653 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1654 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1655 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1656 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1657 +
1658 +
1659 +/* OFFSET */
1660 +
1661 +//U3D_reg0
1662 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1663 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1664 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1665 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1666 +#define RG_PCIE_SPEED_U3_OFST (20)
1667 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1668 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1669 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1670 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1671 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1672 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1673 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1674 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1675 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1676 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1677 +
1678 +//U3D_reg1
1679 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1680 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1681 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1682 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1683 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1684 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1685 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1686 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1687 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1688 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1689 +#define RG_PCIE_MODE_PE2D_OFST (8)
1690 +#define RG_PCIE_MODE_PE2H_OFST (3)
1691 +#define RG_PCIE_MODE_PE1D_OFST (2)
1692 +#define RG_PCIE_MODE_PE1H_OFST (1)
1693 +#define RG_PCIE_MODE_U3_OFST (0)
1694 +
1695 +//U3D_reg4
1696 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1697 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1698 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1699 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1700 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1701 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1702 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1703 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1704 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1705 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1706 +
1707 +//U3D_reg5
1708 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1709 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1710 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1711 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1712 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1713 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1714 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1715 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1716 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1717 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1718 +
1719 +//U3D_reg6
1720 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1721 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1722 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1723 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1724 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1725 +
1726 +//U3D_reg7
1727 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1728 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1729 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1730 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1731 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1732 +
1733 +//U3D_reg8
1734 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1735 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1736 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1737 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1738 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1739 +
1740 +//U3D_reg9
1741 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1742 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1743 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1744 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1745 +
1746 +//U3D_reg10
1747 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1748 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1749 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1750 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1751 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1752 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1753 +
1754 +//U3D_reg12
1755 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1756 +
1757 +//U3D_reg13
1758 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1759 +
1760 +//U3D_reg14
1761 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1762 +
1763 +//U3D_reg15
1764 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1765 +
1766 +//U3D_reg16
1767 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1768 +
1769 +//U3D_reg19
1770 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1771 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1772 +
1773 +//U3D_reg20
1774 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1775 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1776 +
1777 +//U3D_reg21
1778 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1779 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1780 +
1781 +//U3D_reg23
1782 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1783 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1784 +
1785 +//U3D_reg25
1786 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1787 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1788 +
1789 +//U3D_reg26
1790 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1791 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1792 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1793 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1794 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1795 +
1796 +//U3D_reg28
1797 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1798 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1799 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1800 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1801 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1802 +
1803 +//U3D_reg29
1804 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1805 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1806 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1807 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1808 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1809 +
1810 +//U3D_reg30
1811 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1812 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1813 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1814 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1815 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1816 +
1817 +//U3D_reg31
1818 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1819 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1820 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1821 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1822 +
1823 +//U3D_reg32
1824 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1825 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1826 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1827 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1828 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1829 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1830 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1831 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1832 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1833 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1834 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1835 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1836 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1837 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1838 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1839 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1840 +
1841 +//U3D_reg33
1842 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1843 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1844 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1845 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1846 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1847 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1848 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1849 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1850 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1851 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1852 +
1853 +
1854 +///////////////////////////////////////////////////////////////////////////////
1855 +
1856 +struct u3phyd_reg {
1857 + //0x0
1858 + PHY_LE32 phyd_mix0;
1859 + PHY_LE32 phyd_mix1;
1860 + PHY_LE32 phyd_lfps0;
1861 + PHY_LE32 phyd_lfps1;
1862 + //0x10
1863 + PHY_LE32 phyd_impcal0;
1864 + PHY_LE32 phyd_impcal1;
1865 + PHY_LE32 phyd_txpll0;
1866 + PHY_LE32 phyd_txpll1;
1867 + //0x20
1868 + PHY_LE32 phyd_txpll2;
1869 + PHY_LE32 phyd_fl0;
1870 + PHY_LE32 phyd_mix2;
1871 + PHY_LE32 phyd_rx0;
1872 + //0x30
1873 + PHY_LE32 phyd_t2rlb;
1874 + PHY_LE32 phyd_cppat;
1875 + PHY_LE32 phyd_mix3;
1876 + PHY_LE32 phyd_ebufctl;
1877 + //0x40
1878 + PHY_LE32 phyd_pipe0;
1879 + PHY_LE32 phyd_pipe1;
1880 + PHY_LE32 phyd_mix4;
1881 + PHY_LE32 phyd_ckgen0;
1882 + //0x50
1883 + PHY_LE32 phyd_mix5;
1884 + PHY_LE32 phyd_reserved;
1885 + PHY_LE32 phyd_cdr0;
1886 + PHY_LE32 phyd_cdr1;
1887 + //0x60
1888 + PHY_LE32 phyd_pll_0;
1889 + PHY_LE32 phyd_pll_1;
1890 + PHY_LE32 phyd_bcn_det_1;
1891 + PHY_LE32 phyd_bcn_det_2;
1892 + //0x70
1893 + PHY_LE32 eq0;
1894 + PHY_LE32 eq1;
1895 + PHY_LE32 eq2;
1896 + PHY_LE32 eq3;
1897 + //0x80
1898 + PHY_LE32 eq_eye0;
1899 + PHY_LE32 eq_eye1;
1900 + PHY_LE32 eq_eye2;
1901 + PHY_LE32 eq_dfe0;
1902 + //0x90
1903 + PHY_LE32 eq_dfe1;
1904 + PHY_LE32 eq_dfe2;
1905 + PHY_LE32 eq_dfe3;
1906 + PHY_LE32 reserve0;
1907 + //0xa0
1908 + PHY_LE32 phyd_mon0;
1909 + PHY_LE32 phyd_mon1;
1910 + PHY_LE32 phyd_mon2;
1911 + PHY_LE32 phyd_mon3;
1912 + //0xb0
1913 + PHY_LE32 phyd_mon4;
1914 + PHY_LE32 phyd_mon5;
1915 + PHY_LE32 phyd_mon6;
1916 + PHY_LE32 phyd_mon7;
1917 + //0xc0
1918 + PHY_LE32 phya_rx_mon0;
1919 + PHY_LE32 phya_rx_mon1;
1920 + PHY_LE32 phya_rx_mon2;
1921 + PHY_LE32 phya_rx_mon3;
1922 + //0xd0
1923 + PHY_LE32 phya_rx_mon4;
1924 + PHY_LE32 phya_rx_mon5;
1925 + PHY_LE32 phyd_cppat2;
1926 + PHY_LE32 eq_eye3;
1927 + //0xe0
1928 + PHY_LE32 kband_out;
1929 + PHY_LE32 kband_out1;
1930 +};
1931 +
1932 +//U3D_PHYD_MIX0
1933 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1934 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1935 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1936 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1937 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1938 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1939 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1940 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1941 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1942 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1943 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1944 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1945 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1946 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1947 +
1948 +//U3D_PHYD_MIX1
1949 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1950 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1951 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1952 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1953 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1954 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1955 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1956 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1957 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1958 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1959 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1960 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1961 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1962 +
1963 +//U3D_PHYD_LFPS0
1964 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1965 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1966 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1967 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1968 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1969 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1970 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1971 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1972 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1973 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1974 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1975 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1976 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1977 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1978 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1979 +
1980 +//U3D_PHYD_LFPS1
1981 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1982 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1983 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
1984 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
1985 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
1986 +
1987 +//U3D_PHYD_IMPCAL0
1988 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
1989 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
1990 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
1991 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
1992 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
1993 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
1994 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1995 +
1996 +//U3D_PHYD_IMPCAL1
1997 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
1998 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
1999 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
2000 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
2001 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
2002 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
2003 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
2004 +
2005 +//U3D_PHYD_TXPLL0
2006 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
2007 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
2008 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
2009 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
2010 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
2011 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
2012 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
2013 +
2014 +//U3D_PHYD_TXPLL1
2015 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
2016 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
2017 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
2018 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
2019 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
2020 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
2021 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
2022 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
2023 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
2024 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
2025 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2026 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2027 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2028 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2029 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2030 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2031 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2032 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2033 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2034 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2035 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2036 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2037 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2038 +
2039 +//U3D_PHYD_TXPLL2
2040 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2041 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2042 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2043 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2044 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2045 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2046 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2047 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2048 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2049 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2050 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2051 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2052 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2053 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2054 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2055 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2056 +
2057 +//U3D_PHYD_FL0
2058 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2059 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2060 +
2061 +//U3D_PHYD_MIX2
2062 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2063 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2064 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2065 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2066 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2067 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2068 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2069 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2070 +
2071 +//U3D_PHYD_RX0
2072 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2073 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2074 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2075 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2076 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2077 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2078 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2079 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2080 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2081 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2082 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2083 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2084 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2085 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2086 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2087 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2088 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2089 +
2090 +//U3D_PHYD_T2RLB
2091 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2092 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2093 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2094 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2095 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2096 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2097 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2098 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2099 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2100 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2101 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2102 +
2103 +//U3D_PHYD_CPPAT
2104 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2105 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2106 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2107 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2108 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2109 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2110 +
2111 +//U3D_PHYD_MIX3
2112 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2113 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2114 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2115 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2116 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2117 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2118 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2119 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2120 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2121 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2122 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2123 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2124 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2125 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2126 +
2127 +//U3D_PHYD_EBUFCTL
2128 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2129 +
2130 +//U3D_PHYD_PIPE0
2131 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2132 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2133 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2134 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2135 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2136 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2137 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2138 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2139 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2140 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2141 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2142 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2143 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2144 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2145 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2146 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2147 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2148 +
2149 +//U3D_PHYD_PIPE1
2150 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2151 +
2152 +//U3D_PHYD_MIX4
2153 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2154 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2155 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2156 +
2157 +//U3D_PHYD_CKGEN0
2158 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2159 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2160 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2161 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2162 +
2163 +//U3D_PHYD_MIX5
2164 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2165 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2166 +
2167 +//U3D_PHYD_RESERVED
2168 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2169 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2170 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2171 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2172 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2173 +
2174 +//U3D_PHYD_CDR0
2175 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2176 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2177 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2178 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2179 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2180 +
2181 +//U3D_PHYD_CDR1
2182 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2183 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2184 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2185 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2186 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2187 +
2188 +//U3D_PHYD_PLL_0
2189 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2190 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2191 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2192 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2193 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2194 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2195 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2196 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2197 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2198 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2199 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2200 +
2201 +//U3D_PHYD_PLL_1
2202 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2203 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2204 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2205 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2206 +
2207 +//U3D_PHYD_BCN_DET_1
2208 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2209 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2210 +
2211 +//U3D_PHYD_BCN_DET_2
2212 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2213 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2214 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2215 +
2216 +//U3D_EQ0
2217 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2218 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2219 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2220 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2221 +
2222 +//U3D_EQ1
2223 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2224 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2225 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2226 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2227 +
2228 +//U3D_EQ2
2229 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2230 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2231 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2232 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2233 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2234 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2235 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2236 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2237 +
2238 +//U3D_EQ3
2239 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2240 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2241 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2242 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2243 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2244 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2245 +
2246 +//U3D_EQ_EYE0
2247 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2248 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2249 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2250 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2251 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2252 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2253 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2254 +
2255 +//U3D_EQ_EYE1
2256 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2257 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2258 +
2259 +//U3D_EQ_EYE2
2260 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2261 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2262 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2263 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2264 +
2265 +//U3D_EQ_DFE0
2266 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2267 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2268 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2269 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2270 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2271 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2272 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2273 +
2274 +//U3D_EQ_DFE1
2275 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2276 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2277 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2278 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2279 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2280 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2281 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2282 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2283 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2284 +
2285 +//U3D_EQ_DFE2
2286 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2287 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2288 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2289 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2290 +
2291 +//U3D_EQ_DFE3
2292 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2293 +
2294 +//U3D_PHYD_MON0
2295 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2296 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2297 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2298 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2299 +
2300 +//U3D_PHYD_MON1
2301 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2302 +
2303 +//U3D_PHYD_MON2
2304 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2305 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2306 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2307 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2308 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2309 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2310 +
2311 +//U3D_PHYD_MON3
2312 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2313 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2314 +
2315 +//U3D_PHYD_MON4
2316 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2317 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2318 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2319 +
2320 +//U3D_PHYD_MON5
2321 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2322 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2323 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2324 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2325 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2326 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2327 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2328 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2329 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2330 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2331 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2332 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2333 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2334 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2335 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2336 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2337 +
2338 +//U3D_PHYD_MON6
2339 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2340 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2341 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2342 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2343 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2344 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2345 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2346 +
2347 +//U3D_PHYD_MON7
2348 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2349 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2350 +
2351 +//U3D_PHYA_RX_MON0
2352 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2353 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2354 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2355 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2356 +
2357 +//U3D_PHYA_RX_MON1
2358 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2359 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2360 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2361 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2362 +
2363 +//U3D_PHYA_RX_MON2
2364 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2365 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2366 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2367 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2368 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2369 +
2370 +//U3D_PHYA_RX_MON3
2371 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2372 +
2373 +//U3D_PHYA_RX_MON4
2374 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2375 +
2376 +//U3D_PHYA_RX_MON5
2377 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2378 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2379 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2380 +
2381 +//U3D_PHYD_CPPAT2
2382 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2383 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2384 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2385 +
2386 +//U3D_EQ_EYE3
2387 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2388 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2389 +
2390 +//U3D_KBAND_OUT
2391 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2392 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2393 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2394 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2395 +
2396 +//U3D_KBAND_OUT1
2397 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2398 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2399 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2400 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2401 +
2402 +
2403 +/* OFFSET */
2404 +
2405 +//U3D_PHYD_MIX0
2406 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2407 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2408 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2409 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2410 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2411 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2412 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2413 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2414 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2415 +#define RG_SSUSB_PRBS_EN_OFST (13)
2416 +#define RG_SSUSB_BPSLOCK_OFST (12)
2417 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2418 +#define RG_SSUSB_COMCNT_OFST (4)
2419 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2420 +
2421 +//U3D_PHYD_MIX1
2422 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2423 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2424 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2425 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2426 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2427 +#define RG_SSUSB_PDNCTL_OFST (16)
2428 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2429 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2430 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2431 +#define RG_SSUSB_BERT_EN_OFST (7)
2432 +#define RG_SSUSB_SCP_TH_OFST (4)
2433 +#define RG_SSUSB_SCP_EN_OFST (3)
2434 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2435 +
2436 +//U3D_PHYD_LFPS0
2437 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2438 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2439 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2440 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2441 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2442 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2443 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2444 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2445 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2446 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2447 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2448 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2449 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2450 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2451 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2452 +
2453 +//U3D_PHYD_LFPS1
2454 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2455 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2456 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2457 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2458 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2459 +
2460 +//U3D_PHYD_IMPCAL0
2461 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2462 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2463 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2464 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2465 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2466 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2467 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2468 +
2469 +//U3D_PHYD_IMPCAL1
2470 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2471 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2472 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2473 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2474 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2475 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2476 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2477 +
2478 +//U3D_PHYD_TXPLL0
2479 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2480 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2481 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2482 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2483 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2484 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2485 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2486 +
2487 +//U3D_PHYD_TXPLL1
2488 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2489 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2490 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2491 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2492 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2493 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2494 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2495 +#define RG_SSUSB_PLL_PWD_OFST (23)
2496 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2497 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2498 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2499 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2500 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2501 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2502 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2503 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2504 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2505 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2506 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2507 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2508 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2509 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2510 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2511 +
2512 +//U3D_PHYD_TXPLL2
2513 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2514 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2515 +#define RG_SSUSB_TX_LFPS_OFST (29)
2516 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2517 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2518 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2519 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2520 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2521 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2522 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2523 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2524 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2525 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2526 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2527 +#define RG_SSUSB_CDR_PWD_OFST (6)
2528 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2529 +
2530 +//U3D_PHYD_FL0
2531 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2532 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2533 +
2534 +//U3D_PHYD_MIX2
2535 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2536 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2537 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2538 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2539 +#define RG_SSUSB_CDROS_EN_OFST (18)
2540 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2541 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2542 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2543 +
2544 +//U3D_PHYD_RX0
2545 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2546 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2547 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2548 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2549 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2550 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2551 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2552 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2553 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2554 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2555 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2556 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2557 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2558 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2559 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2560 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2561 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2562 +
2563 +//U3D_PHYD_T2RLB
2564 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2565 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2566 +#define RG_SSUSB_BPANSIENC_OFST (26)
2567 +#define RG_SSUSB_VALID_EN_OFST (25)
2568 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2569 +#define RG_SSUSB_K_EMP_OFST (20)
2570 +#define RG_SSUSB_K_FUL_OFST (16)
2571 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2572 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2573 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2574 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2575 +
2576 +//U3D_PHYD_CPPAT
2577 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2578 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2579 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2580 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2581 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2582 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2583 +
2584 +//U3D_PHYD_MIX3
2585 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2586 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2587 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2588 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2589 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2590 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2591 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2592 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2593 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2594 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2595 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2596 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2597 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2598 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2599 +
2600 +//U3D_PHYD_EBUFCTL
2601 +#define RG_SSUSB_EBUFCTL_OFST (0)
2602 +
2603 +//U3D_PHYD_PIPE0
2604 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2605 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2606 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2607 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2608 +#define RG_SSUSB_POWERDOWN_OFST (24)
2609 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2610 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2611 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2612 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2613 +#define RG_SSUSB_TXDATAK_OFST (16)
2614 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2615 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2616 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2617 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2618 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2619 +#define RG_SSUSB_TXMARGIN_OFST (1)
2620 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2621 +
2622 +//U3D_PHYD_PIPE1
2623 +#define RG_SSUSB_TXDATA_OFST (0)
2624 +
2625 +//U3D_PHYD_MIX4
2626 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2627 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2628 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2629 +
2630 +//U3D_PHYD_CKGEN0
2631 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2632 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2633 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2634 +#define RG_SSUSB_RXCK_INV_OFST (0)
2635 +
2636 +//U3D_PHYD_MIX5
2637 +#define RG_SSUSB_PRB_SEL_OFST (16)
2638 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2639 +
2640 +//U3D_PHYD_RESERVED
2641 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2642 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2643 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2644 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2645 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2646 +
2647 +//U3D_PHYD_CDR0
2648 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2649 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2650 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2651 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2652 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2653 +
2654 +//U3D_PHYD_CDR1
2655 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2656 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2657 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2658 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2659 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2660 +
2661 +//U3D_PHYD_PLL_0
2662 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2663 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2664 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2665 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2666 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2667 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2668 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2669 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2670 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2671 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2672 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2673 +
2674 +//U3D_PHYD_PLL_1
2675 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2676 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2677 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2678 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2679 +
2680 +//U3D_PHYD_BCN_DET_1
2681 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2682 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2683 +
2684 +//U3D_PHYD_BCN_DET_2
2685 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2686 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2687 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2688 +
2689 +//U3D_EQ0
2690 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2691 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2692 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2693 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2694 +
2695 +//U3D_EQ1
2696 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2697 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2698 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2699 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2700 +
2701 +//U3D_EQ2
2702 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2703 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2704 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2705 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2706 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2707 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2708 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2709 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2710 +
2711 +//U3D_EQ3
2712 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2713 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2714 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2715 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2716 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2717 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2718 +
2719 +//U3D_EQ_EYE0
2720 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2721 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2722 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2723 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2724 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2725 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2726 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2727 +
2728 +//U3D_EQ_EYE1
2729 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2730 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2731 +
2732 +//U3D_EQ_EYE2
2733 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2734 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2735 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2736 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2737 +
2738 +//U3D_EQ_DFE0
2739 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2740 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2741 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2742 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2743 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2744 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2745 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2746 +
2747 +//U3D_EQ_DFE1
2748 +#define RG_SSUSB_EQ_REV_OFST (16)
2749 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2750 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2751 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2752 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2753 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2754 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2755 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2756 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2757 +
2758 +//U3D_EQ_DFE2
2759 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2760 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2761 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2762 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2763 +
2764 +//U3D_EQ_DFE3
2765 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2766 +
2767 +//U3D_PHYD_MON0
2768 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2769 +#define RGS_SSUSB_LFPS_OFST (12)
2770 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2771 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2772 +
2773 +//U3D_PHYD_MON1
2774 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2775 +
2776 +//U3D_PHYD_MON2
2777 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2778 +#define RGS_SSUSB_RETRACK_OFST (12)
2779 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2780 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2781 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2782 +#define RGS_SSUSB_PDNCTL_OFST (0)
2783 +
2784 +//U3D_PHYD_MON3
2785 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2786 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2787 +
2788 +//U3D_PHYD_MON4
2789 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2790 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2791 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2792 +
2793 +//U3D_PHYD_MON5
2794 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2795 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2796 +#define RGS_SSUSB_SCP_DET_OFST (14)
2797 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2798 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2799 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2800 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2801 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2802 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2803 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2804 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2805 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2806 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2807 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2808 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2809 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2810 +
2811 +//U3D_PHYD_MON6
2812 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2813 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2814 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2815 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2816 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2817 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2818 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2819 +
2820 +//U3D_PHYD_MON7
2821 +#define RGS_SSUSB_FT_OUT_OFST (8)
2822 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2823 +
2824 +//U3D_PHYA_RX_MON0
2825 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2826 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2827 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2828 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2829 +
2830 +//U3D_PHYA_RX_MON1
2831 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2832 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2833 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2834 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2835 +
2836 +//U3D_PHYA_RX_MON2
2837 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2838 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2839 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2840 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2841 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2842 +
2843 +//U3D_PHYA_RX_MON3
2844 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2845 +
2846 +//U3D_PHYA_RX_MON4
2847 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2848 +
2849 +//U3D_PHYA_RX_MON5
2850 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2851 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2852 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2853 +
2854 +//U3D_PHYD_CPPAT2
2855 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2856 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2857 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2858 +
2859 +//U3D_EQ_EYE3
2860 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2861 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2862 +
2863 +//U3D_KBAND_OUT
2864 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2865 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2866 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2867 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2868 +
2869 +//U3D_KBAND_OUT1
2870 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2871 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2872 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2873 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2874 +
2875 +
2876 +///////////////////////////////////////////////////////////////////////////////
2877 +
2878 +struct u3phyd_bank2_reg {
2879 + //0x0
2880 + PHY_LE32 b2_phyd_top1;
2881 + PHY_LE32 b2_phyd_top2;
2882 + PHY_LE32 b2_phyd_top3;
2883 + PHY_LE32 b2_phyd_top4;
2884 + //0x10
2885 + PHY_LE32 b2_phyd_top5;
2886 + PHY_LE32 b2_phyd_top6;
2887 + PHY_LE32 b2_phyd_top7;
2888 + PHY_LE32 b2_phyd_p_sigdet1;
2889 + //0x20
2890 + PHY_LE32 b2_phyd_p_sigdet2;
2891 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2892 + PHY_LE32 b2_phyd_rxdet1;
2893 + PHY_LE32 b2_phyd_rxdet2;
2894 + //0x30
2895 + PHY_LE32 b2_phyd_misc0;
2896 + PHY_LE32 b2_phyd_misc2;
2897 + PHY_LE32 b2_phyd_misc3;
2898 + PHY_LE32 reserve0;
2899 + //0x40
2900 + PHY_LE32 b2_rosc_0;
2901 + PHY_LE32 b2_rosc_1;
2902 + PHY_LE32 b2_rosc_2;
2903 + PHY_LE32 b2_rosc_3;
2904 + //0x50
2905 + PHY_LE32 b2_rosc_4;
2906 + PHY_LE32 b2_rosc_5;
2907 + PHY_LE32 b2_rosc_6;
2908 + PHY_LE32 b2_rosc_7;
2909 + //0x60
2910 + PHY_LE32 b2_rosc_8;
2911 + PHY_LE32 b2_rosc_9;
2912 + PHY_LE32 b2_rosc_a;
2913 + PHY_LE32 reserve1;
2914 + //0x70~0xd0
2915 + PHY_LE32 reserve2[28];
2916 + //0xe0
2917 + PHY_LE32 phyd_version;
2918 + PHY_LE32 phyd_model;
2919 +};
2920 +
2921 +//U3D_B2_PHYD_TOP1
2922 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2923 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2924 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2925 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2926 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2927 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2928 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2929 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2930 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2931 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2932 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2933 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2934 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2935 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2936 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2937 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2938 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2939 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2940 +
2941 +//U3D_B2_PHYD_TOP2
2942 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2943 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2944 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2945 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2946 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2947 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2948 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2949 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2950 +
2951 +//U3D_B2_PHYD_TOP3
2952 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2953 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2954 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2955 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2956 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2957 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2958 +
2959 +//U3D_B2_PHYD_TOP4
2960 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2961 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2962 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2963 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2964 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2965 +
2966 +//U3D_B2_PHYD_TOP5
2967 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2968 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2969 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2970 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2971 +
2972 +//U3D_B2_PHYD_TOP6
2973 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2974 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2975 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2976 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2977 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2978 +
2979 +//U3D_B2_PHYD_TOP7
2980 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2981 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2982 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2983 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
2984 +
2985 +//U3D_B2_PHYD_P_SIGDET1
2986 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
2987 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2988 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2989 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
2990 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
2991 +
2992 +//U3D_B2_PHYD_P_SIGDET2
2993 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
2994 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
2995 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
2996 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
2997 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
2998 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
2999 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
3000 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
3001 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
3002 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
3003 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
3004 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
3005 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
3006 +
3007 +//U3D_B2_PHYD_P_SIGDET_CAL1
3008 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
3009 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
3010 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
3011 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
3012 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
3013 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
3014 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
3015 +
3016 +//U3D_B2_PHYD_RXDET1
3017 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
3018 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
3019 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
3020 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
3021 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
3022 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
3023 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
3024 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3025 +
3026 +//U3D_B2_PHYD_RXDET2
3027 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3028 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3029 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3030 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3031 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3032 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3033 +
3034 +//U3D_B2_PHYD_MISC0
3035 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3036 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3037 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3038 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3039 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3040 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3041 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3042 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3043 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3044 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3045 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3046 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3047 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3048 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3049 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3050 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3051 +
3052 +//U3D_B2_PHYD_MISC2
3053 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3054 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3055 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3056 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3057 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3058 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3059 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3060 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3061 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3062 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3063 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3064 +
3065 +//U3D_B2_PHYD_MISC3
3066 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3067 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3068 +
3069 +//U3D_B2_ROSC_0
3070 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3071 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3072 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3073 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3074 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3075 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3076 +
3077 +//U3D_B2_ROSC_1
3078 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3079 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3080 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3081 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3082 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3083 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3084 +
3085 +//U3D_B2_ROSC_2
3086 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3087 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3088 +
3089 +//U3D_B2_ROSC_3
3090 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3091 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3092 +
3093 +//U3D_B2_ROSC_4
3094 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3095 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3096 +
3097 +//U3D_B2_ROSC_5
3098 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3099 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3100 +
3101 +//U3D_B2_ROSC_6
3102 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3103 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3104 +
3105 +//U3D_B2_ROSC_7
3106 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3107 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3108 +
3109 +//U3D_B2_ROSC_8
3110 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3111 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3112 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3113 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3114 +
3115 +//U3D_B2_ROSC_9
3116 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3117 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3118 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3119 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3120 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3121 +
3122 +//U3D_B2_ROSC_A
3123 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3124 +
3125 +//U3D_PHYD_VERSION
3126 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3127 +
3128 +//U3D_PHYD_MODEL
3129 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3130 +
3131 +
3132 +/* OFFSET */
3133 +
3134 +//U3D_B2_PHYD_TOP1
3135 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3136 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3137 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3138 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3139 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3140 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3141 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3142 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3143 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3144 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3145 +#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
3146 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
3147 +#define RG_SSUSB_RATE_OFST (6)
3148 +#define RG_SSUSB_FORCE_RATE_OFST (5)
3149 +#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
3150 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
3151 +#define RG_SSUSB_PHY_MODE_OFST (1)
3152 +#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
3153 +
3154 +//U3D_B2_PHYD_TOP2
3155 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
3156 +#define RG_SSUSB_IDRV_6DB_OFST (24)
3157 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
3158 +#define RG_SSUSB_IDEM_3P5DB_OFST (16)
3159 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
3160 +#define RG_SSUSB_IDRV_3P5DB_OFST (8)
3161 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
3162 +#define RG_SSUSB_IDRV_0DB_OFST (0)
3163 +
3164 +//U3D_B2_PHYD_TOP3
3165 +#define RG_SSUSB_TX_BIASI_OFST (25)
3166 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
3167 +#define RG_SSUSB_TX_BIASI_EN_OFST (16)
3168 +#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
3169 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
3170 +#define RG_SSUSB_IDEM_6DB_OFST (0)
3171 +
3172 +//U3D_B2_PHYD_TOP4
3173 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
3174 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
3175 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
3176 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
3177 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
3178 +
3179 +//U3D_B2_PHYD_TOP5
3180 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
3181 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
3182 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
3183 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
3184 +
3185 +//U3D_B2_PHYD_TOP6
3186 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
3187 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
3188 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
3189 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
3190 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
3191 +
3192 +//U3D_B2_PHYD_TOP7
3193 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
3194 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
3195 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
3196 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
3197 +
3198 +//U3D_B2_PHYD_P_SIGDET1
3199 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
3200 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
3201 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
3202 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
3203 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
3204 +
3205 +//U3D_B2_PHYD_P_SIGDET2
3206 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
3207 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
3208 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
3209 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
3210 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
3211 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
3212 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
3213 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
3214 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
3215 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
3216 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
3217 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
3218 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
3219 +
3220 +//U3D_B2_PHYD_P_SIGDET_CAL1
3221 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
3222 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
3223 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
3224 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
3225 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
3226 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
3227 +#define RG_SSUSB_P_SIGDET_REK_OFST (0)
3228 +
3229 +//U3D_B2_PHYD_RXDET1
3230 +#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
3231 +#define RG_SSUSB_FORCE_CMDET_OFST (30)
3232 +#define RG_SSUSB_RXDET_EN_OFST (29)
3233 +#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
3234 +#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
3235 +#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
3236 +#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
3237 +#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
3238 +
3239 +//U3D_B2_PHYD_RXDET2
3240 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
3241 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
3242 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
3243 +#define RG_SSUSB_PDN_T_SEL_OFST (18)
3244 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
3245 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
3246 +
3247 +//U3D_B2_PHYD_MISC0
3248 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
3249 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
3250 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
3251 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
3252 +#define RG_SSUSB_LFPS_PSEL_OFST (15)
3253 +#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
3254 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
3255 +#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
3256 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
3257 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
3258 +#define RG_SSUSB_T2RLB_PSEL_OFST (8)
3259 +#define RG_SSUSB_PPCTL_PSEL_OFST (5)
3260 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
3261 +#define RG_SSUSB_BERTLB_PSEL_OFST (2)
3262 +#define RG_SSUSB_RETRACK_DIS_OFST (1)
3263 +#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
3264 +
3265 +//U3D_B2_PHYD_MISC2
3266 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
3267 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
3268 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
3269 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
3270 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
3271 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
3272 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
3273 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
3274 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
3275 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
3276 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
3277 +
3278 +//U3D_B2_PHYD_MISC3
3279 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
3280 +#define RGS_SSUSB_PPERRCNT_OFST (0)
3281 +
3282 +//U3D_B2_ROSC_0
3283 +#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
3284 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
3285 +#define RG_SSUSB_RING_OSC_EN_OFST (3)
3286 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
3287 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
3288 +#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
3289 +
3290 +//U3D_B2_ROSC_1
3291 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
3292 +#define RG_SSUSB_RING_OSC_P3_OFST (19)
3293 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
3294 +#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
3295 +#define RG_SSUSB_RING_OSC_SEL_OFST (8)
3296 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
3297 +
3298 +//U3D_B2_ROSC_2
3299 +#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
3300 +#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
3301 +
3302 +//U3D_B2_ROSC_3
3303 +#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
3304 +#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
3305 +
3306 +//U3D_B2_ROSC_4
3307 +#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
3308 +#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
3309 +
3310 +//U3D_B2_ROSC_5
3311 +#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
3312 +#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
3313 +
3314 +//U3D_B2_ROSC_6
3315 +#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
3316 +#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
3317 +
3318 +//U3D_B2_ROSC_7
3319 +#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
3320 +#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
3321 +
3322 +//U3D_B2_ROSC_8
3323 +#define RG_SSUSB_RING_RESERVE_OFST (16)
3324 +#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
3325 +#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
3326 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
3327 +
3328 +//U3D_B2_ROSC_9
3329 +#define RGS_FM_RING_CNT_OFST (16)
3330 +#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
3331 +#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
3332 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
3333 +#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
3334 +
3335 +//U3D_B2_ROSC_A
3336 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
3337 +
3338 +//U3D_PHYD_VERSION
3339 +#define RGS_SSUSB_PHYD_VERSION_OFST (0)
3340 +
3341 +//U3D_PHYD_MODEL
3342 +#define RGS_SSUSB_PHYD_MODEL_OFST (0)
3343 +
3344 +
3345 +///////////////////////////////////////////////////////////////////////////////
3346 +
3347 +struct sifslv_chip_reg {
3348 + PHY_LE32 xtalbias;
3349 + PHY_LE32 syspll1;
3350 + PHY_LE32 gpio_ctla;
3351 + PHY_LE32 gpio_ctlb;
3352 + PHY_LE32 gpio_ctlc;
3353 +};
3354 +
3355 +//U3D_GPIO_CTLA
3356 +#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
3357 +
3358 +//U3D_GPIO_CTLB
3359 +#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
3360 +
3361 +//U3D_GPIO_CTLC
3362 +#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
3363 +
3364 +/* OFFSET */
3365 +
3366 +//U3D_GPIO_CTLA
3367 +#define RG_C60802_GPIO_CTLA_OFST (0)
3368 +
3369 +//U3D_GPIO_CTLB
3370 +#define RG_C60802_GPIO_CTLB_OFST (0)
3371 +
3372 +//U3D_GPIO_CTLC
3373 +#define RG_C60802_GPIO_CTLC_OFST (0)
3374 +
3375 +///////////////////////////////////////////////////////////////////////////////
3376 +
3377 +struct sifslv_fm_feg {
3378 + //0x0
3379 + PHY_LE32 fmcr0;
3380 + PHY_LE32 fmcr1;
3381 + PHY_LE32 fmcr2;
3382 + PHY_LE32 fmmonr0;
3383 + //0x10
3384 + PHY_LE32 fmmonr1;
3385 +};
3386 +
3387 +//U3D_FMCR0
3388 +#define RG_LOCKTH (0xf<<28) //31:28
3389 +#define RG_MONCLK_SEL (0x3<<26) //27:26
3390 +#define RG_FM_MODE (0x1<<25) //25:25
3391 +#define RG_FREQDET_EN (0x1<<24) //24:24
3392 +#define RG_CYCLECNT (0xffffff<<0) //23:0
3393 +
3394 +//U3D_FMCR1
3395 +#define RG_TARGET (0xffffffff<<0) //31:0
3396 +
3397 +//U3D_FMCR2
3398 +#define RG_OFFSET (0xffffffff<<0) //31:0
3399 +
3400 +//U3D_FMMONR0
3401 +#define USB_FM_OUT (0xffffffff<<0) //31:0
3402 +
3403 +//U3D_FMMONR1
3404 +#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
3405 +#define RG_FRCK_EN (0x1<<8) //8:8
3406 +#define USBPLL_LOCK (0x1<<1) //1:1
3407 +#define USB_FM_VLD (0x1<<0) //0:0
3408 +
3409 +
3410 +/* OFFSET */
3411 +
3412 +//U3D_FMCR0
3413 +#define RG_LOCKTH_OFST (28)
3414 +#define RG_MONCLK_SEL_OFST (26)
3415 +#define RG_FM_MODE_OFST (25)
3416 +#define RG_FREQDET_EN_OFST (24)
3417 +#define RG_CYCLECNT_OFST (0)
3418 +
3419 +//U3D_FMCR1
3420 +#define RG_TARGET_OFST (0)
3421 +
3422 +//U3D_FMCR2
3423 +#define RG_OFFSET_OFST (0)
3424 +
3425 +//U3D_FMMONR0
3426 +#define USB_FM_OUT_OFST (0)
3427 +
3428 +//U3D_FMMONR1
3429 +#define RG_MONCLK_SEL_3_OFST (9)
3430 +#define RG_FRCK_EN_OFST (8)
3431 +#define USBPLL_LOCK_OFST (1)
3432 +#define USB_FM_VLD_OFST (0)
3433 +
3434 +
3435 +///////////////////////////////////////////////////////////////////////////////
3436 +
3437 +PHY_INT32 phy_init(struct u3phy_info *info);
3438 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3439 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3440 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3441 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3442 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3443 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3444 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3445 +
3446 +#endif
3447 +#endif
3448 --- /dev/null
3449 +++ b/drivers/usb/host/mtk-phy-ahb.c
3450 @@ -0,0 +1,58 @@
3451 +#include "mtk-phy.h"
3452 +#ifdef CONFIG_U3D_HAL_SUPPORT
3453 +#include "mu3d_hal_osal.h"
3454 +#endif
3455 +
3456 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3457 +#include <linux/gfp.h>
3458 +#include <linux/kernel.h>
3459 +#include <linux/slab.h>
3460 +
3461 +#ifndef CONFIG_U3D_HAL_SUPPORT
3462 +#define os_writel(addr,data) {\
3463 + (*((volatile PHY_UINT32*)(addr)) = data);\
3464 + }
3465 +#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
3466 +#define os_writelmsk(addr, data, msk) \
3467 + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3468 + }
3469 +#define os_setmsk(addr, msk) \
3470 + { os_writel(addr, os_readl(addr) | msk); \
3471 + }
3472 +#define os_clrmsk(addr, msk) \
3473 + { os_writel(addr, os_readl(addr) &~ msk); \
3474 + }
3475 +/*msk the data first, then umsk with the umsk.*/
3476 +#define os_writelmskumsk(addr, data, msk, umsk) \
3477 +{\
3478 + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3479 +}
3480 +
3481 +#endif
3482 +
3483 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3484 +{
3485 + os_writel(addr, data);
3486 +
3487 + return 0;
3488 +}
3489 +
3490 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3491 +{
3492 + return os_readl(addr);
3493 +}
3494 +
3495 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3496 +{
3497 + os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3498 +
3499 + return 0;
3500 +}
3501 +
3502 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3503 +{
3504 + return ((os_readl(addr)>>((addr%4)*8))&0xff);
3505 +}
3506 +
3507 +#endif
3508 +
3509 --- /dev/null
3510 +++ b/drivers/usb/host/mtk-phy.c
3511 @@ -0,0 +1,102 @@
3512 +#include <linux/gfp.h>
3513 +#include <linux/kernel.h>
3514 +#include <linux/slab.h>
3515 +#define U3_PHY_LIB
3516 +#include "mtk-phy.h"
3517 +#ifdef CONFIG_PROJECT_7621
3518 +#include "mtk-phy-7621.h"
3519 +#endif
3520 +#ifdef CONFIG_PROJECT_PHY
3521 +static struct u3phy_operator project_operators = {
3522 + .init = phy_init,
3523 + .change_pipe_phase = phy_change_pipe_phase,
3524 + .eyescan_init = eyescan_init,
3525 + .eyescan = phy_eyescan,
3526 + .u2_slew_rate_calibration = u2_slew_rate_calibration,
3527 +};
3528 +#endif
3529 +
3530 +
3531 +PHY_INT32 u3phy_init(){
3532 +#ifndef CONFIG_PROJECT_PHY
3533 + PHY_INT32 u3phy_version;
3534 +#endif
3535 +
3536 + if(u3phy != NULL){
3537 + return PHY_TRUE;
3538 + }
3539 +
3540 + u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3541 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3542 + u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3543 +#endif
3544 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3545 + u3phy->phyd_version_addr = 0x2000e4;
3546 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3547 + u3phy_p1->phyd_version_addr = 0x2000e4;
3548 +#endif
3549 +#else
3550 + u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3551 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3552 + u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3553 +#endif
3554 +#endif
3555 +
3556 +#ifdef CONFIG_PROJECT_PHY
3557 +
3558 + u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3559 + u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3560 + u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3561 + u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3562 + u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3563 + u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3564 + u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3565 + u3phy_ops = &project_operators;
3566 +
3567 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3568 + u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3569 + u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3570 + u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3571 + u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3572 + u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3573 + u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3574 + u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3575 +#endif
3576 +#endif
3577 +
3578 + return PHY_TRUE;
3579 +}
3580 +
3581 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3582 + PHY_INT8 cur_value;
3583 + PHY_INT8 new_value;
3584 +
3585 + cur_value = U3PhyReadReg8(addr);
3586 + new_value = (cur_value & (~mask)) | (value << offset);
3587 + //udelay(i2cdelayus);
3588 + U3PhyWriteReg8(addr, new_value);
3589 + return PHY_TRUE;
3590 +}
3591 +
3592 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3593 + PHY_INT32 cur_value;
3594 + PHY_INT32 new_value;
3595 +
3596 + cur_value = U3PhyReadReg32(addr);
3597 + new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3598 + U3PhyWriteReg32(addr, new_value);
3599 + //DRV_MDELAY(100);
3600 +
3601 + return PHY_TRUE;
3602 +}
3603 +
3604 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3605 +
3606 + return ((U3PhyReadReg8(addr) & mask) >> offset);
3607 +}
3608 +
3609 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3610 +
3611 + return ((U3PhyReadReg32(addr) & mask) >> offset);
3612 +}
3613 +
3614 --- /dev/null
3615 +++ b/drivers/usb/host/mtk-phy.h
3616 @@ -0,0 +1,179 @@
3617 +#ifndef __MTK_PHY_NEW_H
3618 +#define __MTK_PHY_NEW_H
3619 +
3620 +//#define CONFIG_U3D_HAL_SUPPORT
3621 +
3622 +/* include system library */
3623 +#include <linux/gfp.h>
3624 +#include <linux/kernel.h>
3625 +#include <linux/slab.h>
3626 +#include <linux/delay.h>
3627 +
3628 +/* Choose PHY R/W implementation */
3629 +//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
3630 +#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
3631 +
3632 +/* Choose PHY version */
3633 +//Select your project by defining one of the followings
3634 +#define CONFIG_PROJECT_7621 //7621
3635 +#define CONFIG_PROJECT_PHY
3636 +
3637 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3638 +#define PHY_BASE 0xBE1D0000
3639 +#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
3640 +#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
3641 +#define U2_PHY_BASE (PHY_BASE+0x800)
3642 +#define U3_PHYD_BASE (PHY_BASE+0x900)
3643 +#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
3644 +#define U3_PHYA_BASE (PHY_BASE+0xb00)
3645 +#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
3646 +
3647 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3648 +#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
3649 +#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
3650 +#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
3651 +#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
3652 +#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
3653 +#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
3654 +#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
3655 +#endif
3656 +
3657 +/*
3658 +
3659 +0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
3660 +0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
3661 +0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
3662 +0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
3663 +0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
3664 +0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
3665 +0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
3666 +*/
3667 +
3668 +
3669 +/* TYPE DEFINE */
3670 +typedef unsigned int PHY_UINT32;
3671 +typedef int PHY_INT32;
3672 +typedef unsigned short PHY_UINT16;
3673 +typedef short PHY_INT16;
3674 +typedef unsigned char PHY_UINT8;
3675 +typedef char PHY_INT8;
3676 +
3677 +typedef PHY_UINT32 __bitwise PHY_LE32;
3678 +
3679 +/* CONSTANT DEFINE */
3680 +#define PHY_FALSE 0
3681 +#define PHY_TRUE 1
3682 +
3683 +/* MACRO DEFINE */
3684 +#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3685 +#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
3686 +
3687 +#define DRV_MDELAY mdelay
3688 +#define DRV_MSLEEP msleep
3689 +#define DRV_UDELAY udelay
3690 +#define DRV_USLEEP usleep
3691 +
3692 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3693 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3694 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3695 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3696 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3697 +
3698 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3699 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3700 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3701 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3702 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3703 +
3704 +struct u3phy_info {
3705 + PHY_INT32 phy_version;
3706 + PHY_INT32 phyd_version_addr;
3707 +
3708 +#ifdef CONFIG_PROJECT_PHY
3709 + struct u2phy_reg *u2phy_regs;
3710 + struct u3phya_reg *u3phya_regs;
3711 + struct u3phya_da_reg *u3phya_da_regs;
3712 + struct u3phyd_reg *u3phyd_regs;
3713 + struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3714 + struct sifslv_chip_reg *sifslv_chip_regs;
3715 + struct sifslv_fm_feg *sifslv_fm_regs;
3716 +#endif
3717 +};
3718 +
3719 +struct u3phy_operator {
3720 + PHY_INT32 (*init) (struct u3phy_info *info);
3721 + PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3722 + PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3723 + PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3724 + PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3725 + PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3726 + PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3727 +};
3728 +
3729 +#ifdef U3_PHY_LIB
3730 +#define AUTOEXT
3731 +#else
3732 +#define AUTOEXT extern
3733 +#endif
3734 +
3735 +AUTOEXT struct u3phy_info *u3phy;
3736 +AUTOEXT struct u3phy_info *u3phy_p1;
3737 +AUTOEXT struct u3phy_operator *u3phy_ops;
3738 +
3739 +/*********eye scan required*********/
3740 +
3741 +#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
3742 +#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3743 +
3744 +typedef enum
3745 +{
3746 + SCAN_UP,
3747 + SCAN_DN
3748 +} enumScanDir;
3749 +
3750 +struct strucScanRegion
3751 +{
3752 + PHY_INT8 bX_tl;
3753 + PHY_INT8 bY_tl;
3754 + PHY_INT8 bX_br;
3755 + PHY_INT8 bY_br;
3756 + PHY_INT8 bDeltaX;
3757 + PHY_INT8 bDeltaY;
3758 +};
3759 +
3760 +struct strucTestCycle
3761 +{
3762 + PHY_UINT16 wEyeCnt;
3763 + PHY_INT8 bNumOfEyeCnt;
3764 + PHY_INT8 bPICalEn;
3765 + PHY_INT8 bNumOfIgnoreCnt;
3766 +};
3767 +
3768 +#define ERRCNT_MAX 128
3769 +#define CYCLE_COUNT_MAX 15
3770 +
3771 +/// the map resolution is 128 x 128 pts
3772 +#define MAX_X 127
3773 +#define MAX_Y 127
3774 +#define MIN_X 0
3775 +#define MIN_Y 0
3776 +
3777 +PHY_INT32 u3phy_init(void);
3778 +
3779 +AUTOEXT struct strucScanRegion _rEye1;
3780 +AUTOEXT struct strucScanRegion _rEye2;
3781 +AUTOEXT struct strucTestCycle _rTestCycle;
3782 +AUTOEXT PHY_UINT8 _bXcurr;
3783 +AUTOEXT PHY_UINT8 _bYcurr;
3784 +AUTOEXT enumScanDir _eScanDir;
3785 +AUTOEXT PHY_INT8 _fgXChged;
3786 +AUTOEXT PHY_INT8 _bPIResult;
3787 +/* use local variable instead to save memory use */
3788 +#if 0
3789 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3790 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3791 +#endif
3792 +
3793 +/***********************************/
3794 +#endif
3795 +
3796 --- a/drivers/usb/host/pci-quirks.h
3797 +++ b/drivers/usb/host/pci-quirks.h
3798 @@ -1,7 +1,7 @@
3799 #ifndef __LINUX_USB_PCI_QUIRKS_H
3800 #define __LINUX_USB_PCI_QUIRKS_H
3801
3802 -#ifdef CONFIG_PCI
3803 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3804 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3805 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3806 #endif /* CONFIG_PCI */
3807 --- a/drivers/usb/host/xhci-dbg.c
3808 +++ b/drivers/usb/host/xhci-dbg.c
3809 @@ -21,6 +21,9 @@
3810 */
3811
3812 #include "xhci.h"
3813 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3814 +#include "xhci-mtk.h"
3815 +#endif
3816
3817 #define XHCI_INIT_VALUE 0x0
3818
3819 --- a/drivers/usb/host/xhci-mem.c
3820 +++ b/drivers/usb/host/xhci-mem.c
3821 @@ -67,6 +67,9 @@ static struct xhci_segment *xhci_segment
3822
3823 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3824 {
3825 + if (!seg)
3826 + return;
3827 +
3828 if (seg->trbs) {
3829 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3830 seg->trbs = NULL;
3831 @@ -1375,9 +1378,17 @@ int xhci_endpoint_init(struct xhci_hcd *
3832 max_burst = (usb_endpoint_maxp(&ep->desc)
3833 & 0x1800) >> 11;
3834 }
3835 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3836 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3837 + max_packet += 2;
3838 +#endif
3839 break;
3840 case USB_SPEED_FULL:
3841 case USB_SPEED_LOW:
3842 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3843 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3844 + max_packet += 2;
3845 +#endif
3846 break;
3847 default:
3848 BUG();
3849 --- /dev/null
3850 +++ b/drivers/usb/host/xhci-mtk-power.c
3851 @@ -0,0 +1,115 @@
3852 +#include "xhci-mtk.h"
3853 +#include "xhci-mtk-power.h"
3854 +#include "xhci.h"
3855 +#include <linux/kernel.h> /* printk() */
3856 +#include <linux/slab.h>
3857 +#include <linux/delay.h>
3858 +
3859 +static int g_num_u3_port;
3860 +static int g_num_u2_port;
3861 +
3862 +
3863 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3864 + int i;
3865 + u32 port_id, temp;
3866 + u32 __iomem *addr;
3867 +
3868 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3869 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3870 +
3871 + for(i=1; i<=g_num_u3_port; i++){
3872 + port_id=i;
3873 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3874 + temp = readl(addr);
3875 + temp = xhci_port_state_to_neutral(temp);
3876 + temp |= PORT_POWER;
3877 + writel(temp, addr);
3878 + }
3879 + for(i=1; i<=g_num_u2_port; i++){
3880 + port_id=i+g_num_u3_port;
3881 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3882 + temp = readl(addr);
3883 + temp = xhci_port_state_to_neutral(temp);
3884 + temp |= PORT_POWER;
3885 + writel(temp, addr);
3886 + }
3887 +}
3888 +
3889 +void enableAllClockPower(){
3890 +
3891 + int i;
3892 + u32 temp;
3893 +
3894 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3895 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3896 +
3897 + //2. Enable xHC
3898 + writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3899 + writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3900 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3901 +
3902 + //1. Enable target ports
3903 + for(i=0; i<g_num_u3_port; i++){
3904 + temp = readl(SSUSB_U3_CTRL(i));
3905 + temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3906 + writel(temp, SSUSB_U3_CTRL(i));
3907 + }
3908 + for(i=0; i<g_num_u2_port; i++){
3909 + temp = readl(SSUSB_U2_CTRL(i));
3910 + temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3911 + writel(temp, SSUSB_U2_CTRL(i));
3912 + }
3913 + msleep(100);
3914 +}
3915 +
3916 +
3917 +//(X)disable clock/power of a port
3918 +//(X)if all ports are disabled, disable IP ctrl power
3919 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3920 +//and IP could be disable if suspended.
3921 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3922 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3923 +//port_index: port number
3924 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3925 +void disablePortClockPower(void){
3926 + int i;
3927 + u32 temp;
3928 +
3929 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3930 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3931 +
3932 + for(i=0; i<g_num_u3_port; i++){
3933 + temp = readl(SSUSB_U3_CTRL(i));
3934 + temp = temp | (SSUSB_U3_PORT_PDN);
3935 + writel(temp, SSUSB_U3_CTRL(i));
3936 + }
3937 + for(i=0; i<g_num_u2_port; i++){
3938 + temp = readl(SSUSB_U2_CTRL(i));
3939 + temp = temp | (SSUSB_U2_PORT_PDN);
3940 + writel(temp, SSUSB_U2_CTRL(i));
3941 + }
3942 + writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3943 +}
3944 +
3945 +//if IP ctrl power is disabled, enable it
3946 +//enable clock/power of a port
3947 +//port_index: port number
3948 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3949 +void enablePortClockPower(int port_index, int port_rev){
3950 + int i;
3951 + u32 temp;
3952 +
3953 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3954 +
3955 + if(port_rev == 0x3){
3956 + temp = readl(SSUSB_U3_CTRL(port_index));
3957 + temp = temp & (~SSUSB_U3_PORT_PDN);
3958 + writel(temp, SSUSB_U3_CTRL(port_index));
3959 + }
3960 + else if(port_rev == 0x2){
3961 + temp = readl(SSUSB_U2_CTRL(port_index));
3962 + temp = temp & (~SSUSB_U2_PORT_PDN);
3963 + writel(temp, SSUSB_U2_CTRL(port_index));
3964 + }
3965 +}
3966 +
3967 --- /dev/null
3968 +++ b/drivers/usb/host/xhci-mtk-power.h
3969 @@ -0,0 +1,13 @@
3970 +#ifndef _XHCI_MTK_POWER_H
3971 +#define _XHCI_MTK_POWER_H
3972 +
3973 +#include <linux/usb.h>
3974 +#include "xhci.h"
3975 +#include "xhci-mtk.h"
3976 +
3977 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3978 +void enableAllClockPower(void);
3979 +void disablePortClockPower(void);
3980 +void enablePortClockPower(int port_index, int port_rev);
3981 +
3982 +#endif
3983 --- /dev/null
3984 +++ b/drivers/usb/host/xhci-mtk-scheduler.c
3985 @@ -0,0 +1,608 @@
3986 +#include "xhci-mtk-scheduler.h"
3987 +#include <linux/kernel.h> /* printk() */
3988 +
3989 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
3990 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
3991 +static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
3992 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
3993 +
3994 +
3995 +int mtk_xhci_scheduler_init(void){
3996 + int i;
3997 +
3998 + for(i=0; i<MAX_EP_NUM; i++){
3999 + ss_out_eps[i] = NULL;
4000 + }
4001 + for(i=0; i<MAX_EP_NUM; i++){
4002 + ss_in_eps[i] = NULL;
4003 + }
4004 + for(i=0; i<MAX_EP_NUM; i++){
4005 + hs_eps[i] = NULL;
4006 + }
4007 + for(i=0; i<MAX_EP_NUM; i++){
4008 + tt_intr_eps[i] = NULL;
4009 + }
4010 + return 0;
4011 +}
4012 +
4013 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4014 + , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
4015 + , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
4016 +
4017 + struct sch_ep **ep_array;
4018 + int i;
4019 +
4020 + if(is_in && dev_speed == USB_SPEED_SUPER ){
4021 + ep_array = (struct sch_ep **)ss_in_eps;
4022 + }
4023 + else if(dev_speed == USB_SPEED_SUPER){
4024 + ep_array = (struct sch_ep **)ss_out_eps;
4025 + }
4026 + else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4027 + ep_array = (struct sch_ep **)hs_eps;
4028 + }
4029 + else{
4030 + ep_array = (struct sch_ep **)tt_intr_eps;
4031 + }
4032 + for(i=0; i<MAX_EP_NUM; i++){
4033 + if(ep_array[i] == NULL){
4034 + tmp_ep->dev_speed = dev_speed;
4035 + tmp_ep->isTT = isTT;
4036 + tmp_ep->is_in = is_in;
4037 + tmp_ep->ep_type = ep_type;
4038 + tmp_ep->maxp = maxp;
4039 + tmp_ep->interval = interval;
4040 + tmp_ep->burst = burst;
4041 + tmp_ep->mult = mult;
4042 + tmp_ep->offset = offset;
4043 + tmp_ep->repeat = repeat;
4044 + tmp_ep->pkts = pkts;
4045 + tmp_ep->cs_count = cs_count;
4046 + tmp_ep->burst_mode = burst_mode;
4047 + tmp_ep->bw_cost = bw_cost;
4048 + tmp_ep->ep = ep;
4049 + ep_array[i] = tmp_ep;
4050 + return SCH_SUCCESS;
4051 + }
4052 + }
4053 + return SCH_FAIL;
4054 +}
4055 +
4056 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4057 + , int td_size){
4058 + int i, j, k;
4059 + int bw_required[3];
4060 + int final_bw_required;
4061 + int bw_required_per_repeat;
4062 + int tmp_bw_required;
4063 + struct sch_ep *cur_sch_ep;
4064 + struct sch_ep **ep_array;
4065 + int cur_offset;
4066 + int cur_ep_offset;
4067 + int tmp_offset;
4068 + int tmp_interval;
4069 + int ep_offset;
4070 + int ep_interval;
4071 + int ep_repeat;
4072 + int ep_mult;
4073 +
4074 + if(is_in){
4075 + ep_array = (struct sch_ep **)ss_in_eps;
4076 + }
4077 + else{
4078 + ep_array = (struct sch_ep **)ss_out_eps;
4079 + }
4080 +
4081 + bw_required[0] = 0;
4082 + bw_required[1] = 0;
4083 + bw_required[2] = 0;
4084 +
4085 + if(repeat == 0){
4086 + final_bw_required = 0;
4087 + for(i=0; i<MAX_EP_NUM; i++){
4088 + cur_sch_ep = ep_array[i];
4089 + if(cur_sch_ep == NULL){
4090 + continue;
4091 + }
4092 + ep_interval = cur_sch_ep->interval;
4093 + ep_offset = cur_sch_ep->offset;
4094 + if(cur_sch_ep->repeat == 0){
4095 + if(ep_interval >= interval){
4096 + tmp_offset = ep_offset + ep_interval - offset;
4097 + tmp_interval = interval;
4098 + }
4099 + else{
4100 + tmp_offset = offset + interval - ep_offset;
4101 + tmp_interval = ep_interval;
4102 + }
4103 + if(tmp_offset % tmp_interval == 0){
4104 + final_bw_required += cur_sch_ep->bw_cost;
4105 + }
4106 + }
4107 + else{
4108 + ep_repeat = cur_sch_ep->repeat;
4109 + ep_mult = cur_sch_ep->mult;
4110 + for(k=0; k<=ep_mult; k++){
4111 + cur_ep_offset = ep_offset+(k*ep_mult);
4112 + if(ep_interval >= interval){
4113 + tmp_offset = cur_ep_offset + ep_interval - offset;
4114 + tmp_interval = interval;
4115 + }
4116 + else{
4117 + tmp_offset = offset + interval - cur_ep_offset;
4118 + tmp_interval = ep_interval;
4119 + }
4120 + if(tmp_offset % tmp_interval == 0){
4121 + final_bw_required += cur_sch_ep->bw_cost;
4122 + break;
4123 + }
4124 + }
4125 + }
4126 + }
4127 + final_bw_required += td_size;
4128 + }
4129 + else{
4130 + bw_required_per_repeat = maxp * (burst+1);
4131 + for(j=0; j<=mult; j++){
4132 + tmp_bw_required = 0;
4133 + cur_offset = offset+(j*repeat);
4134 + for(i=0; i<MAX_EP_NUM; i++){
4135 + cur_sch_ep = ep_array[i];
4136 + if(cur_sch_ep == NULL){
4137 + continue;
4138 + }
4139 + ep_interval = cur_sch_ep->interval;
4140 + ep_offset = cur_sch_ep->offset;
4141 + if(cur_sch_ep->repeat == 0){
4142 + if(ep_interval >= interval){
4143 + tmp_offset = ep_offset + ep_interval - cur_offset;
4144 + tmp_interval = interval;
4145 + }
4146 + else{
4147 + tmp_offset = cur_offset + interval - ep_offset;
4148 + tmp_interval = ep_interval;
4149 + }
4150 + if(tmp_offset % tmp_interval == 0){
4151 + tmp_bw_required += cur_sch_ep->bw_cost;
4152 + }
4153 + }
4154 + else{
4155 + ep_repeat = cur_sch_ep->repeat;
4156 + ep_mult = cur_sch_ep->mult;
4157 + for(k=0; k<=ep_mult; k++){
4158 + cur_ep_offset = ep_offset+(k*ep_repeat);
4159 + if(ep_interval >= interval){
4160 + tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4161 + tmp_interval = interval;
4162 + }
4163 + else{
4164 + tmp_offset = cur_offset + interval - cur_ep_offset;
4165 + tmp_interval = ep_interval;
4166 + }
4167 + if(tmp_offset % tmp_interval == 0){
4168 + tmp_bw_required += cur_sch_ep->bw_cost;
4169 + break;
4170 + }
4171 + }
4172 + }
4173 + }
4174 + bw_required[j] = tmp_bw_required;
4175 + }
4176 + final_bw_required = SS_BW_BOUND;
4177 + for(j=0; j<=mult; j++){
4178 + if(bw_required[j] < final_bw_required){
4179 + final_bw_required = bw_required[j];
4180 + }
4181 + }
4182 + final_bw_required += bw_required_per_repeat;
4183 + }
4184 + return final_bw_required;
4185 +}
4186 +
4187 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4188 + int i;
4189 + int bw_required;
4190 + struct sch_ep *cur_sch_ep;
4191 + int tmp_offset;
4192 + int tmp_interval;
4193 + int ep_offset;
4194 + int ep_interval;
4195 + int cur_tt_isoc_interval; //for isoc tt check
4196 +
4197 + bw_required = 0;
4198 + for(i=0; i<MAX_EP_NUM; i++){
4199 +
4200 + cur_sch_ep = (struct sch_ep *)hs_eps[i];
4201 + if(cur_sch_ep == NULL){
4202 + continue;
4203 + }
4204 + ep_offset = cur_sch_ep->offset;
4205 + ep_interval = cur_sch_ep->interval;
4206 +
4207 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4208 + cur_tt_isoc_interval = ep_interval<<3;
4209 + if(ep_interval >= interval){
4210 + tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4211 + tmp_interval = interval;
4212 + }
4213 + else{
4214 + tmp_offset = offset + interval - ep_offset;
4215 + tmp_interval = cur_tt_isoc_interval;
4216 + }
4217 + if(cur_sch_ep->is_in){
4218 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4219 + bw_required += 188;
4220 + }
4221 + }
4222 + else{
4223 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4224 + bw_required += 188;
4225 + }
4226 + }
4227 + }
4228 + else{
4229 + if(ep_interval >= interval){
4230 + tmp_offset = ep_offset + ep_interval - offset;
4231 + tmp_interval = interval;
4232 + }
4233 + else{
4234 + tmp_offset = offset + interval - ep_offset;
4235 + tmp_interval = ep_interval;
4236 + }
4237 + if(tmp_offset%tmp_interval == 0){
4238 + bw_required += cur_sch_ep->bw_cost;
4239 + }
4240 + }
4241 + }
4242 + bw_required += td_size;
4243 + return bw_required;
4244 +}
4245 +
4246 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4247 + char is_cs;
4248 + int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4249 + int bw_required, max_bw;
4250 + int ss_cs_count;
4251 + int cs_mframe;
4252 + int max_frame;
4253 + int i,j;
4254 + struct sch_ep *cur_sch_ep;
4255 + int ep_offset;
4256 + int ep_interval;
4257 + int ep_cs_count;
4258 + int tt_isoc_interval; //for isoc tt check
4259 + int cur_tt_isoc_interval; //for isoc tt check
4260 + int tmp_offset;
4261 + int tmp_interval;
4262 +
4263 + is_cs = 0;
4264 +
4265 + tt_isoc_interval = interval<<3; //frame to mframe
4266 + if(is_in){
4267 + is_cs = 1;
4268 + }
4269 + s_frame = offset/8;
4270 + s_mframe = offset%8;
4271 + ss_cs_count = (maxp + (188 - 1))/188;
4272 + if(is_cs){
4273 + cs_mframe = offset%8 + 2 + ss_cs_count;
4274 + if (cs_mframe <= 6)
4275 + ss_cs_count += 2;
4276 + else if (cs_mframe == 7)
4277 + ss_cs_count++;
4278 + else if (cs_mframe > 8)
4279 + return -1;
4280 + }
4281 + max_bw = 0;
4282 + if(is_in){
4283 + i=2;
4284 + }
4285 + for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4286 + bw_required = 0;
4287 + for(j=0; j<MAX_EP_NUM; j++){
4288 + cur_sch_ep = (struct sch_ep *)hs_eps[j];
4289 + if(cur_sch_ep == NULL){
4290 + continue;
4291 + }
4292 + ep_offset = cur_sch_ep->offset;
4293 + ep_interval = cur_sch_ep->interval;
4294 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4295 + //isoc tt
4296 + //check if mframe offset overlap
4297 + //if overlap, add 188 to the bw
4298 + cur_tt_isoc_interval = ep_interval<<3;
4299 + if(cur_tt_isoc_interval >= tt_isoc_interval){
4300 + tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
4301 + tmp_interval = tt_isoc_interval;
4302 + }
4303 + else{
4304 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4305 + tmp_interval = cur_tt_isoc_interval;
4306 + }
4307 + if(cur_sch_ep->is_in){
4308 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4309 + bw_required += 188;
4310 + }
4311 + }
4312 + else{
4313 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4314 + bw_required += 188;
4315 + }
4316 + }
4317 +
4318 + }
4319 + else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4320 + //check if mframe
4321 + if(ep_interval >= tt_isoc_interval){
4322 + tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4323 + tmp_interval = tt_isoc_interval;
4324 + }
4325 + else{
4326 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4327 + tmp_interval = ep_interval;
4328 + }
4329 + if(tmp_offset%tmp_interval == 0){
4330 + bw_required += cur_sch_ep->bw_cost;
4331 + }
4332 + }
4333 + }
4334 + bw_required += 188;
4335 + if(bw_required > max_bw){
4336 + max_bw = bw_required;
4337 + }
4338 + }
4339 + return max_bw;
4340 +}
4341 +
4342 +int count_tt_intr_bw(int interval, int frame_offset){
4343 + //check all eps in tt_intr_eps
4344 + int ret;
4345 + int i,j;
4346 + int ep_offset;
4347 + int ep_interval;
4348 + int tmp_offset;
4349 + int tmp_interval;
4350 + ret = SCH_SUCCESS;
4351 + struct sch_ep *cur_sch_ep;
4352 +
4353 + for(i=0; i<MAX_EP_NUM; i++){
4354 + cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4355 + if(cur_sch_ep == NULL){
4356 + continue;
4357 + }
4358 + ep_offset = cur_sch_ep->offset;
4359 + ep_interval = cur_sch_ep->interval;
4360 + if(ep_interval >= interval){
4361 + tmp_offset = ep_offset + ep_interval - frame_offset;
4362 + tmp_interval = interval;
4363 + }
4364 + else{
4365 + tmp_offset = frame_offset + interval - ep_offset;
4366 + tmp_interval = ep_interval;
4367 + }
4368 +
4369 + if(tmp_offset%tmp_interval==0){
4370 + return SCH_FAIL;
4371 + }
4372 + }
4373 + return SCH_SUCCESS;
4374 +}
4375 +
4376 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4377 + int i;
4378 + struct sch_ep **ep_array;
4379 + struct sch_ep *cur_ep;
4380 +
4381 + if (is_in && dev_speed == USB_SPEED_SUPER) {
4382 + ep_array = (struct sch_ep **)ss_in_eps;
4383 + }
4384 + else if (dev_speed == USB_SPEED_SUPER) {
4385 + ep_array = (struct sch_ep **)ss_out_eps;
4386 + }
4387 + else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4388 + ep_array = (struct sch_ep **)hs_eps;
4389 + }
4390 + else {
4391 + ep_array = (struct sch_ep **)tt_intr_eps;
4392 + }
4393 + for (i = 0; i < MAX_EP_NUM; i++) {
4394 + cur_ep = (struct sch_ep *)ep_array[i];
4395 + if(cur_ep != NULL && cur_ep->ep == ep){
4396 + ep_array[i] = NULL;
4397 + return cur_ep;
4398 + }
4399 + }
4400 + return NULL;
4401 +}
4402 +
4403 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4404 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4405 + mtk_u32 bPkts = 0;
4406 + mtk_u32 bCsCount = 0;
4407 + mtk_u32 bBm = 1;
4408 + mtk_u32 bOffset = 0;
4409 + mtk_u32 bRepeat = 0;
4410 + int ret;
4411 + struct mtk_xhci_ep_ctx *temp_ep_ctx;
4412 + int td_size;
4413 + int mframe_idx, frame_idx;
4414 + int bw_cost;
4415 + int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4416 + int cur_offset, cs_mframe;
4417 + int break_out;
4418 + int frame_interval;
4419 +
4420 + printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4421 + , interval, burst, mult, ep, ep_ctx, sch_ep);
4422 + if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4423 + frame_interval = interval >> 3;
4424 + for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4425 + printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4426 + if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4427 + printk(KERN_ERR "check OK............\n");
4428 + bOffset = frame_idx<<3;
4429 + bPkts = 1;
4430 + bCsCount = 3;
4431 + bw_cost = maxp;
4432 + bRepeat = 0;
4433 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4434 + , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4435 + return SCH_FAIL;
4436 + }
4437 + ret = SCH_SUCCESS;
4438 + break;
4439 + }
4440 + }
4441 + }
4442 + else if(isTT && ep_type == USB_EP_ISOC){
4443 + best_bw = HS_BW_BOUND;
4444 + best_bw_idx = -1;
4445 + cur_bw = 0;
4446 + td_size = maxp;
4447 + break_out = 0;
4448 + frame_interval = interval>>3;
4449 + for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4450 + for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4451 + cur_offset = (frame_idx*8) + mframe_idx;
4452 + cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4453 + if(cur_bw > 0 && cur_bw < best_bw){
4454 + best_bw_idx = cur_offset;
4455 + best_bw = cur_bw;
4456 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4457 + break_out = 1;
4458 + break;
4459 + }
4460 + }
4461 + }
4462 + }
4463 + if(best_bw_idx == -1){
4464 + return SCH_FAIL;
4465 + }
4466 + else{
4467 + bOffset = best_bw_idx;
4468 + bPkts = 1;
4469 + bCsCount = (maxp + (188 - 1)) / 188;
4470 + if(is_in){
4471 + cs_mframe = bOffset%8 + 2 + bCsCount;
4472 + if (cs_mframe <= 6)
4473 + bCsCount += 2;
4474 + else if (cs_mframe == 7)
4475 + bCsCount++;
4476 + }
4477 + bw_cost = 188;
4478 + bRepeat = 0;
4479 + if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4480 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4481 + return SCH_FAIL;
4482 + }
4483 + ret = SCH_SUCCESS;
4484 + }
4485 + }
4486 + else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4487 + bPkts = 1;
4488 + ret = SCH_SUCCESS;
4489 + }
4490 + else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4491 + bPkts = 1;
4492 + ret = SCH_SUCCESS;
4493 + }
4494 + else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4495 + best_bw = HS_BW_BOUND;
4496 + best_bw_idx = -1;
4497 + cur_bw = 0;
4498 + td_size = maxp*(burst+1);
4499 + for(cur_offset = 0; cur_offset<interval; cur_offset++){
4500 + cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4501 + if(cur_bw > 0 && cur_bw < best_bw){
4502 + best_bw_idx = cur_offset;
4503 + best_bw = cur_bw;
4504 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4505 + break;
4506 + }
4507 + }
4508 + }
4509 + if(best_bw_idx == -1){
4510 + return SCH_FAIL;
4511 + }
4512 + else{
4513 + bOffset = best_bw_idx;
4514 + bPkts = burst + 1;
4515 + bCsCount = 0;
4516 + bw_cost = td_size;
4517 + bRepeat = 0;
4518 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4519 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4520 + return SCH_FAIL;
4521 + }
4522 + ret = SCH_SUCCESS;
4523 + }
4524 + }
4525 + else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4526 + best_bw = SS_BW_BOUND;
4527 + best_bw_idx = -1;
4528 + cur_bw = 0;
4529 + td_size = maxp * (mult+1) * (burst+1);
4530 + if(mult == 0){
4531 + max_repeat = 0;
4532 + }
4533 + else{
4534 + max_repeat = (interval-1)/(mult+1);
4535 + }
4536 + break_out = 0;
4537 + for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4538 + for(repeat = max_repeat; repeat >= 0; repeat--){
4539 + cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4540 + , repeat, td_size);
4541 + printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4542 + , frame_idx, repeat, td_size, cur_bw);
4543 + if(cur_bw > 0 && cur_bw < best_bw){
4544 + best_bw_idx = frame_idx;
4545 + best_bw_repeat = repeat;
4546 + best_bw = cur_bw;
4547 + if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4548 + break_out = 1;
4549 + break;
4550 + }
4551 + }
4552 + }
4553 + }
4554 + printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4555 + if(best_bw_idx == -1){
4556 + return SCH_FAIL;
4557 + }
4558 + else{
4559 + bOffset = best_bw_idx;
4560 + bCsCount = 0;
4561 + bRepeat = best_bw_repeat;
4562 + if(bRepeat == 0){
4563 + bw_cost = (burst+1)*(mult+1)*maxp;
4564 + bPkts = (burst+1)*(mult+1);
4565 + }
4566 + else{
4567 + bw_cost = (burst+1)*maxp;
4568 + bPkts = (burst+1);
4569 + }
4570 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4571 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4572 + return SCH_FAIL;
4573 + }
4574 + ret = SCH_SUCCESS;
4575 + }
4576 + }
4577 + else{
4578 + bPkts = 1;
4579 + ret = SCH_SUCCESS;
4580 + }
4581 + if(ret == SCH_SUCCESS){
4582 + temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4583 + temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4584 + temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4585 +
4586 + printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4587 + printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4588 + return SCH_SUCCESS;
4589 + }
4590 + else{
4591 + return SCH_FAIL;
4592 + }
4593 +}
4594 --- /dev/null
4595 +++ b/drivers/usb/host/xhci-mtk-scheduler.h
4596 @@ -0,0 +1,77 @@
4597 +#ifndef _XHCI_MTK_SCHEDULER_H
4598 +#define _XHCI_MTK_SCHEDULER_H
4599 +
4600 +#define MTK_SCH_NEW 1
4601 +
4602 +#define SCH_SUCCESS 1
4603 +#define SCH_FAIL 0
4604 +
4605 +#define MAX_EP_NUM 64
4606 +#define SS_BW_BOUND 51000
4607 +#define HS_BW_BOUND 6144
4608 +
4609 +#define USB_EP_CONTROL 0
4610 +#define USB_EP_ISOC 1
4611 +#define USB_EP_BULK 2
4612 +#define USB_EP_INT 3
4613 +
4614 +#define USB_SPEED_LOW 1
4615 +#define USB_SPEED_FULL 2
4616 +#define USB_SPEED_HIGH 3
4617 +#define USB_SPEED_SUPER 5
4618 +
4619 +/* mtk scheduler bitmasks */
4620 +#define BPKTS(p) ((p) & 0x3f)
4621 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
4622 +#define BBM(p) ((p) << 11)
4623 +#define BOFFSET(p) ((p) & 0x3fff)
4624 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
4625 +
4626 +
4627 +#if 1
4628 +typedef unsigned int mtk_u32;
4629 +typedef unsigned long long mtk_u64;
4630 +#endif
4631 +
4632 +#define NULL ((void *)0)
4633 +
4634 +struct mtk_xhci_ep_ctx {
4635 + mtk_u32 ep_info;
4636 + mtk_u32 ep_info2;
4637 + mtk_u64 deq;
4638 + mtk_u32 tx_info;
4639 + /* offset 0x14 - 0x1f reserved for HC internal use */
4640 + mtk_u32 reserved[3];
4641 +};
4642 +
4643 +
4644 +struct sch_ep
4645 +{
4646 + //device info
4647 + int dev_speed;
4648 + int isTT;
4649 + //ep info
4650 + int is_in;
4651 + int ep_type;
4652 + int maxp;
4653 + int interval;
4654 + int burst;
4655 + int mult;
4656 + //scheduling info
4657 + int offset;
4658 + int repeat;
4659 + int pkts;
4660 + int cs_count;
4661 + int burst_mode;
4662 + //other
4663 + int bw_cost; //bandwidth cost in each repeat; including overhead
4664 + mtk_u32 *ep; //address of usb_endpoint pointer
4665 +};
4666 +
4667 +int mtk_xhci_scheduler_init(void);
4668 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4669 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4670 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4671 +
4672 +
4673 +#endif
4674 --- /dev/null
4675 +++ b/drivers/usb/host/xhci-mtk.c
4676 @@ -0,0 +1,265 @@
4677 +#include "xhci-mtk.h"
4678 +#include "xhci-mtk-power.h"
4679 +#include "xhci.h"
4680 +#include "mtk-phy.h"
4681 +#ifdef CONFIG_C60802_SUPPORT
4682 +#include "mtk-phy-c60802.h"
4683 +#endif
4684 +#include "xhci-mtk-scheduler.h"
4685 +#include <linux/kernel.h> /* printk() */
4686 +#include <linux/slab.h>
4687 +#include <linux/delay.h>
4688 +#include <asm/uaccess.h>
4689 +#include <linux/dma-mapping.h>
4690 +#include <linux/platform_device.h>
4691 +
4692 +void setInitialReg(void )
4693 +{
4694 + __u32 __iomem *addr;
4695 + u32 temp;
4696 +
4697 + /* set SSUSB DMA burst size to 128B */
4698 + addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4699 + temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4700 + writel(temp, addr);
4701 +
4702 + /* extend U3 LTSSM Polling.LFPS timeout value */
4703 + addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4704 + temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4705 + writel(temp, addr);
4706 +
4707 + /* EOF */
4708 + addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4709 + temp = SYNC_HS_EOF_VALUE;
4710 + writel(temp, addr);
4711 +
4712 +#if defined (CONFIG_PERIODIC_ENP)
4713 + /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4714 + addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4715 + temp = readl(addr);
4716 + temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4717 + writel(temp, addr);
4718 +#endif
4719 +
4720 + /* Doorbell handling */
4721 + addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4722 + temp = 0x1;
4723 + writel(temp, addr);
4724 +
4725 + /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4726 + /* Port 0 */
4727 + addr = U2_PHY_BASE + U2_PHYD_CR1;
4728 + temp = readl(addr);
4729 + temp &= ~(0x3 << 18);
4730 + temp |= (1 << 18);
4731 + writel(temp, addr);
4732 +
4733 + /* Port 1 */
4734 + addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4735 + temp = readl(addr);
4736 + temp &= ~(0x3 << 18);
4737 + temp |= (1 << 18);
4738 + writel(temp, addr);
4739 +}
4740 +
4741 +
4742 +void setLatchSel(void){
4743 + __u32 __iomem *latch_sel_addr;
4744 + u32 latch_sel_value;
4745 + latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4746 + latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4747 + writel(latch_sel_value, latch_sel_addr);
4748 +}
4749 +
4750 +void reinitIP(void){
4751 + __u32 __iomem *ip_reset_addr;
4752 + u32 ip_reset_value;
4753 +
4754 + enableAllClockPower();
4755 + mtk_xhci_scheduler_init();
4756 +}
4757 +
4758 +void dbg_prb_out(void){
4759 + mtk_probe_init(0x0f0f0f0f);
4760 + mtk_probe_out(0xffffffff);
4761 + mtk_probe_out(0x01010101);
4762 + mtk_probe_out(0x02020202);
4763 + mtk_probe_out(0x04040404);
4764 + mtk_probe_out(0x08080808);
4765 + mtk_probe_out(0x10101010);
4766 + mtk_probe_out(0x20202020);
4767 + mtk_probe_out(0x40404040);
4768 + mtk_probe_out(0x80808080);
4769 + mtk_probe_out(0x55555555);
4770 + mtk_probe_out(0xaaaaaaaa);
4771 +}
4772 +
4773 +
4774 +
4775 +///////////////////////////////////////////////////////////////////////////////
4776 +
4777 +#define RET_SUCCESS 0
4778 +#define RET_FAIL 1
4779 +
4780 +static int dbg_u3w(int argc, char**argv)
4781 +{
4782 + int u4TimingValue;
4783 + char u1TimingValue;
4784 + int u4TimingAddress;
4785 +
4786 + if (argc<3)
4787 + {
4788 + printk(KERN_ERR "Arg: address value\n");
4789 + return RET_FAIL;
4790 + }
4791 + u3phy_init();
4792 +
4793 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4794 + u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4795 + u1TimingValue = u4TimingValue & 0xff;
4796 + /* access MMIO directly */
4797 + writel(u1TimingValue, u4TimingAddress);
4798 + printk(KERN_ERR "Write done\n");
4799 + return RET_SUCCESS;
4800 +
4801 +}
4802 +
4803 +static int dbg_u3r(int argc, char**argv)
4804 +{
4805 + char u1ReadTimingValue;
4806 + int u4TimingAddress;
4807 + if (argc<2)
4808 + {
4809 + printk(KERN_ERR "Arg: address\n");
4810 + return 0;
4811 + }
4812 + u3phy_init();
4813 + mdelay(500);
4814 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4815 + /* access MMIO directly */
4816 + u1ReadTimingValue = readl(u4TimingAddress);
4817 + printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4818 + return 0;
4819 +}
4820 +
4821 +static int dbg_u3init(int argc, char**argv)
4822 +{
4823 + int ret;
4824 + ret = u3phy_init();
4825 + printk(KERN_ERR "phy registers and operations initial done\n");
4826 + if(u3phy_ops->u2_slew_rate_calibration){
4827 + u3phy_ops->u2_slew_rate_calibration(u3phy);
4828 + }
4829 + else{
4830 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4831 + }
4832 + if(u3phy_ops->init(u3phy) == PHY_TRUE)
4833 + return RET_SUCCESS;
4834 + return RET_FAIL;
4835 +}
4836 +
4837 +void dbg_setU1U2(int argc, char**argv){
4838 + struct xhci_hcd *xhci;
4839 + int u1_value;
4840 + int u2_value;
4841 + u32 port_id, temp;
4842 + u32 __iomem *addr;
4843 +
4844 + if (argc<3)
4845 + {
4846 + printk(KERN_ERR "Arg: u1value u2value\n");
4847 + return RET_FAIL;
4848 + }
4849 +
4850 + u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4851 + u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4852 + addr = (SSUSB_U3_XHCI_BASE + 0x424);
4853 + temp = readl(addr);
4854 + temp = temp & (~(0x0000ffff));
4855 + temp = temp | u1_value | (u2_value<<8);
4856 + writel(temp, addr);
4857 +}
4858 +///////////////////////////////////////////////////////////////////////////////
4859 +
4860 +int call_function(char *buf)
4861 +{
4862 + int i;
4863 + int argc;
4864 + char *argv[80];
4865 +
4866 + argc = 0;
4867 + do
4868 + {
4869 + argv[argc] = strsep(&buf, " ");
4870 + printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4871 + argc++;
4872 + } while (buf);
4873 + if (!strcmp("dbg.r", argv[0]))
4874 + dbg_prb_out();
4875 + else if (!strcmp("dbg.u3w", argv[0]))
4876 + dbg_u3w(argc, argv);
4877 + else if (!strcmp("dbg.u3r", argv[0]))
4878 + dbg_u3r(argc, argv);
4879 + else if (!strcmp("dbg.u3i", argv[0]))
4880 + dbg_u3init(argc, argv);
4881 + else if (!strcmp("pw.u1u2", argv[0]))
4882 + dbg_setU1U2(argc, argv);
4883 + return 0;
4884 +}
4885 +
4886 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4887 +{
4888 + char w_buf[200];
4889 + char r_buf[200] = "this is a test";
4890 + int len = 200;
4891 +
4892 + switch (cmd) {
4893 + case IOCTL_READ:
4894 + copy_to_user((char *) arg, r_buf, len);
4895 + printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4896 + break;
4897 + case IOCTL_WRITE:
4898 + copy_from_user(w_buf, (char *) arg, len);
4899 + printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4900 +
4901 + //invoke function
4902 + return call_function(w_buf);
4903 + break;
4904 + default:
4905 + return -ENOTTY;
4906 + }
4907 +
4908 + return len;
4909 +}
4910 +
4911 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4912 +{
4913 +
4914 + printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4915 + return 0;
4916 +}
4917 +
4918 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4919 +{
4920 +
4921 + printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4922 + return 0;
4923 +}
4924 +
4925 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4926 +{
4927 +
4928 + printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4929 + return 0;
4930 +}
4931 +
4932 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4933 +{
4934 +
4935 + printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4936 + return 0;
4937 +}
4938 +
4939 +
4940 +
4941 +
4942 --- /dev/null
4943 +++ b/drivers/usb/host/xhci-mtk.h
4944 @@ -0,0 +1,120 @@
4945 +#ifndef _XHCI_MTK_H
4946 +#define _XHCI_MTK_H
4947 +
4948 +#include <linux/usb.h>
4949 +#include "xhci.h"
4950 +
4951 +#define SSUSB_U3_XHCI_BASE 0xBE1C0000
4952 +#define SSUSB_U3_MAC_BASE 0xBE1C2400
4953 +#define SSUSB_U3_SYS_BASE 0xBE1C2600
4954 +#define SSUSB_U2_SYS_BASE 0xBE1C3400
4955 +#define SSUB_SIF_SLV_TOP 0xBE1D0000
4956 +#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
4957 +
4958 +#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
4959 +#define U3_PIPE_LATCH_TX 0
4960 +#define U3_PIPE_LATCH_RX 0
4961 +
4962 +#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
4963 +#define U3_REF_CK_PAR 0xb0
4964 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
4965 +#define U3_RX_UX_EXIT_LFPS_REF 3
4966 +#define U3_REF_CK_VAL 10
4967 +
4968 +#define U3_TIMING_PULSE_CTRL 0xb4
4969 +#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4970 +
4971 +#define USB20_TIMING_PARAMETER 0x40
4972 +#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4973 +
4974 +#define LINK_PM_TIMER 0x8
4975 +#define PM_LC_TIMEOUT_VALUE 3
4976 +
4977 +#define XHCI_IMOD 0x624
4978 +#define XHCI_IMOD_MT7621_VALUE 0x10
4979 +
4980 +#define SSUSB_HDMA_CFG 0x950
4981 +#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
4982 +
4983 +#define U3_LTSSM_TIMING_PARAMETER3 0x2514
4984 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
4985 +
4986 +#define U2_PHYD_CR1 0x64
4987 +
4988 +#define SSUSB_IP_SPAR0 0xC8
4989 +
4990 +#define SYNC_HS_EOF 0x938
4991 +#define SYNC_HS_EOF_VALUE 0x201F3
4992 +
4993 +#define HSCH_CFG1 0x960
4994 +#define SCH2_FIFO_DEPTH_OFFSET 16
4995 +
4996 +
4997 +#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
4998 +#define SSUSB_IP_SW_RST (1<<0)
4999 +#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
5000 +#define SSUSB_IP_PDN (1<<0)
5001 +#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
5002 +#define SSUSB_U3_PORT_DIS (1<<0)
5003 +#define SSUSB_U3_PORT_PDN (1<<1)
5004 +#define SSUSB_U3_PORT_HOST_SEL (1<<2)
5005 +#define SSUSB_U3_PORT_CKBG_EN (1<<3)
5006 +#define SSUSB_U3_PORT_MAC_RST (1<<4)
5007 +#define SSUSB_U3_PORT_PHYD_RST (1<<5)
5008 +#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
5009 +#define SSUSB_U2_PORT_DIS (1<<0)
5010 +#define SSUSB_U2_PORT_PDN (1<<1)
5011 +#define SSUSB_U2_PORT_HOST_SEL (1<<2)
5012 +#define SSUSB_U2_PORT_CKBG_EN (1<<3)
5013 +#define SSUSB_U2_PORT_MAC_RST (1<<4)
5014 +#define SSUSB_U2_PORT_PHYD_RST (1<<5)
5015 +#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
5016 +
5017 +#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
5018 +#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
5019 +
5020 +
5021 +#define XHCI_MTK_TEST_MAJOR 234
5022 +#define DEVICE_NAME "xhci_mtk_test"
5023 +
5024 +#define CLI_MAGIC 'CLI'
5025 +#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
5026 +#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
5027 +
5028 +void reinitIP(void);
5029 +void setInitialReg(void);
5030 +void dbg_prb_out(void);
5031 +int call_function(char *buf);
5032 +
5033 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5034 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5035 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5036 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5037 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5038 +
5039 +/*
5040 + mediatek probe out
5041 +*/
5042 +/************************************************************************************/
5043 +
5044 +#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
5045 +#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
5046 +
5047 +static inline void mtk_probe_init(const u32 byte){
5048 + __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5049 + writel(byte, ptr);
5050 +}
5051 +
5052 +static inline void mtk_probe_out(const u32 value){
5053 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5054 + writel(value, ptr);
5055 +}
5056 +
5057 +static inline u32 mtk_probe_value(void){
5058 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5059 +
5060 + return readl(ptr);
5061 +}
5062 +
5063 +
5064 +#endif
5065 --- a/drivers/usb/host/xhci-plat.c
5066 +++ b/drivers/usb/host/xhci-plat.c
5067 @@ -27,6 +27,13 @@ static void xhci_plat_quirks(struct devi
5068 * dev struct in order to setup MSI
5069 */
5070 xhci->quirks |= XHCI_PLAT;
5071 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5072 + /* MTK host controller gives a spurious successful event after a
5073 + * short transfer. Ignore it.
5074 + */
5075 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5076 + xhci->quirks |= XHCI_LPM_SUPPORT;
5077 +#endif
5078 }
5079
5080 /* called during probe() after chip reset completes */
5081 @@ -99,13 +106,19 @@ static int xhci_plat_probe(struct platfo
5082
5083 driver = &xhci_plat_xhci_driver;
5084
5085 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5086 + irq = XHC_IRQ;
5087 +#else
5088 irq = platform_get_irq(pdev, 0);
5089 +#endif
5090 if (irq < 0)
5091 return -ENODEV;
5092
5093 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5095 if (!res)
5096 return -ENODEV;
5097 +#endif
5098
5099 /* Initialize dma_mask and coherent_dma_mask to 32-bits */
5100 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5101 @@ -120,8 +133,13 @@ static int xhci_plat_probe(struct platfo
5102 if (!hcd)
5103 return -ENOMEM;
5104
5105 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5106 + hcd->rsrc_start = (uint32_t)XHC_IO_START;
5107 + hcd->rsrc_len = XHC_IO_LENGTH;
5108 +#else
5109 hcd->rsrc_start = res->start;
5110 hcd->rsrc_len = resource_size(res);
5111 +#endif
5112
5113 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
5114 driver->description)) {
5115 --- a/drivers/usb/host/xhci-ring.c
5116 +++ b/drivers/usb/host/xhci-ring.c
5117 @@ -232,7 +232,6 @@ static void inc_enq(struct xhci_hcd *xhc
5118 */
5119 if (!chain && !more_trbs_coming)
5120 break;
5121 -
5122 /* If we're not dealing with 0.95 hardware or
5123 * isoc rings on AMD 0.96 host,
5124 * carry over the chain bit of the previous TRB
5125 @@ -268,16 +267,20 @@ static void inc_enq(struct xhci_hcd *xhc
5126 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5127 unsigned int num_trbs)
5128 {
5129 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5130 int num_trbs_in_deq_seg;
5131 +#endif
5132
5133 if (ring->num_trbs_free < num_trbs)
5134 return 0;
5135
5136 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5137 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5138 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5139 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5140 return 0;
5141 }
5142 +#endif
5143
5144 return 1;
5145 }
5146 @@ -2970,6 +2973,7 @@ static int prepare_ring(struct xhci_hcd
5147 next = ring->enqueue;
5148
5149 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5150 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5151 /* If we're not dealing with 0.95 hardware or isoc rings
5152 * on AMD 0.96 host, clear the chain bit.
5153 */
5154 @@ -2979,7 +2983,9 @@ static int prepare_ring(struct xhci_hcd
5155 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5156 else
5157 next->link.control |= cpu_to_le32(TRB_CHAIN);
5158 -
5159 +#else
5160 + next->link.control &= cpu_to_le32(~TRB_CHAIN);
5161 +#endif
5162 wmb();
5163 next->link.control ^= cpu_to_le32(TRB_CYCLE);
5164
5165 @@ -3109,6 +3115,9 @@ static void giveback_first_trb(struct xh
5166 start_trb->field[3] |= cpu_to_le32(start_cycle);
5167 else
5168 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5169 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5170 + wmb();
5171 +#endif
5172 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5173 }
5174
5175 @@ -3164,6 +3173,29 @@ static u32 xhci_td_remainder(unsigned in
5176 return (remainder >> 10) << 17;
5177 }
5178
5179 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5180 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5181 +{
5182 + u32 max = 31;
5183 + int remainder, td_packet_count, packet_transferred;
5184 +
5185 + //0 for the last TRB
5186 + //FIXME: need to workaround if there is ZLP in this TD
5187 + if (td_running_total + trb_buffer_length == td_transfer_size)
5188 + return 0;
5189 +
5190 + //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5191 + packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5192 + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5193 + remainder = td_packet_count - packet_transferred;
5194 +
5195 + if (remainder > max)
5196 + return max << 17;
5197 + else
5198 + return remainder << 17;
5199 +}
5200 +#endif
5201 +
5202 /*
5203 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5204 * packets remaining in the TD (*not* including this TRB).
5205 @@ -3301,6 +3333,7 @@ static int queue_bulk_sg_tx(struct xhci_
5206 }
5207
5208 /* Set the TRB length, TD size, and interrupter fields. */
5209 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5210 if (xhci->hci_version < 0x100) {
5211 remainder = xhci_td_remainder(
5212 urb->transfer_buffer_length -
5213 @@ -3310,6 +3343,13 @@ static int queue_bulk_sg_tx(struct xhci_
5214 trb_buff_len, total_packet_count, urb,
5215 num_trbs - 1);
5216 }
5217 +#else
5218 + if (num_trbs > 1)
5219 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5220 + running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5221 +#endif
5222 +
5223 +
5224 length_field = TRB_LEN(trb_buff_len) |
5225 remainder |
5226 TRB_INTR_TARGET(0);
5227 @@ -3372,6 +3412,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5228 int running_total, trb_buff_len, ret;
5229 unsigned int total_packet_count;
5230 u64 addr;
5231 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5232 + int max_packet;
5233 +#endif
5234
5235 if (urb->num_sgs)
5236 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5237 @@ -3397,6 +3440,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5238 running_total += TRB_MAX_BUFF_SIZE;
5239 }
5240 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
5241 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5242 + switch(urb->dev->speed){
5243 + case USB_SPEED_SUPER:
5244 + max_packet = urb->ep->desc.wMaxPacketSize;
5245 + break;
5246 + case USB_SPEED_HIGH:
5247 + case USB_SPEED_FULL:
5248 + case USB_SPEED_LOW:
5249 + case USB_SPEED_WIRELESS:
5250 + case USB_SPEED_UNKNOWN:
5251 + default:
5252 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5253 + break;
5254 + }
5255 + if((urb->transfer_flags & URB_ZERO_PACKET)
5256 + && ((urb->transfer_buffer_length % max_packet) == 0)){
5257 + num_trbs++;
5258 + }
5259 +#endif
5260
5261 ret = prepare_transfer(xhci, xhci->devs[slot_id],
5262 ep_index, urb->stream_id,
5263 @@ -3456,6 +3518,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5264 field |= TRB_ISP;
5265
5266 /* Set the TRB length, TD size, and interrupter fields. */
5267 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5268 if (xhci->hci_version < 0x100) {
5269 remainder = xhci_td_remainder(
5270 urb->transfer_buffer_length -
5271 @@ -3465,6 +3528,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5272 trb_buff_len, total_packet_count, urb,
5273 num_trbs - 1);
5274 }
5275 +#else
5276 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5277 +#endif
5278 +
5279 length_field = TRB_LEN(trb_buff_len) |
5280 remainder |
5281 TRB_INTR_TARGET(0);
5282 @@ -3554,7 +3621,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5283 field |= 0x1;
5284
5285 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
5286 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5287 + if (1) {
5288 +#else
5289 if (xhci->hci_version == 0x100) {
5290 +#endif
5291 if (urb->transfer_buffer_length > 0) {
5292 if (setup->bRequestType & USB_DIR_IN)
5293 field |= TRB_TX_TYPE(TRB_DATA_IN);
5294 @@ -3578,7 +3649,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5295 field = TRB_TYPE(TRB_DATA);
5296
5297 length_field = TRB_LEN(urb->transfer_buffer_length) |
5298 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5299 xhci_td_remainder(urb->transfer_buffer_length) |
5300 +#else
5301 + //CC: MTK style, no scatter-gather for control transfer
5302 + 0 |
5303 +#endif
5304 TRB_INTR_TARGET(0);
5305 if (urb->transfer_buffer_length > 0) {
5306 if (setup->bRequestType & USB_DIR_IN)
5307 @@ -3589,7 +3665,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5308 length_field,
5309 field | ep_ring->cycle_state);
5310 }
5311 -
5312 +
5313 /* Save the DMA address of the last TRB in the TD */
5314 td->last_trb = ep_ring->enqueue;
5315
5316 @@ -3701,6 +3777,9 @@ static int xhci_queue_isoc_tx(struct xhc
5317 u64 start_addr, addr;
5318 int i, j;
5319 bool more_trbs_coming;
5320 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5321 + int max_packet;
5322 +#endif
5323
5324 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5325
5326 @@ -3714,6 +3793,21 @@ static int xhci_queue_isoc_tx(struct xhc
5327 start_trb = &ep_ring->enqueue->generic;
5328 start_cycle = ep_ring->cycle_state;
5329
5330 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5331 + switch(urb->dev->speed){
5332 + case USB_SPEED_SUPER:
5333 + max_packet = urb->ep->desc.wMaxPacketSize;
5334 + break;
5335 + case USB_SPEED_HIGH:
5336 + case USB_SPEED_FULL:
5337 + case USB_SPEED_LOW:
5338 + case USB_SPEED_WIRELESS:
5339 + case USB_SPEED_UNKNOWN:
5340 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5341 + break;
5342 + }
5343 +#endif
5344 +
5345 urb_priv = urb->hcpriv;
5346 /* Queue the first TRB, even if it's zero-length */
5347 for (i = 0; i < num_tds; i++) {
5348 @@ -3785,9 +3879,13 @@ static int xhci_queue_isoc_tx(struct xhc
5349 } else {
5350 td->last_trb = ep_ring->enqueue;
5351 field |= TRB_IOC;
5352 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5353 + if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5354 +#else
5355 if (xhci->hci_version == 0x100 &&
5356 !(xhci->quirks &
5357 XHCI_AVOID_BEI)) {
5358 +#endif
5359 /* Set BEI bit except for the last td */
5360 if (i < num_tds - 1)
5361 field |= TRB_BEI;
5362 @@ -3802,6 +3900,7 @@ static int xhci_queue_isoc_tx(struct xhc
5363 trb_buff_len = td_remain_len;
5364
5365 /* Set the TRB length, TD size, & interrupter fields. */
5366 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5367 if (xhci->hci_version < 0x100) {
5368 remainder = xhci_td_remainder(
5369 td_len - running_total);
5370 @@ -3811,6 +3910,10 @@ static int xhci_queue_isoc_tx(struct xhc
5371 total_packet_count, urb,
5372 (trbs_per_td - j - 1));
5373 }
5374 +#else
5375 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5376 +#endif
5377 +
5378 length_field = TRB_LEN(trb_buff_len) |
5379 remainder |
5380 TRB_INTR_TARGET(0);
5381 --- a/drivers/usb/host/xhci.c
5382 +++ b/drivers/usb/host/xhci.c
5383 @@ -32,6 +32,16 @@
5384 #include "xhci.h"
5385 #include "xhci-trace.h"
5386
5387 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5388 +#include <asm/uaccess.h>
5389 +#include <linux/dma-mapping.h>
5390 +#include <linux/platform_device.h>
5391 +#include "mtk-phy.h"
5392 +#include "xhci-mtk-scheduler.h"
5393 +#include "xhci-mtk-power.h"
5394 +#include "xhci-mtk.h"
5395 +#endif
5396 +
5397 #define DRIVER_AUTHOR "Sarah Sharp"
5398 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5399
5400 @@ -46,6 +56,18 @@ static unsigned int quirks;
5401 module_param(quirks, uint, S_IRUGO);
5402 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
5403
5404 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5405 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5406 +static struct file_operations xhci_mtk_test_fops = {
5407 + .owner = THIS_MODULE,
5408 + .read = xhci_mtk_test_read,
5409 + .write = xhci_mtk_test_write,
5410 + .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
5411 + .open = xhci_mtk_test_open,
5412 + .release = xhci_mtk_test_release,
5413 +};
5414 +#endif
5415 +
5416 /* TODO: copied from ehci-hcd.c - can this be refactored? */
5417 /*
5418 * xhci_handshake - spin reading hc until handshake completes or fails
5419 @@ -198,7 +220,7 @@ int xhci_reset(struct xhci_hcd *xhci)
5420 return ret;
5421 }
5422
5423 -#ifdef CONFIG_PCI
5424 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5425 static int xhci_free_msi(struct xhci_hcd *xhci)
5426 {
5427 int i;
5428 @@ -401,6 +423,7 @@ static int xhci_try_enable_msi(struct us
5429 return ret;
5430 }
5431 hcd->irq = pdev->irq;
5432 +
5433 return 0;
5434 }
5435
5436 @@ -444,6 +467,11 @@ static void compliance_mode_recovery(uns
5437 "Attempting compliance mode recovery");
5438 hcd = xhci->shared_hcd;
5439
5440 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5441 + temp |= (1 << 31);
5442 + writel(temp, xhci->usb3_ports[i]);
5443 +#endif
5444 +
5445 if (hcd->state == HC_STATE_SUSPENDED)
5446 usb_hcd_resume_root_hub(hcd);
5447
5448 @@ -493,6 +521,9 @@ bool xhci_compliance_mode_recovery_timer
5449 {
5450 const char *dmi_product_name, *dmi_sys_vendor;
5451
5452 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5453 + return true;
5454 +#endif
5455 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5456 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5457 if (!dmi_product_name || !dmi_sys_vendor)
5458 @@ -538,6 +569,10 @@ int xhci_init(struct usb_hcd *hcd)
5459 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5460 "xHCI doesn't need link TRB QUIRK");
5461 }
5462 +
5463 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5464 + mtk_xhci_scheduler_init();
5465 +#endif
5466 retval = xhci_mem_init(xhci, GFP_KERNEL);
5467 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
5468
5469 @@ -622,7 +657,11 @@ int xhci_run(struct usb_hcd *hcd)
5470 "// Set the interrupt modulation register");
5471 temp = readl(&xhci->ir_set->irq_control);
5472 temp &= ~ER_IRQ_INTERVAL_MASK;
5473 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5474 + temp |= (u32) 16;
5475 +#else
5476 temp |= (u32) 160;
5477 +#endif
5478 writel(temp, &xhci->ir_set->irq_control);
5479
5480 /* Set the HCD state before we enable the irqs */
5481 @@ -643,6 +682,9 @@ int xhci_run(struct usb_hcd *hcd)
5482 xhci_queue_vendor_command(xhci, 0, 0, 0,
5483 TRB_TYPE(TRB_NEC_GET_FW));
5484
5485 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5486 + enableXhciAllPortPower(xhci);
5487 +#endif
5488 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5489 "Finished xhci_run for USB2 roothub");
5490 return 0;
5491 @@ -1010,7 +1052,6 @@ int xhci_resume(struct xhci_hcd *xhci, b
5492
5493 /* If restore operation fails, re-initialize the HC during resume */
5494 if ((temp & STS_SRE) || hibernated) {
5495 -
5496 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
5497 !(xhci_all_ports_seen_u0(xhci))) {
5498 del_timer_sync(&xhci->comp_mode_recovery_timer);
5499 @@ -1613,6 +1654,13 @@ int xhci_drop_endpoint(struct usb_hcd *h
5500 u32 drop_flag;
5501 u32 new_add_flags, new_drop_flags, new_slot_info;
5502 int ret;
5503 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5504 +#if MTK_SCH_NEW
5505 + struct sch_ep *sch_ep = NULL;
5506 + int isTT;
5507 + int ep_type;
5508 +#endif
5509 +#endif
5510
5511 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5512 if (ret <= 0)
5513 @@ -1670,6 +1718,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
5514
5515 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5516
5517 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5518 +#if MTK_SCH_NEW
5519 + slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5520 + if ((slot_ctx->tt_info & 0xff) > 0) {
5521 + isTT = 1;
5522 + }
5523 + else {
5524 + isTT = 0;
5525 + }
5526 + if (usb_endpoint_xfer_int(&ep->desc)) {
5527 + ep_type = USB_EP_INT;
5528 + }
5529 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5530 + ep_type = USB_EP_ISOC;
5531 + }
5532 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5533 + ep_type = USB_EP_BULK;
5534 + }
5535 + else
5536 + ep_type = USB_EP_CONTROL;
5537 +
5538 + sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5539 + , isTT, ep_type, (mtk_u32 *)ep);
5540 + if (sch_ep != NULL) {
5541 + kfree(sch_ep);
5542 + }
5543 + else {
5544 + xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5545 + }
5546 +#else
5547 + mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5548 +#endif
5549 +#endif
5550 +
5551 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
5552 (unsigned int) ep->desc.bEndpointAddress,
5553 udev->slot_id,
5554 @@ -1705,6 +1787,18 @@ int xhci_add_endpoint(struct usb_hcd *hc
5555 u32 new_add_flags, new_drop_flags, new_slot_info;
5556 struct xhci_virt_device *virt_dev;
5557 int ret = 0;
5558 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5559 + struct xhci_ep_ctx *in_ep_ctx;
5560 +#if MTK_SCH_NEW
5561 + struct sch_ep *sch_ep;
5562 + int isTT;
5563 + int ep_type;
5564 + int maxp = 0;
5565 + int burst = 0;
5566 + int mult = 0;
5567 + int interval;
5568 +#endif
5569 +#endif
5570
5571 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5572 if (ret <= 0) {
5573 @@ -1772,6 +1866,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
5574 return -ENOMEM;
5575 }
5576
5577 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5578 + in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5579 +#if MTK_SCH_NEW
5580 + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5581 + if ((slot_ctx->tt_info & 0xff) > 0) {
5582 + isTT = 1;
5583 + }
5584 + else {
5585 + isTT = 0;
5586 + }
5587 + if (usb_endpoint_xfer_int(&ep->desc)) {
5588 + ep_type = USB_EP_INT;
5589 + }
5590 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5591 + ep_type = USB_EP_ISOC;
5592 + }
5593 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5594 + ep_type = USB_EP_BULK;
5595 + }
5596 + else
5597 + ep_type = USB_EP_CONTROL;
5598 +
5599 + if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5600 + || udev->speed == USB_SPEED_LOW) {
5601 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5602 + burst = ep->desc.wMaxPacketSize >> 11;
5603 + mult = 0;
5604 + }
5605 + else if (udev->speed == USB_SPEED_SUPER) {
5606 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5607 + burst = ep->ss_ep_comp.bMaxBurst;
5608 + mult = ep->ss_ep_comp.bmAttributes & 0x3;
5609 + }
5610 + interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5611 + sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5612 + if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5613 + isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5614 + , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5615 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5616 +
5617 + return -ENOSPC;
5618 + }
5619 +#else
5620 + if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5621 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5622 +
5623 + return -ENOSPC;
5624 + }
5625 +#endif
5626 +#endif
5627 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5628 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5629
5630 @@ -2766,7 +2910,7 @@ int xhci_check_bandwidth(struct usb_hcd
5631 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
5632 ctrl_ctx->drop_flags == 0)
5633 return 0;
5634 -
5635 +
5636 xhci_dbg(xhci, "New Input Control Context:\n");
5637 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
5638 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
5639 @@ -4370,10 +4514,14 @@ static u16 xhci_call_host_update_timeout
5640 u16 *timeout)
5641 {
5642 if (state == USB3_LPM_U1) {
5643 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5644 if (xhci->quirks & XHCI_INTEL_HOST)
5645 +#endif
5646 return xhci_calculate_intel_u1_timeout(udev, desc);
5647 } else {
5648 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5649 if (xhci->quirks & XHCI_INTEL_HOST)
5650 +#endif
5651 return xhci_calculate_intel_u2_timeout(udev, desc);
5652 }
5653
5654 @@ -4758,7 +4906,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5655 hcd->self.no_sg_constraint = 1;
5656
5657 /* XHCI controllers don't stop the ep queue on short packets :| */
5658 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5659 hcd->self.no_stop_on_short = 1;
5660 +#endif
5661
5662 if (usb_hcd_is_primary_hcd(hcd)) {
5663 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
5664 @@ -4821,6 +4971,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5665 goto error;
5666 xhci_dbg(xhci, "Reset complete\n");
5667
5668 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5669 + setInitialReg();
5670 +#endif
5671 +
5672 /* Set dma_mask and coherent_dma_mask to 64-bits,
5673 * if xHC supports 64-bit addressing */
5674 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5675 @@ -4845,8 +4999,21 @@ MODULE_DESCRIPTION(DRIVER_DESC);
5676 MODULE_AUTHOR(DRIVER_AUTHOR);
5677 MODULE_LICENSE("GPL");
5678
5679 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5680 +static struct platform_device xhci_platform_dev = {
5681 + .name = "xhci-hcd",
5682 + .id = -1,
5683 + .dev = {
5684 + .coherent_dma_mask = 0xffffffff,
5685 + },
5686 +};
5687 +#endif
5688 +
5689 static int __init xhci_hcd_init(void)
5690 {
5691 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5692 + struct platform_device *pPlatformDev;
5693 +#endif
5694 int retval;
5695
5696 retval = xhci_register_pci();
5697 @@ -4859,6 +5026,33 @@ static int __init xhci_hcd_init(void)
5698 pr_debug("Problem registering platform driver.\n");
5699 goto unreg_pci;
5700 }
5701 +
5702 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5703 + retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5704 +
5705 + u3phy_init();
5706 + if (u3phy_ops->u2_slew_rate_calibration) {
5707 + u3phy_ops->u2_slew_rate_calibration(u3phy);
5708 + u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5709 + }
5710 + else{
5711 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5712 + }
5713 + u3phy_ops->init(u3phy);
5714 + reinitIP();
5715 +
5716 + pPlatformDev = &xhci_platform_dev;
5717 + memset(pPlatformDev, 0, sizeof(struct platform_device));
5718 + pPlatformDev->name = "xhci-hcd";
5719 + pPlatformDev->id = -1;
5720 + pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5721 + pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5722 +
5723 + retval = platform_device_register(&xhci_platform_dev);
5724 + if (retval < 0)
5725 + xhci_unregister_plat();
5726 +#endif
5727 +
5728 /*
5729 * Check the compiler generated sizes of structures that must be laid
5730 * out in specific ways for hardware access.
5731 @@ -4876,6 +5070,7 @@ static int __init xhci_hcd_init(void)
5732 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5733 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5734 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5735 +
5736 return 0;
5737 unreg_pci:
5738 xhci_unregister_pci();
5739 --- a/drivers/usb/host/xhci.h
5740 +++ b/drivers/usb/host/xhci.h
5741 @@ -29,9 +29,24 @@
5742 #include <linux/usb/hcd.h>
5743
5744 /* Code sharing between pci-quirks and xhci hcd */
5745 -#include "xhci-ext-caps.h"
5746 +#include "xhci-ext-caps.h"
5747 #include "pci-quirks.h"
5748
5749 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5750 +#define XHC_IRQ (22 + 8)
5751 +#define XHC_IO_START 0x1E1C0000
5752 +#define XHC_IO_LENGTH 0x10000
5753 +/* mtk scheduler bitmasks */
5754 +#define BPKTS(p) ((p) & 0x3f)
5755 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
5756 +#define BBM(p) ((p) << 11)
5757 +#define BOFFSET(p) ((p) & 0x3fff)
5758 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
5759 +#endif
5760 +
5761 +
5762 +
5763 +
5764 /* xHCI PCI Configuration Registers */
5765 #define XHCI_SBRN_OFFSET (0x60)
5766
5767 @@ -1577,8 +1592,12 @@ struct xhci_hcd {
5768 /* Compliance Mode Recovery Data */
5769 struct timer_list comp_mode_recovery_timer;
5770 u32 port_status_u0;
5771 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5772 +#define COMP_MODE_RCVRY_MSECS 5000
5773 +#else
5774 /* Compliance Mode Timer Triggered every 2 seconds */
5775 #define COMP_MODE_RCVRY_MSECS 2000
5776 +#endif
5777 };
5778
5779 /* convert between an HCD pointer and the corresponding EHCI_HCD */
5780 @@ -1726,7 +1745,7 @@ void xhci_urb_free_priv(struct xhci_hcd
5781 void xhci_free_command(struct xhci_hcd *xhci,
5782 struct xhci_command *command);
5783
5784 -#ifdef CONFIG_PCI
5785 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5786 /* xHCI PCI glue */
5787 int xhci_register_pci(void);
5788 void xhci_unregister_pci(void);
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