target/linux/ramips/patches-3.14/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:15:12 +0100
   4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   9 Acked-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/spi/Kconfig      |    6 +
  12  drivers/spi/Makefile     |    1 +
  13  drivers/spi/spi-rt2880.c |  432 ++++++++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 439 insertions(+)
  15  create mode 100644 drivers/spi/spi-rt2880.c
  16
  17 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  18 index 581ee2a..009f8f3 100644
  19 --- a/drivers/spi/Kconfig
  20 +++ b/drivers/spi/Kconfig
  21 @@ -381,6 +381,12 @@ config SPI_RSPI
  22         help
  23           SPI driver for Renesas RSPI and QSPI blocks.
  24
  25 +config SPI_RT2880
  26 +       tristate "Ralink RT288x SPI Controller"
  27 +       depends on RALINK
  28 +       help
  29 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  30 +
  31  config SPI_S3C24XX
  32         tristate "Samsung S3C24XX series SPI"
  33         depends on ARCH_S3C24XX
  34 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  35 index 95af48d..1f647e5 100644
  36 --- a/drivers/spi/Makefile
  37 +++ b/drivers/spi/Makefile
  38 @@ -60,6 +60,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA)  += spi-pxa2xx-dma.o
  39  obj-$(CONFIG_SPI_PXA2XX)               += spi-pxa2xx-platform.o
  40  obj-$(CONFIG_SPI_PXA2XX_PCI)           += spi-pxa2xx-pci.o
  41  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  42 +obj-$(CONFIG_SPI_RT2880)               += spi-rt2880.o
  43  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  44  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  45  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  46 diff --git a/drivers/spi/spi-rt2880.c b/drivers/spi/spi-rt2880.c
  47 new file mode 100644
  48 index 0000000..ac9de67
  49 --- /dev/null
  50 +++ b/drivers/spi/spi-rt2880.c
  51 @@ -0,0 +1,432 @@
  52 +/*
  53 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
  54 + *
  55 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  56 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  57 + *
  58 + * Some parts are based on spi-orion.c:
  59 + *   Author: Shadi Ammouri <shadi@marvell.com>
  60 + *   Copyright (C) 2007-2008 Marvell Ltd.
  61 + *
  62 + * This program is free software; you can redistribute it and/or modify
  63 + * it under the terms of the GNU General Public License version 2 as
  64 + * published by the Free Software Foundation.
  65 + */
  66 +
  67 +#include <linux/init.h>
  68 +#include <linux/module.h>
  69 +#include <linux/clk.h>
  70 +#include <linux/err.h>
  71 +#include <linux/delay.h>
  72 +#include <linux/io.h>
  73 +#include <linux/reset.h>
  74 +#include <linux/spi/spi.h>
  75 +#include <linux/platform_device.h>
  76 +
  77 +#define DRIVER_NAME                    "spi-rt2880"
  78 +/* only one slave is supported*/
  79 +#define RALINK_NUM_CHIPSELECTS         1
  80 +/* in usec */
  81 +#define RALINK_SPI_WAIT_MAX_LOOP       2000
  82 +
  83 +#define RAMIPS_SPI_STAT                        0x00
  84 +#define RAMIPS_SPI_CFG                 0x10
  85 +#define RAMIPS_SPI_CTL                 0x14
  86 +#define RAMIPS_SPI_DATA                        0x20
  87 +#define RAMIPS_SPI_FIFO_STAT           0x38
  88 +
  89 +/* SPISTAT register bit field */
  90 +#define SPISTAT_BUSY                   BIT(0)
  91 +
  92 +/* SPICFG register bit field */
  93 +#define SPICFG_LSBFIRST                        0
  94 +#define SPICFG_MSBFIRST                        BIT(8)
  95 +#define SPICFG_SPICLKPOL               BIT(6)
  96 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
  97 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
  98 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
  99 +#define SPICFG_SPICLK_DIV2             0
 100 +#define SPICFG_SPICLK_DIV4             1
 101 +#define SPICFG_SPICLK_DIV8             2
 102 +#define SPICFG_SPICLK_DIV16            3
 103 +#define SPICFG_SPICLK_DIV32            4
 104 +#define SPICFG_SPICLK_DIV64            5
 105 +#define SPICFG_SPICLK_DIV128           6
 106 +#define SPICFG_SPICLK_DISABLE          7
 107 +
 108 +/* SPICTL register bit field */
 109 +#define SPICTL_HIZSDO                  BIT(3)
 110 +#define SPICTL_STARTWR                 BIT(2)
 111 +#define SPICTL_STARTRD                 BIT(1)
 112 +#define SPICTL_SPIENA                  BIT(0)
 113 +
 114 +/* SPIFIFOSTAT register bit field */
 115 +#define SPIFIFOSTAT_TXFULL             BIT(17)
 116 +
 117 +struct rt2880_spi {
 118 +       struct spi_master       *master;
 119 +       void __iomem            *base;
 120 +       unsigned int            sys_freq;
 121 +       unsigned int            speed;
 122 +       struct clk              *clk;
 123 +       spinlock_t              lock;
 124 +};
 125 +
 126 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
 127 +{
 128 +       return spi_master_get_devdata(spi->master);
 129 +}
 130 +
 131 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
 132 +{
 133 +       return ioread32(rs->base + reg);
 134 +}
 135 +
 136 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
 137 +{
 138 +       iowrite32(val, rs->base + reg);
 139 +}
 140 +
 141 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 142 +{
 143 +       void __iomem *addr = rs->base + reg;
 144 +       unsigned long flags;
 145 +       u32 val;
 146 +
 147 +       spin_lock_irqsave(&rs->lock, flags);
 148 +       val = ioread32(addr);
 149 +       val |= mask;
 150 +       iowrite32(val, addr);
 151 +       spin_unlock_irqrestore(&rs->lock, flags);
 152 +}
 153 +
 154 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 155 +{
 156 +       void __iomem *addr = rs->base + reg;
 157 +       unsigned long flags;
 158 +       u32 val;
 159 +
 160 +       spin_lock_irqsave(&rs->lock, flags);
 161 +       val = ioread32(addr);
 162 +       val &= ~mask;
 163 +       iowrite32(val, addr);
 164 +       spin_unlock_irqrestore(&rs->lock, flags);
 165 +}
 166 +
 167 +static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 168 +{
 169 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 170 +       u32 rate;
 171 +       u32 prescale;
 172 +       u32 reg;
 173 +
 174 +       dev_dbg(&spi->dev, "speed:%u\n", speed);
 175 +
 176 +       /*
 177 +        * the supported rates are: 2, 4, 8, ... 128
 178 +        * round up as we look for equal or less speed
 179 +        */
 180 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 181 +       dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 182 +       rate = roundup_pow_of_two(rate);
 183 +       dev_dbg(&spi->dev, "rate-2:%u\n", rate);
 184 +
 185 +       /* check if requested speed is too small */
 186 +       if (rate > 128)
 187 +               return -EINVAL;
 188 +
 189 +       if (rate < 2)
 190 +               rate = 2;
 191 +
 192 +       /* Convert the rate to SPI clock divisor value. */
 193 +       prescale = ilog2(rate / 2);
 194 +       dev_dbg(&spi->dev, "prescale:%u\n", prescale);
 195 +
 196 +       reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 197 +       reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
 198 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 199 +       rs->speed = speed;
 200 +       return 0;
 201 +}
 202 +
 203 +/*
 204 + * called only when no transfer is active on the bus
 205 + */
 206 +static int
 207 +rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 208 +{
 209 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 210 +       unsigned int speed = spi->max_speed_hz;
 211 +       int rc;
 212 +
 213 +       if ((t != NULL) && t->speed_hz)
 214 +               speed = t->speed_hz;
 215 +
 216 +       if (rs->speed != speed) {
 217 +               dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
 218 +               rc = rt2880_spi_baudrate_set(spi, speed);
 219 +               if (rc)
 220 +                       return rc;
 221 +       }
 222 +
 223 +       return 0;
 224 +}
 225 +
 226 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
 227 +{
 228 +       if (enable)
 229 +               rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 230 +       else
 231 +               rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 232 +}
 233 +
 234 +static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 235 +{
 236 +       int i;
 237 +
 238 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 239 +               u32 status;
 240 +
 241 +               status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
 242 +               if ((status & SPISTAT_BUSY) == 0)
 243 +                       return 0;
 244 +
 245 +               cpu_relax();
 246 +               udelay(1);
 247 +       }
 248 +
 249 +       return -ETIMEDOUT;
 250 +}
 251 +
 252 +static unsigned int
 253 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 254 +{
 255 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 256 +       unsigned count = 0;
 257 +       u8 *rx = xfer->rx_buf;
 258 +       const u8 *tx = xfer->tx_buf;
 259 +       int err;
 260 +
 261 +       dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
 262 +                 (tx != NULL) ? "tx" : "  ",
 263 +                 (rx != NULL) ? "rx" : "  ");
 264 +
 265 +       if (tx) {
 266 +               for (count = 0; count < xfer->len; count++) {
 267 +                       rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
 268 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 269 +                       err = rt2880_spi_wait_till_ready(rs);
 270 +                       if (err) {
 271 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 272 +                               goto out;
 273 +                       }
 274 +               }
 275 +       }
 276 +
 277 +       if (rx) {
 278 +               for (count = 0; count < xfer->len; count++) {
 279 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 280 +                       err = rt2880_spi_wait_till_ready(rs);
 281 +                       if (err) {
 282 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 283 +                               goto out;
 284 +                       }
 285 +                       rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
 286 +               }
 287 +       }
 288 +
 289 +out:
 290 +       return count;
 291 +}
 292 +
 293 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
 294 +                                          struct spi_message *m)
 295 +{
 296 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 297 +       struct spi_device *spi = m->spi;
 298 +       struct spi_transfer *t = NULL;
 299 +       int par_override = 0;
 300 +       int status = 0;
 301 +       int cs_active = 0;
 302 +
 303 +       /* Load defaults */
 304 +       status = rt2880_spi_setup_transfer(spi, NULL);
 305 +       if (status < 0)
 306 +               goto msg_done;
 307 +
 308 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 309 +               if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 310 +                       dev_err(&spi->dev,
 311 +                               "message rejected: invalid transfer data buffers\n");
 312 +                       status = -EIO;
 313 +                       goto msg_done;
 314 +               }
 315 +
 316 +               if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
 317 +                       dev_err(&spi->dev,
 318 +                               "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
 319 +                               (rs->sys_freq / 128), t->speed_hz);
 320 +                       status = -EIO;
 321 +                       goto msg_done;
 322 +               }
 323 +
 324 +               if (par_override || t->speed_hz || t->bits_per_word) {
 325 +                       par_override = 1;
 326 +                       status = rt2880_spi_setup_transfer(spi, t);
 327 +                       if (status < 0)
 328 +                               goto msg_done;
 329 +                       if (!t->speed_hz && !t->bits_per_word)
 330 +                               par_override = 0;
 331 +               }
 332 +
 333 +               if (!cs_active) {
 334 +                       rt2880_spi_set_cs(rs, 1);
 335 +                       cs_active = 1;
 336 +               }
 337 +
 338 +               if (t->len)
 339 +                       m->actual_length += rt2880_spi_write_read(spi, t);
 340 +
 341 +               if (t->delay_usecs)
 342 +                       udelay(t->delay_usecs);
 343 +
 344 +               if (t->cs_change) {
 345 +                       rt2880_spi_set_cs(rs, 0);
 346 +                       cs_active = 0;
 347 +               }
 348 +       }
 349 +
 350 +msg_done:
 351 +       if (cs_active)
 352 +               rt2880_spi_set_cs(rs, 0);
 353 +
 354 +       m->status = status;
 355 +       spi_finalize_current_message(master);
 356 +
 357 +       return 0;
 358 +}
 359 +
 360 +static int rt2880_spi_setup(struct spi_device *spi)
 361 +{
 362 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 363 +
 364 +       if ((spi->max_speed_hz == 0) ||
 365 +           (spi->max_speed_hz > (rs->sys_freq / 2)))
 366 +               spi->max_speed_hz = (rs->sys_freq / 2);
 367 +
 368 +       if (spi->max_speed_hz < (rs->sys_freq / 128)) {
 369 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 370 +                       spi->max_speed_hz);
 371 +               return -EINVAL;
 372 +       }
 373 +
 374 +       /*
 375 +        * baudrate & width will be set rt2880_spi_setup_transfer
 376 +        */
 377 +       return 0;
 378 +}
 379 +
 380 +static void rt2880_spi_reset(struct rt2880_spi *rs)
 381 +{
 382 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG,
 383 +                        SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
 384 +                        SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 385 +       rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 386 +}
 387 +
 388 +static int rt2880_spi_probe(struct platform_device *pdev)
 389 +{
 390 +       struct spi_master *master;
 391 +       struct rt2880_spi *rs;
 392 +       unsigned long flags;
 393 +       void __iomem *base;
 394 +       struct resource *r;
 395 +       int status = 0;
 396 +       struct clk *clk;
 397 +
 398 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 399 +       base = devm_ioremap_resource(&pdev->dev, r);
 400 +       if (IS_ERR(base))
 401 +               return PTR_ERR(base);
 402 +
 403 +       clk = devm_clk_get(&pdev->dev, NULL);
 404 +       if (IS_ERR(clk)) {
 405 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 406 +                       status);
 407 +               return PTR_ERR(clk);
 408 +       }
 409 +
 410 +       status = clk_prepare_enable(clk);
 411 +       if (status)
 412 +               return status;
 413 +
 414 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 415 +       if (master == NULL) {
 416 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 417 +               return -ENOMEM;
 418 +       }
 419 +
 420 +       /* we support only mode 0, and no options */
 421 +       master->mode_bits = 0;
 422 +
 423 +       master->setup = rt2880_spi_setup;
 424 +       master->transfer_one_message = rt2880_spi_transfer_one_message;
 425 +       master->num_chipselect = RALINK_NUM_CHIPSELECTS;
 426 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 427 +       master->dev.of_node = pdev->dev.of_node;
 428 +
 429 +       dev_set_drvdata(&pdev->dev, master);
 430 +
 431 +       rs = spi_master_get_devdata(master);
 432 +       rs->base = base;
 433 +       rs->clk = clk;
 434 +       rs->master = master;
 435 +       rs->sys_freq = clk_get_rate(rs->clk);
 436 +       dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 437 +       spin_lock_irqsave(&rs->lock, flags);
 438 +
 439 +       device_reset(&pdev->dev);
 440 +
 441 +       rt2880_spi_reset(rs);
 442 +
 443 +       return spi_register_master(master);
 444 +}
 445 +
 446 +static int rt2880_spi_remove(struct platform_device *pdev)
 447 +{
 448 +       struct spi_master *master;
 449 +       struct rt2880_spi *rs;
 450 +
 451 +       master = dev_get_drvdata(&pdev->dev);
 452 +       rs = spi_master_get_devdata(master);
 453 +
 454 +       clk_disable(rs->clk);
 455 +       spi_unregister_master(master);
 456 +
 457 +       return 0;
 458 +}
 459 +
 460 +MODULE_ALIAS("platform:" DRIVER_NAME);
 461 +
 462 +static const struct of_device_id rt2880_spi_match[] = {
 463 +       { .compatible = "ralink,rt2880-spi" },
 464 +       {},
 465 +};
 466 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 467 +
 468 +static struct platform_driver rt2880_spi_driver = {
 469 +       .driver = {
 470 +               .name = DRIVER_NAME,
 471 +               .owner = THIS_MODULE,
 472 +               .of_match_table = rt2880_spi_match,
 473 +       },
 474 +       .probe = rt2880_spi_probe,
 475 +       .remove = rt2880_spi_remove,
 476 +};
 477 +
 478 +module_platform_driver(rt2880_spi_driver);
 479 +
 480 +MODULE_DESCRIPTION("Ralink SPI driver");
 481 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 482 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 483 +MODULE_LICENSE("GPL");
 484 --
 485 1.7.10.4
 486