target/linux/ramips/patches-3.14/0055-asoc-add-mt7620-support.patch

   1 From 241188942603dc73f62cf2553c53cae2235c9957 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:31:47 +0100
   4 Subject: [PATCH 55/57] asoc: add mt7620 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/ralink/of.c            |    2 +
   9  sound/soc/Kconfig                |    1 +
  10  sound/soc/Makefile               |    1 +
  11  sound/soc/ralink/Kconfig         |   15 ++
  12  sound/soc/ralink/Makefile        |   11 +
  13  sound/soc/ralink/mt7620-i2s.c    |  466 ++++++++++++++++++++++++++++++++++++++
  14  sound/soc/ralink/mt7620-wm8960.c |  125 ++++++++++
  15  sound/soc/soc-io.c               |   10 -
  16  8 files changed, 621 insertions(+), 10 deletions(-)
  17  create mode 100644 sound/soc/ralink/Kconfig
  18  create mode 100644 sound/soc/ralink/Makefile
  19  create mode 100644 sound/soc/ralink/mt7620-i2s.c
  20  create mode 100644 sound/soc/ralink/mt7620-wm8960.c
  21
  22 diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
  23 index 405b79c..dfda6e6 100644
  24 --- a/arch/mips/ralink/of.c
  25 +++ b/arch/mips/ralink/of.c
  26 @@ -15,6 +15,7 @@
  27  #include <linux/of_fdt.h>
  28  #include <linux/kernel.h>
  29  #include <linux/bootmem.h>
  30 +#include <linux/module.h>
  31  #include <linux/of_platform.h>
  32  #include <linux/of_address.h>
  33
  34 @@ -26,6 +27,7 @@
  35  #include "common.h"
  36
  37  __iomem void *rt_sysc_membase;
  38 +EXPORT_SYMBOL(rt_sysc_membase);
  39  __iomem void *rt_memc_membase;
  40
  41  extern struct boot_param_header __dtb_start;
  42 diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
  43 index d62ce48..de91f58 100644
  44 --- a/sound/soc/Kconfig
  45 +++ b/sound/soc/Kconfig
  46 @@ -47,6 +47,7 @@ source "sound/soc/kirkwood/Kconfig"
  47  source "sound/soc/intel/Kconfig"
  48  source "sound/soc/mxs/Kconfig"
  49  source "sound/soc/pxa/Kconfig"
  50 +source "sound/soc/ralink/Kconfig"
  51  source "sound/soc/samsung/Kconfig"
  52  source "sound/soc/s6000/Kconfig"
  53  source "sound/soc/sh/Kconfig"
  54 diff --git a/sound/soc/Makefile b/sound/soc/Makefile
  55 index 62a1822..1d9398c 100644
  56 --- a/sound/soc/Makefile
  57 +++ b/sound/soc/Makefile
  58 @@ -24,6 +24,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/
  59  obj-$(CONFIG_SND_SOC)  += omap/
  60  obj-$(CONFIG_SND_SOC)  += kirkwood/
  61  obj-$(CONFIG_SND_SOC)  += pxa/
  62 +obj-$(CONFIG_SND_SOC)  += ralink/
  63  obj-$(CONFIG_SND_SOC)  += samsung/
  64  obj-$(CONFIG_SND_SOC)  += s6000/
  65  obj-$(CONFIG_SND_SOC)  += sh/
  66 diff --git a/sound/soc/ralink/Kconfig b/sound/soc/ralink/Kconfig
  67 new file mode 100644
  68 index 0000000..d462622
  69 --- /dev/null
  70 +++ b/sound/soc/ralink/Kconfig
  71 @@ -0,0 +1,15 @@
  72 +config SND_MT7620_SOC_I2S
  73 +       depends on SOC_MT7620 && SND_SOC
  74 +       select SND_SOC_GENERIC_DMAENGINE_PCM
  75 +       tristate "SoC Audio (I2S protocol) for Ralink MT7620 SoC"
  76 +       help
  77 +         Say Y if you want to use I2S protocol and I2S codec on Ingenic MT7620
  78 +         based boards.
  79 +
  80 +config SND_MT7620_SOC_WM8960
  81 +       tristate "SoC Audio support for Ralink WM8960"
  82 +       select SND_MT7620_SOC_I2S
  83 +       select SND_SOC_WM8960
  84 +       help
  85 +         Say Y if you want to add support for ASoC audio on the Qi LB60 board
  86 +         a.k.a Qi Ben NanoNote.
  87 diff --git a/sound/soc/ralink/Makefile b/sound/soc/ralink/Makefile
  88 new file mode 100644
  89 index 0000000..3d79980
  90 --- /dev/null
  91 +++ b/sound/soc/ralink/Makefile
  92 @@ -0,0 +1,11 @@
  93 +#
  94 +# Jz4740 Platform Support
  95 +#
  96 +snd-soc-mt7620-i2s-objs := mt7620-i2s.o
  97 +
  98 +obj-$(CONFIG_SND_MT7620_SOC_I2S) += snd-soc-mt7620-i2s.o
  99 +
 100 +# Jz4740 Machine Support
 101 +snd-soc-mt7620-wm8960-objs := mt7620-wm8960.o
 102 +
 103 +obj-$(CONFIG_SND_MT7620_SOC_WM8960) += snd-soc-mt7620-wm8960.o
 104 diff --git a/sound/soc/ralink/mt7620-i2s.c b/sound/soc/ralink/mt7620-i2s.c
 105 new file mode 100644
 106 index 0000000..846db03
 107 --- /dev/null
 108 +++ b/sound/soc/ralink/mt7620-i2s.c
 109 @@ -0,0 +1,466 @@
 110 +/*
 111 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 112 + *
 113 + *  This program is free software; you can redistribute it and/or modify it
 114 + *  under  the terms of the GNU General  Public License as published by the
 115 + *  Free Software Foundation;  either version 2 of the License, or (at your
 116 + *  option) any later version.
 117 + *
 118 + *  You should have received a copy of the GNU General Public License along
 119 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 120 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 121 + *
 122 + */
 123 +
 124 +#include <linux/init.h>
 125 +#include <linux/io.h>
 126 +#include <linux/kernel.h>
 127 +#include <linux/module.h>
 128 +#include <linux/platform_device.h>
 129 +#include <linux/slab.h>
 130 +
 131 +#include <linux/delay.h>
 132 +
 133 +#include <linux/dma-mapping.h>
 134 +
 135 +#include <sound/core.h>
 136 +#include <sound/pcm.h>
 137 +#include <sound/pcm_params.h>
 138 +#include <sound/soc.h>
 139 +#include <sound/initval.h>
 140 +#include <sound/dmaengine_pcm.h>
 141 +
 142 +#include <ralink_regs.h>
 143 +
 144 +#define I2S_REG_CFG0           0x00
 145 +#define I2S_REG_CFG0_EN                BIT(31)
 146 +#define I2S_REG_CFG0_DMA_EN    BIT(30)
 147 +#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
 148 +#define I2S_REG_CFG0_TX_EN     BIT(24)
 149 +#define I2S_REG_CFG0_RX_EN     BIT(20)
 150 +#define I2S_REG_CFG0_SLAVE     BIT(16)
 151 +#define I2S_REG_CFG0_RX_THRES  12
 152 +#define I2S_REG_CFG0_TX_THRES  4
 153 +#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
 154 +                                       (4 << I2S_REG_CFG0_TX_THRES)
 155 +
 156 +#define I2S_REG_INT_STATUS     0x04
 157 +#define I2S_REG_INT_EN         0x08
 158 +#define I2S_REG_FF_STATUS      0x0c
 159 +#define I2S_REG_WREG           0x10
 160 +#define I2S_REG_RREG           0x14
 161 +#define I2S_REG_CFG1           0x18
 162 +
 163 +#define I2S_REG_DIVCMP         0x20
 164 +#define I2S_REG_DIVINT         0x24
 165 +#define I2S_REG_CLK_EN         BIT(31)
 166 +
 167 +struct mt7620_i2s {
 168 +       struct resource *mem;
 169 +       void __iomem *base;
 170 +       dma_addr_t phys_base;
 171 +
 172 +       struct snd_dmaengine_dai_dma_data playback_dma_data;
 173 +       struct snd_dmaengine_dai_dma_data capture_dma_data;
 174 +};
 175 +
 176 +static inline uint32_t mt7620_i2s_read(const struct mt7620_i2s *i2s,
 177 +       unsigned int reg)
 178 +{
 179 +       return readl(i2s->base + reg);
 180 +}
 181 +
 182 +static inline void mt7620_i2s_write(const struct mt7620_i2s *i2s,
 183 +       unsigned int reg, uint32_t value)
 184 +{
 185 +       //printk("i2s --> %p = 0x%08X\n", i2s->base + reg, value);
 186 +       writel(value, i2s->base + reg);
 187 +}
 188 +
 189 +static int mt7620_i2s_startup(struct snd_pcm_substream *substream,
 190 +       struct snd_soc_dai *dai)
 191 +{
 192 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 193 +       uint32_t cfg;
 194 +
 195 +       if (dai->active)
 196 +               return 0;
 197 +
 198 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 199 +       cfg |= I2S_REG_CFG0_EN;
 200 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 201 +
 202 +       return 0;
 203 +}
 204 +
 205 +static void mt7620_i2s_shutdown(struct snd_pcm_substream *substream,
 206 +       struct snd_soc_dai *dai)
 207 +{
 208 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 209 +       uint32_t cfg;
 210 +
 211 +       if (dai->active)
 212 +               return;
 213 +
 214 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 215 +       cfg &= ~I2S_REG_CFG0_EN;
 216 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 217 +}
 218 +
 219 +static int mt7620_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 220 +       struct snd_soc_dai *dai)
 221 +{
 222 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 223 +
 224 +       uint32_t cfg;
 225 +       uint32_t mask;
 226 +
 227 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 228 +               mask = I2S_REG_CFG0_TX_EN;
 229 +       else
 230 +               mask = I2S_REG_CFG0_RX_EN;
 231 +
 232 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 233 +
 234 +       switch (cmd) {
 235 +       case SNDRV_PCM_TRIGGER_START:
 236 +       case SNDRV_PCM_TRIGGER_RESUME:
 237 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 238 +               cfg |= mask;
 239 +               break;
 240 +       case SNDRV_PCM_TRIGGER_STOP:
 241 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 242 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 243 +               cfg &= ~mask;
 244 +               break;
 245 +       default:
 246 +               return -EINVAL;
 247 +       }
 248 +
 249 +       if (cfg & (I2S_REG_CFG0_TX_EN | I2S_REG_CFG0_RX_EN))
 250 +               cfg |= I2S_REG_CFG0_DMA_EN;
 251 +       else
 252 +               cfg &= ~I2S_REG_CFG0_DMA_EN;
 253 +
 254 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 255 +
 256 +       return 0;
 257 +}
 258 +
 259 +static int mt7620_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 260 +{
 261 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 262 +       uint32_t cfg;
 263 +
 264 +       cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 265 +
 266 +       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 267 +       case SND_SOC_DAIFMT_CBS_CFS:
 268 +               cfg |= I2S_REG_CFG0_SLAVE;
 269 +               break;
 270 +       case SND_SOC_DAIFMT_CBM_CFM:
 271 +               cfg &= ~I2S_REG_CFG0_SLAVE;
 272 +               break;
 273 +       case SND_SOC_DAIFMT_CBM_CFS:
 274 +       default:
 275 +               return -EINVAL;
 276 +       }
 277 +
 278 +       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 279 +       case SND_SOC_DAIFMT_I2S:
 280 +       case SND_SOC_DAIFMT_MSB:
 281 +               cfg &= ~I2S_REG_CFG0_BYTE_SWAP;
 282 +               break;
 283 +       case SND_SOC_DAIFMT_LSB:
 284 +               cfg |= I2S_REG_CFG0_BYTE_SWAP;
 285 +               break;
 286 +       default:
 287 +               return -EINVAL;
 288 +       }
 289 +
 290 +       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 291 +       case SND_SOC_DAIFMT_NB_NF:
 292 +               break;
 293 +       default:
 294 +               return -EINVAL;
 295 +       }
 296 +
 297 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 298 +
 299 +       return 0;
 300 +}
 301 +
 302 +static int mt7620_i2s_hw_params(struct snd_pcm_substream *substream,
 303 +       struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 304 +{
 305 +
 306 +       return 0;
 307 +}
 308 +
 309 +unsigned long i2sMaster_inclk_int[11] = {
 310 +       78,     56,     52,     39,     28,     26,     19,     14,     13,     9,      6};
 311 +unsigned long i2sMaster_inclk_comp[11] = {
 312 +       64,     352,    42,     32,     176,    21,     272,    88,     10,     455,    261};
 313 +
 314 +
 315 +static int mt7620_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 316 +       unsigned int freq, int dir)
 317 +{
 318 +        struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 319 +
 320 +       printk("Internal REFCLK with fractional division\n");
 321 +
 322 +       mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
 323 +       mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
 324 +               i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
 325 +
 326 +/*     struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 327 +       struct clk *parent;
 328 +       int ret = 0;
 329 +
 330 +       switch (clk_id) {
 331 +       case JZ4740_I2S_CLKSRC_EXT:
 332 +               parent = clk_get(NULL, "ext");
 333 +               clk_set_parent(i2s->clk_i2s, parent);
 334 +               break;
 335 +       case JZ4740_I2S_CLKSRC_PLL:
 336 +               parent = clk_get(NULL, "pll half");
 337 +               clk_set_parent(i2s->clk_i2s, parent);
 338 +               ret = clk_set_rate(i2s->clk_i2s, freq);
 339 +               break;
 340 +       default:
 341 +               return -EINVAL;
 342 +       }
 343 +       clk_put(parent);
 344 +
 345 +       return ret;*/
 346 +       return 0;
 347 +}
 348 +
 349 +static int mt7620_i2s_suspend(struct snd_soc_dai *dai)
 350 +{
 351 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 352 +       uint32_t cfg;
 353 +
 354 +       if (dai->active) {
 355 +               cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 356 +               cfg &= ~I2S_REG_CFG0_TX_EN;
 357 +               mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 358 +       }
 359 +
 360 +       return 0;
 361 +}
 362 +
 363 +static int mt7620_i2s_resume(struct snd_soc_dai *dai)
 364 +{
 365 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 366 +       uint32_t cfg;
 367 +
 368 +       if (dai->active) {
 369 +               cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
 370 +               cfg |= I2S_REG_CFG0_TX_EN;
 371 +               mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
 372 +       }
 373 +
 374 +       return 0;
 375 +}
 376 +
 377 +static void mt7620_i2c_init_pcm_config(struct mt7620_i2s *i2s)
 378 +{
 379 +       struct snd_dmaengine_dai_dma_data *dma_data;
 380 +
 381 +       /* Playback */
 382 +       dma_data = &i2s->playback_dma_data;
 383 +       dma_data->maxburst = 16;
 384 +       dma_data->slave_id = 2; //JZ4740_DMA_TYPE_AIC_TRANSMIT;
 385 +       dma_data->addr = i2s->phys_base + I2S_REG_WREG;
 386 +
 387 +       /* Capture */
 388 +       dma_data = &i2s->capture_dma_data;
 389 +       dma_data->maxburst = 16;
 390 +       dma_data->slave_id = 3; //JZ4740_DMA_TYPE_AIC_RECEIVE;
 391 +       dma_data->addr = i2s->phys_base + I2S_REG_RREG;
 392 +}
 393 +
 394 +static int mt7620_i2s_dai_probe(struct snd_soc_dai *dai)
 395 +{
 396 +       struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 397 +       uint32_t data;
 398 +
 399 +       mt7620_i2c_init_pcm_config(i2s);
 400 +       dai->playback_dma_data = &i2s->playback_dma_data;
 401 +       dai->capture_dma_data = &i2s->capture_dma_data;
 402 +
 403 +       /* set share pins to i2s/gpio mode and i2c mode */
 404 +       data = rt_sysc_r32(0x60);
 405 +       data &= 0xFFFFFFE2;
 406 +       data |= 0x00000018;
 407 +       rt_sysc_w32(data, 0x60);
 408 +
 409 +       printk("Internal REFCLK with fractional division\n");
 410 +
 411 +       mt7620_i2s_write(i2s, I2S_REG_CFG0, I2S_REG_CFG0_DFT_THRES);
 412 +       mt7620_i2s_write(i2s, I2S_REG_CFG1, 0);
 413 +       mt7620_i2s_write(i2s, I2S_REG_INT_EN, 0);
 414 +
 415 +       mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
 416 +       mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
 417 +               i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
 418 +
 419 +       return 0;
 420 +}
 421 +
 422 +static int mt7620_i2s_dai_remove(struct snd_soc_dai *dai)
 423 +{
 424 +       return 0;
 425 +}
 426 +
 427 +static const struct snd_soc_dai_ops mt7620_i2s_dai_ops = {
 428 +       .startup = mt7620_i2s_startup,
 429 +       .shutdown = mt7620_i2s_shutdown,
 430 +       .trigger = mt7620_i2s_trigger,
 431 +       .hw_params = mt7620_i2s_hw_params,
 432 +       .set_fmt = mt7620_i2s_set_fmt,
 433 +       .set_sysclk = mt7620_i2s_set_sysclk,
 434 +};
 435 +
 436 +#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
 437 +               SNDRV_PCM_FMTBIT_S16_LE)
 438 +
 439 +static struct snd_soc_dai_driver mt7620_i2s_dai = {
 440 +       .probe = mt7620_i2s_dai_probe,
 441 +       .remove = mt7620_i2s_dai_remove,
 442 +       .playback = {
 443 +               .channels_min = 1,
 444 +               .channels_max = 2,
 445 +               .rates = SNDRV_PCM_RATE_8000_48000,
 446 +               .formats = JZ4740_I2S_FMTS,
 447 +       },
 448 +       .capture = {
 449 +               .channels_min = 2,
 450 +               .channels_max = 2,
 451 +               .rates = SNDRV_PCM_RATE_8000_48000,
 452 +               .formats = JZ4740_I2S_FMTS,
 453 +       },
 454 +       .symmetric_rates = 1,
 455 +       .ops = &mt7620_i2s_dai_ops,
 456 +       .suspend = mt7620_i2s_suspend,
 457 +       .resume = mt7620_i2s_resume,
 458 +};
 459 +
 460 +static const struct snd_pcm_hardware mt7620_pcm_hardware = {
 461 +       .info = SNDRV_PCM_INFO_MMAP |
 462 +               SNDRV_PCM_INFO_MMAP_VALID |
 463 +               SNDRV_PCM_INFO_INTERLEAVED |
 464 +               SNDRV_PCM_INFO_BLOCK_TRANSFER,
 465 +       .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
 466 +       .period_bytes_min       = PAGE_SIZE,
 467 +       .period_bytes_max       = 64 * 1024,
 468 +       .periods_min            = 2,
 469 +       .periods_max            = 128,
 470 +       .buffer_bytes_max       = 128 * 1024,
 471 +       .fifo_size              = 32,
 472 +};
 473 +
 474 +static const struct snd_dmaengine_pcm_config mt7620_dmaengine_pcm_config = {
 475 +       .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 476 +       .pcm_hardware = &mt7620_pcm_hardware,
 477 +       .prealloc_buffer_size = 256 * PAGE_SIZE,
 478 +};
 479 +
 480 +static const struct snd_soc_component_driver mt7620_i2s_component = {
 481 +       .name = "mt7620-i2s",
 482 +};
 483 +
 484 +static int mt7620_i2s_dev_probe(struct platform_device *pdev)
 485 +{
 486 +       struct mt7620_i2s *i2s;
 487 +       int ret;
 488 +
 489 +       snd_dmaengine_pcm_register(&pdev->dev,
 490 +               &mt7620_dmaengine_pcm_config,
 491 +               SND_DMAENGINE_PCM_FLAG_COMPAT);
 492 +
 493 +       i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
 494 +       if (!i2s)
 495 +               return -ENOMEM;
 496 +
 497 +       i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 498 +       if (!i2s->mem) {
 499 +               ret = -ENOENT;
 500 +               goto err_free;
 501 +       }
 502 +
 503 +       i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
 504 +                               pdev->name);
 505 +       if (!i2s->mem) {
 506 +               ret = -EBUSY;
 507 +               goto err_free;
 508 +       }
 509 +
 510 +       i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
 511 +       if (!i2s->base) {
 512 +               ret = -EBUSY;
 513 +               goto err_release_mem_region;
 514 +       }
 515 +
 516 +       i2s->phys_base = i2s->mem->start;
 517 +
 518 +       platform_set_drvdata(pdev, i2s);
 519 +       ret = snd_soc_register_component(&pdev->dev, &mt7620_i2s_component,
 520 +                                        &mt7620_i2s_dai, 1);
 521 +
 522 +       if (!ret) {
 523 +               dev_err(&pdev->dev, "loaded\n");
 524 +               return ret;
 525 +       }
 526 +
 527 +       dev_err(&pdev->dev, "Failed to register DAI\n");
 528 +       iounmap(i2s->base);
 529 +
 530 +err_release_mem_region:
 531 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 532 +err_free:
 533 +       kfree(i2s);
 534 +
 535 +       return ret;
 536 +}
 537 +
 538 +static int mt7620_i2s_dev_remove(struct platform_device *pdev)
 539 +{
 540 +       struct mt7620_i2s *i2s = platform_get_drvdata(pdev);
 541 +
 542 +       snd_soc_unregister_component(&pdev->dev);
 543 +
 544 +       iounmap(i2s->base);
 545 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 546 +
 547 +       kfree(i2s);
 548 +
 549 +       snd_dmaengine_pcm_unregister(&pdev->dev);
 550 +
 551 +       return 0;
 552 +}
 553 +
 554 +static const struct of_device_id mt7620_i2s_match[] = {
 555 +       { .compatible = "ralink,mt7620a-i2s" },
 556 +       {},
 557 +};
 558 +MODULE_DEVICE_TABLE(of, mt7620_i2s_match);
 559 +
 560 +static struct platform_driver mt7620_i2s_driver = {
 561 +       .probe = mt7620_i2s_dev_probe,
 562 +       .remove = mt7620_i2s_dev_remove,
 563 +       .driver = {
 564 +               .name = "mt7620-i2s",
 565 +               .owner = THIS_MODULE,
 566 +               .of_match_table = mt7620_i2s_match,
 567 +       },
 568 +};
 569 +
 570 +module_platform_driver(mt7620_i2s_driver);
 571 +
 572 +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
 573 +MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
 574 +MODULE_LICENSE("GPL");
 575 +MODULE_ALIAS("platform:mt7620-i2s");
 576 diff --git a/sound/soc/ralink/mt7620-wm8960.c b/sound/soc/ralink/mt7620-wm8960.c
 577 new file mode 100644
 578 index 0000000..c0f6389
 579 --- /dev/null
 580 +++ b/sound/soc/ralink/mt7620-wm8960.c
 581 @@ -0,0 +1,125 @@
 582 +/*
 583 + * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
 584 + *
 585 + * This program is free software; you can redistribute it and/or modify
 586 + * it under the terms of the GNU General Public License version 2 as
 587 + * published by the Free Software Foundation.
 588 + *
 589 + *  You should have received a copy of the  GNU General Public License along
 590 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 591 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 592 + *
 593 + */
 594 +
 595 +#include <linux/module.h>
 596 +#include <linux/moduleparam.h>
 597 +#include <linux/of.h>
 598 +#include <linux/timer.h>
 599 +#include <linux/interrupt.h>
 600 +#include <linux/platform_device.h>
 601 +#include <sound/core.h>
 602 +#include <sound/pcm.h>
 603 +#include <sound/soc.h>
 604 +
 605 +
 606 +static const struct snd_soc_dapm_widget mt7620_wm8960_widgets[] = {
 607 +       SND_SOC_DAPM_SPK("Speaker", NULL),
 608 +};
 609 +
 610 +static const struct snd_soc_dapm_route mt7620_wm8960_routes[] = {
 611 +       {"Speaker", NULL, "HP_L"},
 612 +       {"Speaker", NULL, "HP_R"},
 613 +};
 614 +
 615 +#define MT7620_DAIFMT (SND_SOC_DAIFMT_I2S | \
 616 +                       SND_SOC_DAIFMT_NB_NF | \
 617 +                       SND_SOC_DAIFMT_CBM_CFM)
 618 +
 619 +static int mt7620_wm8960_codec_init(struct snd_soc_pcm_runtime *rtd)
 620 +{
 621 +       struct snd_soc_codec *codec = rtd->codec;
 622 +       struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 623 +       struct snd_soc_dapm_context *dapm = &codec->dapm;
 624 +       int ret;
 625 +
 626 +       snd_soc_dapm_enable_pin(dapm, "HP_L");
 627 +       snd_soc_dapm_enable_pin(dapm, "HP_R");
 628 +
 629 +       ret = snd_soc_dai_set_fmt(cpu_dai, MT7620_DAIFMT);
 630 +       if (ret < 0) {
 631 +               dev_err(codec->dev, "Failed to set cpu dai format: %d\n", ret);
 632 +               return ret;
 633 +       }
 634 +
 635 +       return 0;
 636 +}
 637 +
 638 +static struct snd_soc_dai_link mt7620_wm8960_dai = {
 639 +       .name = "mt7620",
 640 +       .stream_name = "mt7620",
 641 +       .init = mt7620_wm8960_codec_init,
 642 +       .codec_dai_name = "wm8960-hifi",
 643 +};
 644 +
 645 +static struct snd_soc_card mt7620_wm8960 = {
 646 +       .name = "mt7620-wm8960",
 647 +       .owner = THIS_MODULE,
 648 +       .dai_link = &mt7620_wm8960_dai,
 649 +       .num_links = 1,
 650 +
 651 +       .dapm_widgets = mt7620_wm8960_widgets,
 652 +       .num_dapm_widgets = ARRAY_SIZE(mt7620_wm8960_widgets),
 653 +       .dapm_routes = mt7620_wm8960_routes,
 654 +       .num_dapm_routes = ARRAY_SIZE(mt7620_wm8960_routes),
 655 +};
 656 +
 657 +static int mt7620_wm8960_probe(struct platform_device *pdev)
 658 +{
 659 +       struct device_node *np = pdev->dev.of_node;
 660 +       struct snd_soc_card *card = &mt7620_wm8960;
 661 +       int ret;
 662 +
 663 +       card->dev = &pdev->dev;
 664 +
 665 +       mt7620_wm8960_dai.cpu_of_node = of_parse_phandle(np, "cpu-dai", 0);
 666 +       mt7620_wm8960_dai.codec_of_node = of_parse_phandle(np, "codec-dai", 0);
 667 +       mt7620_wm8960_dai.platform_of_node = mt7620_wm8960_dai.cpu_of_node;
 668 +
 669 +       ret = snd_soc_register_card(card);
 670 +       if (ret) {
 671 +               dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
 672 +                       ret);
 673 +       }
 674 +       return ret;
 675 +}
 676 +
 677 +static int mt7620_wm8960_remove(struct platform_device *pdev)
 678 +{
 679 +       struct snd_soc_card *card = platform_get_drvdata(pdev);
 680 +
 681 +       snd_soc_unregister_card(card);
 682 +       return 0;
 683 +}
 684 +
 685 +static const struct of_device_id mt7620_audio_match[] = {
 686 +       { .compatible = "ralink,wm8960-audio" },
 687 +       {},
 688 +};
 689 +MODULE_DEVICE_TABLE(of, mt7620_audio_match);
 690 +
 691 +static struct platform_driver mt7620_wm8960_driver = {
 692 +       .driver         = {
 693 +               .name   = "wm8960-audio",
 694 +               .owner  = THIS_MODULE,
 695 +               .of_match_table = mt7620_audio_match,
 696 +       },
 697 +       .probe          = mt7620_wm8960_probe,
 698 +       .remove         = mt7620_wm8960_remove,
 699 +};
 700 +
 701 +module_platform_driver(mt7620_wm8960_driver);
 702 +
 703 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 704 +MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support");
 705 +MODULE_LICENSE("GPL v2");
 706 +MODULE_ALIAS("platform:qi-lb60-audio");
 707 diff --git a/sound/soc/soc-io.c b/sound/soc/soc-io.c
 708 index aa886cc..3fdc8c8 100644
 709 --- a/sound/soc/soc-io.c
 710 +++ b/sound/soc/soc-io.c
 711 @@ -19,7 +19,6 @@
 712
 713  #include <trace/events/asoc.h>
 714
 715 -#ifdef CONFIG_REGMAP
 716  static int hw_write(struct snd_soc_codec *codec, unsigned int reg,
 717                     unsigned int value)
 718  {
 719 @@ -135,12 +134,3 @@ int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
 720         return PTR_ERR_OR_ZERO(codec->control_data);
 721  }
 722  EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
 723 -#else
 724 -int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
 725 -                              int addr_bits, int data_bits,
 726 -                              enum snd_soc_control_type control)
 727 -{
 728 -       return -ENOTSUPP;
 729 -}
 730 -EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
 731 -#endif
 732 --
 733 1.7.10.4
 734