target/linux/ramips/patches-3.18/0016-MIPS-ralink-add-MT7621-pcie-driver.patch

   1 From 95d7eb13a864ef666cea7f0e86349e86d80d28ce Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 16 Mar 2014 05:22:39 +0000
   4 Subject: [PATCH 16/57] MIPS: ralink: add MT7621 pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/pci/Makefile     |    1 +
   9  arch/mips/pci/pci-mt7621.c |  797 ++++++++++++++++++++++++++++++++++++++++++++
  10  2 files changed, 798 insertions(+)
  11  create mode 100644 arch/mips/pci/pci-mt7621.c
  12
  13 --- a/arch/mips/pci/Makefile
  14 +++ b/arch/mips/pci/Makefile
  15 @@ -42,6 +42,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
  16  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  17  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  18  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  19 +obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  20  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  21  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  22  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  23 --- /dev/null
  24 +++ b/arch/mips/pci/pci-mt7621.c
  25 @@ -0,0 +1,813 @@
  26 +/**************************************************************************
  27 + *
  28 + *  BRIEF MODULE DESCRIPTION
  29 + *     PCI init for Ralink RT2880 solution
  30 + *
  31 + *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  32 + *
  33 + *  This program is free software; you can redistribute  it and/or modify it
  34 + *  under  the terms of  the GNU General  Public License as published by the
  35 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  36 + *  option) any later version.
  37 + *
  38 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  39 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  40 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  41 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  42 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  43 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  44 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  45 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  46 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  47 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48 + *
  49 + *  You should have received a copy of the  GNU General Public License along
  50 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  51 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  52 + *
  53 + *
  54 + **************************************************************************
  55 + * May 2007 Bruce Chang
  56 + * Initial Release
  57 + *
  58 + * May 2009 Bruce Chang
  59 + * support RT2880/RT3883 PCIe
  60 + *
  61 + * May 2011 Bruce Chang
  62 + * support RT6855/MT7620 PCIe
  63 + *
  64 + **************************************************************************
  65 + */
  66 +
  67 +#include <linux/types.h>
  68 +#include <linux/pci.h>
  69 +#include <linux/kernel.h>
  70 +#include <linux/slab.h>
  71 +#include <linux/version.h>
  72 +#include <asm/pci.h>
  73 +#include <asm/io.h>
  74 +#include <linux/init.h>
  75 +#include <linux/module.h>
  76 +#include <linux/delay.h>
  77 +#include <linux/of.h>
  78 +#include <linux/of_pci.h>
  79 +#include <linux/platform_device.h>
  80 +
  81 +#include <ralink_regs.h>
  82 +
  83 +extern void pcie_phy_init(void);
  84 +extern void chk_phy_pll(void);
  85 +
  86 +/*
  87 + * These functions and structures provide the BIOS scan and mapping of the PCI
  88 + * devices.
  89 + */
  90 +
  91 +#define CONFIG_PCIE_PORT0
  92 +#define CONFIG_PCIE_PORT1
  93 +#define CONFIG_PCIE_PORT2
  94 +#define RALINK_PCIE0_CLK_EN             (1<<24)
  95 +#define RALINK_PCIE1_CLK_EN             (1<<25)
  96 +#define RALINK_PCIE2_CLK_EN             (1<<26)
  97 +
  98 +#define RALINK_PCI_CONFIG_ADDR                         0x20
  99 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
 100 +#define SURFBOARDINT_PCIE0       12      /* PCIE0 */
 101 +#define RALINK_INT_PCIE0         SURFBOARDINT_PCIE0
 102 +#define RALINK_INT_PCIE1         SURFBOARDINT_PCIE1
 103 +#define RALINK_INT_PCIE2         SURFBOARDINT_PCIE2
 104 +#define SURFBOARDINT_PCIE1       32     /* PCIE1 */
 105 +#define SURFBOARDINT_PCIE2       33     /* PCIE2 */
 106 +#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
 107 +#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
 108 +#define RALINK_PCIE0_RST                (1<<24)
 109 +#define RALINK_PCIE1_RST                (1<<25)
 110 +#define RALINK_PCIE2_RST                (1<<26)
 111 +#define RALINK_SYSCTL_BASE              0xBE000000
 112 +
 113 +#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
 114 +#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
 115 +#define RALINK_PCI_BASE                 0xBE140000
 116 +
 117 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
 118 +#define RT6855_PCIE0_OFFSET     0x2000
 119 +#define RT6855_PCIE1_OFFSET     0x3000
 120 +#define RT6855_PCIE2_OFFSET     0x4000
 121 +
 122 +#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
 123 +#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
 124 +#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
 125 +#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
 126 +#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
 127 +#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
 128 +#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
 129 +#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
 130 +
 131 +#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
 132 +#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
 133 +#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
 134 +#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
 135 +#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 136 +#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
 137 +#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
 138 +#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 139 +
 140 +#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 141 +#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
 142 +#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
 143 +#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 144 +#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 145 +#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
 146 +#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
 147 +#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 148 +
 149 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
 150 +#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
 151 +
 152 +
 153 +#define MV_WRITE(ofs, data)  \
 154 +        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 155 +#define MV_READ(ofs, data)   \
 156 +               *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 157 +#define MV_READ_DATA(ofs)    \
 158 +                       le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 159 +
 160 +#define MV_WRITE_16(ofs, data)  \
 161 +        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
 162 +#define MV_READ_16(ofs, data)   \
 163 +               *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
 164 +
 165 +#define MV_WRITE_8(ofs, data)  \
 166 +        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
 167 +#define MV_READ_8(ofs, data)   \
 168 +               *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 169 +
 170 +
 171 +
 172 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
 173 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
 174 +
 175 +#define RALINK_SYSTEM_CONTROL_BASE     0xbe000000
 176 +#define GPIO_PERST
 177 +#define ASSERT_SYSRST_PCIE(val)                do {    \
 178 +                                               if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 179 +                                                       RALINK_RSTCTRL |= val;  \
 180 +                                               else    \
 181 +                                                       RALINK_RSTCTRL &= ~val; \
 182 +                                       } while(0)
 183 +#define DEASSERT_SYSRST_PCIE(val)      do {    \
 184 +                                               if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 185 +                                                       RALINK_RSTCTRL &= ~val; \
 186 +                                               else    \
 187 +                                                       RALINK_RSTCTRL |= val;  \
 188 +                                       } while(0)
 189 +#define RALINK_SYSCFG1                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
 190 +#define RALINK_CLKCFG1                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
 191 +#define RALINK_RSTCTRL                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
 192 +#define RALINK_GPIOMODE                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
 193 +#define RALINK_PCIE_CLK_GEN            *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
 194 +#define RALINK_PCIE_CLK_GEN1           *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
 195 +#define PPLL_CFG1                      *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
 196 +#define PPLL_DRV                       *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
 197 +//RALINK_SYSCFG1 bit
 198 +#define RALINK_PCI_HOST_MODE_EN                (1<<7)
 199 +#define RALINK_PCIE_RC_MODE_EN         (1<<8)
 200 +//RALINK_RSTCTRL bit
 201 +#define RALINK_PCIE_RST                        (1<<23)
 202 +#define RALINK_PCI_RST                 (1<<24)
 203 +//RALINK_CLKCFG1 bit
 204 +#define RALINK_PCI_CLK_EN              (1<<19)
 205 +#define RALINK_PCIE_CLK_EN             (1<<21)
 206 +//RALINK_GPIOMODE bit
 207 +#define PCI_SLOTx2                     (1<<11)
 208 +#define PCI_SLOTx1                     (2<<11)
 209 +//MTK PCIE PLL bit
 210 +#define PDRV_SW_SET                    (1<<31)
 211 +#define LC_CKDRVPD_                    (1<<19)
 212 +
 213 +#define MEMORY_BASE 0x0
 214 +static int pcie_link_status = 0;
 215 +
 216 +#define PCI_ACCESS_READ_1  0
 217 +#define PCI_ACCESS_READ_2  1
 218 +#define PCI_ACCESS_READ_4  2
 219 +#define PCI_ACCESS_WRITE_1 3
 220 +#define PCI_ACCESS_WRITE_2 4
 221 +#define PCI_ACCESS_WRITE_4 5
 222 +
 223 +static int config_access(unsigned char access_type, struct pci_bus *bus,
 224 +                       unsigned int devfn, unsigned int where, u32 * data)
 225 +{
 226 +       unsigned int slot = PCI_SLOT(devfn);
 227 +       u8 func = PCI_FUNC(devfn);
 228 +       uint32_t address_reg, data_reg;
 229 +       unsigned int address;
 230 +
 231 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 232 +       data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 233 +
 234 +       address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 235 +       MV_WRITE(address_reg, address);
 236 +
 237 +       switch(access_type) {
 238 +       case PCI_ACCESS_WRITE_1:
 239 +               MV_WRITE_8(data_reg+(where&0x3), *data);
 240 +               break;
 241 +       case PCI_ACCESS_WRITE_2:
 242 +               MV_WRITE_16(data_reg+(where&0x3), *data);
 243 +               break;
 244 +       case PCI_ACCESS_WRITE_4:
 245 +               MV_WRITE(data_reg, *data);
 246 +               break;
 247 +       case PCI_ACCESS_READ_1:
 248 +               MV_READ_8( data_reg+(where&0x3), data);
 249 +               break;
 250 +       case PCI_ACCESS_READ_2:
 251 +               MV_READ_16(data_reg+(where&0x3), data);
 252 +               break;
 253 +       case PCI_ACCESS_READ_4:
 254 +               MV_READ(data_reg, data);
 255 +               break;
 256 +       default:
 257 +               printk("no specify access type\n");
 258 +               break;
 259 +       }
 260 +       return 0;
 261 +}
 262 +
 263 +static int
 264 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
 265 +{
 266 +       return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
 267 +}
 268 +
 269 +static int
 270 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
 271 +{
 272 +       return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
 273 +}
 274 +
 275 +static int
 276 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
 277 +{
 278 +       return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
 279 +}
 280 +
 281 +static int
 282 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
 283 +{
 284 +       if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
 285 +               return -1;
 286 +
 287 +       return PCIBIOS_SUCCESSFUL;
 288 +}
 289 +
 290 +static int
 291 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
 292 +{
 293 +       if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
 294 +               return -1;
 295 +
 296 +       return PCIBIOS_SUCCESSFUL;
 297 +}
 298 +
 299 +static int
 300 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
 301 +{
 302 +       if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
 303 +               return -1;
 304 +
 305 +       return PCIBIOS_SUCCESSFUL;
 306 +}
 307 +
 308 +
 309 +static int
 310 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 311 +{
 312 +       switch (size) {
 313 +       case 1:
 314 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 315 +       case 2:
 316 +               return read_config_word(bus, devfn, where, (u16 *) val);
 317 +       default:
 318 +               return read_config_dword(bus, devfn, where, val);
 319 +       }
 320 +}
 321 +
 322 +static int
 323 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 324 +{
 325 +       switch (size) {
 326 +       case 1:
 327 +               return write_config_byte(bus, devfn, where, (u8) val);
 328 +       case 2:
 329 +               return write_config_word(bus, devfn, where, (u16) val);
 330 +       default:
 331 +               return write_config_dword(bus, devfn, where, val);
 332 +       }
 333 +}
 334 +
 335 +struct pci_ops mt7621_pci_ops= {
 336 +       .read           =  pci_config_read,
 337 +       .write          = pci_config_write,
 338 +};
 339 +
 340 +static struct resource mt7621_res_pci_mem1 = {
 341 +       .name           = "PCI MEM1",
 342 +       .start          = RALINK_PCI_MM_MAP_BASE,
 343 +       .end            = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
 344 +       .flags          = IORESOURCE_MEM,
 345 +};
 346 +static struct resource mt7621_res_pci_io1 = {
 347 +       .name           = "PCI I/O1",
 348 +       .start          = RALINK_PCI_IO_MAP_BASE,
 349 +       .end            = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
 350 +       .flags          = IORESOURCE_IO,
 351 +};
 352 +
 353 +static struct pci_controller mt7621_controller = {
 354 +       .pci_ops        = &mt7621_pci_ops,
 355 +       .mem_resource   = &mt7621_res_pci_mem1,
 356 +       .io_resource    = &mt7621_res_pci_io1,
 357 +       .mem_offset     = 0x00000000UL,
 358 +       .io_offset      = 0x00000000UL,
 359 +       .io_map_base    = 0xa0000000,
 360 +};
 361 +
 362 +static void
 363 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
 364 +{
 365 +       unsigned int address_reg, data_reg, address;
 366 +
 367 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 368 +        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 369 +       address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 370 +        MV_WRITE(address_reg, address);
 371 +        MV_READ(data_reg, val);
 372 +       return;
 373 +}
 374 +
 375 +static void
 376 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
 377 +{
 378 +       unsigned int address_reg, data_reg, address;
 379 +
 380 +       address_reg = RALINK_PCI_CONFIG_ADDR;
 381 +       data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 382 +       address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 383 +       MV_WRITE(address_reg, address);
 384 +       MV_WRITE(data_reg, val);
 385 +       return;
 386 +}
 387 +
 388 +
 389 +int __init
 390 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 391 +{
 392 +       u16 cmd;
 393 +       u32 val;
 394 +       int irq = 0;
 395 +
 396 +       if ((dev->bus->number == 0) && (slot == 0)) {
 397 +               write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 398 +               read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 399 +               printk("BAR0 at slot 0 = %x\n", val);
 400 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 401 +       } else if((dev->bus->number == 0) && (slot == 0x1)) {
 402 +               write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 403 +               read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 404 +               printk("BAR0 at slot 1 = %x\n", val);
 405 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 406 +       } else if((dev->bus->number == 0) && (slot == 0x2)) {
 407 +               write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 408 +               read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 409 +               printk("BAR0 at slot 2 = %x\n", val);
 410 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 411 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 412 +               switch (pcie_link_status) {
 413 +               case 2:
 414 +               case 6:
 415 +                       irq = RALINK_INT_PCIE1;
 416 +                       break;
 417 +               case 4:
 418 +                       irq = RALINK_INT_PCIE2;
 419 +                       break;
 420 +               default:
 421 +                       irq = RALINK_INT_PCIE0;
 422 +               }
 423 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 424 +       } else if ((dev->bus->number == 2) && (slot == 0x0)) {
 425 +               switch (pcie_link_status) {
 426 +               case 5:
 427 +               case 6:
 428 +                       irq = RALINK_INT_PCIE2;
 429 +                       break;
 430 +               default:
 431 +                       irq = RALINK_INT_PCIE1;
 432 +               }
 433 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 434 +       } else if ((dev->bus->number == 2) && (slot == 0x1)) {
 435 +               switch (pcie_link_status) {
 436 +               case 5:
 437 +               case 6:
 438 +                       irq = RALINK_INT_PCIE2;
 439 +                       break;
 440 +               default:
 441 +                       irq = RALINK_INT_PCIE1;
 442 +               }
 443 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 444 +       } else if ((dev->bus->number ==3) && (slot == 0x0)) {
 445 +               irq = RALINK_INT_PCIE2;
 446 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 447 +       } else if ((dev->bus->number ==3) && (slot == 0x1)) {
 448 +               irq = RALINK_INT_PCIE2;
 449 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 450 +       } else if ((dev->bus->number ==3) && (slot == 0x2)) {
 451 +               irq = RALINK_INT_PCIE2;
 452 +               printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 453 +       } else {
 454 +               printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 455 +               return 0;
 456 +       }
 457 +
 458 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 459 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 460 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 461 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 462 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 463 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 464 +       return irq;
 465 +}
 466 +
 467 +void
 468 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
 469 +{
 470 +//     printk("0x%p:", addr);
 471 +//     printk(" %x", *addr);
 472 +       *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
 473 +       *(unsigned int *)(addr) |= val << start_b;
 474 +//     printk(" -> %x\n", *addr);
 475 +}
 476 +
 477 +void
 478 +bypass_pipe_rst(void)
 479 +{
 480 +#if defined (CONFIG_PCIE_PORT0)
 481 +       /* PCIe Port 0 */
 482 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 483 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 484 +#endif
 485 +#if defined (CONFIG_PCIE_PORT1)
 486 +       /* PCIe Port 1 */
 487 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 488 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 489 +#endif
 490 +#if defined (CONFIG_PCIE_PORT2)
 491 +       /* PCIe Port 2 */
 492 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);       // rg_pe1_pipe_rst_b
 493 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);       // rg_pe1_pipe_cmd_frc[4]
 494 +#endif
 495 +}
 496 +
 497 +void
 498 +set_phy_for_ssc(void)
 499 +{
 500 +       unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
 501 +
 502 +       reg = (reg >> 6) & 0x7;
 503 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
 504 +       /* Set PCIe Port0 & Port1 PHY to disable SSC */
 505 +       /* Debug Xtal Type */
 506 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);     // rg_pe1_frc_h_xtal_type
 507 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);     // rg_pe1_h_xtal_type
 508 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 0 enable control
 509 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 1 enable control
 510 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 0 disable
 511 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 1 disable
 512 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 513 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 514 +               printk("***** Xtal 40MHz *****\n");
 515 +       } else {                        // 25MHz | 20MHz Xtal
 516 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 517 +               if (reg >= 6) {
 518 +                       printk("***** Xtal 25MHz *****\n");
 519 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);     // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 520 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 521 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 522 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 523 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 524 +               } else {
 525 +                       printk("***** Xtal 20MHz *****\n");
 526 +               }
 527 +       }
 528 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);     // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 529 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);     // RG_PE1_H_PLL_BC
 530 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);     // RG_PE1_H_PLL_BP
 531 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);     // RG_PE1_H_PLL_IR
 532 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);     // RG_PE1_H_PLL_IC
 533 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);     // RG_PE1_H_PLL_BR
 534 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);     // RG_PE1_PLL_DIVEN
 535 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 536 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);     // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 537 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);     // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv
 538 +       }
 539 +       /* Enable PHY and disable force mode */
 540 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 0 enable
 541 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 1 enable
 542 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 0 disable control
 543 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 1 disable control
 544 +#endif
 545 +#if defined (CONFIG_PCIE_PORT2)
 546 +       /* Set PCIe Port2 PHY to disable SSC */
 547 +       /* Debug Xtal Type */
 548 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);       // rg_pe1_frc_h_xtal_type
 549 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);       // rg_pe1_h_xtal_type
 550 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);       // rg_pe1_frc_phy_en               //Force Port 0 enable control
 551 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);       // rg_pe1_phy_en                   //Port 0 disable
 552 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 553 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 554 +       } else {                        // 25MHz | 20MHz Xtal
 555 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 556 +               if (reg >= 6) {         // 25MHz Xtal
 557 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);       // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 558 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 559 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 560 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 561 +                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 562 +               }
 563 +       }
 564 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);       // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 565 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);       // RG_PE1_H_PLL_BC
 566 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);       // RG_PE1_H_PLL_BP
 567 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);       // RG_PE1_H_PLL_IR
 568 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);       // RG_PE1_H_PLL_IC
 569 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);       // RG_PE1_H_PLL_BR
 570 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);       // RG_PE1_PLL_DIVEN
 571 +       if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 572 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);       // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 573 +               set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);       // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv
 574 +       }
 575 +       /* Enable PHY and disable force mode */
 576 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);       // rg_pe1_phy_en                   //Port 0 enable
 577 +       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);       // rg_pe1_frc_phy_en               //Force Port 0 disable control
 578 +#endif
 579 +}
 580 +
 581 +static int mt7621_pci_probe(struct platform_device *pdev)
 582 +{
 583 +       unsigned long val = 0;
 584 +
 585 +       iomem_resource.start = 0;
 586 +       iomem_resource.end= ~0;
 587 +       ioport_resource.start= 0;
 588 +       ioport_resource.end = ~0;
 589 +
 590 +#if defined (CONFIG_PCIE_PORT0)
 591 +       val = RALINK_PCIE0_RST;
 592 +#endif
 593 +#if defined (CONFIG_PCIE_PORT1)
 594 +       val |= RALINK_PCIE1_RST;
 595 +#endif
 596 +#if defined (CONFIG_PCIE_PORT2)
 597 +       val |= RALINK_PCIE2_RST;
 598 +#endif
 599 +       ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 600 +       printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 601 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
 602 +       *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 603 +       *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
 604 +       mdelay(100);
 605 +       *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 606 +       mdelay(100);
 607 +       *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
 608 +
 609 +       mdelay(100);
 610 +#else
 611 +       *(unsigned int *)(0xbe000060) &= ~0x00000c00;
 612 +#endif
 613 +#if defined (CONFIG_PCIE_PORT0)
 614 +       val = RALINK_PCIE0_RST;
 615 +#endif
 616 +#if defined (CONFIG_PCIE_PORT1)
 617 +       val |= RALINK_PCIE1_RST;
 618 +#endif
 619 +#if defined (CONFIG_PCIE_PORT2)
 620 +       val |= RALINK_PCIE2_RST;
 621 +#endif
 622 +       DEASSERT_SYSRST_PCIE(val);
 623 +       printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 624 +
 625 +       if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
 626 +               bypass_pipe_rst();
 627 +       set_phy_for_ssc();
 628 +       printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 629 +
 630 +#if defined (CONFIG_PCIE_PORT0)
 631 +       read_config(0, 0, 0, 0x70c, &val);
 632 +       printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 633 +#endif
 634 +#if defined (CONFIG_PCIE_PORT1)
 635 +       read_config(0, 1, 0, 0x70c, &val);
 636 +       printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 637 +#endif
 638 +#if defined (CONFIG_PCIE_PORT2)
 639 +       read_config(0, 2, 0, 0x70c, &val);
 640 +       printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 641 +#endif
 642 +
 643 +       RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
 644 +       RALINK_SYSCFG1 &= ~(0x30);
 645 +       RALINK_SYSCFG1 |= (2<<4);
 646 +       RALINK_PCIE_CLK_GEN &= 0x7fffffff;
 647 +       RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
 648 +       RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
 649 +       RALINK_PCIE_CLK_GEN |= 0x80000000;
 650 +       mdelay(50);
 651 +       RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
 652 +
 653 +
 654 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/
 655 +       *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
 656 +       mdelay(100);
 657 +#else
 658 +       RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
 659 +#endif
 660 +       mdelay(500);
 661 +
 662 +
 663 +       mdelay(500);
 664 +#if defined (CONFIG_PCIE_PORT0)
 665 +       if(( RALINK_PCI0_STATUS & 0x1) == 0)
 666 +       {
 667 +               printk("PCIE0 no card, disable it(RST&CLK)\n");
 668 +               ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 669 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
 670 +               pcie_link_status &= ~(1<<0);
 671 +       } else {
 672 +               pcie_link_status |= 1<<0;
 673 +               RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 674 +       }
 675 +#endif
 676 +#if defined (CONFIG_PCIE_PORT1)
 677 +       if(( RALINK_PCI1_STATUS & 0x1) == 0)
 678 +       {
 679 +               printk("PCIE1 no card, disable it(RST&CLK)\n");
 680 +               ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 681 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
 682 +               pcie_link_status &= ~(1<<1);
 683 +       } else {
 684 +               pcie_link_status |= 1<<1;
 685 +               RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 686 +       }
 687 +#endif
 688 +#if defined (CONFIG_PCIE_PORT2)
 689 +       if (( RALINK_PCI2_STATUS & 0x1) == 0) {
 690 +               printk("PCIE2 no card, disable it(RST&CLK)\n");
 691 +               ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 692 +               RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
 693 +               pcie_link_status &= ~(1<<2);
 694 +       } else {
 695 +               pcie_link_status |= 1<<2;
 696 +               RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
 697 +       }
 698 +#endif
 699 +       if (pcie_link_status == 0)
 700 +               return 0;
 701 +
 702 +/*
 703 +pcie(2/1/0) link status        pcie2_num       pcie1_num       pcie0_num
 704 +3'b000                 x               x               x
 705 +3'b001                 x               x               0
 706 +3'b010                 x               0               x
 707 +3'b011                 x               1               0
 708 +3'b100                 0               x               x
 709 +3'b101                 1               x               0
 710 +3'b110                 1               0               x
 711 +3'b111                 2               1               0
 712 +*/
 713 +       switch(pcie_link_status) {
 714 +       case 2:
 715 +               RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
 716 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 717 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 718 +               break;
 719 +       case 4:
 720 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 721 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 722 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 723 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;    //port2
 724 +               break;
 725 +       case 5:
 726 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 727 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;    //port0
 728 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 729 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 730 +               break;
 731 +       case 6:
 732 +               RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 733 +               RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;    //port0
 734 +               RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 735 +               RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 736 +               break;
 737 +       }
 738 +       printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
 739 +       //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
 740 +
 741 +/*
 742 +       ioport_resource.start = mt7621_res_pci_io1.start;
 743 +       ioport_resource.end = mt7621_res_pci_io1.end;
 744 +*/
 745 +
 746 +       RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
 747 +       RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
 748 +
 749 +#if defined (CONFIG_PCIE_PORT0)
 750 +       //PCIe0
 751 +       if((pcie_link_status & 0x1) != 0) {
 752 +               RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 753 +               RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
 754 +               RALINK_PCI0_CLASS = 0x06040001;
 755 +               printk("PCIE0 enabled\n");
 756 +       }
 757 +#endif
 758 +#if defined (CONFIG_PCIE_PORT1)
 759 +       //PCIe1
 760 +       if ((pcie_link_status & 0x2) != 0) {
 761 +               RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 762 +               RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
 763 +               RALINK_PCI1_CLASS = 0x06040001;
 764 +               printk("PCIE1 enabled\n");
 765 +       }
 766 +#endif
 767 +#if defined (CONFIG_PCIE_PORT2)
 768 +       //PCIe2
 769 +       if ((pcie_link_status & 0x4) != 0) {
 770 +               RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 771 +               RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
 772 +               RALINK_PCI2_CLASS = 0x06040001;
 773 +               printk("PCIE2 enabled\n");
 774 +       }
 775 +#endif
 776 +
 777 +
 778 +       switch(pcie_link_status) {
 779 +       case 7:
 780 +               read_config(0, 2, 0, 0x4, &val);
 781 +               write_config(0, 2, 0, 0x4, val|0x4);
 782 +               // write_config(0, 1, 0, 0x4, val|0x7);
 783 +               read_config(0, 2, 0, 0x70c, &val);
 784 +               val &= ~(0xff)<<8;
 785 +               val |= 0x50<<8;
 786 +               write_config(0, 2, 0, 0x70c, val);
 787 +       case 3:
 788 +       case 5:
 789 +       case 6:
 790 +               read_config(0, 1, 0, 0x4, &val);
 791 +               write_config(0, 1, 0, 0x4, val|0x4);
 792 +               // write_config(0, 1, 0, 0x4, val|0x7);
 793 +               read_config(0, 1, 0, 0x70c, &val);
 794 +               val &= ~(0xff)<<8;
 795 +               val |= 0x50<<8;
 796 +               write_config(0, 1, 0, 0x70c, val);
 797 +       default:
 798 +               read_config(0, 0, 0, 0x4, &val);
 799 +               write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
 800 +               // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
 801 +               read_config(0, 0, 0, 0x70c, &val);
 802 +               val &= ~(0xff)<<8;
 803 +               val |= 0x50<<8;
 804 +               write_config(0, 0, 0, 0x70c, val);
 805 +       }
 806 +
 807 +       pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
 808 +       register_pci_controller(&mt7621_controller);
 809 +       return 0;
 810 +
 811 +}
 812 +
 813 +int pcibios_plat_dev_init(struct pci_dev *dev)
 814 +{
 815 +       return 0;
 816 +}
 817 +
 818 +static const struct of_device_id mt7621_pci_ids[] = {
 819 +       { .compatible = "mediatek,mt7621-pci" },
 820 +       {},
 821 +};
 822 +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 823 +
 824 +static struct platform_driver mt7621_pci_driver = {
 825 +       .probe = mt7621_pci_probe,
 826 +       .driver = {
 827 +               .name = "mt7621-pci",
 828 +               .owner = THIS_MODULE,
 829 +               .of_match_table = of_match_ptr(mt7621_pci_ids),
 830 +       },
 831 +};
 832 +
 833 +static int __init mt7621_pci_init(void)
 834 +{
 835 +       return platform_driver_register(&mt7621_pci_driver);
 836 +}
 837 +
 838 +arch_initcall(mt7621_pci_init);