target/linux/ramips/patches-3.18/0026-MIPS-ralink-add-mt7628an-support.patch

   1 From a375beba066516ecafddebc765454ac6ec599f3d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 6 Aug 2014 18:26:08 +0200
   4 Subject: [PATCH 26/57] MIPS: ralink: add mt7628an support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/mt7620.h |   11 ++
   9  arch/mips/ralink/Kconfig                   |    2 +-
  10  arch/mips/ralink/mt7620.c                  |  266 +++++++++++++++++++++++-----
  11  3 files changed, 232 insertions(+), 47 deletions(-)
  12
  13 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  14 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  15 @@ -13,6 +13,13 @@
  16  #ifndef _MT7620_REGS_H_
  17  #define _MT7620_REGS_H_
  18
  19 +enum mt762x_soc_type {
  20 +       MT762X_SOC_UNKNOWN = 0,
  21 +       MT762X_SOC_MT7620A,
  22 +       MT762X_SOC_MT7620N,
  23 +       MT762X_SOC_MT7628AN,
  24 +};
  25 +
  26  #define MT7620_SYSC_BASE               0x10000000
  27
  28  #define SYSC_REG_CHIP_NAME0            0x00
  29 @@ -27,6 +34,7 @@
  30
  31  #define MT7620_CHIP_NAME0              0x3637544d
  32  #define MT7620_CHIP_NAME1              0x20203032
  33 +#define MT7628_CHIP_NAME1              0x20203832
  34
  35  #define SYSCFG0_XTAL_FREQ_SEL          BIT(6)
  36
  37 @@ -71,6 +79,9 @@
  38  #define SYSCFG0_DRAM_TYPE_DDR1         1
  39  #define SYSCFG0_DRAM_TYPE_DDR2         2
  40
  41 +#define SYSCFG0_DRAM_TYPE_DDR2_MT7628  0
  42 +#define SYSCFG0_DRAM_TYPE_DDR1_MT7628  1
  43 +
  44  #define MT7620_DRAM_BASE               0x0
  45  #define MT7620_SDRAM_SIZE_MIN          2
  46  #define MT7620_SDRAM_SIZE_MAX          64
  47 --- a/arch/mips/ralink/Kconfig
  48 +++ b/arch/mips/ralink/Kconfig
  49 @@ -41,7 +41,7 @@ choice
  50                 select HW_HAS_PCI
  51
  52         config SOC_MT7620
  53 -               bool "MT7620"
  54 +               bool "MT7620/8"
  55
  56         config SOC_MT7621
  57                 bool "MT7621"
  58 --- a/arch/mips/ralink/mt7620.c
  59 +++ b/arch/mips/ralink/mt7620.c
  60 @@ -42,6 +42,8 @@
  61  #define CLKCFG_FFRAC_MASK      0x001f
  62  #define CLKCFG_FFRAC_USB_VAL   0x0003
  63
  64 +enum mt762x_soc_type mt762x_soc;
  65 +
  66  /* does the board have sdram or ddram */
  67  static int dram_type;
  68
  69 @@ -159,6 +161,125 @@ struct ralink_pinmux rt_gpio_pinmux = {
  70         .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
  71  };
  72
  73 +static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
  74 +       FUNC("sdcx", 3, 19, 1),
  75 +       FUNC("utif", 2, 19, 1),
  76 +       FUNC("gpio", 1, 19, 1),
  77 +       FUNC("pwm", 0, 19, 1),
  78 +};
  79 +
  80 +static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
  81 +       FUNC("sdcx", 3, 18, 1),
  82 +       FUNC("utif", 2, 18, 1),
  83 +       FUNC("gpio", 1, 18, 1),
  84 +       FUNC("pwm", 0, 18, 1),
  85 +};
  86 +
  87 +static struct rt2880_pmx_func uart2_grp_mt7628[] = {
  88 +       FUNC("sdcx", 3, 20, 2),
  89 +       FUNC("pwm", 2, 20, 2),
  90 +       FUNC("gpio", 1, 20, 2),
  91 +       FUNC("uart", 0, 20, 2),
  92 +};
  93 +
  94 +static struct rt2880_pmx_func uart1_grp_mt7628[] = {
  95 +       FUNC("sdcx", 3, 45, 2),
  96 +       FUNC("pwm", 2, 45, 2),
  97 +       FUNC("gpio", 1, 45, 2),
  98 +       FUNC("uart", 0, 45, 2),
  99 +};
 100 +
 101 +static struct rt2880_pmx_func i2c_grp_mt7628[] = {
 102 +       FUNC("-", 3, 4, 2),
 103 +       FUNC("debug", 2, 4, 2),
 104 +       FUNC("gpio", 1, 4, 2),
 105 +       FUNC("i2c", 0, 4, 2),
 106 +};
 107 +
 108 +static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
 109 +static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
 110 +static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
 111 +static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
 112 +
 113 +static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
 114 +       FUNC("jtag", 3, 22, 8),
 115 +       FUNC("utif", 2, 22, 8),
 116 +       FUNC("gpio", 1, 22, 8),
 117 +       FUNC("sdcx", 0, 22, 8),
 118 +};
 119 +
 120 +static struct rt2880_pmx_func uart0_grp_mt7628[] = {
 121 +       FUNC("-", 3, 12, 2),
 122 +       FUNC("-", 2, 12, 2),
 123 +       FUNC("gpio", 1, 12, 2),
 124 +       FUNC("uart", 0, 12, 2),
 125 +};
 126 +
 127 +static struct rt2880_pmx_func i2s_grp_mt7628[] = {
 128 +       FUNC("antenna", 3, 0, 4),
 129 +       FUNC("pcm", 2, 0, 4),
 130 +       FUNC("gpio", 1, 0, 4),
 131 +       FUNC("i2s", 0, 0, 4),
 132 +};
 133 +
 134 +static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
 135 +       FUNC("-", 3, 6, 1),
 136 +       FUNC("refclk", 2, 6, 1),
 137 +       FUNC("gpio", 1, 6, 1),
 138 +       FUNC("spi", 0, 6, 1),
 139 +};
 140 +
 141 +static struct rt2880_pmx_func spis_grp_mt7628[] = {
 142 +       FUNC("pwm", 3, 14, 4),
 143 +       FUNC("util", 2, 14, 4),
 144 +       FUNC("gpio", 1, 14, 4),
 145 +       FUNC("spis", 0, 14, 4),
 146 +};
 147 +
 148 +static struct rt2880_pmx_func gpio_grp_mt7628[] = {
 149 +       FUNC("pcie", 3, 11, 1),
 150 +       FUNC("refclk", 2, 11, 1),
 151 +       FUNC("gpio", 1, 11, 1),
 152 +       FUNC("gpio", 0, 11, 1),
 153 +};
 154 +
 155 +#define MT7628_GPIO_MODE_MASK  0x3
 156 +
 157 +#define MT7628_GPIO_MODE_PWM1  30
 158 +#define MT7628_GPIO_MODE_PWM0  28
 159 +#define MT7628_GPIO_MODE_UART2 26
 160 +#define MT7628_GPIO_MODE_UART1 24
 161 +#define MT7628_GPIO_MODE_I2C   20
 162 +#define MT7628_GPIO_MODE_REFCLK        18
 163 +#define MT7628_GPIO_MODE_PERST 16
 164 +#define MT7628_GPIO_MODE_WDT   14
 165 +#define MT7628_GPIO_MODE_SPI   12
 166 +#define MT7628_GPIO_MODE_SDMODE        10
 167 +#define MT7628_GPIO_MODE_UART0 8
 168 +#define MT7628_GPIO_MODE_I2S   6
 169 +#define MT7628_GPIO_MODE_CS1   4
 170 +#define MT7628_GPIO_MODE_SPIS  2
 171 +#define MT7628_GPIO_MODE_GPIO  0
 172 +
 173 +static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
 174 +       GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1),
 175 +       GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0),
 176 +       GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2),
 177 +       GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART1),
 178 +       GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2C),
 179 +       GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
 180 +       GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
 181 +       GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
 182 +       GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
 183 +       GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SDMODE),
 184 +       GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART0),
 185 +       GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2S),
 186 +       GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_CS1),
 187 +       GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SPIS),
 188 +       GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_GPIO),
 189 +       { 0 }
 190 +};
 191 +
 192  static __init u32
 193  mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
 194  {
 195 @@ -309,29 +430,42 @@ void __init ralink_clk_init(void)
 196
 197         xtal_rate = mt7620_get_xtal_rate();
 198
 199 -       cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 200 -       pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
 201 -
 202 -       cpu_rate = mt7620_get_cpu_rate(pll_rate);
 203 -       dram_rate = mt7620_get_dram_rate(pll_rate);
 204 -       sys_rate = mt7620_get_sys_rate(cpu_rate);
 205 -       periph_rate = mt7620_get_periph_rate(xtal_rate);
 206 -
 207  #define RFMT(label)    label ":%lu.%03luMHz "
 208  #define RINT(x)                ((x) / 1000000)
 209  #define RFRAC(x)       (((x) / 1000) % 1000)
 210
 211 -       pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
 212 -                RINT(xtal_rate), RFRAC(xtal_rate),
 213 -                RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
 214 -                RINT(pll_rate), RFRAC(pll_rate));
 215 +       if (mt762x_soc == MT762X_SOC_MT7628AN) {
 216 +               if (xtal_rate == MHZ(40))
 217 +                       cpu_rate = MHZ(580);
 218 +               else
 219 +                       cpu_rate = MHZ(575);
 220 +               dram_rate = sys_rate = cpu_rate / 3;
 221 +               periph_rate = MHZ(40);
 222 +
 223 +               ralink_clk_add("10000d00.uartlite", periph_rate);
 224 +               ralink_clk_add("10000e00.uartlite", periph_rate);
 225 +       } else {
 226 +               cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 227 +               pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
 228 +
 229 +               cpu_rate = mt7620_get_cpu_rate(pll_rate);
 230 +               dram_rate = mt7620_get_dram_rate(pll_rate);
 231 +               sys_rate = mt7620_get_sys_rate(cpu_rate);
 232 +               periph_rate = mt7620_get_periph_rate(xtal_rate);
 233 +
 234 +               pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
 235 +                        RINT(xtal_rate), RFRAC(xtal_rate),
 236 +                        RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
 237 +                        RINT(pll_rate), RFRAC(pll_rate));
 238 +
 239 +               ralink_clk_add("10000500.uart", periph_rate);
 240 +       }
 241
 242         pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
 243                  RINT(cpu_rate), RFRAC(cpu_rate),
 244                  RINT(dram_rate), RFRAC(dram_rate),
 245                  RINT(sys_rate), RFRAC(sys_rate),
 246                  RINT(periph_rate), RFRAC(periph_rate));
 247 -
 248  #undef RFRAC
 249  #undef RINT
 250  #undef RFMT
 251 @@ -339,12 +473,11 @@ void __init ralink_clk_init(void)
 252         ralink_clk_add("cpu", cpu_rate);
 253         ralink_clk_add("10000100.timer", periph_rate);
 254         ralink_clk_add("10000120.watchdog", periph_rate);
 255 -       ralink_clk_add("10000500.uart", periph_rate);
 256         ralink_clk_add("10000b00.spi", sys_rate);
 257         ralink_clk_add("10000c00.uartlite", periph_rate);
 258         ralink_clk_add("10180000.wmac", xtal_rate);
 259
 260 -       if (IS_ENABLED(CONFIG_USB)) {
 261 +       if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
 262                 /*
 263                  * When the CPU goes into sleep mode, the BUS clock will be too low for
 264                  * USB to function properly
 265 @@ -367,6 +500,52 @@ void __init ralink_of_remap(void)
 266                 panic("Failed to remap core resources");
 267  }
 268
 269 +static __init void
 270 +mt7620_dram_init(struct ralink_soc_info *soc_info)
 271 +{
 272 +       switch (dram_type) {
 273 +       case SYSCFG0_DRAM_TYPE_SDRAM:
 274 +               pr_info("Board has SDRAM\n");
 275 +               soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
 276 +               soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
 277 +               break;
 278 +
 279 +       case SYSCFG0_DRAM_TYPE_DDR1:
 280 +               pr_info("Board has DDR1\n");
 281 +               soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 282 +               soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 283 +               break;
 284 +
 285 +       case SYSCFG0_DRAM_TYPE_DDR2:
 286 +               pr_info("Board has DDR2\n");
 287 +               soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 288 +               soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 289 +               break;
 290 +       default:
 291 +               BUG();
 292 +       }
 293 +}
 294 +
 295 +static __init void
 296 +mt7628_dram_init(struct ralink_soc_info *soc_info)
 297 +{
 298 +       switch (dram_type) {
 299 +       case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
 300 +               pr_info("Board has DDR1\n");
 301 +               soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 302 +               soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 303 +               break;
 304 +
 305 +       case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
 306 +               pr_info("Board has DDR2\n");
 307 +               soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 308 +               soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 309 +               break;
 310 +       default:
 311 +               BUG();
 312 +       }
 313 +}
 314 +
 315  void prom_soc_init(struct ralink_soc_info *soc_info)
 316  {
 317         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
 318 @@ -384,18 +563,25 @@ void prom_soc_init(struct ralink_soc_inf
 319         rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 320         bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
 321
 322 -       if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
 323 -               panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 324 -
 325 -       if (bga) {
 326 -               name = "MT7620A";
 327 -               soc_info->compatible = "ralink,mt7620a-soc";
 328 -       } else {
 329 -               name = "MT7620N";
 330 -               soc_info->compatible = "ralink,mt7620n-soc";
 331 +       if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
 332 +               if (bga) {
 333 +                       mt762x_soc = MT762X_SOC_MT7620A;
 334 +                       name = "MT7620A";
 335 +                       soc_info->compatible = "ralink,mt7620a-soc";
 336 +               } else {
 337 +                       mt762x_soc = MT762X_SOC_MT7620N;
 338 +                       name = "MT7620N";
 339 +                       soc_info->compatible = "ralink,mt7620n-soc";
 340  #ifdef CONFIG_PCI
 341 -               panic("mt7620n is only supported for non pci kernels");
 342 +                       panic("mt7620n is only supported for non pci kernels");
 343  #endif
 344 +               }
 345 +       } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
 346 +               mt762x_soc = MT762X_SOC_MT7628AN;
 347 +               name = "MT7628AN";
 348 +               soc_info->compatible = "ralink,mt7628an-soc";
 349 +       } else {
 350 +               panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 351         }
 352
 353         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 354 @@ -407,28 +593,11 @@ void prom_soc_init(struct ralink_soc_inf
 355         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 356         dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
 357
 358 -       switch (dram_type) {
 359 -       case SYSCFG0_DRAM_TYPE_SDRAM:
 360 -               pr_info("Board has SDRAM\n");
 361 -               soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
 362 -               soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
 363 -               break;
 364 -
 365 -       case SYSCFG0_DRAM_TYPE_DDR1:
 366 -               pr_info("Board has DDR1\n");
 367 -               soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
 368 -               soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
 369 -               break;
 370 -
 371 -       case SYSCFG0_DRAM_TYPE_DDR2:
 372 -               pr_info("Board has DDR2\n");
 373 -               soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
 374 -               soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
 375 -               break;
 376 -       default:
 377 -               BUG();
 378 -       }
 379         soc_info->mem_base = MT7620_DRAM_BASE;
 380 +       if (mt762x_soc == MT762X_SOC_MT7628AN)
 381 +               mt7628_dram_init(soc_info);
 382 +       else
 383 +               mt7620_dram_init(soc_info);
 384
 385         pmu0 = __raw_readl(sysc + PMU0_CFG);
 386         pmu1 = __raw_readl(sysc + PMU1_CFG);
 387 @@ -437,4 +606,9 @@ void prom_soc_init(struct ralink_soc_inf
 388                 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
 389         pr_info("Digital PMU set to %s control\n",
 390                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 391 +
 392 +       if (mt762x_soc == MT762X_SOC_MT7628AN)
 393 +               rt2880_pinmux_data = mt7628an_pinmux_data;
 394 +       else
 395 +               rt2880_pinmux_data = mt7620a_pinmux_data;
 396  }