target/linux/ramips/patches-3.18/0048-GPIO-ralink-add-mt7621-gpio-controller.patch

   1 From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:00:32 +0100
   4 Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/Kconfig          |    3 +
   9  drivers/gpio/Kconfig       |    6 ++
  10  drivers/gpio/Makefile      |    1 +
  11  drivers/gpio/gpio-mt7621.c |  177 ++++++++++++++++++++++++++++++++++++++++++++
  12  4 files changed, 187 insertions(+)
  13  create mode 100644 drivers/gpio/gpio-mt7621.c
  14
  15 --- a/arch/mips/Kconfig
  16 +++ b/arch/mips/Kconfig
  17 @@ -455,6 +455,9 @@ config RALINK
  18         select RESET_CONTROLLER
  19         select PINCTRL
  20         select PINCTRL_RT2880
  21 +       select ARCH_HAS_RESET_CONTROLLER
  22 +       select RESET_CONTROLLER
  23 +       select ARCH_REQUIRE_GPIOLIB
  24
  25  config SGI_IP22
  26         bool "SGI IP22 (Indy/Indigo2)"
  27 --- a/drivers/gpio/Kconfig
  28 +++ b/drivers/gpio/Kconfig
  29 @@ -898,6 +898,12 @@ config GPIO_BCM_KONA
  30         help
  31           Turn on GPIO support for Broadcom "Kona" chips.
  32
  33 +config GPIO_MT7621
  34 +       bool "Mediatek GPIO Support"
  35 +       depends on SOC_MT7620 || SOC_MT7621
  36 +       help
  37 +         Say yes here to support the Mediatek SoC GPIO device
  38 +
  39  comment "USB GPIO expanders:"
  40
  41  config GPIO_VIPERBOARD
  42 --- a/drivers/gpio/Makefile
  43 +++ b/drivers/gpio/Makefile
  44 @@ -107,3 +107,5 @@ obj-$(CONFIG_GPIO_XILINX)   += gpio-xilinx
  45  obj-$(CONFIG_GPIO_XTENSA)      += gpio-xtensa.o
  46  obj-$(CONFIG_GPIO_ZEVIO)       += gpio-zevio.o
  47  obj-$(CONFIG_GPIO_ZYNQ)                += gpio-zynq.o
  48 +obj-$(CONFIG_GPIO_MT7621)      += gpio-mt7621.o
  49 +
  50 --- /dev/null
  51 +++ b/drivers/gpio/gpio-mt7621.c
  52 @@ -0,0 +1,354 @@
  53 +/*
  54 + * This program is free software; you can redistribute it and/or modify it
  55 + * under the terms of the GNU General Public License version 2 as published
  56 + * by the Free Software Foundation.
  57 + *
  58 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  59 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  60 + */
  61 +
  62 +#include <linux/io.h>
  63 +#include <linux/err.h>
  64 +#include <linux/gpio.h>
  65 +#include <linux/module.h>
  66 +#include <linux/of_irq.h>
  67 +#include <linux/spinlock.h>
  68 +#include <linux/irqdomain.h>
  69 +#include <linux/interrupt.h>
  70 +#include <linux/platform_device.h>
  71 +
  72 +#define MTK_MAX_BANK           3
  73 +#define MTK_BANK_WIDTH         32
  74 +
  75 +enum mediatek_gpio_reg {
  76 +       GPIO_REG_CTRL = 0,
  77 +       GPIO_REG_POL,
  78 +       GPIO_REG_DATA,
  79 +       GPIO_REG_DSET,
  80 +       GPIO_REG_DCLR,
  81 +       GPIO_REG_REDGE,
  82 +       GPIO_REG_FEDGE,
  83 +       GPIO_REG_HLVL,
  84 +       GPIO_REG_LLVL,
  85 +       GPIO_REG_STAT,
  86 +       GPIO_REG_EDGE,
  87 +};
  88 +
  89 +static void __iomem *mediatek_gpio_membase;
  90 +static int mediatek_gpio_irq;
  91 +static struct irq_domain *mediatek_gpio_irq_domain;
  92 +static atomic_t irq_refcount = ATOMIC_INIT(0);
  93 +
  94 +struct mtk_gc {
  95 +       struct gpio_chip chip;
  96 +       spinlock_t lock;
  97 +       int bank;
  98 +       u32 rising;
  99 +       u32 falling;
 100 +} *gc_map[MTK_MAX_BANK];
 101 +
 102 +static inline struct mtk_gc
 103 +*to_mediatek_gpio(struct gpio_chip *chip)
 104 +{
 105 +       struct mtk_gc *mgc;
 106 +
 107 +       mgc = container_of(chip, struct mtk_gc, chip);
 108 +
 109 +       return mgc;
 110 +}
 111 +
 112 +static inline void
 113 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
 114 +{
 115 +       iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
 116 +}
 117 +
 118 +static inline u32
 119 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
 120 +{
 121 +       return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
 122 +}
 123 +
 124 +static void
 125 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 126 +{
 127 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 128 +
 129 +       mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
 130 +}
 131 +
 132 +static int
 133 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
 134 +{
 135 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 136 +
 137 +       return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 138 +}
 139 +
 140 +static int
 141 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 142 +{
 143 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 144 +       unsigned long flags;
 145 +       u32 t;
 146 +
 147 +       spin_lock_irqsave(&rg->lock, flags);
 148 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 149 +       t &= ~BIT(offset);
 150 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 151 +       spin_unlock_irqrestore(&rg->lock, flags);
 152 +
 153 +       return 0;
 154 +}
 155 +
 156 +static int
 157 +mediatek_gpio_direction_output(struct gpio_chip *chip,
 158 +                                       unsigned offset, int value)
 159 +{
 160 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 161 +       unsigned long flags;
 162 +       u32 t;
 163 +
 164 +       spin_lock_irqsave(&rg->lock, flags);
 165 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 166 +       t |= BIT(offset);
 167 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 168 +       mediatek_gpio_set(chip, offset, value);
 169 +       spin_unlock_irqrestore(&rg->lock, flags);
 170 +
 171 +       return 0;
 172 +}
 173 +
 174 +static int
 175 +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 176 +{
 177 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 178 +       unsigned long flags;
 179 +       u32 t;
 180 +
 181 +       spin_lock_irqsave(&rg->lock, flags);
 182 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 183 +       spin_unlock_irqrestore(&rg->lock, flags);
 184 +
 185 +       if (t & BIT(offset))
 186 +               return 0;
 187 +
 188 +       return 1;
 189 +}
 190 +
 191 +static int
 192 +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 193 +{
 194 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 195 +
 196 +       return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
 197 +}
 198 +
 199 +static int
 200 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
 201 +{
 202 +       const __be32 *id = of_get_property(bank, "reg", NULL);
 203 +       struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
 204 +                               sizeof(struct mtk_gc), GFP_KERNEL);
 205 +
 206 +       if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
 207 +               return -ENOMEM;
 208 +
 209 +       gc_map[be32_to_cpu(*id)] = rg;
 210 +
 211 +       memset(rg, 0, sizeof(struct mtk_gc));
 212 +
 213 +       spin_lock_init(&rg->lock);
 214 +
 215 +       rg->chip.dev = &pdev->dev;
 216 +       rg->chip.label = dev_name(&pdev->dev);
 217 +       rg->chip.of_node = bank;
 218 +       rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
 219 +       rg->chip.ngpio = MTK_BANK_WIDTH;
 220 +       rg->chip.direction_input = mediatek_gpio_direction_input;
 221 +       rg->chip.direction_output = mediatek_gpio_direction_output;
 222 +       rg->chip.get_direction = mediatek_gpio_get_direction;
 223 +       rg->chip.get = mediatek_gpio_get;
 224 +       rg->chip.set = mediatek_gpio_set;
 225 +       if (mediatek_gpio_irq_domain)
 226 +               rg->chip.to_irq = mediatek_gpio_to_irq;
 227 +       rg->bank = be32_to_cpu(*id);
 228 +
 229 +       /* set polarity to low for all gpios */
 230 +       mtk_gpio_w32(rg, GPIO_REG_POL, 0);
 231 +
 232 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 233 +
 234 +       return gpiochip_add(&rg->chip);
 235 +}
 236 +
 237 +static void
 238 +mediatek_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 239 +{
 240 +       int i;
 241 +
 242 +       for (i = 0; i < MTK_MAX_BANK; i++) {
 243 +               struct mtk_gc *rg = gc_map[i];
 244 +               unsigned long pending;
 245 +               int bit;
 246 +
 247 +               if (!rg)
 248 +                       continue;
 249 +
 250 +               pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
 251 +
 252 +               for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
 253 +                       u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
 254 +
 255 +                       generic_handle_irq(map);
 256 +                       mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
 257 +               }
 258 +       }
 259 +}
 260 +
 261 +static void
 262 +mediatek_gpio_irq_unmask(struct irq_data *d)
 263 +{
 264 +       int pin = d->hwirq;
 265 +       int bank = pin / 32;
 266 +       struct mtk_gc *rg = gc_map[bank];
 267 +       unsigned long flags;
 268 +       u32 rise, fall;
 269 +
 270 +       if (!rg)
 271 +               return;
 272 +
 273 +       rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
 274 +       fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
 275 +
 276 +       spin_lock_irqsave(&rg->lock, flags);
 277 +       mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
 278 +       mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
 279 +       spin_unlock_irqrestore(&rg->lock, flags);
 280 +}
 281 +
 282 +static void
 283 +mediatek_gpio_irq_mask(struct irq_data *d)
 284 +{
 285 +       int pin = d->hwirq;
 286 +       int bank = pin / 32;
 287 +       struct mtk_gc *rg = gc_map[bank];
 288 +       unsigned long flags;
 289 +       u32 rise, fall;
 290 +
 291 +       if (!rg)
 292 +               return;
 293 +
 294 +       rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
 295 +       fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
 296 +
 297 +       spin_lock_irqsave(&rg->lock, flags);
 298 +       mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
 299 +       mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
 300 +       spin_unlock_irqrestore(&rg->lock, flags);
 301 +}
 302 +
 303 +static int
 304 +mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
 305 +{
 306 +       int pin = d->hwirq;
 307 +       int bank = pin / 32;
 308 +       struct mtk_gc *rg = gc_map[bank];
 309 +       u32 mask = BIT(d->hwirq);
 310 +
 311 +       if (!rg)
 312 +               return -1;
 313 +
 314 +       if (type == IRQ_TYPE_PROBE) {
 315 +               if ((rg->rising | rg->falling) & mask)
 316 +                       return 0;
 317 +
 318 +               type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 319 +       }
 320 +
 321 +       if (type & IRQ_TYPE_EDGE_RISING)
 322 +               rg->rising |= mask;
 323 +       else
 324 +               rg->rising &= ~mask;
 325 +
 326 +       if (type & IRQ_TYPE_EDGE_FALLING)
 327 +               rg->falling |= mask;
 328 +       else
 329 +               rg->falling &= ~mask;
 330 +
 331 +       return 0;
 332 +}
 333 +
 334 +static struct irq_chip mediatek_gpio_irq_chip = {
 335 +       .name           = "GPIO",
 336 +       .irq_unmask     = mediatek_gpio_irq_unmask,
 337 +       .irq_mask       = mediatek_gpio_irq_mask,
 338 +       .irq_mask_ack   = mediatek_gpio_irq_mask,
 339 +       .irq_set_type   = mediatek_gpio_irq_type,
 340 +};
 341 +
 342 +static int
 343 +mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 344 +{
 345 +       irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
 346 +       irq_set_handler_data(irq, d);
 347 +
 348 +       return 0;
 349 +}
 350 +
 351 +static const struct irq_domain_ops irq_domain_ops = {
 352 +       .xlate = irq_domain_xlate_onecell,
 353 +       .map = mediatek_gpio_gpio_map,
 354 +};
 355 +
 356 +static int
 357 +mediatek_gpio_probe(struct platform_device *pdev)
 358 +{
 359 +       struct device_node *bank, *np = pdev->dev.of_node;
 360 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 361 +
 362 +       mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
 363 +       if (IS_ERR(mediatek_gpio_membase))
 364 +               return PTR_ERR(mediatek_gpio_membase);
 365 +
 366 +       mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
 367 +       if (mediatek_gpio_irq) {
 368 +               mediatek_gpio_irq_domain = irq_domain_add_linear(np,
 369 +                       MTK_MAX_BANK * MTK_BANK_WIDTH,
 370 +                       &irq_domain_ops, NULL);
 371 +               if (!mediatek_gpio_irq_domain)
 372 +                       dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
 373 +       }
 374 +
 375 +       for_each_child_of_node(np, bank)
 376 +               if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
 377 +                       mediatek_gpio_bank_probe(pdev, bank);
 378 +
 379 +       if (mediatek_gpio_irq_domain)
 380 +               irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
 381 +
 382 +       return 0;
 383 +}
 384 +
 385 +static const struct of_device_id mediatek_gpio_match[] = {
 386 +       { .compatible = "mtk,mt7621-gpio" },
 387 +       {},
 388 +};
 389 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
 390 +
 391 +static struct platform_driver mediatek_gpio_driver = {
 392 +       .probe = mediatek_gpio_probe,
 393 +       .driver = {
 394 +               .name = "mt7621_gpio",
 395 +               .owner = THIS_MODULE,
 396 +               .of_match_table = mediatek_gpio_match,
 397 +       },
 398 +};
 399 +
 400 +static int __init
 401 +mediatek_gpio_init(void)
 402 +{
 403 +       return platform_driver_register(&mediatek_gpio_driver);
 404 +}
 405 +
 406 +subsys_initcall(mediatek_gpio_init);