target/linux/ramips/patches-3.18/0060-soc_type.patch

   1 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
   2 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
   3 @@ -13,14 +13,6 @@
   4  #ifndef _MT7620_REGS_H_
   5  #define _MT7620_REGS_H_
   6
   7 -enum mt762x_soc_type {
   8 -       MT762X_SOC_UNKNOWN = 0,
   9 -       MT762X_SOC_MT7620A,
  10 -       MT762X_SOC_MT7620N,
  11 -       MT762X_SOC_MT7628AN,
  12 -};
  13 -extern enum mt762x_soc_type mt762x_soc;
  14 -
  15  #define MT7620_SYSC_BASE               0x10000000
  16
  17  #define SYSC_REG_CHIP_NAME0            0x00
  18 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
  19 +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
  20 @@ -13,6 +13,20 @@
  21  #ifndef _RALINK_REGS_H_
  22  #define _RALINK_REGS_H_
  23
  24 +enum ralink_soc_type {
  25 +       RALINK_UNKNOWN = 0,
  26 +       RT305X_SOC_RT3050,
  27 +       RT305X_SOC_RT3052,
  28 +       RT305X_SOC_RT3350,
  29 +       RT305X_SOC_RT3352,
  30 +       RT305X_SOC_RT5350,
  31 +       MT762X_SOC_MT7620A,
  32 +       MT762X_SOC_MT7620N,
  33 +       MT762X_SOC_MT7621AT,
  34 +       MT762X_SOC_MT7628AN,
  35 +};
  36 +extern enum ralink_soc_type ralink_soc;
  37 +
  38  extern __iomem void *rt_sysc_membase;
  39  extern __iomem void *rt_memc_membase;
  40
  41 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
  42 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
  43 @@ -13,25 +13,16 @@
  44  #ifndef _RT305X_REGS_H_
  45  #define _RT305X_REGS_H_
  46
  47 -enum rt305x_soc_type {
  48 -       RT305X_SOC_UNKNOWN = 0,
  49 -       RT305X_SOC_RT3050,
  50 -       RT305X_SOC_RT3052,
  51 -       RT305X_SOC_RT3350,
  52 -       RT305X_SOC_RT3352,
  53 -       RT305X_SOC_RT5350,
  54 -};
  55 -
  56 -extern enum rt305x_soc_type rt305x_soc;
  57 +extern enum ralink_soc_type ralink_soc;
  58
  59  static inline int soc_is_rt3050(void)
  60  {
  61 -       return rt305x_soc == RT305X_SOC_RT3050;
  62 +       return ralink_soc == RT305X_SOC_RT3050;
  63  }
  64
  65  static inline int soc_is_rt3052(void)
  66  {
  67 -       return rt305x_soc == RT305X_SOC_RT3052;
  68 +       return ralink_soc == RT305X_SOC_RT3052;
  69  }
  70
  71  static inline int soc_is_rt305x(void)
  72 @@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void)
  73
  74  static inline int soc_is_rt3350(void)
  75  {
  76 -       return rt305x_soc == RT305X_SOC_RT3350;
  77 +       return ralink_soc == RT305X_SOC_RT3350;
  78  }
  79
  80  static inline int soc_is_rt3352(void)
  81  {
  82 -       return rt305x_soc == RT305X_SOC_RT3352;
  83 +       return ralink_soc == RT305X_SOC_RT3352;
  84  }
  85
  86  static inline int soc_is_rt5350(void)
  87  {
  88 -       return rt305x_soc == RT305X_SOC_RT5350;
  89 +       return ralink_soc == RT305X_SOC_RT5350;
  90  }
  91
  92  #define RT305X_SYSC_BASE               0x10000000
  93 --- a/arch/mips/ralink/mt7620.c
  94 +++ b/arch/mips/ralink/mt7620.c
  95 @@ -43,8 +43,6 @@
  96  #define CLKCFG_FFRAC_MASK      0x001f
  97  #define CLKCFG_FFRAC_USB_VAL   0x0003
  98
  99 -enum mt762x_soc_type mt762x_soc;
 100 -
 101  /* does the board have sdram or ddram */
 102  static int dram_type;
 103
 104 @@ -375,7 +373,7 @@ void __init ralink_clk_init(void)
 105  #define RINT(x)                ((x) / 1000000)
 106  #define RFRAC(x)       (((x) / 1000) % 1000)
 107
 108 -       if (mt762x_soc == MT762X_SOC_MT7628AN) {
 109 +       if (ralink_soc == MT762X_SOC_MT7628AN) {
 110                 if (xtal_rate == MHZ(40))
 111                         cpu_rate = MHZ(580);
 112                 else
 113 @@ -420,7 +418,7 @@ void __init ralink_clk_init(void)
 114         ralink_clk_add("10000e00.uart2", periph_rate);
 115         ralink_clk_add("10180000.wmac", xtal_rate);
 116
 117 -       if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
 118 +       if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) {
 119                 /*
 120                  * When the CPU goes into sleep mode, the BUS clock will be too low for
 121                  * USB to function properly
 122 @@ -508,11 +506,11 @@ void prom_soc_init(struct ralink_soc_inf
 123
 124         if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
 125                 if (bga) {
 126 -                       mt762x_soc = MT762X_SOC_MT7620A;
 127 +                       ralink_soc = MT762X_SOC_MT7620A;
 128                         name = "MT7620A";
 129                         soc_info->compatible = "ralink,mt7620a-soc";
 130                 } else {
 131 -                       mt762x_soc = MT762X_SOC_MT7620N;
 132 +                       ralink_soc = MT762X_SOC_MT7620N;
 133                         name = "MT7620N";
 134                         soc_info->compatible = "ralink,mt7620n-soc";
 135  #ifdef CONFIG_PCI
 136 @@ -520,7 +518,7 @@ void prom_soc_init(struct ralink_soc_inf
 137  #endif
 138                 }
 139         } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
 140 -               mt762x_soc = MT762X_SOC_MT7628AN;
 141 +               ralink_soc = MT762X_SOC_MT7628AN;
 142                 name = "MT7628AN";
 143                 soc_info->compatible = "ralink,mt7628an-soc";
 144         } else {
 145 @@ -537,7 +535,7 @@ void prom_soc_init(struct ralink_soc_inf
 146         dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
 147
 148         soc_info->mem_base = MT7620_DRAM_BASE;
 149 -       if (mt762x_soc == MT762X_SOC_MT7628AN)
 150 +       if (ralink_soc == MT762X_SOC_MT7628AN)
 151                 mt7628_dram_init(soc_info);
 152         else
 153                 mt7620_dram_init(soc_info);
 154 @@ -550,7 +548,7 @@ void prom_soc_init(struct ralink_soc_inf
 155         pr_info("Digital PMU set to %s control\n",
 156                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 157
 158 -       if (mt762x_soc == MT762X_SOC_MT7628AN)
 159 +       if (ralink_soc == MT762X_SOC_MT7628AN)
 160                 rt2880_pinmux_data = mt7628an_pinmux_data;
 161         else
 162                 rt2880_pinmux_data = mt7620a_pinmux_data;
 163 --- a/arch/mips/ralink/rt305x.c
 164 +++ b/arch/mips/ralink/rt305x.c
 165 @@ -21,8 +21,6 @@
 166
 167  #include "common.h"
 168
 169 -enum rt305x_soc_type rt305x_soc;
 170 -
 171  static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
 172  static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
 173  static struct rt2880_pmx_func uartf_func[] = {
 174 @@ -234,24 +232,24 @@ void prom_soc_init(struct ralink_soc_inf
 175
 176                 icache_sets = (read_c0_config1() >> 22) & 7;
 177                 if (icache_sets == 1) {
 178 -                       rt305x_soc = RT305X_SOC_RT3050;
 179 +                       ralink_soc = RT305X_SOC_RT3050;
 180                         name = "RT3050";
 181                         soc_info->compatible = "ralink,rt3050-soc";
 182                 } else {
 183 -                       rt305x_soc = RT305X_SOC_RT3052;
 184 +                       ralink_soc = RT305X_SOC_RT3052;
 185                         name = "RT3052";
 186                         soc_info->compatible = "ralink,rt3052-soc";
 187                 }
 188         } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
 189 -               rt305x_soc = RT305X_SOC_RT3350;
 190 +               ralink_soc = RT305X_SOC_RT3350;
 191                 name = "RT3350";
 192                 soc_info->compatible = "ralink,rt3350-soc";
 193         } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
 194 -               rt305x_soc = RT305X_SOC_RT3352;
 195 +               ralink_soc = RT305X_SOC_RT3352;
 196                 name = "RT3352";
 197                 soc_info->compatible = "ralink,rt3352-soc";
 198         } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
 199 -               rt305x_soc = RT305X_SOC_RT5350;
 200 +               ralink_soc = RT305X_SOC_RT5350;
 201                 name = "RT5350";
 202                 soc_info->compatible = "ralink,rt5350-soc";
 203         } else {
 204 --- a/arch/mips/ralink/prom.c
 205 +++ b/arch/mips/ralink/prom.c
 206 @@ -15,9 +15,13 @@
 207  #include <asm/bootinfo.h>
 208  #include <asm/addrspace.h>
 209
 210 +#include <asm/mach-ralink/ralink_regs.h>
 211 +
 212  #include "common.h"
 213
 214  struct ralink_soc_info soc_info;
 215 +enum ralink_soc_type ralink_soc;
 216 +EXPORT_SYMBOL_GPL(ralink_soc);
 217
 218  const char *get_system_type(void)
 219  {
 220 --- a/arch/mips/ralink/mt7621.c
 221 +++ b/arch/mips/ralink/mt7621.c
 222 @@ -193,6 +193,7 @@ void prom_soc_init(struct ralink_soc_inf
 223         soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
 224         soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
 225         soc_info->mem_base = MT7621_DRAM_BASE;
 226 +       ralink_soc = MT762X_SOC_MT7621AT;
 227
 228         rt2880_pinmux_data = mt7621_pinmux_data;
 229