ralink: mt7621 add ECHI OCHI XCHI support
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.18 / 0062-mt7621-add-ECHI-OCHI-XCHI-support.patch
1 --- a/drivers/usb/Makefile
2 +++ b/drivers/usb/Makefile
3 @@ -11,6 +11,8 @@ obj-$(CONFIG_USB_DWC2) += dwc2/
4
5 obj-$(CONFIG_USB_MON) += mon/
6
7 +obj-$(CONFIG_USB_PHY) += phy/
8 +
9 obj-$(CONFIG_PCI) += host/
10 obj-$(CONFIG_USB_EHCI_HCD) += host/
11 obj-$(CONFIG_USB_ISP116X_HCD) += host/
12 --- a/drivers/usb/core/hcd-pci.c
13 +++ b/drivers/usb/core/hcd-pci.c
14 @@ -214,8 +214,13 @@ int usb_hcd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
15 goto disable_pci;
16 }
17
18 +
19 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
20 + hcd->amd_resume_bug = 0;
21 +#else
22 hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
23 driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
24 +#endif
25
26 if (driver->flags & HCD_MEMORY) {
27 /* EHCI, OHCI */
28 --- a/drivers/usb/core/hub.c
29 +++ b/drivers/usb/core/hub.c
30 @@ -1286,7 +1286,7 @@ static void hub_quiesce(struct usb_hub *hub, enum hub_quiescing_type type)
31 if (type != HUB_SUSPEND) {
32 /* Disconnect all the children */
33 for (i = 0; i < hdev->maxchild; ++i) {
34 - if (hub->ports[i]->child)
35 + if (hub->ports[i] && hub->ports[i]->child)
36 usb_disconnect(&hub->ports[i]->child);
37 }
38 }
39 --- a/drivers/usb/core/port.c
40 +++ b/drivers/usb/core/port.c
41 @@ -480,8 +480,10 @@ void usb_hub_remove_port_device(struct usb_hub *hub, int port1)
42 struct usb_port *port_dev = hub->ports[port1 - 1];
43 struct usb_port *peer;
44
45 - peer = port_dev->peer;
46 - if (peer)
47 - unlink_peers(port_dev, peer);
48 - device_unregister(&port_dev->dev);
49 + if(port_dev) {
50 + peer = port_dev->peer;
51 + if (peer)
52 + unlink_peers(port_dev, peer);
53 + device_unregister(&port_dev->dev);
54 + }
55 }
56 --- a/drivers/usb/host/Kconfig
57 +++ b/drivers/usb/host/Kconfig
58 @@ -32,7 +32,12 @@ config USB_XHCI_PCI
59 default y
60
61 config USB_XHCI_PLATFORM
62 - tristate
63 + tristate "xHCI platform"
64 +
65 +config USB_MT7621_XHCI_PLATFORM
66 + bool "MTK MT7621 xHCI"
67 + depends on USB_XHCI_PLATFORM
68 + depends on SOC_MT7621
69
70 config USB_XHCI_MVEBU
71 tristate "xHCI support for Marvell Armada 375/38x"
72 --- a/drivers/usb/host/Makefile
73 +++ b/drivers/usb/host/Makefile
74 @@ -16,7 +16,12 @@ xhci-hcd-y := xhci.o xhci-mem.o
75 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
76 xhci-hcd-y += xhci-trace.o
77
78 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
79 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
80 +endif
81 +
82 xhci-plat-hcd-y := xhci-plat.o
83 +
84 ifneq ($(CONFIG_USB_XHCI_MVEBU), )
85 xhci-plat-hcd-y += xhci-mvebu.o
86 endif
87 @@ -26,9 +31,14 @@ endif
88
89 obj-$(CONFIG_USB_WHCI_HCD) += whci/
90
91 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
92 obj-$(CONFIG_PCI) += pci-quirks.o
93 +endif
94
95 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
96 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
97 +endif
98 +
99 obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
100
101 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
102 --- a/drivers/usb/host/ehci-platform.c
103 +++ b/drivers/usb/host/ehci-platform.c
104 @@ -33,6 +33,8 @@
105 #include <linux/usb.h>
106 #include <linux/usb/hcd.h>
107 #include <linux/usb/ehci_pdriver.h>
108 +#include <linux/usb/phy.h>
109 +#include <linux/usb/otg.h>
110
111 #include "ehci.h"
112
113 @@ -255,6 +257,15 @@ static int ehci_platform_probe(struct platform_device *dev)
114 hcd->rsrc_start = res_mem->start;
115 hcd->rsrc_len = resource_size(res_mem);
116
117 +#ifdef CONFIG_USB_PHY
118 + hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
119 + if (!IS_ERR_OR_NULL(hcd->phy)) {
120 + otg_set_host(hcd->phy->otg,
121 + &hcd->self);
122 + usb_phy_init(hcd->phy);
123 + }
124 +#endif
125 +
126 hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
127 if (IS_ERR(hcd->regs)) {
128 err = PTR_ERR(hcd->regs);
129 --- /dev/null
130 +++ b/drivers/usb/host/mtk-phy-7621.c
131 @@ -0,0 +1,445 @@
132 +#include "mtk-phy.h"
133 +
134 +#ifdef CONFIG_PROJECT_7621
135 +#include "mtk-phy-7621.h"
136 +
137 +//not used on SoC
138 +PHY_INT32 phy_init(struct u3phy_info *info){
139 + return PHY_TRUE;
140 +}
141 +
142 +//not used on SoC
143 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
144 + return PHY_TRUE;
145 +}
146 +
147 +//--------------------------------------------------------
148 +// Function : fgEyeScanHelper_CheckPtInRegion()
149 +// Description : Check if the test point is in a rectangle region.
150 +// If it is in the rectangle, also check if this point
151 +// is on the multiple of deltaX and deltaY.
152 +// Parameter : strucScanRegion * prEye - the region
153 +// BYTE bX
154 +// BYTE bY
155 +// Return : BYTE - TRUE : This point needs to be tested
156 +// FALSE: This point will be omitted
157 +// Note : First check within the rectangle.
158 +// Secondly, use modulous to check if the point will be tested.
159 +//--------------------------------------------------------
160 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
161 +{
162 + PHY_INT8 fgValid = true;
163 +
164 +
165 + /// Be careful, the axis origin is on the TOP-LEFT corner.
166 + /// Therefore the top-left point has the minimum X and Y
167 + /// Botton-right point is the maximum X and Y
168 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
169 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
170 + {
171 + // With the region, now check whether or not the input test point is
172 + // on the multiples of X and Y
173 + // Do not have to worry about negative value, because we have already
174 + // check the input bX, and bY is within the region.
175 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
176 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
177 + {
178 + // if the division will have remainder, that means
179 + // the input test point is on the multiples of X and Y
180 + fgValid = false;
181 + }
182 + else
183 + {
184 + }
185 + }
186 + else
187 + {
188 +
189 + fgValid = false;
190 + }
191 + return fgValid;
192 +}
193 +
194 +//--------------------------------------------------------
195 +// Function : EyeScanHelper_RunTest()
196 +// Description : Enable the test, and wait til it is completed
197 +// Parameter : None
198 +// Return : None
199 +// Note : None
200 +//--------------------------------------------------------
201 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
202 +{
203 + DRV_UDELAY(100);
204 + // Disable the test
205 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
206 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
207 + DRV_UDELAY(100);
208 + // Run the test
209 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
210 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
211 + DRV_UDELAY(100);
212 + // Wait til it's done
213 + //RGS_SSUSB_RX_EYE_CNT_RDY
214 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
215 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
216 +}
217 +
218 +//--------------------------------------------------------
219 +// Function : fgEyeScanHelper_CalNextPoint()
220 +// Description : Calcualte the test point for the measurement
221 +// Parameter : None
222 +// Return : BOOL - TRUE : the next point is within the
223 +// boundaryof HW limit
224 +// FALSE: the next point is out of the HW limit
225 +// Note : The next point is obtained by calculating
226 +// from the bottom left of the region rectangle
227 +// and then scanning up until it reaches the upper
228 +// limit. At this time, the x will increment, and
229 +// start scanning downwards until the y hits the
230 +// zero.
231 +//--------------------------------------------------------
232 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
233 +{
234 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
235 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
236 + )
237 + {
238 + /// Reaches the limit of Y axis
239 + /// Increment X
240 + _bXcurr++;
241 + _fgXChged = true;
242 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
243 +
244 + if (_bXcurr > MAX_X)
245 + {
246 + return false;
247 + }
248 + }
249 + else
250 + {
251 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
252 + _fgXChged = false;
253 + }
254 + return PHY_TRUE;
255 +}
256 +
257 +PHY_INT32 eyescan_init(struct u3phy_info *info){
258 + //initial PHY setting
259 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
260 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
261 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
262 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
263 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
264 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
265 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
266 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
267 + return PHY_TRUE;
268 +}
269 +
270 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
271 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
272 + PHY_INT32 cOfst = 0;
273 + PHY_UINT8 bIdxX = 0;
274 + PHY_UINT8 bIdxY = 0;
275 + //PHY_INT8 bCnt = 0;
276 + PHY_UINT8 bIdxCycCnt = 0;
277 + PHY_INT8 fgValid;
278 + PHY_INT8 cX;
279 + PHY_INT8 cY;
280 + PHY_UINT8 bExtendCnt;
281 + PHY_INT8 isContinue;
282 + //PHY_INT8 isBreak;
283 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
284 + //PHY_UINT32 temp;
285 +
286 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
287 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
288 +
289 + _rEye1.bX_tl = x_t1;
290 + _rEye1.bY_tl = y_t1;
291 + _rEye1.bX_br = x_br;
292 + _rEye1.bY_br = y_br;
293 + _rEye1.bDeltaX = delta_x;
294 + _rEye1.bDeltaY = delta_y;
295 +
296 + _rEye2.bX_tl = x_t1;
297 + _rEye2.bY_tl = y_t1;
298 + _rEye2.bX_br = x_br;
299 + _rEye2.bY_br = y_br;
300 + _rEye2.bDeltaX = delta_x;
301 + _rEye2.bDeltaY = delta_y;
302 +
303 + _rTestCycle.wEyeCnt = eye_cnt;
304 + _rTestCycle.bNumOfEyeCnt = num_cnt;
305 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
306 + _rTestCycle.bPICalEn = PI_cal_en;
307 +
308 + _bXcurr = 0;
309 + _bYcurr = 0;
310 + _eScanDir = SCAN_DN;
311 + _fgXChged = false;
312 +
313 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
314 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
315 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
316 +
317 + //force SIGDET to OFF
318 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
319 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
320 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
321 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
322 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
323 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
324 +
325 + // RX_TRI_DET_EN to Disable
326 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
327 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
328 +
329 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
330 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
331 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
332 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
333 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
334 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
335 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
336 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
337 +
338 +
339 + if (PI_cal_en){
340 + // PI Calibration
341 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
342 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
343 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
344 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
345 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
346 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
347 +
348 + DRV_UDELAY(20);
349 +
350 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
351 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
352 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
353 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
354 +
355 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
356 + }
357 + // Read Initial DAC
358 + // Set CYCLE
359 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
360 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
361 +
362 + // Eye Monitor Feature
363 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
364 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
365 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
366 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
367 +
368 + // Move X,Y to the top-left corner
369 + for (cOfst = 0; cOfst >= -64; cOfst--)
370 + {
371 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
372 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
373 + }
374 + for (cOfst = 0; cOfst < 64; cOfst++)
375 + {
376 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
377 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
378 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
379 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
380 + }
381 + //ClearErrorResult
382 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
383 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
384 + {
385 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
386 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
387 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
388 + }
389 + }
390 + }
391 + isContinue = true;
392 + while(isContinue){
393 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
394 + // The point is within the boundary, then let's check if it is within
395 + // the testing region.
396 + // The point is only test-able if one of the eye region
397 + // includes this point.
398 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
399 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
400 + // Translate bX and bY to 2's complement from where the origin was on the
401 + // top left corner.
402 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
403 + cX = (_bXcurr ^ 0x40);
404 + cY = (_bYcurr ^ 0x3F);
405 +
406 + // Set X if necessary
407 + if (_fgXChged == true)
408 + {
409 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
410 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
411 + }
412 + // Set Y
413 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
414 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
415 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
416 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
417 +
418 + /// Test this point!
419 + if (fgValid){
420 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
421 + {
422 + //run test
423 + EyeScanHelper_RunTest(info);
424 + }
425 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
426 + {
427 + EyeScanHelper_RunTest(info);
428 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
429 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
430 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
431 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
432 +
433 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
434 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
435 +
436 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
437 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
438 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
439 + }
440 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
441 + }
442 + else{
443 +
444 + }
445 + if (fgEyeScanHelper_CalNextPoint() == false){
446 +#if 0
447 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
448 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
449 +#endif
450 + printk(KERN_ERR "end of eye scan\n");
451 + isContinue = false;
452 + }
453 + }
454 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
455 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
456 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
457 +
458 + // Move X,Y to the top-left corner
459 + for (cOfst = 63; cOfst >= 0; cOfst--)
460 + {
461 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
462 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
463 + }
464 + for (cOfst = 63; cOfst >= 0; cOfst--)
465 + {
466 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
467 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
468 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
469 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
470 +
471 + }
472 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
473 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
474 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
475 +
476 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
477 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
478 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
479 +
480 + return PHY_TRUE;
481 +}
482 +
483 +//not used on SoC
484 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
485 + return PHY_TRUE;
486 +}
487 +
488 +//not used on SoC
489 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
490 + return PHY_TRUE;
491 +}
492 +
493 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
494 + PHY_INT32 i=0;
495 + //PHY_INT32 j=0;
496 + //PHY_INT8 u1SrCalVal = 0;
497 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
498 + PHY_INT32 fgRet = 0;
499 + PHY_INT32 u4FmOut = 0;
500 + PHY_INT32 u4Tmp = 0;
501 + //PHY_INT32 temp;
502 +
503 + // => RG_USB20_HSTX_SRCAL_EN = 1
504 + // enable HS TX SR calibration
505 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
506 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
507 + DRV_MSLEEP(1);
508 +
509 + // => RG_FRCK_EN = 1
510 + // Enable free run clock
511 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
512 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
513 +
514 + // MT6290 HS signal quality patch
515 + // => RG_CYCLECNT = 400
516 + // Setting cyclecnt =400
517 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
518 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
519 +
520 + // => RG_FREQDET_EN = 1
521 + // Enable frequency meter
522 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
523 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
524 +
525 + // wait for FM detection done, set 10ms timeout
526 + for(i=0; i<10; i++){
527 + // => u4FmOut = USB_FM_OUT
528 + // read FM_OUT
529 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
530 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
531 +
532 + // check if FM detection done
533 + if (u4FmOut != 0)
534 + {
535 + fgRet = 0;
536 + printk("FM detection done! loop = %d\n", i);
537 +
538 + break;
539 + }
540 +
541 + fgRet = 1;
542 + DRV_MSLEEP(1);
543 + }
544 + // => RG_FREQDET_EN = 0
545 + // disable frequency meter
546 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
547 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
548 +
549 + // => RG_FRCK_EN = 0
550 + // disable free run clock
551 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
552 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
553 +
554 + // => RG_USB20_HSTX_SRCAL_EN = 0
555 + // disable HS TX SR calibration
556 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
557 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
558 + DRV_MSLEEP(1);
559 +
560 + if(u4FmOut == 0){
561 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
562 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
563 +
564 + fgRet = 1;
565 + }
566 + else{
567 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
568 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
569 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
570 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
571 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
572 + }
573 + return fgRet;
574 +}
575 +
576 +#endif
577 --- /dev/null
578 +++ b/drivers/usb/host/mtk-phy-7621.h
579 @@ -0,0 +1,2871 @@
580 +#ifdef CONFIG_PROJECT_7621
581 +#ifndef __MTK_PHY_7621_H
582 +#define __MTK_PHY_7621_H
583 +
584 +#define U2_SR_COEF_7621 28
585 +
586 +///////////////////////////////////////////////////////////////////////////////
587 +
588 +struct u2phy_reg {
589 + //0x0
590 + PHY_LE32 u2phyac0;
591 + PHY_LE32 u2phyac1;
592 + PHY_LE32 u2phyac2;
593 + PHY_LE32 reserve0;
594 + //0x10
595 + PHY_LE32 u2phyacr0;
596 + PHY_LE32 u2phyacr1;
597 + PHY_LE32 u2phyacr2;
598 + PHY_LE32 u2phyacr3;
599 + //0x20
600 + PHY_LE32 u2phyacr4;
601 + PHY_LE32 u2phyamon0;
602 + PHY_LE32 reserve1[2];
603 + //0x30~0x50
604 + PHY_LE32 reserve2[12];
605 + //0x60
606 + PHY_LE32 u2phydcr0;
607 + PHY_LE32 u2phydcr1;
608 + PHY_LE32 u2phydtm0;
609 + PHY_LE32 u2phydtm1;
610 + //0x70
611 + PHY_LE32 u2phydmon0;
612 + PHY_LE32 u2phydmon1;
613 + PHY_LE32 u2phydmon2;
614 + PHY_LE32 u2phydmon3;
615 + //0x80
616 + PHY_LE32 u2phybc12c;
617 + PHY_LE32 u2phybc12c1;
618 + PHY_LE32 reserve3[2];
619 + //0x90~0xe0
620 + PHY_LE32 reserve4[24];
621 + //0xf0
622 + PHY_LE32 reserve6[3];
623 + PHY_LE32 regfcom;
624 +};
625 +
626 +//U3D_U2PHYAC0
627 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
628 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
629 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
630 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
631 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
632 +#define RG_USB20_REF_EN (0x1<<15) //15:15
633 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
634 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
635 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
636 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
637 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
638 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
639 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
640 +
641 +//U3D_U2PHYAC1
642 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
643 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
644 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
645 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
646 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
647 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
648 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
649 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
650 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
651 +
652 +//U3D_U2PHYAC2
653 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
654 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
655 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
656 +
657 +//U3D_U2PHYACR0
658 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
659 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
660 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
661 +#define RG_USB20_LS_CR (0x7<<12) //14:12
662 +#define RG_USB20_FS_CR (0x7<<8) //10:8
663 +#define RG_USB20_LS_SR (0x7<<4) //6:4
664 +#define RG_USB20_FS_SR (0x7<<0) //2:0
665 +
666 +//U3D_U2PHYACR1
667 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
668 +#define RG_USB20_SQD (0x3<<24) //25:24
669 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
670 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
671 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
672 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
673 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
674 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
675 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
676 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
677 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
678 +
679 +//U3D_U2PHYACR2
680 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
681 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
682 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
683 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
684 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
685 +#define RG_USB20_DISCD (0x3<<20) //21:20
686 +#define RG_USB20_DISCTH (0xf<<16) //19:16
687 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
688 +#define RG_USB20_SQCAL (0xf<<8) //11:8
689 +#define RG_USB20_SQTH (0xf<<0) //3:0
690 +
691 +//U3D_U2PHYACR3
692 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
693 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
694 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
695 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
696 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
697 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
698 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
699 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
700 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
701 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
702 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
703 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
704 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
705 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
706 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
707 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
708 +
709 +//U3D_U2PHYACR4
710 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
711 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
712 +#define USB20_DP_100K_EN (0x1<<16) //16:16
713 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
714 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
715 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
716 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
717 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
718 +#define USB20_GPIO_MODE (0x1<<8) //8:8
719 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
720 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
721 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
722 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
723 +
724 +//U3D_U2PHYAMON0
725 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
726 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
727 +
728 +//U3D_U2PHYDCR0
729 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
730 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
731 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
732 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
733 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
734 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
735 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
736 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
737 +#define RG_USB20_TX_TST (0x1<<5) //5:5
738 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
739 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
740 +
741 +//U3D_U2PHYDCR1
742 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
743 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
744 +#define RG_DEBUG_EN (0x1<<22) //22:22
745 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
746 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
747 +#define RG_USB20_BERTH (0x3<<16) //17:16
748 +#define RG_USB20_LBMODE (0x3<<13) //14:13
749 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
750 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
751 +
752 +//U3D_U2PHYDTM0
753 +#define RG_UART_MODE (0x3<<30) //31:30
754 +#define FORCE_UART_I (0x1<<29) //29:29
755 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
756 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
757 +#define FORCE_UART_EN (0x1<<26) //26:26
758 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
759 +#define FORCE_DRVVBUS (0x1<<24) //24:24
760 +#define FORCE_DATAIN (0x1<<23) //23:23
761 +#define FORCE_TXVALID (0x1<<22) //22:22
762 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
763 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
764 +#define FORCE_XCVRSEL (0x1<<19) //19:19
765 +#define FORCE_SUSPENDM (0x1<<18) //18:18
766 +#define FORCE_TERMSEL (0x1<<17) //17:17
767 +#define FORCE_OPMODE (0x1<<16) //16:16
768 +#define UTMI_MUXSEL (0x1<<15) //15:15
769 +#define RG_RESET (0x1<<14) //14:14
770 +#define RG_DATAIN (0xf<<10) //13:10
771 +#define RG_TXVALIDH (0x1<<9) //9:9
772 +#define RG_TXVALID (0x1<<8) //8:8
773 +#define RG_DMPULLDOWN (0x1<<7) //7:7
774 +#define RG_DPPULLDOWN (0x1<<6) //6:6
775 +#define RG_XCVRSEL (0x3<<4) //5:4
776 +#define RG_SUSPENDM (0x1<<3) //3:3
777 +#define RG_TERMSEL (0x1<<2) //2:2
778 +#define RG_OPMODE (0x3<<0) //1:0
779 +
780 +//U3D_U2PHYDTM1
781 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
782 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
783 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
784 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
785 +#define RG_UART_I (0x1<<19) //19:19
786 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
787 +#define RG_UART_TX_OE (0x1<<17) //17:17
788 +#define RG_UART_EN (0x1<<16) //16:16
789 +#define FORCE_VBUSVALID (0x1<<13) //13:13
790 +#define FORCE_SESSEND (0x1<<12) //12:12
791 +#define FORCE_BVALID (0x1<<11) //11:11
792 +#define FORCE_AVALID (0x1<<10) //10:10
793 +#define FORCE_IDDIG (0x1<<9) //9:9
794 +#define FORCE_IDPULLUP (0x1<<8) //8:8
795 +#define RG_VBUSVALID (0x1<<5) //5:5
796 +#define RG_SESSEND (0x1<<4) //4:4
797 +#define RG_BVALID (0x1<<3) //3:3
798 +#define RG_AVALID (0x1<<2) //2:2
799 +#define RG_IDDIG (0x1<<1) //1:1
800 +#define RG_IDPULLUP (0x1<<0) //0:0
801 +
802 +//U3D_U2PHYDMON0
803 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
804 +
805 +//U3D_U2PHYDMON1
806 +#define USB20_UART_O (0x1<<31) //31:31
807 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
808 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
809 +#define AD_USB20_BVALID (0x1<<28) //28:28
810 +#define USB20_IDDIG (0x1<<27) //27:27
811 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
812 +#define AD_USB20_SESSEND (0x1<<25) //25:25
813 +#define AD_USB20_AVALID (0x1<<24) //24:24
814 +#define USB20_LINE_STATE (0x3<<22) //23:22
815 +#define USB20_HST_DISCON (0x1<<21) //21:21
816 +#define USB20_TX_READY (0x1<<20) //20:20
817 +#define USB20_RX_ERROR (0x1<<19) //19:19
818 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
819 +#define USB20_RX_VALIDH (0x1<<17) //17:17
820 +#define USB20_RX_VALID (0x1<<16) //16:16
821 +#define USB20_DATA_OUT (0xffff<<0) //15:0
822 +
823 +//U3D_U2PHYDMON2
824 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
825 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
826 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
827 +#define USB20_PROBE_OUT (0xff<<0) //7:0
828 +
829 +//U3D_U2PHYDMON3
830 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
831 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
832 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
833 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
834 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
835 +
836 +//U3D_U2PHYBC12C
837 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
838 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
839 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
840 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
841 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
842 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
843 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
844 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
845 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
846 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
847 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
848 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
849 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
850 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
851 +#define RG_CHGDT_EN (0x1<<0) //0:0
852 +
853 +//U3D_U2PHYBC12C1
854 +#define RG_CHGDT_REV (0xff<<0) //7:0
855 +
856 +//U3D_REGFCOM
857 +#define RG_PAGE (0xff<<24) //31:24
858 +#define I2C_MODE (0x1<<16) //16:16
859 +
860 +
861 +/* OFFSET */
862 +
863 +//U3D_U2PHYAC0
864 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
865 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
866 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
867 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
868 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
869 +#define RG_USB20_REF_EN_OFST (15)
870 +#define RG_USB20_INTR_EN_OFST (14)
871 +#define RG_USB20_BG_TRIM_OFST (8)
872 +#define RG_USB20_BG_RBSEL_OFST (6)
873 +#define RG_USB20_BG_RASEL_OFST (4)
874 +#define RG_USB20_BGR_DIV_OFST (2)
875 +#define RG_SIFSLV_CHP_EN_OFST (1)
876 +#define RG_SIFSLV_BGR_EN_OFST (0)
877 +
878 +//U3D_U2PHYAC1
879 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
880 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
881 +#define RG_USB20_MPX_SEL_OFST (16)
882 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
883 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
884 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
885 +#define RG_USB20_USBPLL_LF_OFST (2)
886 +#define RG_USB20_USBPLL_BR_OFST (1)
887 +#define RG_USB20_USBPLL_BP_OFST (0)
888 +
889 +//U3D_U2PHYAC2
890 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
891 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
892 +#define RG_USB20_CLKREF_REV_OFST (0)
893 +
894 +//U3D_U2PHYACR0
895 +#define RG_USB20_ICUSB_EN_OFST (24)
896 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
897 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
898 +#define RG_USB20_LS_CR_OFST (12)
899 +#define RG_USB20_FS_CR_OFST (8)
900 +#define RG_USB20_LS_SR_OFST (4)
901 +#define RG_USB20_FS_SR_OFST (0)
902 +
903 +//U3D_U2PHYACR1
904 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
905 +#define RG_USB20_SQD_OFST (24)
906 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
907 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
908 +#define RG_USB20_PHYD_MONEN_OFST (18)
909 +#define RG_USB20_INLPBK_EN_OFST (17)
910 +#define RG_USB20_CHIRP_EN_OFST (16)
911 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
912 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
913 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
914 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
915 +
916 +//U3D_U2PHYACR2
917 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
918 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
919 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
920 +#define RG_USB20_OTG_VBUSTH_OFST (24)
921 +#define RG_USB20_DISC_FIT_EN_OFST (22)
922 +#define RG_USB20_DISCD_OFST (20)
923 +#define RG_USB20_DISCTH_OFST (16)
924 +#define RG_USB20_SQCAL_EN_OFST (15)
925 +#define RG_USB20_SQCAL_OFST (8)
926 +#define RG_USB20_SQTH_OFST (0)
927 +
928 +//U3D_U2PHYACR3
929 +#define RG_USB20_HSTX_DBIST_OFST (28)
930 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
931 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
932 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
933 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
934 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
935 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
936 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
937 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
938 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
939 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
940 +#define RG_USB20_EN_PU_DM_OFST (11)
941 +#define RG_USB20_EN_PD_DM_OFST (10)
942 +#define RG_USB20_EN_PU_DP_OFST (9)
943 +#define RG_USB20_EN_PD_DP_OFST (8)
944 +#define RG_USB20_PHY_REV_OFST (0)
945 +
946 +//U3D_U2PHYACR4
947 +#define RG_USB20_DP_100K_MODE_OFST (18)
948 +#define RG_USB20_DM_100K_EN_OFST (17)
949 +#define USB20_DP_100K_EN_OFST (16)
950 +#define USB20_GPIO_DM_I_OFST (15)
951 +#define USB20_GPIO_DP_I_OFST (14)
952 +#define USB20_GPIO_DM_OE_OFST (13)
953 +#define USB20_GPIO_DP_OE_OFST (12)
954 +#define RG_USB20_GPIO_CTL_OFST (9)
955 +#define USB20_GPIO_MODE_OFST (8)
956 +#define RG_USB20_TX_BIAS_EN_OFST (5)
957 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
958 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
959 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
960 +
961 +//U3D_U2PHYAMON0
962 +#define RGO_USB20_GPIO_DM_O_OFST (1)
963 +#define RGO_USB20_GPIO_DP_O_OFST (0)
964 +
965 +//U3D_U2PHYDCR0
966 +#define RG_USB20_CDR_TST_OFST (30)
967 +#define RG_USB20_GATED_ENB_OFST (29)
968 +#define RG_USB20_TESTMODE_OFST (26)
969 +#define RG_USB20_PLL_STABLE_OFST (25)
970 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
971 +#define RG_USB20_PHYD_RESERVE_OFST (8)
972 +#define RG_USB20_EBTHRLD_OFST (7)
973 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
974 +#define RG_USB20_TX_TST_OFST (5)
975 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
976 +#define RG_USB20_CDR_FILT_OFST (0)
977 +
978 +//U3D_U2PHYDCR1
979 +#define RG_USB20_PROBE_SEL_OFST (24)
980 +#define RG_USB20_DRVVBUS_OFST (23)
981 +#define RG_DEBUG_EN_OFST (22)
982 +#define RG_USB20_OTG_PROBE_OFST (20)
983 +#define RG_USB20_SW_PLLMODE_OFST (18)
984 +#define RG_USB20_BERTH_OFST (16)
985 +#define RG_USB20_LBMODE_OFST (13)
986 +#define RG_USB20_FORCE_TAP_OFST (12)
987 +#define RG_USB20_TAPSEL_OFST (0)
988 +
989 +//U3D_U2PHYDTM0
990 +#define RG_UART_MODE_OFST (30)
991 +#define FORCE_UART_I_OFST (29)
992 +#define FORCE_UART_BIAS_EN_OFST (28)
993 +#define FORCE_UART_TX_OE_OFST (27)
994 +#define FORCE_UART_EN_OFST (26)
995 +#define FORCE_USB_CLKEN_OFST (25)
996 +#define FORCE_DRVVBUS_OFST (24)
997 +#define FORCE_DATAIN_OFST (23)
998 +#define FORCE_TXVALID_OFST (22)
999 +#define FORCE_DM_PULLDOWN_OFST (21)
1000 +#define FORCE_DP_PULLDOWN_OFST (20)
1001 +#define FORCE_XCVRSEL_OFST (19)
1002 +#define FORCE_SUSPENDM_OFST (18)
1003 +#define FORCE_TERMSEL_OFST (17)
1004 +#define FORCE_OPMODE_OFST (16)
1005 +#define UTMI_MUXSEL_OFST (15)
1006 +#define RG_RESET_OFST (14)
1007 +#define RG_DATAIN_OFST (10)
1008 +#define RG_TXVALIDH_OFST (9)
1009 +#define RG_TXVALID_OFST (8)
1010 +#define RG_DMPULLDOWN_OFST (7)
1011 +#define RG_DPPULLDOWN_OFST (6)
1012 +#define RG_XCVRSEL_OFST (4)
1013 +#define RG_SUSPENDM_OFST (3)
1014 +#define RG_TERMSEL_OFST (2)
1015 +#define RG_OPMODE_OFST (0)
1016 +
1017 +//U3D_U2PHYDTM1
1018 +#define RG_USB20_PRBS7_EN_OFST (31)
1019 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
1020 +#define RG_USB20_CLK48M_EN_OFST (23)
1021 +#define RG_USB20_CLK60M_EN_OFST (22)
1022 +#define RG_UART_I_OFST (19)
1023 +#define RG_UART_BIAS_EN_OFST (18)
1024 +#define RG_UART_TX_OE_OFST (17)
1025 +#define RG_UART_EN_OFST (16)
1026 +#define FORCE_VBUSVALID_OFST (13)
1027 +#define FORCE_SESSEND_OFST (12)
1028 +#define FORCE_BVALID_OFST (11)
1029 +#define FORCE_AVALID_OFST (10)
1030 +#define FORCE_IDDIG_OFST (9)
1031 +#define FORCE_IDPULLUP_OFST (8)
1032 +#define RG_VBUSVALID_OFST (5)
1033 +#define RG_SESSEND_OFST (4)
1034 +#define RG_BVALID_OFST (3)
1035 +#define RG_AVALID_OFST (2)
1036 +#define RG_IDDIG_OFST (1)
1037 +#define RG_IDPULLUP_OFST (0)
1038 +
1039 +//U3D_U2PHYDMON0
1040 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1041 +
1042 +//U3D_U2PHYDMON1
1043 +#define USB20_UART_O_OFST (31)
1044 +#define RGO_USB20_LB_PASS_OFST (30)
1045 +#define RGO_USB20_LB_DONE_OFST (29)
1046 +#define AD_USB20_BVALID_OFST (28)
1047 +#define USB20_IDDIG_OFST (27)
1048 +#define AD_USB20_VBUSVALID_OFST (26)
1049 +#define AD_USB20_SESSEND_OFST (25)
1050 +#define AD_USB20_AVALID_OFST (24)
1051 +#define USB20_LINE_STATE_OFST (22)
1052 +#define USB20_HST_DISCON_OFST (21)
1053 +#define USB20_TX_READY_OFST (20)
1054 +#define USB20_RX_ERROR_OFST (19)
1055 +#define USB20_RX_ACTIVE_OFST (18)
1056 +#define USB20_RX_VALIDH_OFST (17)
1057 +#define USB20_RX_VALID_OFST (16)
1058 +#define USB20_DATA_OUT_OFST (0)
1059 +
1060 +//U3D_U2PHYDMON2
1061 +#define RGO_TXVALID_CNT_OFST (24)
1062 +#define RGO_RXACTIVE_CNT_OFST (16)
1063 +#define RGO_USB20_LB_BERCNT_OFST (8)
1064 +#define USB20_PROBE_OUT_OFST (0)
1065 +
1066 +//U3D_U2PHYDMON3
1067 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1068 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1069 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1070 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1071 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1072 +
1073 +//U3D_U2PHYBC12C
1074 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1075 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1076 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1077 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1078 +#define RG_CHGDT_VDATSRC_OFST (13)
1079 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1080 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1081 +#define RG_CHGDT_ISRC_DP_OFST (7)
1082 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1083 +#define RG_CHGDT_VDAT_DM_OFST (5)
1084 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1085 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1086 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1087 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1088 +#define RG_CHGDT_EN_OFST (0)
1089 +
1090 +//U3D_U2PHYBC12C1
1091 +#define RG_CHGDT_REV_OFST (0)
1092 +
1093 +//U3D_REGFCOM
1094 +#define RG_PAGE_OFST (24)
1095 +#define I2C_MODE_OFST (16)
1096 +
1097 +
1098 +///////////////////////////////////////////////////////////////////////////////
1099 +
1100 +struct u3phya_reg {
1101 + //0x0
1102 + PHY_LE32 reg0;
1103 + PHY_LE32 reg1;
1104 + PHY_LE32 reg2;
1105 + PHY_LE32 reg3;
1106 + //0x10
1107 + PHY_LE32 reg4;
1108 + PHY_LE32 reg5;
1109 + PHY_LE32 reg6;
1110 + PHY_LE32 reg7;
1111 + //0x20
1112 + PHY_LE32 reg8;
1113 + PHY_LE32 reg9;
1114 + PHY_LE32 rega;
1115 + PHY_LE32 regb;
1116 + //0x30
1117 + PHY_LE32 regc;
1118 + PHY_LE32 regd;
1119 + PHY_LE32 rege;
1120 +};
1121 +
1122 +//U3D_reg0
1123 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1124 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1125 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1126 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1127 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1128 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1129 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1130 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1131 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1132 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1133 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1134 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1135 +
1136 +//U3D_reg1
1137 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1138 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1139 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1140 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1141 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1142 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1143 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1144 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1145 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1146 +
1147 +//U3D_reg2
1148 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1149 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1150 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1151 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1152 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1153 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1154 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1155 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1156 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1157 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1158 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1159 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1160 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1161 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1162 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1163 +
1164 +//U3D_reg3
1165 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1166 +
1167 +//U3D_reg4
1168 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1169 +
1170 +//U3D_reg5
1171 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1172 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1173 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1174 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1175 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1176 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1177 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1178 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1179 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1180 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1181 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1182 +
1183 +//U3D_reg6
1184 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1185 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1186 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1187 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1188 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1189 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1190 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1191 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1192 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1193 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1194 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1195 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1196 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1197 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1198 +
1199 +//U3D_reg7
1200 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1201 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1202 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1203 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1204 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1205 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1206 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1207 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1208 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1209 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1210 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1211 +
1212 +//U3D_reg8
1213 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1214 +
1215 +//U3D_reg9
1216 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1217 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1218 +
1219 +//U3D_regA
1220 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1221 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1222 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1223 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1224 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1225 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1226 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1227 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1228 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1229 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1230 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1231 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1232 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1233 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1234 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1235 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1236 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1237 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1238 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1239 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1240 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1241 +
1242 +//U3D_regB
1243 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1244 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1245 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1246 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1247 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1248 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1249 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1250 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1251 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1252 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1253 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1254 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1255 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1256 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1257 +
1258 +//U3D_regC
1259 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1260 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1261 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1262 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1263 +
1264 +//U3D_redD
1265 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1266 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1267 +
1268 +//U3D_regE
1269 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1270 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1271 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1272 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1273 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1274 +
1275 +
1276 +/* OFFSET */
1277 +
1278 +//U3D_reg0
1279 +#define RG_SSUSB_BGR_EN_OFST (31)
1280 +#define RG_SSUSB_CHPEN_OFST (30)
1281 +#define RG_SSUSB_BG_DIV_OFST (28)
1282 +#define RG_SSUSB_INTR_EN_OFST (26)
1283 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1284 +#define RG_SSUSB_MPX_SEL_OFST (16)
1285 +#define RG_SSUSB_REF_EN_OFST (15)
1286 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1287 +#define RG_SSUSB_BG_RASEL_OFST (9)
1288 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1289 +#define RG_SSUSB_BG_MONEN_OFST (6)
1290 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1291 +
1292 +//U3D_reg1
1293 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1294 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1295 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1296 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1297 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1298 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1299 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1300 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1301 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1302 +
1303 +//U3D_reg2
1304 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1305 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1306 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1307 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1308 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1309 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1310 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1311 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1312 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1313 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1314 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1315 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1316 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1317 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1318 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1319 +
1320 +//U3D_reg3
1321 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1322 +
1323 +//U3D_reg4
1324 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1325 +
1326 +//U3D_reg5
1327 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1328 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1329 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1330 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1331 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1332 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1333 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1334 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1335 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1336 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1337 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1338 +
1339 +//U3D_reg6
1340 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1341 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1342 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1343 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1344 +#define RG_SSUSB_TX_SR_OFST (20)
1345 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1346 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1347 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1348 +#define RG_SSUSB_CKMON_EN_OFST (11)
1349 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1350 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1351 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1352 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1353 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1354 +
1355 +//U3D_reg7
1356 +#define RG_SSUSB_RESERVE_OFST (12)
1357 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1358 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1359 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1360 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1361 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1362 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1363 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1364 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1365 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1366 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1367 +
1368 +//U3D_reg8
1369 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1370 +
1371 +//U3D_reg9
1372 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1373 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1374 +
1375 +//U3D_regA
1376 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1377 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1378 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1379 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1380 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1381 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1382 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1383 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1384 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1385 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1386 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1387 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1388 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1389 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1390 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1391 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1392 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1393 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1394 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1395 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1396 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1397 +
1398 +//U3D_regB
1399 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1400 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1401 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1402 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1403 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1404 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1405 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1406 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1407 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1408 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1409 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1410 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1411 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1412 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1413 +
1414 +//U3D_regC
1415 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1416 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1417 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1418 +#define RG_PCIE_RX_RESERVE_OFST (0)
1419 +
1420 +//U3D_redD
1421 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1422 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1423 +
1424 +//U3D_regE
1425 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1426 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1427 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1428 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1429 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1430 +
1431 +///////////////////////////////////////////////////////////////////////////////
1432 +
1433 +struct u3phya_da_reg {
1434 + //0x0
1435 + PHY_LE32 reg0;
1436 + PHY_LE32 reg1;
1437 + PHY_LE32 reg4;
1438 + PHY_LE32 reg5;
1439 + //0x10
1440 + PHY_LE32 reg6;
1441 + PHY_LE32 reg7;
1442 + PHY_LE32 reg8;
1443 + PHY_LE32 reg9;
1444 + //0x20
1445 + PHY_LE32 reg10;
1446 + PHY_LE32 reg12;
1447 + PHY_LE32 reg13;
1448 + PHY_LE32 reg14;
1449 + //0x30
1450 + PHY_LE32 reg15;
1451 + PHY_LE32 reg16;
1452 + PHY_LE32 reg19;
1453 + PHY_LE32 reg20;
1454 + //0x40
1455 + PHY_LE32 reg21;
1456 + PHY_LE32 reg23;
1457 + PHY_LE32 reg25;
1458 + PHY_LE32 reg26;
1459 + //0x50
1460 + PHY_LE32 reg28;
1461 + PHY_LE32 reg29;
1462 + PHY_LE32 reg30;
1463 + PHY_LE32 reg31;
1464 + //0x60
1465 + PHY_LE32 reg32;
1466 + PHY_LE32 reg33;
1467 +};
1468 +
1469 +//U3D_reg0
1470 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1471 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1472 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1473 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1474 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1475 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1476 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1477 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1478 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1479 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1480 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1481 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1482 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1483 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1484 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1485 +
1486 +//U3D_reg1
1487 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1488 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1489 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1490 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1491 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1492 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1493 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1494 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1495 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1496 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1497 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1498 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1499 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1500 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1501 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1502 +
1503 +//U3D_reg4
1504 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1505 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1506 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1507 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1508 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1509 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1510 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1511 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1512 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1513 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1514 +
1515 +//U3D_reg5
1516 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1517 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1518 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1519 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1520 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1521 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1522 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1523 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1524 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1525 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1526 +
1527 +//U3D_reg6
1528 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1529 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1530 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1531 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1532 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1533 +
1534 +//U3D_reg7
1535 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1536 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1537 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1538 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1539 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1540 +
1541 +//U3D_reg8
1542 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1543 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1544 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1545 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1546 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1547 +
1548 +//U3D_reg9
1549 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1550 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1551 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1552 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1553 +
1554 +//U3D_reg10
1555 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1556 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1557 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1558 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1559 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1560 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1561 +
1562 +//U3D_reg12
1563 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1564 +
1565 +//U3D_reg13
1566 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1567 +
1568 +//U3D_reg14
1569 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1570 +
1571 +//U3D_reg15
1572 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1573 +
1574 +//U3D_reg16
1575 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1576 +
1577 +//U3D_reg19
1578 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1579 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1580 +
1581 +//U3D_reg20
1582 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1583 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1584 +
1585 +//U3D_reg21
1586 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1587 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1588 +
1589 +//U3D_reg23
1590 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1591 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1592 +
1593 +//U3D_reg25
1594 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1595 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1596 +
1597 +//U3D_reg26
1598 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1599 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1600 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1601 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1602 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1603 +
1604 +//U3D_reg28
1605 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1606 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1607 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1608 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1609 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1610 +
1611 +//U3D_reg29
1612 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1613 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1614 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1615 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1616 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1617 +
1618 +//U3D_reg30
1619 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1620 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1621 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1622 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1623 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1624 +
1625 +//U3D_reg31
1626 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1627 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1628 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1629 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1630 +
1631 +//U3D_reg32
1632 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1633 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1634 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1635 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1636 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1637 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1638 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1639 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1640 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1641 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1642 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1643 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1644 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1645 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1646 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1647 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1648 +
1649 +//U3D_reg33
1650 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1651 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1652 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1653 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1654 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1655 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1656 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1657 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1658 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1659 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1660 +
1661 +
1662 +/* OFFSET */
1663 +
1664 +//U3D_reg0
1665 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1666 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1667 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1668 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1669 +#define RG_PCIE_SPEED_U3_OFST (20)
1670 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1671 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1672 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1673 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1674 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1675 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1676 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1677 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1678 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1679 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1680 +
1681 +//U3D_reg1
1682 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1683 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1684 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1685 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1686 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1687 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1688 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1689 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1690 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1691 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1692 +#define RG_PCIE_MODE_PE2D_OFST (8)
1693 +#define RG_PCIE_MODE_PE2H_OFST (3)
1694 +#define RG_PCIE_MODE_PE1D_OFST (2)
1695 +#define RG_PCIE_MODE_PE1H_OFST (1)
1696 +#define RG_PCIE_MODE_U3_OFST (0)
1697 +
1698 +//U3D_reg4
1699 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1700 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1701 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1702 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1703 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1704 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1705 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1706 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1707 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1708 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1709 +
1710 +//U3D_reg5
1711 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1712 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1713 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1714 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1715 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1716 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1717 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1718 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1719 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1720 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1721 +
1722 +//U3D_reg6
1723 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1724 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1725 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1726 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1727 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1728 +
1729 +//U3D_reg7
1730 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1731 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1732 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1733 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1734 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1735 +
1736 +//U3D_reg8
1737 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1738 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1739 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1740 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1741 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1742 +
1743 +//U3D_reg9
1744 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1745 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1746 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1747 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1748 +
1749 +//U3D_reg10
1750 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1751 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1752 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1753 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1754 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1755 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1756 +
1757 +//U3D_reg12
1758 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1759 +
1760 +//U3D_reg13
1761 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1762 +
1763 +//U3D_reg14
1764 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1765 +
1766 +//U3D_reg15
1767 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1768 +
1769 +//U3D_reg16
1770 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1771 +
1772 +//U3D_reg19
1773 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1774 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1775 +
1776 +//U3D_reg20
1777 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1778 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1779 +
1780 +//U3D_reg21
1781 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1782 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1783 +
1784 +//U3D_reg23
1785 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1786 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1787 +
1788 +//U3D_reg25
1789 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1790 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1791 +
1792 +//U3D_reg26
1793 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1794 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1795 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1796 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1797 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1798 +
1799 +//U3D_reg28
1800 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1801 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1802 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1803 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1804 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1805 +
1806 +//U3D_reg29
1807 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1808 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1809 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1810 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1811 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1812 +
1813 +//U3D_reg30
1814 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1815 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1816 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1817 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1818 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1819 +
1820 +//U3D_reg31
1821 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1822 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1823 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1824 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1825 +
1826 +//U3D_reg32
1827 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1828 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1829 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1830 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1831 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1832 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1833 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1834 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1835 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1836 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1837 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1838 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1839 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1840 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1841 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1842 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1843 +
1844 +//U3D_reg33
1845 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1846 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1847 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1848 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1849 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1850 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1851 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1852 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1853 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1854 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1855 +
1856 +
1857 +///////////////////////////////////////////////////////////////////////////////
1858 +
1859 +struct u3phyd_reg {
1860 + //0x0
1861 + PHY_LE32 phyd_mix0;
1862 + PHY_LE32 phyd_mix1;
1863 + PHY_LE32 phyd_lfps0;
1864 + PHY_LE32 phyd_lfps1;
1865 + //0x10
1866 + PHY_LE32 phyd_impcal0;
1867 + PHY_LE32 phyd_impcal1;
1868 + PHY_LE32 phyd_txpll0;
1869 + PHY_LE32 phyd_txpll1;
1870 + //0x20
1871 + PHY_LE32 phyd_txpll2;
1872 + PHY_LE32 phyd_fl0;
1873 + PHY_LE32 phyd_mix2;
1874 + PHY_LE32 phyd_rx0;
1875 + //0x30
1876 + PHY_LE32 phyd_t2rlb;
1877 + PHY_LE32 phyd_cppat;
1878 + PHY_LE32 phyd_mix3;
1879 + PHY_LE32 phyd_ebufctl;
1880 + //0x40
1881 + PHY_LE32 phyd_pipe0;
1882 + PHY_LE32 phyd_pipe1;
1883 + PHY_LE32 phyd_mix4;
1884 + PHY_LE32 phyd_ckgen0;
1885 + //0x50
1886 + PHY_LE32 phyd_mix5;
1887 + PHY_LE32 phyd_reserved;
1888 + PHY_LE32 phyd_cdr0;
1889 + PHY_LE32 phyd_cdr1;
1890 + //0x60
1891 + PHY_LE32 phyd_pll_0;
1892 + PHY_LE32 phyd_pll_1;
1893 + PHY_LE32 phyd_bcn_det_1;
1894 + PHY_LE32 phyd_bcn_det_2;
1895 + //0x70
1896 + PHY_LE32 eq0;
1897 + PHY_LE32 eq1;
1898 + PHY_LE32 eq2;
1899 + PHY_LE32 eq3;
1900 + //0x80
1901 + PHY_LE32 eq_eye0;
1902 + PHY_LE32 eq_eye1;
1903 + PHY_LE32 eq_eye2;
1904 + PHY_LE32 eq_dfe0;
1905 + //0x90
1906 + PHY_LE32 eq_dfe1;
1907 + PHY_LE32 eq_dfe2;
1908 + PHY_LE32 eq_dfe3;
1909 + PHY_LE32 reserve0;
1910 + //0xa0
1911 + PHY_LE32 phyd_mon0;
1912 + PHY_LE32 phyd_mon1;
1913 + PHY_LE32 phyd_mon2;
1914 + PHY_LE32 phyd_mon3;
1915 + //0xb0
1916 + PHY_LE32 phyd_mon4;
1917 + PHY_LE32 phyd_mon5;
1918 + PHY_LE32 phyd_mon6;
1919 + PHY_LE32 phyd_mon7;
1920 + //0xc0
1921 + PHY_LE32 phya_rx_mon0;
1922 + PHY_LE32 phya_rx_mon1;
1923 + PHY_LE32 phya_rx_mon2;
1924 + PHY_LE32 phya_rx_mon3;
1925 + //0xd0
1926 + PHY_LE32 phya_rx_mon4;
1927 + PHY_LE32 phya_rx_mon5;
1928 + PHY_LE32 phyd_cppat2;
1929 + PHY_LE32 eq_eye3;
1930 + //0xe0
1931 + PHY_LE32 kband_out;
1932 + PHY_LE32 kband_out1;
1933 +};
1934 +
1935 +//U3D_PHYD_MIX0
1936 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1937 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1938 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1939 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1940 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1941 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1942 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1943 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1944 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1945 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1946 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1947 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1948 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1949 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1950 +
1951 +//U3D_PHYD_MIX1
1952 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1953 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1954 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1955 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1956 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1957 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1958 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1959 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1960 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1961 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1962 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1963 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1964 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1965 +
1966 +//U3D_PHYD_LFPS0
1967 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1968 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1969 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1970 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1971 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1972 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1973 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1974 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1975 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1976 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1977 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1978 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1979 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1980 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1981 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1982 +
1983 +//U3D_PHYD_LFPS1
1984 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1985 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1986 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
1987 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
1988 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
1989 +
1990 +//U3D_PHYD_IMPCAL0
1991 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
1992 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
1993 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
1994 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
1995 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
1996 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
1997 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1998 +
1999 +//U3D_PHYD_IMPCAL1
2000 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
2001 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
2002 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
2003 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
2004 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
2005 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
2006 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
2007 +
2008 +//U3D_PHYD_TXPLL0
2009 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
2010 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
2011 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
2012 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
2013 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
2014 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
2015 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
2016 +
2017 +//U3D_PHYD_TXPLL1
2018 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
2019 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
2020 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
2021 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
2022 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
2023 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
2024 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
2025 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
2026 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
2027 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
2028 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2029 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2030 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2031 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2032 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2033 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2034 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2035 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2036 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2037 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2038 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2039 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2040 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2041 +
2042 +//U3D_PHYD_TXPLL2
2043 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2044 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2045 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2046 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2047 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2048 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2049 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2050 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2051 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2052 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2053 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2054 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2055 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2056 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2057 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2058 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2059 +
2060 +//U3D_PHYD_FL0
2061 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2062 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2063 +
2064 +//U3D_PHYD_MIX2
2065 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2066 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2067 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2068 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2069 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2070 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2071 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2072 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2073 +
2074 +//U3D_PHYD_RX0
2075 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2076 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2077 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2078 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2079 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2080 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2081 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2082 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2083 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2084 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2085 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2086 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2087 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2088 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2089 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2090 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2091 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2092 +
2093 +//U3D_PHYD_T2RLB
2094 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2095 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2096 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2097 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2098 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2099 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2100 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2101 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2102 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2103 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2104 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2105 +
2106 +//U3D_PHYD_CPPAT
2107 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2108 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2109 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2110 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2111 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2112 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2113 +
2114 +//U3D_PHYD_MIX3
2115 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2116 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2117 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2118 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2119 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2120 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2121 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2122 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2123 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2124 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2125 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2126 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2127 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2128 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2129 +
2130 +//U3D_PHYD_EBUFCTL
2131 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2132 +
2133 +//U3D_PHYD_PIPE0
2134 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2135 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2136 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2137 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2138 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2139 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2140 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2141 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2142 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2143 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2144 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2145 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2146 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2147 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2148 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2149 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2150 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2151 +
2152 +//U3D_PHYD_PIPE1
2153 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2154 +
2155 +//U3D_PHYD_MIX4
2156 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2157 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2158 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2159 +
2160 +//U3D_PHYD_CKGEN0
2161 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2162 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2163 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2164 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2165 +
2166 +//U3D_PHYD_MIX5
2167 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2168 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2169 +
2170 +//U3D_PHYD_RESERVED
2171 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2172 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2173 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2174 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2175 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2176 +
2177 +//U3D_PHYD_CDR0
2178 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2179 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2180 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2181 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2182 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2183 +
2184 +//U3D_PHYD_CDR1
2185 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2186 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2187 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2188 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2189 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2190 +
2191 +//U3D_PHYD_PLL_0
2192 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2193 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2194 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2195 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2196 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2197 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2198 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2199 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2200 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2201 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2202 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2203 +
2204 +//U3D_PHYD_PLL_1
2205 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2206 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2207 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2208 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2209 +
2210 +//U3D_PHYD_BCN_DET_1
2211 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2212 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2213 +
2214 +//U3D_PHYD_BCN_DET_2
2215 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2216 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2217 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2218 +
2219 +//U3D_EQ0
2220 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2221 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2222 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2223 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2224 +
2225 +//U3D_EQ1
2226 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2227 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2228 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2229 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2230 +
2231 +//U3D_EQ2
2232 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2233 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2234 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2235 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2236 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2237 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2238 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2239 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2240 +
2241 +//U3D_EQ3
2242 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2243 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2244 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2245 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2246 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2247 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2248 +
2249 +//U3D_EQ_EYE0
2250 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2251 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2252 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2253 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2254 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2255 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2256 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2257 +
2258 +//U3D_EQ_EYE1
2259 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2260 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2261 +
2262 +//U3D_EQ_EYE2
2263 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2264 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2265 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2266 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2267 +
2268 +//U3D_EQ_DFE0
2269 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2270 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2271 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2272 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2273 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2274 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2275 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2276 +
2277 +//U3D_EQ_DFE1
2278 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2279 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2280 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2281 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2282 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2283 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2284 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2285 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2286 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2287 +
2288 +//U3D_EQ_DFE2
2289 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2290 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2291 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2292 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2293 +
2294 +//U3D_EQ_DFE3
2295 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2296 +
2297 +//U3D_PHYD_MON0
2298 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2299 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2300 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2301 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2302 +
2303 +//U3D_PHYD_MON1
2304 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2305 +
2306 +//U3D_PHYD_MON2
2307 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2308 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2309 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2310 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2311 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2312 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2313 +
2314 +//U3D_PHYD_MON3
2315 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2316 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2317 +
2318 +//U3D_PHYD_MON4
2319 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2320 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2321 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2322 +
2323 +//U3D_PHYD_MON5
2324 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2325 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2326 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2327 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2328 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2329 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2330 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2331 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2332 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2333 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2334 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2335 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2336 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2337 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2338 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2339 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2340 +
2341 +//U3D_PHYD_MON6
2342 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2343 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2344 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2345 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2346 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2347 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2348 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2349 +
2350 +//U3D_PHYD_MON7
2351 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2352 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2353 +
2354 +//U3D_PHYA_RX_MON0
2355 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2356 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2357 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2358 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2359 +
2360 +//U3D_PHYA_RX_MON1
2361 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2362 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2363 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2364 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2365 +
2366 +//U3D_PHYA_RX_MON2
2367 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2368 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2369 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2370 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2371 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2372 +
2373 +//U3D_PHYA_RX_MON3
2374 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2375 +
2376 +//U3D_PHYA_RX_MON4
2377 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2378 +
2379 +//U3D_PHYA_RX_MON5
2380 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2381 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2382 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2383 +
2384 +//U3D_PHYD_CPPAT2
2385 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2386 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2387 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2388 +
2389 +//U3D_EQ_EYE3
2390 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2391 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2392 +
2393 +//U3D_KBAND_OUT
2394 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2395 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2396 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2397 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2398 +
2399 +//U3D_KBAND_OUT1
2400 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2401 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2402 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2403 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2404 +
2405 +
2406 +/* OFFSET */
2407 +
2408 +//U3D_PHYD_MIX0
2409 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2410 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2411 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2412 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2413 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2414 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2415 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2416 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2417 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2418 +#define RG_SSUSB_PRBS_EN_OFST (13)
2419 +#define RG_SSUSB_BPSLOCK_OFST (12)
2420 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2421 +#define RG_SSUSB_COMCNT_OFST (4)
2422 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2423 +
2424 +//U3D_PHYD_MIX1
2425 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2426 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2427 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2428 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2429 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2430 +#define RG_SSUSB_PDNCTL_OFST (16)
2431 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2432 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2433 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2434 +#define RG_SSUSB_BERT_EN_OFST (7)
2435 +#define RG_SSUSB_SCP_TH_OFST (4)
2436 +#define RG_SSUSB_SCP_EN_OFST (3)
2437 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2438 +
2439 +//U3D_PHYD_LFPS0
2440 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2441 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2442 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2443 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2444 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2445 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2446 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2447 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2448 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2449 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2450 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2451 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2452 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2453 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2454 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2455 +
2456 +//U3D_PHYD_LFPS1
2457 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2458 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2459 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2460 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2461 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2462 +
2463 +//U3D_PHYD_IMPCAL0
2464 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2465 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2466 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2467 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2468 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2469 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2470 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2471 +
2472 +//U3D_PHYD_IMPCAL1
2473 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2474 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2475 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2476 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2477 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2478 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2479 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2480 +
2481 +//U3D_PHYD_TXPLL0
2482 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2483 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2484 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2485 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2486 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2487 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2488 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2489 +
2490 +//U3D_PHYD_TXPLL1
2491 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2492 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2493 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2494 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2495 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2496 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2497 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2498 +#define RG_SSUSB_PLL_PWD_OFST (23)
2499 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2500 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2501 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2502 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2503 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2504 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2505 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2506 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2507 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2508 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2509 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2510 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2511 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2512 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2513 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2514 +
2515 +//U3D_PHYD_TXPLL2
2516 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2517 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2518 +#define RG_SSUSB_TX_LFPS_OFST (29)
2519 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2520 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2521 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2522 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2523 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2524 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2525 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2526 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2527 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2528 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2529 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2530 +#define RG_SSUSB_CDR_PWD_OFST (6)
2531 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2532 +
2533 +//U3D_PHYD_FL0
2534 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2535 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2536 +
2537 +//U3D_PHYD_MIX2
2538 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2539 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2540 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2541 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2542 +#define RG_SSUSB_CDROS_EN_OFST (18)
2543 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2544 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2545 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2546 +
2547 +//U3D_PHYD_RX0
2548 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2549 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2550 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2551 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2552 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2553 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2554 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2555 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2556 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2557 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2558 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2559 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2560 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2561 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2562 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2563 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2564 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2565 +
2566 +//U3D_PHYD_T2RLB
2567 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2568 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2569 +#define RG_SSUSB_BPANSIENC_OFST (26)
2570 +#define RG_SSUSB_VALID_EN_OFST (25)
2571 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2572 +#define RG_SSUSB_K_EMP_OFST (20)
2573 +#define RG_SSUSB_K_FUL_OFST (16)
2574 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2575 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2576 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2577 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2578 +
2579 +//U3D_PHYD_CPPAT
2580 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2581 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2582 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2583 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2584 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2585 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2586 +
2587 +//U3D_PHYD_MIX3
2588 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2589 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2590 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2591 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2592 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2593 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2594 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2595 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2596 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2597 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2598 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2599 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2600 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2601 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2602 +
2603 +//U3D_PHYD_EBUFCTL
2604 +#define RG_SSUSB_EBUFCTL_OFST (0)
2605 +
2606 +//U3D_PHYD_PIPE0
2607 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2608 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2609 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2610 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2611 +#define RG_SSUSB_POWERDOWN_OFST (24)
2612 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2613 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2614 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2615 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2616 +#define RG_SSUSB_TXDATAK_OFST (16)
2617 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2618 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2619 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2620 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2621 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2622 +#define RG_SSUSB_TXMARGIN_OFST (1)
2623 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2624 +
2625 +//U3D_PHYD_PIPE1
2626 +#define RG_SSUSB_TXDATA_OFST (0)
2627 +
2628 +//U3D_PHYD_MIX4
2629 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2630 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2631 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2632 +
2633 +//U3D_PHYD_CKGEN0
2634 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2635 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2636 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2637 +#define RG_SSUSB_RXCK_INV_OFST (0)
2638 +
2639 +//U3D_PHYD_MIX5
2640 +#define RG_SSUSB_PRB_SEL_OFST (16)
2641 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2642 +
2643 +//U3D_PHYD_RESERVED
2644 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2645 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2646 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2647 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2648 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2649 +
2650 +//U3D_PHYD_CDR0
2651 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2652 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2653 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2654 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2655 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2656 +
2657 +//U3D_PHYD_CDR1
2658 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2659 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2660 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2661 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2662 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2663 +
2664 +//U3D_PHYD_PLL_0
2665 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2666 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2667 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2668 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2669 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2670 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2671 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2672 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2673 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2674 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2675 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2676 +
2677 +//U3D_PHYD_PLL_1
2678 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2679 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2680 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2681 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2682 +
2683 +//U3D_PHYD_BCN_DET_1
2684 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2685 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2686 +
2687 +//U3D_PHYD_BCN_DET_2
2688 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2689 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2690 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2691 +
2692 +//U3D_EQ0
2693 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2694 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2695 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2696 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2697 +
2698 +//U3D_EQ1
2699 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2700 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2701 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2702 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2703 +
2704 +//U3D_EQ2
2705 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2706 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2707 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2708 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2709 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2710 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2711 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2712 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2713 +
2714 +//U3D_EQ3
2715 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2716 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2717 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2718 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2719 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2720 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2721 +
2722 +//U3D_EQ_EYE0
2723 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2724 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2725 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2726 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2727 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2728 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2729 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2730 +
2731 +//U3D_EQ_EYE1
2732 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2733 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2734 +
2735 +//U3D_EQ_EYE2
2736 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2737 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2738 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2739 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2740 +
2741 +//U3D_EQ_DFE0
2742 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2743 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2744 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2745 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2746 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2747 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2748 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2749 +
2750 +//U3D_EQ_DFE1
2751 +#define RG_SSUSB_EQ_REV_OFST (16)
2752 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2753 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2754 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2755 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2756 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2757 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2758 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2759 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2760 +
2761 +//U3D_EQ_DFE2
2762 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2763 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2764 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2765 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2766 +
2767 +//U3D_EQ_DFE3
2768 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2769 +
2770 +//U3D_PHYD_MON0
2771 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2772 +#define RGS_SSUSB_LFPS_OFST (12)
2773 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2774 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2775 +
2776 +//U3D_PHYD_MON1
2777 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2778 +
2779 +//U3D_PHYD_MON2
2780 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2781 +#define RGS_SSUSB_RETRACK_OFST (12)
2782 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2783 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2784 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2785 +#define RGS_SSUSB_PDNCTL_OFST (0)
2786 +
2787 +//U3D_PHYD_MON3
2788 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2789 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2790 +
2791 +//U3D_PHYD_MON4
2792 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2793 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2794 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2795 +
2796 +//U3D_PHYD_MON5
2797 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2798 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2799 +#define RGS_SSUSB_SCP_DET_OFST (14)
2800 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2801 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2802 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2803 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2804 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2805 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2806 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2807 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2808 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2809 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2810 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2811 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2812 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2813 +
2814 +//U3D_PHYD_MON6
2815 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2816 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2817 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2818 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2819 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2820 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2821 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2822 +
2823 +//U3D_PHYD_MON7
2824 +#define RGS_SSUSB_FT_OUT_OFST (8)
2825 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2826 +
2827 +//U3D_PHYA_RX_MON0
2828 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2829 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2830 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2831 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2832 +
2833 +//U3D_PHYA_RX_MON1
2834 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2835 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2836 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2837 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2838 +
2839 +//U3D_PHYA_RX_MON2
2840 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2841 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2842 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2843 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2844 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2845 +
2846 +//U3D_PHYA_RX_MON3
2847 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2848 +
2849 +//U3D_PHYA_RX_MON4
2850 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2851 +
2852 +//U3D_PHYA_RX_MON5
2853 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2854 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2855 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2856 +
2857 +//U3D_PHYD_CPPAT2
2858 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2859 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2860 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2861 +
2862 +//U3D_EQ_EYE3
2863 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2864 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2865 +
2866 +//U3D_KBAND_OUT
2867 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2868 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2869 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2870 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2871 +
2872 +//U3D_KBAND_OUT1
2873 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2874 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2875 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2876 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2877 +
2878 +
2879 +///////////////////////////////////////////////////////////////////////////////
2880 +
2881 +struct u3phyd_bank2_reg {
2882 + //0x0
2883 + PHY_LE32 b2_phyd_top1;
2884 + PHY_LE32 b2_phyd_top2;
2885 + PHY_LE32 b2_phyd_top3;
2886 + PHY_LE32 b2_phyd_top4;
2887 + //0x10
2888 + PHY_LE32 b2_phyd_top5;
2889 + PHY_LE32 b2_phyd_top6;
2890 + PHY_LE32 b2_phyd_top7;
2891 + PHY_LE32 b2_phyd_p_sigdet1;
2892 + //0x20
2893 + PHY_LE32 b2_phyd_p_sigdet2;
2894 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2895 + PHY_LE32 b2_phyd_rxdet1;
2896 + PHY_LE32 b2_phyd_rxdet2;
2897 + //0x30
2898 + PHY_LE32 b2_phyd_misc0;
2899 + PHY_LE32 b2_phyd_misc2;
2900 + PHY_LE32 b2_phyd_misc3;
2901 + PHY_LE32 reserve0;
2902 + //0x40
2903 + PHY_LE32 b2_rosc_0;
2904 + PHY_LE32 b2_rosc_1;
2905 + PHY_LE32 b2_rosc_2;
2906 + PHY_LE32 b2_rosc_3;
2907 + //0x50
2908 + PHY_LE32 b2_rosc_4;
2909 + PHY_LE32 b2_rosc_5;
2910 + PHY_LE32 b2_rosc_6;
2911 + PHY_LE32 b2_rosc_7;
2912 + //0x60
2913 + PHY_LE32 b2_rosc_8;
2914 + PHY_LE32 b2_rosc_9;
2915 + PHY_LE32 b2_rosc_a;
2916 + PHY_LE32 reserve1;
2917 + //0x70~0xd0
2918 + PHY_LE32 reserve2[28];
2919 + //0xe0
2920 + PHY_LE32 phyd_version;
2921 + PHY_LE32 phyd_model;
2922 +};
2923 +
2924 +//U3D_B2_PHYD_TOP1
2925 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2926 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2927 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2928 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2929 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2930 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2931 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2932 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2933 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2934 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2935 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2936 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2937 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2938 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2939 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2940 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2941 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2942 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2943 +
2944 +//U3D_B2_PHYD_TOP2
2945 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2946 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2947 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2948 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2949 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2950 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2951 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2952 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2953 +
2954 +//U3D_B2_PHYD_TOP3
2955 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2956 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2957 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2958 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2959 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2960 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2961 +
2962 +//U3D_B2_PHYD_TOP4
2963 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2964 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2965 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2966 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2967 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2968 +
2969 +//U3D_B2_PHYD_TOP5
2970 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2971 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2972 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2973 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2974 +
2975 +//U3D_B2_PHYD_TOP6
2976 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2977 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2978 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2979 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2980 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2981 +
2982 +//U3D_B2_PHYD_TOP7
2983 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2984 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2985 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2986 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
2987 +
2988 +//U3D_B2_PHYD_P_SIGDET1
2989 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
2990 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2991 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2992 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
2993 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
2994 +
2995 +//U3D_B2_PHYD_P_SIGDET2
2996 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
2997 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
2998 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
2999 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
3000 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
3001 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
3002 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
3003 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
3004 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
3005 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
3006 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
3007 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
3008 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
3009 +
3010 +//U3D_B2_PHYD_P_SIGDET_CAL1
3011 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
3012 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
3013 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
3014 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
3015 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
3016 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
3017 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
3018 +
3019 +//U3D_B2_PHYD_RXDET1
3020 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
3021 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
3022 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
3023 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
3024 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
3025 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
3026 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
3027 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3028 +
3029 +//U3D_B2_PHYD_RXDET2
3030 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3031 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3032 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3033 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3034 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3035 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3036 +
3037 +//U3D_B2_PHYD_MISC0
3038 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3039 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3040 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3041 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3042 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3043 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3044 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3045 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3046 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3047 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3048 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3049 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3050 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3051 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3052 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3053 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3054 +
3055 +//U3D_B2_PHYD_MISC2
3056 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3057 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3058 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3059 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3060 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3061 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3062 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3063 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3064 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3065 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3066 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3067 +
3068 +//U3D_B2_PHYD_MISC3
3069 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3070 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3071 +
3072 +//U3D_B2_ROSC_0
3073 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3074 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3075 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3076 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3077 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3078 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3079 +
3080 +//U3D_B2_ROSC_1
3081 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3082 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3083 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3084 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3085 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3086 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3087 +
3088 +//U3D_B2_ROSC_2
3089 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3090 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3091 +
3092 +//U3D_B2_ROSC_3
3093 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3094 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3095 +
3096 +//U3D_B2_ROSC_4
3097 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3098 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3099 +
3100 +//U3D_B2_ROSC_5
3101 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3102 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3103 +
3104 +//U3D_B2_ROSC_6
3105 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3106 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3107 +
3108 +//U3D_B2_ROSC_7
3109 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3110 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3111 +
3112 +//U3D_B2_ROSC_8
3113 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3114 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3115 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3116 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3117 +
3118 +//U3D_B2_ROSC_9
3119 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3120 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3121 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3122 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3123 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3124 +
3125 +//U3D_B2_ROSC_A
3126 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3127 +
3128 +//U3D_PHYD_VERSION
3129 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3130 +
3131 +//U3D_PHYD_MODEL
3132 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3133 +
3134 +
3135 +/* OFFSET */
3136 +
3137 +//U3D_B2_PHYD_TOP1
3138 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3139 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3140 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3141 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3142 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3143 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3144 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3145 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3146 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3147 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3148 +