ramips: add alsa driver
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.18 / 500-alsa.patch
1 --- a/sound/soc/Kconfig
2 +++ b/sound/soc/Kconfig
3 @@ -56,6 +56,7 @@
4 source "sound/soc/tegra/Kconfig"
5 source "sound/soc/txx9/Kconfig"
6 source "sound/soc/ux500/Kconfig"
7 +source "sound/soc/mtk/Kconfig"
8
9 # Supported codecs
10 source "sound/soc/codecs/Kconfig"
11 --- a/sound/soc/Makefile
12 +++ b/sound/soc/Makefile
13 @@ -33,3 +33,4 @@
14 obj-$(CONFIG_SND_SOC) += tegra/
15 obj-$(CONFIG_SND_SOC) += txx9/
16 obj-$(CONFIG_SND_SOC) += ux500/
17 +obj-$(CONFIG_SND_SOC) += mtk/
18 --- a/sound/soc/codecs/Kconfig
19 +++ b/sound/soc/codecs/Kconfig
20 @@ -725,7 +725,7 @@
21 tristate
22
23 config SND_SOC_WM8960
24 - tristate
25 + tristate "WM8960"
26
27 config SND_SOC_WM8961
28 tristate
29 --- /dev/null
30 +++ b/sound/soc/mtk/Kconfig
31 @@ -0,0 +1,35 @@
32 +config SND_MT76XX_SOC
33 + tristate "SoC Audio for MT76XX APSoC Machine"
34 + depends on SND_SOC && (SOC_MT7620 || SOC_MT7621)
35 +
36 + help
37 + Say Y or M if you want to add support for codecs attached to
38 + the MTK I2S interface.
39 +
40 +choice
41 + prompt "Selected SoC type"
42 + depends on SND_MT76XX_SOC
43 + default SND_MT76XX_SOC_MT7620
44 +
45 +config SND_MT76XX_SOC_MT7620
46 + bool "MT7620"
47 + depends on SOC_MT7620
48 +
49 +config SND_MT76XX_SOC_MT7628
50 + bool "MT7628"
51 + depends on SOC_MT7620
52 +
53 +config SND_MT76XX_SOC_MT7621
54 + bool "MT7621"
55 + depends on SOC_MT7621
56 +
57 +endchoice
58 +
59 +config SND_MT76XX_PCM
60 + tristate "MTK SoC Audio PCM Platform"
61 + depends on SND_MT76XX_SOC
62 +
63 +config SND_MT76XX_I2S
64 + tristate "MTK SoC I2S Support"
65 + depends on SND_MT76XX_SOC
66 +
67 --- /dev/null
68 +++ b/sound/soc/mtk/Makefile
69 @@ -0,0 +1,39 @@
70 +KBUILD_CFLAGS += -I$(srctree)
71 +
72 +ifeq ($(CONFIG_SND_MT76XX_SOC_MT7620),y)
73 +KBUILD_CFLAGS += -DCONFIG_MT7620 -DCONFIG_RALINK_MT7620
74 +endif
75 +ifeq ($(CONFIG_SND_MT76XX_SOC_MT7628),y)
76 +KBUILD_CFLAGS += -DCONFIG_MT7628 -DCONFIG_RALINK_MT7628
77 +endif
78 +ifeq ($(CONFIG_SOC_MT7620),y)
79 +KBUILD_CFLAGS += -DRALINK_SYSCTL_BASE=0xB0000000
80 +KBUILD_CFLAGS += -DRALINK_INTCL_BASE=0xB0000200
81 +KBUILD_CFLAGS += -DRALINK_PIO_BASE=0xB0000600
82 +KBUILD_CFLAGS += -DRALINK_I2S_BASE=0xB0000A00
83 +KBUILD_CFLAGS += -DRALINK_GDMA_BASE=0xB0002800
84 +KBUILD_CFLAGS += -DCONFIG_GDMA_EVERYBODY
85 +KBUILD_CFLAGS += -DCONFIG_SND_MT76XX_SOC
86 +KBUILD_CFLAGS += -DCONFIG_I2S_WM8960
87 +KBUILD_CFLAGS += -DCONFIG_I2S_MCLK_12P288MHZ
88 +KBUILD_CFLAGS += -DCONFIG_GDMA_EVERYBODY
89 +KBUILD_CFLAGS += -DSURFBOARDINT_DMA=15
90 +KBUILD_CFLAGS += -DRALINK_INTCTL_DMA=128
91 +KBUILD_CFLAGS += -DCONFIG_SND_SOC_WM8960
92 +endif
93 +
94 +# MTK APSoC Platform Support
95 +snd-soc-mt76xx-i2s-ctl-objs := i2s_ctrl.o i2s_debug.o #i2c_wm8960.o
96 +snd-soc-mt76xx-pcm-objs := mt76xx_pcm.o
97 +snd-soc-mt76xx-i2s-objs := mt76xx_i2s.o
98 +
99 +obj-$(CONFIG_SND_MT76XX_PCM) += snd-soc-mt76xx-pcm.o
100 +obj-$(CONFIG_SND_MT76XX_I2S) += snd-soc-mt76xx-i2s-ctl.o snd-soc-mt76xx-i2s.o
101 +
102 +# MTK APSoC Machine Support
103 +snd-soc-mt76xx-machine-objs := mt76xx_machine.o
104 +
105 +obj-$(CONFIG_SND_MT76XX_SOC) += i2c_wm8960.o ralink_gdma.o snd-soc-mt76xx-machine.o
106 +
107 +
108 +
109 --- /dev/null
110 +++ b/sound/soc/mtk/i2c_wm8960.c
111 @@ -0,0 +1,492 @@
112 +#include <linux/kernel.h>
113 +#include <linux/version.h>
114 +#include <linux/init.h>
115 +#include <linux/module.h>
116 +#include <linux/slab.h>
117 +#include <linux/i2c.h>
118 +#include <linux/delay.h>
119 +#include <linux/interrupt.h>
120 +#include <linux/fs.h>
121 +#include <linux/fcntl.h>
122 +#include <linux/cdev.h>
123 +#if defined(CONFIG_ARCH_MT7623)
124 +#include <mt_i2c.h>
125 +#include <mach/mt_gpio.h>
126 +#endif
127 +#include "i2c_wm8960.h"
128 +#include "i2s_ctrl.h"
129 +
130 +
131 +#define BUF_SIZE 20
132 +
133 +#undef MSG
134 +#define MSG printk
135 +
136 +
137 +#if defined(CONFIG_ARCH_MT7623)
138 +/*FIXME*/
139 +//static struct i2c_board_info __initdata i2c_devs1 = { I2C_BOARD_INFO("codec_wm8960", (0X34>>1))};
140 +static struct i2c_board_info __initdata i2c_devs1 = { I2C_BOARD_INFO("codec_wm8960", (0X34))};
141 +
142 +#endif
143 +unsigned long wm_reg_data[56];
144 +struct wm8960_data *wmio;
145 +
146 +struct wm8960_data {
147 + struct i2c_client *client;
148 + struct device *dev;
149 + const char *name;
150 +};
151 +
152 +
153 +void i2c_WM8960_write(u32 reg, u32 data)
154 +{
155 + int ret;
156 + struct i2c_msg msg;
157 + u8 buf[2]={0};
158 +
159 +#if defined(CONFIG_ARCH_MT7623)
160 + unsigned int ext_flag = 0;
161 +
162 + ext_flag &= 0x7FFFFFFF;
163 + ext_flag |= I2C_A_FILTER_MSG;
164 + ext_flag |= I2C_POLLING_FLAG;
165 +#endif
166 +
167 + wm_reg_data[reg] = data;
168 +
169 + buf[0]= (reg<<1)|(0x01&(data>>8));
170 + buf[1]= (data&0xFF);
171 +
172 +#if defined(CONFIG_ARCH_MT7623)
173 + /*FIXME*/
174 + //msg.addr = wmio->client->addr;
175 + msg.addr = wmio->client->addr>>1;
176 +
177 +#else
178 + msg.addr = wmio->client->addr>>1;
179 +#endif
180 + msg.flags = 0;
181 + msg.buf = (char *)buf;
182 + msg.len = 2;
183 +#if defined(CONFIG_ARCH_MT7623)
184 + msg.timing = 80;
185 + msg.ext_flag = ext_flag & 0x7FFFFFFF;
186 +#endif
187 +
188 + ret = i2c_transfer(wmio->client->adapter, &msg, 1);
189 + MSG("[WM8960(%02X)=0x%08X]\n",(unsigned int)reg,(unsigned int)data);
190 +
191 + if (ret <= 0)
192 + printk("%s: i2c write error!\n", __func__);
193 +}
194 +
195 +
196 +
197 +// Reset and power up the WM8960
198 +void audiohw_preinit(void)
199 +{
200 + memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
201 +
202 + i2c_WM8960_write(RESET, RESET_RESET); // Reset (0x0F)
203 +
204 + mdelay(50);
205 + wm_reg_data[RESET] = 0xFFFF;
206 + mdelay(50);
207 +}
208 +
209 +void audiohw_set_apll(int srate)
210 +{
211 + unsigned long data;
212 +
213 + if((srate==8000) || (srate==12000) || (srate==16000) || (srate==24000) || (srate==32000) || (srate==48000))
214 + {
215 + // Provide 12.288MHz SYSCLK
216 + data = wm_reg_data[PLL1];
217 + i2c_WM8960_write(PLL1, data | PLL1_OPCLKDIV_1 | PLL1_SDM_FRACTIONAL | PLL1_PLLPRESCALE_1 | PLL1_PLLN(0x8)); // PLL1 (0x34)
218 +
219 + i2c_WM8960_write(PLL2, PLL2_PLLK_23_16(0x31)); // PLL2 (0x35)
220 + i2c_WM8960_write(PLL3, PLL3_PLLK_15_8(0x26)); // PLL3 (0x36)
221 + i2c_WM8960_write(PLL4, PLL4_PLLK_7_0(0xe9)); // PLL4 (0x37)
222 + }
223 + else if ((srate==11025) || (srate==22050) || (srate==44100))
224 + {
225 + //Provide 11.2896MHz SYSCLK
226 + data = wm_reg_data[PLL1];
227 + i2c_WM8960_write(PLL1, data | PLL1_OPCLKDIV_1 | PLL1_SDM_FRACTIONAL | PLL1_PLLPRESCALE_1 | PLL1_PLLN(0x7)); //PLL1 (0x34)
228 +
229 + i2c_WM8960_write(PLL2, PLL2_PLLK_23_16(0x86)); //PLL2 (0x35)
230 + i2c_WM8960_write(PLL3, PLL3_PLLK_15_8(0xc2)); //PLL3 (0x36)
231 + i2c_WM8960_write(PLL4, PLL4_PLLK_7_0(0x26)); //PLL4 (0x37)
232 + }
233 + else
234 + {
235 + printk("Not support this srate\n");
236 + }
237 + mdelay(3);
238 +}
239 +
240 +
241 +void audiohw_set_frequency(int fsel, int pll_en)
242 +{
243 + MSG("audiohw_set_frequency_=0x%08X\n",fsel);
244 +
245 + if (pll_en)
246 + {
247 + printk("PLL enable\n");
248 + i2c_WM8960_write(CLOCKING1, (fsel<<3) | CLOCKING1_SYSCLKDIV_2 | CLOCKING1_CLKSEL_PLL); //CLOCKING (0x04)=>0x05
249 +
250 + }
251 + else
252 + {
253 + printk("PLL disable\n");
254 + i2c_WM8960_write(CLOCKING1, (fsel<<3));//| CLOCKING1_SYSCLKDIV_2); //CLOCKING (0x04)
255 + }
256 +
257 +}
258 +
259 +//FIXME
260 +int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r)
261 +{
262 + MSG("audiohw_set_lineout_vol_\n");
263 + switch(Aout)
264 + {
265 + case 1:
266 + //i2c_WM8960_write(LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(0x7f)); //LOUT1(0x02)
267 + //i2c_WM8960_write(ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(0x7f)); //ROUT1(0x03)
268 + i2c_WM8960_write(LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(vol_l)); //LOUT1(0x02)
269 + i2c_WM8960_write(ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(vol_r)); //ROUT1(0x03)
270 + break;
271 + case 2:
272 + i2c_WM8960_write(LSPK, LSPK_SPKLVU|LSPK_SPKLZC| LSPK_SPKLVOL(vol_l));
273 + i2c_WM8960_write(RSPK, RSPK_SPKRVU|RSPK_SPKRZC| RSPK_SPKRVOL(vol_r));
274 + break;
275 + default:
276 + break;
277 + }
278 + return 0;
279 +}
280 +
281 +//FIXME
282 +int audiohw_set_linein_vol(int vol_l, int vol_r)
283 +{
284 + MSG("audiohw_set_linein_vol_\n");
285 +
286 + i2c_WM8960_write(LINV, LINV_IPVU|LINV_LINVOL(vol_l)); //LINV(0x00)=>0x12b
287 + i2c_WM8960_write(RINV, RINV_IPVU|RINV_RINVOL(vol_r)); //LINV(0x01)=>0x12b
288 +
289 + return 0;
290 +}
291 +
292 +//Set signal path
293 +int audiohw_postinit(int bSlave, int AIn, int AOut, int pll_en, int wordLen24b)
294 +{
295 +
296 + int i;
297 + unsigned long data;
298 +
299 + if(wm_reg_data[RESET]!=0xFFFF)
300 + return 0;
301 +
302 + if(bSlave)
303 + {
304 + MSG("WM8960 slave.....\n");
305 + if(wordLen24b)
306 + {
307 + printk("24 bit word length\n");
308 + i2c_WM8960_write(AINTFCE1, AINTFCE1_WL_24 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
309 + }
310 + else
311 + {
312 + printk("16 bit word length\n");
313 + i2c_WM8960_write(AINTFCE1, AINTFCE1_WL_16 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
314 + }
315 + }
316 + else
317 + {
318 + MSG("WM8960 master.....\n");
319 + i2c_WM8960_write(CLOCKING2, 0x1c4);//CLOCKING2_BCLKDIV(0x1c4)); //CLOCKING2(0x08)
320 +
321 + if(wordLen24b)
322 + {
323 + printk("24 bit word length\n");
324 + i2c_WM8960_write(AINTFCE1, AINTFCE1_MS | AINTFCE1_WL_24 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
325 + }
326 + else
327 + {
328 + printk("16 bit word length\n");
329 + i2c_WM8960_write(AINTFCE1, AINTFCE1_MS | AINTFCE1_WL_16 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
330 + }
331 + mdelay(5);
332 + }
333 +
334 +
335 + //From app notes: allow Vref to stabilize to reduce clicks
336 + for(i = 0; i < 1000*HZ; i++);
337 +
338 + if(AIn > 0)
339 + {
340 + data = wm_reg_data[PWRMGMT1];
341 + i2c_WM8960_write(PWRMGMT1, data|PWRMGMT1_ADCL|PWRMGMT1_ADCR|PWRMGMT1_AINL |PWRMGMT1_AINR);//|PWRMGMT1_MICB);//PWRMGMT1(0x19)
342 +
343 + data = wm_reg_data[ADDITIONAL1];
344 + i2c_WM8960_write(ADDITIONAL1, data|ADDITIONAL1_DATSEL(0x01)); //ADDITIONAL1(0x17)
345 + i2c_WM8960_write(LADCVOL, LADCVOL_LAVU_EN|LADCVOL_LADCVOL(0xc3)); //LADCVOL(0x15)
346 + i2c_WM8960_write(RADCVOL, RADCVOL_RAVU_EN|RADCVOL_RADCVOL(0xc3)); //RADCVOL(0x16)
347 + i2c_WM8960_write(ADCLPATH, ADCLPATH_LMN1|ADCLPATH_LMIC2B);//|ADCLPATH_LMICBOOST_13DB); //ADCLPATH(0x20)=>(0x108)
348 + i2c_WM8960_write(ADCRPATH, ADCRPATH_RMN1|ADCRPATH_RMIC2B);//|ADCRPATH_RMICBOOST_13DB); //ADCRPATH(0x21)=>(0x108)
349 + i2c_WM8960_write(PWRMGMT3, PWRMGMT3_LMIC|PWRMGMT3_RMIC); //PWRMGMT3(0x2f)
350 +
351 + //i2c_WM8960_write(LINBMIX, 0x000); //LINBMIX(0x2B)
352 +
353 + if (AOut<=0)
354 + {
355 + i2c_WM8960_write(AINTFCE2, 0x40); //FIXME:(0x09)
356 +
357 + data = wm_reg_data[PWRMGMT2];
358 + if(pll_en)
359 + {
360 + i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_PLL_EN|PWRMGMT2_DACL|PWRMGMT2_DACR); //PWRMGMT2(0x1a)
361 + }
362 + else
363 + {
364 + i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_DACL|PWRMGMT2_DACR); //PWRMGMT2(0x1a)
365 +
366 + }
367 + }
368 + }
369 + if(AOut>0)
370 + {
371 + //Power management 2 setting
372 + data = wm_reg_data[PWRMGMT2];
373 +
374 + if(pll_en)
375 + {
376 + i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_PLL_EN|PWRMGMT2_DACL|PWRMGMT2_DACR|PWRMGMT2_LOUT1|PWRMGMT2_ROUT1|PWRMGMT2_SPKL|PWRMGMT2_SPKR); //PWRMGMT2(0x1a)
377 + }
378 + else
379 + {
380 + i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_DACL|PWRMGMT2_DACR|PWRMGMT2_LOUT1|PWRMGMT2_ROUT1|PWRMGMT2_SPKL|PWRMGMT2_SPKR); //PWRMGMT2(0x1a)
381 +
382 + }
383 +
384 + mdelay(10);
385 +
386 + i2c_WM8960_write(AINTFCE2, 0x40); //FIXME:(0x09)
387 +
388 + i2c_WM8960_write(LEFTGAIN, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff)); //LEFTGAIN(0x0a)
389 + i2c_WM8960_write(RIGHTGAIN, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff)); //RIGHTGAIN(0x0b)
390 +
391 + i2c_WM8960_write(LEFTMIX1, 0x100); //LEFTMIX1(0x22)
392 + i2c_WM8960_write(RIGHTMIX2, 0x100); //RIGHTMIX2(0x25)
393 +
394 + data = wm_reg_data[PWRMGMT3]; //FIXME
395 + i2c_WM8960_write(PWRMGMT3, data|PWRMGMT3_ROMIX|PWRMGMT3_LOMIX); //PWRMGMT3(0x2f)
396 +
397 + data = wm_reg_data[CLASSDCTRL1]; //CLASSDCTRL1(0x31) SPEAKER FIXME
398 + i2c_WM8960_write(CLASSDCTRL1, 0xf7);//data|CLASSDCTRL1_OP_LRSPK);
399 +
400 + data = wm_reg_data[CLASSDCTRL3]; //CLASSDCTRL3(0x33)
401 + i2c_WM8960_write(CLASSDCTRL3, 0xad);//data|(0x1b));
402 + }
403 +
404 + i2c_WM8960_write(DACCTRL1, 0x000); //DACCTRL1(0x05)
405 +
406 + data = wm_reg_data[PWRMGMT1];
407 + i2c_WM8960_write(PWRMGMT1, data|0x1c0); //FIXME:PWRMGMT1(0x19)
408 +
409 +
410 + printk("WM8960 All initial ok!\n");
411 +
412 + return 0;
413 +
414 +}
415 +
416 +void audiohw_micboost(int boostgain)
417 +{
418 + unsigned long data;
419 +
420 + data = wm_reg_data[ADCLPATH];
421 + i2c_WM8960_write(ADCLPATH, data|(boostgain << 4));
422 +
423 + data = wm_reg_data[ADCRPATH];
424 + i2c_WM8960_write(ADCRPATH, data|(boostgain << 4));
425 +}
426 +
427 +void audiohw_micin(int enableMic)
428 +{
429 + unsigned long data;
430 +
431 + if (enableMic==1)
432 + {
433 + data = wm_reg_data[PWRMGMT1];
434 + i2c_WM8960_write(PWRMGMT1, data|PWRMGMT1_MICB);
435 + }
436 +#if 1
437 + else
438 + {
439 + data = wm_reg_data[PWRMGMT1];
440 + i2c_WM8960_write(PWRMGMT1, data & (~(PWRMGMT1_MICB)));
441 + }
442 +#endif
443 +}
444 +
445 +void audiohw_mute( bool mute)
446 +{
447 + //Mute: Set DACMU = 1 to soft-mute the audio DACs.
448 + //Unmute: Set DACMU = 0 to soft-un-mute the audio DACs.
449 + i2c_WM8960_write(DACCTRL1, mute ? DACCTRL1_DACMU : 0);
450 +}
451 +
452 +
453 +//Nice shutdown of WM8960 codec
454 +void audiohw_close(void)
455 +{
456 + i2c_WM8960_write(DACCTRL1,DACCTRL1_DACMU); //0x05->0x08
457 + i2c_WM8960_write(PWRMGMT1, 0x000); //0x19->0x000
458 + mdelay(400);
459 + i2c_WM8960_write(PWRMGMT2, 0x000); //0x1a->0x000
460 +
461 +}
462 +
463 +void audiohw_loopback(int fsel)
464 +{
465 +}
466 +
467 +void audiohw_codec_exlbk(void)
468 +{
469 + memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
470 +
471 + i2c_WM8960_write(LINV, 0x117); //0x00->0x117
472 + i2c_WM8960_write(RINV, 0x117); //0x01->0x117
473 + i2c_WM8960_write(LOUT1, 0x179); //0x02->0x179
474 + i2c_WM8960_write(ROUT1, 0x179); //0x03->0x179
475 + i2c_WM8960_write(CLOCKING1, 0x00); //0x04->0x00
476 + //i2c_WM8960_write(CLOCKING1, 0x40); //0x04->0x00
477 + i2c_WM8960_write(DACCTRL1, 0x00); //0x05->0x00
478 + i2c_WM8960_write(AINTFCE2, 0x41); //0x09->0x41
479 + i2c_WM8960_write(LADCVOL, 0x1c3); //0x15->0x1c3
480 + i2c_WM8960_write(RADCVOL, 0x1c3); //0x16->0x1c3
481 + i2c_WM8960_write(PWRMGMT1, 0xfc); //0x19->0xfc
482 + i2c_WM8960_write(PWRMGMT2, 0x1e0); //0x1a->0x1e0
483 + i2c_WM8960_write(ADCLPATH, 0x108); //0x20->0x108
484 + i2c_WM8960_write(ADCRPATH, 0x108); //0x21->0x108
485 + i2c_WM8960_write(LEFTMIX1, 0x150); //0x22->0x150
486 + i2c_WM8960_write(RIGHTMIX2, 0x150); //0x25->0x150
487 + i2c_WM8960_write(BYPASS1, 0x00); //0x2d->0x00
488 + i2c_WM8960_write(BYPASS2, 0x00); //0x2e->0x00
489 + i2c_WM8960_write(PWRMGMT3, 0x3c); //0x2f->0x3c
490 +}
491 +
492 +void audiohw_bypass(void)
493 +{
494 + int i;
495 +
496 + memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
497 + i2c_WM8960_write(RESET, 0x000); //0x0f(R15)->0x000
498 +
499 + for(i = 0; i < 1000*HZ; i++);
500 +
501 + i2c_WM8960_write(PWRMGMT1, 0xf0); //0x19(R25)->0xf0
502 + i2c_WM8960_write(PWRMGMT2, 0x60); //0x1a(R26)->0x60
503 + i2c_WM8960_write(PWRMGMT3, 0x3c); //0x2f(R47)->0x3c
504 + i2c_WM8960_write(LINV, 0x117); // 0x00(R0)->0x117
505 + i2c_WM8960_write(RINV, 0x117); // 0x01(R1)->0x117
506 + i2c_WM8960_write(ADCLPATH, 0x108); //0x20(R32)->0x108
507 + i2c_WM8960_write(ADCRPATH, 0x108); //0x21(R33)->0x108
508 + i2c_WM8960_write(BYPASS1, 0x80); //0x2d(R45)->0x80
509 + i2c_WM8960_write(BYPASS2, 0x80); //0x2e(R46)->0x80
510 + i2c_WM8960_write(LOUT1, 0x179); // 0x02(R2)->0x179
511 + i2c_WM8960_write(ROUT1, 0x179); // 0x03(R3)->0x179
512 +}
513 +EXPORT_SYMBOL(audiohw_set_frequency);
514 +EXPORT_SYMBOL(audiohw_close);
515 +EXPORT_SYMBOL(audiohw_postinit);
516 +EXPORT_SYMBOL(audiohw_preinit);
517 +EXPORT_SYMBOL(audiohw_set_apll);
518 +EXPORT_SYMBOL(audiohw_codec_exlbk);
519 +EXPORT_SYMBOL(audiohw_bypass);
520 +EXPORT_SYMBOL(audiohw_set_lineout_vol);
521 +EXPORT_SYMBOL(audiohw_set_linein_vol);
522 +EXPORT_SYMBOL(audiohw_micin);
523 +EXPORT_SYMBOL(audiohw_mute);
524 +EXPORT_SYMBOL(audiohw_loopback);
525 +EXPORT_SYMBOL(audiohw_micboost);
526 +
527 +static int codec_wm8960_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
528 +{
529 + struct wm8960_data *wm;
530 +
531 +printk("*******Enter %s********\n", __func__);
532 +
533 + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
534 + return -EIO;
535 +
536 + wm = devm_kzalloc(&client->dev, sizeof(struct wm8960_data), GFP_KERNEL);
537 + if (!wm)
538 + return -ENOMEM;
539 +
540 +#if defined(CONFIG_ARCH_MT7623)
541 + mt_set_gpio_mode(GPIO242, GPIO_MODE_04);
542 + mt_set_gpio_mode(GPIO243, GPIO_MODE_04);
543 +#endif
544 + wm->client = client;
545 + wm->dev = &client->dev;
546 + wm->name = id->name;
547 + i2c_set_clientdata(client, wm);
548 + wmio = wm;
549 +
550 + memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
551 +
552 + return 0;
553 +}
554 +
555 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
556 +static int codec_wm8960_i2c_remove(struct i2c_client *client)
557 +#else
558 +static int __devexit codec_wm8960_i2c_remove(struct i2c_client *client)
559 +#endif
560 +{
561 + struct wm8960_data *wm = i2c_get_clientdata(client);
562 + kfree(wm);
563 +
564 + return 0;
565 +}
566 +
567 +static const struct i2c_device_id wm8960_id[] = {
568 + { "codec_wm8960", 0 },
569 + {}
570 +};
571 +
572 +static struct i2c_driver codec_wm8960_i2c_driver = {
573 + .driver = {
574 + .name = "codec_wm8960"
575 + },
576 + .probe = codec_wm8960_i2c_probe,
577 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
578 + .remove = codec_wm8960_i2c_remove,
579 +#else
580 + .remove = __devexit_p(codec_wm8960_i2c_remove),
581 +#endif
582 + .id_table = wm8960_id,
583 +};
584 +static int __init wm8960_i2c_init(void)
585 +{
586 +#if defined(CONFIG_ARCH_MT7623)
587 + i2c_register_board_info(1, &i2c_devs1, 1);
588 +#endif
589 + return i2c_add_driver(&codec_wm8960_i2c_driver);;
590 +}
591 +
592 +static void __exit wm8960_i2c_exit(void)
593 +{
594 + i2c_del_driver(&codec_wm8960_i2c_driver);
595 +}
596 +
597 +module_init(wm8960_i2c_init);
598 +module_exit(wm8960_i2c_exit);
599 +
600 +MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
601 +MODULE_DESCRIPTION("WM8960 I2C client driver");
602 +MODULE_LICENSE("GPL");
603 +
604 --- /dev/null
605 +++ b/sound/soc/mtk/i2c_wm8960.h
606 @@ -0,0 +1,288 @@
607 +/* wm8960.h -- WM8960 Soc Audio driver */
608 +#ifndef _WM8960_H
609 +#define _WM8960_H
610 +
611 +#define bool unsigned char
612 +#define false 0
613 +#define true 1
614 +
615 +/* volume/balance/treble/bass interdependency */
616 +#define VOLUME_MIN -730
617 +#define VOLUME_MAX 60
618 +
619 +
620 +/* Register addresses and bits */
621 +#define OUTPUT_MUTED 0x2f
622 +#define OUTPUT_0DB 0x79
623 +
624 +#define LINV 0x00
625 +#define LINV_IPVU (1 << 8) /* FIXME */
626 +#define LINV_LINMUTE (1 << 7)
627 +#define LINV_LIZC (1 << 6)
628 +#define LINV_LINVOL(x) ((x) & 0x3f)
629 +
630 +#define RINV 0x01
631 +#define RINV_IPVU (1 << 8) /* FIXME */
632 +#define RINV_RINMUTE (1 << 7)
633 +#define RINV_RIZC (1 << 6)
634 +#define RINV_RINVOL(x) ((x) & 0x3f)
635 +
636 +#define LOUT1 0x02
637 +#define LOUT1_LO1VU (1 << 8)
638 +#define LOUT1_LO1ZC (1 << 7)
639 +#define LOUT1_LOUT1VOL(x) ((x) & 0x7f)
640 +
641 +#define ROUT1 0x03
642 +#define ROUT1_RO1VU (1 << 8)
643 +#define ROUT1_RO1ZC (1 << 7)
644 +#define ROUT1_ROUT1VOL(x) ((x) & 0x7f)
645 +
646 +#define CLOCKING1 0x04 /* FIXME */
647 +#define CLOCKING1_ADCDIV(x) (((x) & 0x7) << 6)
648 +#define CLOCKING1_DACDIV(x) (((x) & 0x7) << 3)
649 +#define CLOCKING1_SYSCLKDIV_1 (0 << 1)
650 +#define CLOCKING1_SYSCLKDIV_2 (2 << 1)
651 +#define CLOCKING1_CLKSEL_MCLK (0 << 0)
652 +#define CLOCKING1_CLKSEL_PLL (1 << 0)
653 +
654 +#define DACCTRL1 0x05
655 +#define DACCTRL1_DATTENUATE (1 << 7)
656 +#define DACCTRL1_DACMU (1 << 3)
657 +#define DACCTRL1_DEEMPH_48 (3 << 1)
658 +#define DACCTRL1_DEEMPH_44 (2 << 1)
659 +#define DACCTRL1_DEEMPH_32 (1 << 1)
660 +#define DACCTRL1_DEEMPH_NONE (0 << 1)
661 +#define DACCTRL1_DEEMPH(x) ((x) & (0x3 << 1))
662 +
663 +#define DACCTRL2 0x06
664 +
665 +#define AINTFCE1 0x07
666 +#define AINTFCE1_BCLKINV (1 << 7)
667 +#define AINTFCE1_MS (1 << 6)
668 +#define AINTFCE1_LRSWAP (1 << 5)
669 +#define AINTFCE1_LRP (1 << 4)
670 +#define AINTFCE1_WL_32 (3 << 2)
671 +#define AINTFCE1_WL_24 (2 << 2)
672 +#define AINTFCE1_WL_20 (1 << 2)
673 +#define AINTFCE1_WL_16 (0 << 2)
674 +#define AINTFCE1_WL(x) (((x) & 0x3) << 2)
675 +#define AINTFCE1_FORMAT_DSP (3 << 0)
676 +#define AINTFCE1_FORMAT_I2S (2 << 0)
677 +#define AINTFCE1_FORMAT_LJUST (1 << 0)
678 +#define AINTFCE1_FORMAT_RJUST (0 << 0)
679 +#define AINTFCE1_FORMAT(x) ((x) & 0x3)
680 +
681 +/* FIXME */
682 +#define CLOCKING2 0x08
683 +#define CLOCKING2_DCLKDIV(x) (((x) & 0x7) << 6)
684 +#define CLOCKING2_BCLKDIV(x) (((x) & 0xf) << 0)
685 +
686 +#define AINTFCE2 0x09
687 +#define AINTFCE2_ALRCGPIO_ALRC (0 << 6)
688 +#define AINTFCE2_ALRCGPIO_GPIO (1 << 6)
689 +#define AINTFCE2_LOOPBACK (1 << 0)
690 +
691 +#define LEFTGAIN 0x0a
692 +#define LEFTGAIN_LDVU (1 << 8)
693 +#define LEFTGAIN_LDACVOL(x) ((x) & 0xff)
694 +
695 +#define RIGHTGAIN 0x0b
696 +#define RIGHTGAIN_RDVU (1 << 8)
697 +#define RIGHTGAIN_RDACVOL(x) ((x) & 0xff)
698 +
699 +#define RESET 0x0f
700 +#define RESET_RESET 0x000
701 +
702 +#define ALC1 0x11
703 +#define ALC1_ALCOFF (0x0 << 7)
704 +#define ALC1_ALCRONLY (0x1 << 7)
705 +#define ALC1_ALCLONLY (0x2 << 7)
706 +#define ALC1_ALCSTEREO (0x3 << 7)
707 +#define ALC1_ALCSEL(x) (((x) & 0x3) << 7)
708 +#define ALC1_SET_MAXGAIN(x) ((x & 0x7) << 4)
709 +#define ALC1_GET_MAXGAIN(x) ((x) & (0x7 << 4))
710 +#define ALC1_ALCL(x) ((x) & 0x0f)
711 +
712 +#define ALC2 0x12
713 +#define ALC2_MINGAIN(x) ((x & 0x7) << 4)
714 +#define ALC2_HLD(x) ((x) & 0x0f)
715 +
716 +#define ALC3 0x13
717 +#define ALC3_SET_DCY(x) ((x & 0x0f) << 4)
718 +#define ALC3_GET_DCY(x) ((x) & (0x0f << 4))
719 +#define ALC3_ATK(x) ((x) & 0x0f)
720 +
721 +#define NOISEGATE 0x14
722 +#define NOISEGATE_SET_NGTH(x) ((x & 0x1f) << 3)
723 +#define NOISEGATE_GET_NGTH(x) ((x) & (0x1f << 3))
724 +#define NOISEGATE_NGAT_ENABLE 1
725 +
726 +#define LADCVOL 0x15
727 +#define LADCVOL_LAVU_EN (1 << 8)
728 +#define LADCVOL_LADCVOL(x) ((x) & 0x0ff)
729 +
730 +#define RADCVOL 0x16
731 +#define RADCVOL_RAVU_EN (1 << 8)
732 +#define RADCVOL_RADCVOL(x) ((x) & 0x0ff)
733 +
734 +#define ADDITIONAL1 0x17
735 +#define ADDITIONAL1_TSDEN (1 << 8)
736 +#define ADDITIONAL1_VSEL_LOWEST (0 << 6)
737 +#define ADDITIONAL1_VSEL_LOW (1 << 6)
738 +#define ADDITIONAL1_VSEL_DEFAULT2 (2 << 6)
739 +#define ADDITIONAL1_VSEL_DEFAULT (3 << 6)
740 +#define ADDITIONAL1_VSEL(x) (((x) & 0x3) << 6)
741 +#define ADDITIONAL1_DMONOMIX_STEREO (0 << 4)
742 +#define ADDITIONAL1_DMONOMIX_MONO (1 << 4)
743 +#define ADDITIONAL1_DATSEL(x) (((x) & 0x3) << 2)
744 +#define ADDITIONAL1_TOCLKSEL (1 << 1)
745 +#define ADDITIONAL1_TOEN (1 << 0)
746 +
747 +#define ADDITIONAL2 0x18
748 +#define ADDITIONAL2_HPSWEN (1 << 6)
749 +#define ADDITIONAL2_HPSWPOL (1 << 5)
750 +#define ADDITIONAL2_TRIS (1 << 3)
751 +#define ADDITIONAL2_LRCM_ON (1 << 2)
752 +
753 +#define PWRMGMT1 0x19
754 +#define PWRMGMT1_VMIDSEL_DISABLED (0 << 7)
755 +#define PWRMGMT1_VMIDSEL_50K (1 << 7)
756 +#define PWRMGMT1_VMIDSEL_250K (2 << 7)
757 +#define PWRMGMT1_VMIDSEL_5K (3 << 7)
758 +#define PWRMGMT1_VREF (1 << 6)
759 +#define PWRMGMT1_AINL (1 << 5)
760 +#define PWRMGMT1_AINR (1 << 4)
761 +#define PWRMGMT1_ADCL (1 << 3)
762 +#define PWRMGMT1_ADCR (1 << 2)
763 +#define PWRMGMT1_MICB (1 << 1)
764 +#define PWRMGMT1_DIGENB (1 << 0)
765 +
766 +#define PWRMGMT2 0x1a
767 +#define PWRMGMT2_DACL (1 << 8)
768 +#define PWRMGMT2_DACR (1 << 7)
769 +#define PWRMGMT2_LOUT1 (1 << 6)
770 +#define PWRMGMT2_ROUT1 (1 << 5)
771 +#define PWRMGMT2_SPKL (1 << 4)
772 +#define PWRMGMT2_SPKR (1 << 3)
773 +#define PWRMGMT2_OUT3 (1 << 1)
774 +#define PWRMGMT2_PLL_EN (1 << 0)
775 +
776 +#define ADDITIONAL3 0x1b
777 +#define ADDITIONAL3_VROI (1 << 6)
778 +#define ADDITIONAL3_OUT3CAP (1 << 3)
779 +#define ADDITIONAL3_ADC_ALC_SR(x) ((x) & 0x7)
780 +
781 +#define ANTIPOP1 0x1c
782 +#define ANTIPOP2 0x1d
783 +
784 +#define ADCLPATH 0x20
785 +#define ADCLPATH_LMN1 (1 << 8)
786 +#define ADCLPATH_LMP3 (1 << 7)
787 +#define ADCLPATH_LMP2 (1 << 6)
788 +#define ADCLPATH_LMICBOOST_29DB (0x3 << 4)
789 +#define ADCLPATH_LMICBOOST_20DB (0x2 << 4)
790 +#define ADCLPATH_LMICBOOST_13DB (0x1 << 4)
791 +#define ADCLPATH_SET_LMICBOOST(x) ((x & 0x3) << 4)
792 +#define ADCLPATH_LMIC2B (1 << 3)
793 +
794 +
795 +#define ADCRPATH 0x21
796 +#define ADCRPATH_RMN1 (1 << 8)
797 +#define ADCRPATH_RMP3 (1 << 7)
798 +#define ADCRPATH_RMP2 (1 << 6)
799 +#define ADCRPATH_RMICBOOST_29DB (0x3 << 4)
800 +#define ADCRPATH_RMICBOOST_20DB (0x2 << 4)
801 +#define ADCRPATH_RMICBOOST_13DB (0x1 << 4)
802 +#define ADCRPATH_SET_RMICBOOST(x) ((x & 0x3) << 4)
803 +#define ADCRPATH_RMIC2B (1 << 3)
804 +
805 +
806 +#define LEFTMIX1 0x22
807 +#define LEFTMIX1_LD2LO (1 << 8)
808 +#define LEFTMIX1_LI2LO (1 << 7)
809 +#define LEFTMIX1_LI2LO_DEFAULT (5 << 4)
810 +#define LEFTMIX1_LI2LOVOL(x) (((x) & 0x7) << 4)
811 +
812 +#define RIGHTMIX2 0x25
813 +#define RIGHTMIX2_RD2RO (1 << 8)
814 +#define RIGHTMIX2_RI2RO (1 << 7)
815 +#define RIGHTMIX2_RI2RO_DEFAULT (5 << 4)
816 +#define RIGHTMIX2_RI2ROVOL(x) (((x) & 0x7) << 4)
817 +
818 +#define MONOMIX1 0x26
819 +#define MONOMIX1_L2MO (1 << 7)
820 +
821 +#define MONOMIX2 0x27
822 +#define MONOMIX2_R2MO (1 << 7)
823 +
824 +#define LSPK 0x28
825 +#define LSPK_SPKLVU (1 << 8)
826 +#define LSPK_SPKLZC (1 << 7)
827 +#define LSPK_SPKLVOL(x) ((x) & 0x7f)
828 +
829 +#define RSPK 0x29
830 +#define RSPK_SPKRVU (1 << 8)
831 +#define RSPK_SPKRZC (1 << 7)
832 +#define RSPK_SPKRVOL(x) ((x) & 0x7f)
833 +
834 +#define OUT3V 0x2a
835 +#define LINBMIX 0x2b
836 +#define RINBMIX 0x2c
837 +#define BYPASS1 0x2d
838 +#define BYPASS2 0x2e
839 +
840 +#define PWRMGMT3 0x2f
841 +#define PWRMGMT3_LMIC (1<<5)
842 +#define PWRMGMT3_RMIC (1<<4)
843 +#define PWRMGMT3_LOMIX (1<<3)
844 +#define PWRMGMT3_ROMIX (1<<2)
845 +
846 +#define ADDITIONAL4 0x30
847 +
848 +#define CLASSDCTRL1 0x31
849 +#define CLASSDCTRL1_OP_OFF (0<<6)
850 +#define CLASSDCTRL1_OP_LSPK (1<<6)
851 +#define CLASSDCTRL1_OP_RSPK (2<<6)
852 +#define CLASSDCTRL1_OP_LRSPK (3<<6)
853 +
854 +#define CLASSDCTRL3 0x33
855 +
856 +#define PLL1 0x34
857 +#define PLL1_OPCLKDIV_1 (0<<6)
858 +#define PLL1_OPCLKDIV_2 (1<<6)
859 +#define PLL1_OPCLKDIV_3 (2<<6)
860 +#define PLL1_OPCLKDIV_4 (3<<6)
861 +#define PLL1_OPCLKDIV_5p5 (4<<6)
862 +#define PLL1_OPCLKDIV_6 (5<<6)
863 +#define PLL1_SDM_INTERGER (0<<5)
864 +#define PLL1_SDM_FRACTIONAL (1<<5)
865 +#define PLL1_PLLPRESCALE_1 (0<<4)
866 +#define PLL1_PLLPRESCALE_2 (1<<4)
867 +#define PLL1_PLLN(x) ((x) & 0xf)
868 +
869 +#define PLL2 0x35
870 +#define PLL2_PLLK_23_16(x) ((x) & 0x1ff)
871 +
872 +#define PLL3 0x36
873 +#define PLL3_PLLK_15_8(x) ((x) & 0x1ff)
874 +
875 +#define PLL4 0x37
876 +#define PLL4_PLLK_7_0(x) ((x) & 0x1ff)
877 +
878 +/* codec API */
879 +void audiohw_preinit(void);
880 +int audiohw_postinit(int bSlave, int AIn, int AOut, int pll_en, int wordLen24b);
881 +void audiohw_close(void);
882 +void audiohw_set_frequency(int fsel, int pll_en);
883 +void audiohw_mute(bool mute);
884 +void audiohw_micboost(int boostgain);
885 +void audiohw_micin(int enableMic);
886 +void audiohw_set_apll(int srate);
887 +int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
888 +int audiohw_set_linein_vol(int vol_l, int vol_r);
889 +void audiohw_mute( bool mute);
890 +void audiohw_loopback(int fsel);
891 +void audiohw_codec_exlbk(void);
892 +void audiohw_bypass(void);
893 +
894 +#endif /* _WM875x_H */
895 --- /dev/null
896 +++ b/sound/soc/mtk/i2s_ctrl.c
897 @@ -0,0 +1,3524 @@
898 +#include <linux/init.h>
899 +#include <linux/version.h>
900 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
901 +#include <linux/sched.h>
902 +#endif
903 +#include <linux/module.h>
904 +#include <linux/kernel.h> /* _printk() */
905 +#include <linux/slab.h> /* kmalloc() */
906 +#include <linux/fs.h> /* everything... */
907 +#include <linux/errno.h> /* error codes */
908 +#include <linux/types.h> /* size_t */
909 +#include <linux/proc_fs.h>
910 +#include <linux/fcntl.h> /* O_ACCMODE */
911 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14)
912 +#include <asm/system.h> /* cli(), *_flags */
913 +#endif
914 +#include <asm/uaccess.h> /* copy_from/to_user */
915 +#include <linux/interrupt.h>
916 +#include <linux/mm.h>
917 +#include <linux/mm_types.h>
918 +#include <linux/pci.h>
919 +#include <linux/delay.h>
920 +#include "ralink_gdma.h"
921 +#if defined(CONFIG_I2S_WITH_AEC)
922 +#include "../aec/aec_api.h"
923 +#endif
924 +
925 +#ifdef CONFIG_DEVFS_FS
926 +#include <linux/devfs_fs_kernel.h>
927 +static devfs_handle_t devfs_handle;
928 +#endif
929 +
930 +#include "i2s_ctrl.h"
931 +
932 +#if defined(CONFIG_SND_MT76XX_SOC)
933 +#include <sound/soc/mtk/mt76xx_machine.h>
934 +#endif
935 +
936 +#if defined(CONFIG_I2S_WM8750)
937 +#include "../codec/i2c_wm8750.h"
938 +#endif
939 +#if defined(CONFIG_I2S_WM8751)
940 +#include "../codec/i2c_wm8751.h"
941 +#endif
942 +#if defined(CONFIG_I2S_WM8960)
943 +#include "i2c_wm8960.h"
944 +#endif
945 +
946 +static int i2sdrv_major = 191;
947 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
948 +#else
949 +static struct class *i2smodule_class;
950 +#endif
951 +
952 +static int _printk(char *fmt, ...)
953 +{
954 + return 0;
955 +}
956 +
957 +/* external functions declarations */
958 +#if defined(CONFIG_I2S_WM8960)
959 +extern void audiohw_set_frequency(int fsel, int codec_pll_en);
960 +void audiohw_set_apll(int srate);
961 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
962 +extern void audiohw_set_frequency(int fsel);
963 +#endif
964 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
965 +extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
966 +extern int audiohw_set_master_vol(int vol_l, int vol_r);
967 +extern int audiohw_set_linein_vol(int vol_l, int vol_r);
968 +#endif
969 +
970 +extern void audiohw_micboost(int boostgain);
971 +
972 +extern int GdmaI2sTx(uint32_t Src, uint32_t Dst, uint8_t TxNo, uint16_t TransCount,
973 + void (*DoneIntCallback)(uint32_t data),
974 + void (*UnMaskIntCallback)(uint32_t data));
975 +
976 +extern int GdmaI2sRx(uint32_t Src, uint32_t Dst, uint8_t RxNo, uint16_t TransCount,
977 + void (*DoneIntCallback)(uint32_t data),
978 + void (*UnMaskIntCallback)(uint32_t data));
979 +
980 +extern int GdmaMaskChannel(uint32_t ChNum);
981 +
982 +extern int GdmaUnMaskChannel(uint32_t ChNum);
983 +
984 +/* internal functions declarations */
985 +irqreturn_t i2s_irq_isr(int irq, void *irqaction);
986 +int i2s_debug_cmd(unsigned int cmd, unsigned long arg);
987 +
988 +/* forward declarations for _fops */
989 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
990 +static long i2s_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
991 +#else
992 +static int i2s_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
993 +#endif
994 +static int i2s_mmap(struct file *file, struct vm_area_struct *vma);
995 +static int i2s_open(struct inode *inode, struct file *file);
996 +static int i2s_release(struct inode *inode, struct file *file);
997 +int i2s_mmap_alloc(unsigned long size);
998 +int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size);
999 +
1000 +/* global varable definitions */
1001 +i2s_config_type i2s_config;
1002 +i2s_status_type i2s_status;
1003 +i2s_config_type* pi2s_config = &i2s_config;;
1004 +i2s_status_type* pi2s_status = &i2s_status;;
1005 +
1006 +static inline long
1007 +ugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout)
1008 +{
1009 + unsigned long flags;
1010 + wait_queue_t wait;
1011 +
1012 + init_waitqueue_entry(&wait, current);
1013 +
1014 + __set_current_state(TASK_INTERRUPTIBLE);
1015 + spin_lock_irqsave(&q->lock, flags);
1016 + __add_wait_queue(q, &wait);
1017 + spin_unlock(&q->lock);
1018 +
1019 + timeout = schedule_timeout(timeout);
1020 +
1021 + spin_lock_irq(&q->lock);
1022 + __remove_wait_queue(q, &wait);
1023 + spin_unlock_irqrestore(&q->lock, flags);
1024 +
1025 + return timeout;
1026 +}
1027 +
1028 +#define interruptible_sleep_on(x) \
1029 + ugly_hack_sleep_on_timeout(x, MAX_SCHEDULE_TIMEOUT);
1030 +
1031 +
1032 +#if defined(ARM_ARCH)
1033 +static dma_addr_t i2s_txdma_addr0, i2s_txdma_addr1;
1034 +static dma_addr_t i2s_rxdma_addr0, i2s_rxdma_addr1;
1035 +#define I2S_TX_FIFO_WREG_PHY (I2S_TX_FIFO_WREG & 0x1FFFFFFF)
1036 +#define I2S_RX_FIFO_RREG_PHY (I2S_RX_FIFO_RREG & 0x1FFFFFFF)
1037 +#else
1038 +static dma_addr_t i2s_txdma_addr, i2s_rxdma_addr;
1039 +#endif
1040 +static dma_addr_t i2s_mmap_addr[MAX_I2S_PAGE*2];
1041 + /* 8khz 11.025khz 12khz 16khz 22.05khz 24Khz 32khz 44.1khz 48khz 88.2khz 96khz*/
1042 +unsigned long i2s_inclk_15p625Mhz[11] = {60<<8, 43<<8, 40<<8, 30<<8, 21<<8, 19<<8, 14<<8, 10<<8, 9<<8, 7<<8, 4<<8};
1043 +unsigned long i2s_exclk_12p288Mhz[11] = {47<<8, 34<<8, 31<<8, 23<<8, 16<<8, 15<<8, 11<<8, 8<<8, 7<<8, 5<<8, 3<<8};
1044 +unsigned long i2s_exclk_12Mhz[11] = {46<<8, 33<<8, 30<<8, 22<<8, 16<<8, 15<<8, 11<<8, 8<<8, 7<<8, 5<<8, 3<<8};
1045 +#if defined(CONFIG_I2S_WM8750) || defined(CONFIG_SND_SOC_WM8750)
1046 + /* 8k 11.025k 12k 16k 22.05k 24k 32k 44.1k 48k 88.2k 96k*/
1047 +unsigned long i2s_codec_12p288Mhz[11] = {0x0C, 0x00, 0x10, 0x14, 0x38, 0x38, 0x18, 0x20, 0x00, 0x00, 0x1C};
1048 +unsigned long i2s_codec_12Mhz[11] = {0x0C, 0x32, 0x10, 0x14, 0x37, 0x38, 0x18, 0x22, 0x00, 0x3E, 0x1C};
1049 +unsigned long i2s_codec_24p576Mhz[11] = {0x4C, 0x00, 0x50, 0x54, 0x00, 0x78, 0x58, 0x00, 0x40, 0x00, 0x5C};
1050 +unsigned long i2s_codec_18p432Mhz[11] = {0x0e, 0x32, 0x12, 0x16, 0x36, 0x3a, 0x1a, 0x22, 0x02, 0x3e, 0x1e};
1051 +#endif
1052 +#if defined(CONFIG_I2S_WM8751) || defined(CONFIG_SND_SOC_WM8751)
1053 +unsigned long i2s_codec_12p288Mhz[11] = {0x04, 0x00, 0x10, 0x14, 0x38, 0x38, 0x18, 0x20, 0x00, 0x00, 0x1C};
1054 +unsigned long i2s_codec_12Mhz[11] = {0x04, 0x32, 0x10, 0x14, 0x37, 0x38, 0x18, 0x22, 0x00, 0x3E, 0x1C};
1055 +#endif
1056 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_SND_SOC_WM8960)
1057 +unsigned long i2s_codec_12p288Mhz[11] = {0x36, 0x24, 0x24, 0x1b, 0x12, 0x12, 0x09, 0x00, 0x00, 0x00, 0x00};
1058 +unsigned long i2s_codec_12Mhz[11] = {0x36, 0x24, 0x24, 0x1b, 0x12, 0x12, 0x09, 0x00, 0x00, 0x00, 0x00};
1059 +#endif
1060 +EXPORT_SYMBOL(i2s_codec_12p288Mhz);
1061 +EXPORT_SYMBOL(i2s_codec_12Mhz);
1062 +
1063 +#if defined(CONFIG_RALINK_RT6855A)
1064 + /* 8K 11.025k 12k 16k 22.05k 24k 32k 44.1K 48k 88.2k 96k */
1065 +unsigned long i2s_inclk_int[11] = { 97, 70, 65, 48, 35, 32, 24, 17, 16, 12, 8};
1066 +unsigned long i2s_inclk_comp[11] = { 336, 441, 53, 424, 220, 282, 212, 366, 141, 185, 70};
1067 +#elif defined (CONFIG_RALINK_MT7621)
1068 +#ifdef MT7621_ASIC_BOARD
1069 +#if defined (CONFIG_I2S_MCLK_12P288MHZ)
1070 +unsigned long i2s_inclk_int[11] = { 576, 384, 0, 288, 192, 192, 144, 96, 96, 48, 48};
1071 +unsigned long i2s_inclk_comp[11] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1072 +#elif defined(CONFIG_I2S_MCLK_12MHZ)
1073 +unsigned long i2s_inclk_int[11] = {1171, 850, 0, 585, 425, 390, 292, 212, 195, 106, 97};
1074 +unsigned long i2s_inclk_comp[11] = { 448, 174, 0, 480, 87, 320, 496, 299, 160, 149, 336};
1075 +#endif
1076 +#else //MT7621_FPGA_BOARD
1077 +unsigned long i2s_inclk_int[11] = { 529, 384, 0, 264, 192, 176, 132, 96, 88, 48, 44};
1078 +unsigned long i2s_inclk_comp[11] = { 102, 0, 0, 307, 0, 204, 153, 0, 102, 0, 51};
1079 +#endif
1080 +#elif defined (CONFIG_RALINK_MT7628)
1081 +#ifdef MT7628_ASIC_BOARD
1082 + /* 8K 11.025k 12k 16k 22.05k 24k 32k 44.1K 48k 88.2k 96k 176k 192k */
1083 +unsigned long i2s_inclk_int_16bit[13] = {937, 680, 0, 468, 340, 312, 234, 170, 156, 85, 78, 42, 39};
1084 +unsigned long i2s_inclk_comp_16bit[13]= {256, 139, 0, 384, 69, 256, 192, 34, 128, 17, 64, 267, 32};
1085 +unsigned long i2s_inclk_int_24bit[13] = {625, 404, 0, 312, 226, 208, 156, 113, 104, 56, 52, 28, 26};
1086 +unsigned long i2s_inclk_comp_24bit[13]= { 0, 404, 0, 256, 387, 170, 128, 193, 85, 352, 42, 176, 21};
1087 +#else
1088 + /* 8K 11.025k 12k 16k 22.05k 24k 32k 44.1K 48k 88.2k 96k 176k 192k */
1089 +unsigned long i2s_inclk_int_16bit[13] = {468, 340, 0, 234, 170, 156, 117, 85, 78, 42, 39, 21, 19};
1090 +unsigned long i2s_inclk_comp_16bit[13]= {384, 69, 0, 192, 34, 128, 96, 17, 64, 264, 32, 133, 272};
1091 +unsigned long i2s_inclk_int_24bit[13] = {312, 202, 0, 156, 113, 104, 78, 56, 52, 28, 26, 14, 13};
1092 +unsigned long i2s_inclk_comp_24bit[13]= {256, 202, 0, 128, 193, 85, 64, 352, 42, 176, 21, 88, 10};
1093 +#endif
1094 +#elif defined (CONFIG_ARCH_MT7623)
1095 +#if defined MT7623_ASIC_BOARD
1096 + /* 8K 11.025k 12k 16k 22.05k 24k 32k 44.1K 48k 88.2k 96k 176k 192k */
1097 +unsigned long i2s_inclk_int_16bit[13] = {576, 384, 0, 288, 192, 192, 144, 96, 96, 48, 48, 24, 24};
1098 +unsigned long i2s_inclk_comp_16bit[13]= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1099 +unsigned long i2s_inclk_int_24bit[13] = {384, 256, 0, 192, 128, 128, 96, 64, 64, 32, 32, 16, 16};
1100 +unsigned long i2s_inclk_comp_24bit[13]= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1101 +#else
1102 + /* 8K 11.025k 12k 16k 22.05k 24k 32k 44.1K 48k 88.2k 96k 176k 192k */
1103 +unsigned long i2s_inclk_int_16bit[13] = {72, 48, 0, 36, 24, 24, 18, 12, 12, 6, 6, 3, 3};
1104 +unsigned long i2s_inclk_comp_16bit[13]= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1105 +unsigned long i2s_inclk_int_24bit[13] = {48, 32, 0, 24, 16, 16, 12, 8, 8, 4, 4, 2, 2};
1106 +unsigned long i2s_inclk_comp_24bit[13]= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1107 +#endif
1108 +#else
1109 + /* 8K 11.025k 12k 16k 22.05k 24k 32k 44.1K 48k 88.2k 96k */
1110 +unsigned long i2s_inclk_int[11] = { 78, 56, 52, 39, 28, 26, 19, 14, 13, 9, 6};
1111 +unsigned long i2s_inclk_comp[11] = { 64, 352, 42, 32, 176, 21, 272, 88, 10, 455, 261};
1112 +#endif
1113 +
1114 +#if defined(CONFIG_I2S_WITH_AEC)
1115 +aecFuncTbl_t *aecFuncP;
1116 +#endif
1117 +/* USB mode 22.05Khz register value in datasheet is 0x36 but will cause slow clock, 0x37 is correct value */
1118 +/* USB mode 44.1Khz register value in datasheet is 0x22 but will cause slow clock, 0x23 is correct value */
1119 +
1120 +struct tasklet_struct i2s_tx_tasklet;
1121 +struct tasklet_struct i2s_rx_tasklet;
1122 +EXPORT_SYMBOL(i2s_tx_tasklet);
1123 +EXPORT_SYMBOL(i2s_rx_tasklet);
1124 +
1125 +char test_buf[I2S_PAGE_SIZE];
1126 +char test_buf_1[I2S_PAGE_SIZE];
1127 +char test_buf_2[I2S_PAGE_SIZE];
1128 +
1129 +static const struct file_operations i2s_fops = {
1130 + owner : THIS_MODULE,
1131 + mmap : i2s_mmap,
1132 + open : i2s_open,
1133 + release : i2s_release,
1134 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1135 + unlocked_ioctl: i2s_ioctl,
1136 +#else
1137 + ioctl : i2s_ioctl,
1138 +#endif
1139 +};
1140 +
1141 +int __init i2s_mod_init(void)
1142 +{
1143 + int result;
1144 +
1145 + _printk("******* i2s module init **********\n");
1146 + /* register device with kernel */
1147 +#ifdef CONFIG_DEVFS_FS
1148 + if(devfs_register_chrdev(i2sdrv_major, I2SDRV_DEVNAME , &i2s_fops)) {
1149 + _printk(KERN_WARNING " i2s: can't create device node - %s\n", I2SDRV_DEVNAME);
1150 + return -EIO;
1151 + }
1152 +
1153 + devfs_handle = devfs_register(NULL, I2SDRV_DEVNAME, DEVFS_FL_DEFAULT, i2sdrv_major, 0,
1154 + S_IFCHR | S_IRUGO | S_IWUGO, &i2s_fops, NULL);
1155 +#else
1156 + result = register_chrdev(i2sdrv_major, I2SDRV_DEVNAME, &i2s_fops);
1157 + if (result < 0) {
1158 + _printk(KERN_WARNING "i2s: can't get major %d\n",i2sdrv_major);
1159 + return result;
1160 + }
1161 +
1162 + if (i2sdrv_major == 0) {
1163 + i2sdrv_major = result; /* dynamic */
1164 + }
1165 +#endif
1166 +
1167 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1168 +#else
1169 + i2smodule_class=class_create(THIS_MODULE, I2SDRV_DEVNAME);
1170 + if (IS_ERR(i2smodule_class))
1171 + return -EFAULT;
1172 + device_create(i2smodule_class, NULL, MKDEV(i2sdrv_major, 0), I2SDRV_DEVNAME);
1173 +#endif
1174 +
1175 +#if defined(CONFIG_I2S_WITH_AEC)
1176 + _printk("AEC FuncP init \n");
1177 + /*Add by mtk04880*/
1178 + aecFuncP = kmalloc(sizeof(aecFuncTbl_t), GFP_KERNEL);
1179 + /*If aecFuncP cannot request memory,it will be ignored in I2S module. Since AEC & I2S are independent
1180 + * when AEC module is inserted,It will return err message (but I2S will keep running without AEC support)
1181 + * */
1182 + if(aecFuncP){
1183 + memset(aecFuncP,0,sizeof(aecFuncTbl_t));
1184 + }
1185 +#endif
1186 +
1187 + return 0;
1188 +}
1189 +
1190 +void i2s_mod_exit(void)
1191 +{
1192 + _printk("************ i2s module exit *************\n");
1193 +#ifdef CONFIG_DEVFS_FS
1194 + devfs_unregister_chrdev(i2sdrv_major, I2SDRV_DEVNAME);
1195 + devfs_unregister(devfs_handle);
1196 +#else
1197 + unregister_chrdev(i2sdrv_major, I2SDRV_DEVNAME);
1198 +#endif
1199 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1200 +#else
1201 + device_destroy(i2smodule_class,MKDEV(i2sdrv_major, 0));
1202 + class_destroy(i2smodule_class);
1203 +#endif
1204 + return ;
1205 +}
1206 +
1207 +
1208 +int i2s_open(struct inode *inode, struct file *filp)
1209 +{
1210 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1211 + int Ret;
1212 +#endif
1213 + int minor = iminor(inode);
1214 +
1215 + if (minor >= I2S_MAX_DEV)
1216 + return -ENODEV;
1217 +
1218 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1219 + MOD_INC_USE_COUNT;
1220 +#else
1221 + try_module_get(THIS_MODULE);
1222 +#endif
1223 +
1224 + if (filp->f_flags & O_NONBLOCK) {
1225 + MSG("filep->f_flags O_NONBLOCK set\n");
1226 + return -EAGAIN;
1227 + }
1228 +
1229 + /* set i2s_config */
1230 + filp->private_data = pi2s_config;
1231 + memset(pi2s_config, 0, sizeof(i2s_config_type));
1232 +#ifdef I2S_STATISTIC
1233 + memset(pi2s_status, 0, sizeof(i2s_status_type));
1234 +#endif
1235 + i2s_param_init(pi2s_config);
1236 +
1237 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1238 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1239 + Ret = request_irq(SURFBOARDINT_I2S, i2s_irq_isr, IRQF_DISABLED, "Ralink_I2S", NULL);
1240 +#else
1241 + Ret = request_irq(SURFBOARDINT_I2S, i2s_irq_isr, SA_INTERRUPT, "Ralink_I2S", NULL);
1242 +#endif
1243 +
1244 + if(Ret){
1245 + MSG("IRQ %d is not free.\n", SURFBOARDINT_I2S);
1246 + i2s_release(inode, filp);
1247 + return -1;
1248 + }
1249 +#endif
1250 +
1251 + init_waitqueue_head(&(pi2s_config->i2s_tx_qh));
1252 + init_waitqueue_head(&(pi2s_config->i2s_rx_qh));
1253 + spin_lock_init(&pi2s_config->lock);
1254 +
1255 + return 0;
1256 +}
1257 +
1258 +
1259 +static int i2s_release(struct inode *inode, struct file *filp)
1260 +{
1261 + i2s_config_type* ptri2s_config;
1262 +
1263 + /* decrement usage count */
1264 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1265 + MOD_DEC_USE_COUNT;
1266 +#else
1267 + module_put(THIS_MODULE);
1268 +#endif
1269 +
1270 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1271 + free_irq(SURFBOARDINT_I2S, NULL);
1272 +#endif
1273 +
1274 + ptri2s_config = filp->private_data;
1275 + if(ptri2s_config==NULL)
1276 + goto EXIT;
1277 +#ifdef CONFIG_I2S_MMAP
1278 + i2s_mem_unmap(ptri2s_config);
1279 +#else
1280 + i2s_txbuf_free(ptri2s_config);
1281 + i2s_rxbuf_free(ptri2s_config);
1282 +#endif
1283 + /* free buffer */
1284 + i2s_txPagebuf_free(ptri2s_config);
1285 + i2s_rxPagebuf_free(ptri2s_config);
1286 +EXIT:
1287 + MSG("i2s_release succeeds\n");
1288 + return 0;
1289 +}
1290 +
1291 +int i2s_mmap_alloc(unsigned long size)
1292 +{
1293 + int i;
1294 + u32 page_size;
1295 + int first_index;
1296 +
1297 + page_size = I2S_PAGE_SIZE;
1298 +
1299 + if ((pi2s_config->mmap_index == 0) || (pi2s_config->mmap_index == MAX_I2S_PAGE))
1300 + {
1301 + MSG("mmap_index=%d\n", pi2s_config->mmap_index);
1302 +
1303 + first_index = pi2s_config->mmap_index;
1304 + pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] = kmalloc(size, GFP_DMA);
1305 + i2s_mmap_addr[pi2s_config->mmap_index] = (dma_addr_t)dma_map_single(NULL, pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], size, DMA_BIDIRECTIONAL);
1306 +
1307 + if( pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] == NULL )
1308 + {
1309 + MSG("i2s_mmap failed\n");
1310 + return -1;
1311 + }
1312 + }
1313 + else
1314 + {
1315 + _printk("illegal index:%d\n", pi2s_config->mmap_index);
1316 + return -1;
1317 + }
1318 +
1319 + _printk("MMAP[%d]=0x%08X, i2s_mmap_addr[%d]=0x%08x\n",
1320 + pi2s_config->mmap_index, (u32)pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index],
1321 + pi2s_config->mmap_index, i2s_mmap_addr[pi2s_config->mmap_index]);
1322 +
1323 + memset(pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], 0, size);
1324 + pi2s_config->mmap_index++;
1325 +
1326 + for (i=1; i<MAX_I2S_PAGE; i++)
1327 + {
1328 + i2s_mmap_addr[pi2s_config->mmap_index] = i2s_mmap_addr[first_index] + i*page_size;
1329 + pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] = pi2s_config->pMMAPBufPtr[first_index] + i*page_size;
1330 +
1331 + _printk("MMAP[%d]=0x%08X, i2s_mmap_addr[%d]=0x%08x\n",pi2s_config->mmap_index, (u32)pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], pi2s_config->mmap_index, i2s_mmap_addr[pi2s_config->mmap_index]);
1332 +
1333 + /* Notice: The last mmap_index's value should be MAX_I2S_PAGE or MAX_I2S_PAGE*2 */
1334 + pi2s_config->mmap_index++;
1335 + }
1336 +
1337 + return 0;
1338 +}
1339 +
1340 +int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size)
1341 +{
1342 + int nRet;
1343 +
1344 + if((pi2s_config->pMMAPBufPtr[0]!=NULL) && (pi2s_config->mmap_index == MAX_I2S_PAGE))
1345 + {
1346 + MSG("i2s_mmap_remap:0\n");
1347 + nRet = remap_pfn_range(vma, vma->vm_start, virt_to_phys((void *)pi2s_config->pMMAPBufPtr[0]) >> PAGE_SHIFT, size, vma->vm_page_prot);
1348 +
1349 + if( nRet != 0 )
1350 + {
1351 + _printk("i2s_mmap->remap_pfn_range failed\n");
1352 + return -EIO;
1353 + }
1354 + }
1355 +
1356 + if((pi2s_config->pMMAPBufPtr[MAX_I2S_PAGE]!=NULL) && (pi2s_config->mmap_index == MAX_I2S_PAGE*2))
1357 + {
1358 + MSG("i2s_mmap_remap:%d\n", MAX_I2S_PAGE);
1359 +
1360 + nRet = remap_pfn_range(vma, vma->vm_start, virt_to_phys((void *)pi2s_config->pMMAPBufPtr[MAX_I2S_PAGE]) >> PAGE_SHIFT, size, vma->vm_page_prot);
1361 +
1362 + if( nRet != 0 )
1363 + {
1364 + _printk("i2s_mmap->remap_pfn_range failed\n");
1365 + return -EIO;
1366 + }
1367 + }
1368 +
1369 + return 0;
1370 +}
1371 +
1372 +static int i2s_mmap(struct file *filp, struct vm_area_struct *vma)
1373 +{
1374 + unsigned long size = vma->vm_end-vma->vm_start;
1375 + _printk("page_size=%d, ksize=%lu\n", I2S_PAGE_SIZE, size);
1376 +
1377 + if((pi2s_config->pMMAPBufPtr[0]==NULL)&&(pi2s_config->mmap_index!=0))
1378 + pi2s_config->mmap_index = 0;
1379 +
1380 + _printk("%s: vm_start=%08X,vm_end=%08X\n", __func__, (u32)vma->vm_start, (u32)vma->vm_end);
1381 +
1382 + /* Do memory allocate and dma sync */
1383 + i2s_mmap_alloc(size);
1384 +
1385 + i2s_mmap_remap(vma, size);
1386 +
1387 +
1388 + return 0;
1389 +}
1390 +
1391 +int i2s_mem_unmap(i2s_config_type* ptri2s_config)
1392 +{
1393 + u32 page_size;
1394 +
1395 + page_size = I2S_PAGE_SIZE;
1396 +
1397 + if(ptri2s_config->pMMAPBufPtr[0])
1398 + {
1399 + _printk("ummap MMAP[0]=0x%08X\n", (u32)ptri2s_config->pMMAPBufPtr[0]);
1400 + dma_unmap_single(NULL, i2s_mmap_addr[0], MAX_I2S_PAGE*page_size, DMA_BIDIRECTIONAL);
1401 + kfree(ptri2s_config->pMMAPBufPtr[0]);
1402 + }
1403 +
1404 + if(ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE])
1405 + {
1406 + _printk("ummap MMAP[%d]=0x%08X\n", MAX_I2S_PAGE, (u32)ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]);
1407 + dma_unmap_single(NULL, i2s_mmap_addr[MAX_I2S_PAGE], MAX_I2S_PAGE*page_size, DMA_BIDIRECTIONAL);
1408 + kfree(ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]);
1409 + }
1410 +
1411 + ptri2s_config->mmap_index = 0;
1412 +
1413 + return 0;
1414 +}
1415 +
1416 +int i2s_param_init(i2s_config_type* ptri2s_config)
1417 +{
1418 + ptri2s_config->dmach = GDMA_I2S_TX0;
1419 + ptri2s_config->tx_ff_thres = CONFIG_I2S_TFF_THRES;
1420 + ptri2s_config->tx_ch_swap = CONFIG_I2S_CH_SWAP;
1421 + ptri2s_config->rx_ff_thres = CONFIG_I2S_TFF_THRES;
1422 + ptri2s_config->rx_ch_swap = CONFIG_I2S_CH_SWAP;
1423 + ptri2s_config->slave_en = CONFIG_I2S_SLAVE_EN;
1424 + ptri2s_config->codec_pll_en = CONFIG_I2S_CODEC_PLL_EN;
1425 +
1426 + ptri2s_config->bRxDMAEnable = 0;
1427 + ptri2s_config->bTxDMAEnable = 0;
1428 + //ptri2s_config->bALSAEnable = 0;
1429 + ptri2s_config->srate = 44100;
1430 + ptri2s_config->txvol = 0;
1431 + ptri2s_config->rxvol = 0;
1432 + ptri2s_config->lbk = 0;
1433 + ptri2s_config->extlbk = 0;
1434 + ptri2s_config->txrx_coexist = 0;
1435 + ptri2s_config->wordlen_24b = 0;
1436 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
1437 + ptri2s_config->sys_endian = 0;
1438 + ptri2s_config->fmt = 0;
1439 +#endif
1440 + ptri2s_config->micboost = 0;
1441 + ptri2s_config->micin = 0;
1442 +
1443 + return 0;
1444 +}
1445 +
1446 +int i2s_txbuf_alloc(i2s_config_type* ptri2s_config)
1447 +{
1448 + int i;
1449 +
1450 + for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
1451 + {
1452 +#if defined(CONFIG_I2S_MMAP)
1453 + ptri2s_config->pMMAPTxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i];
1454 +#else
1455 + if(ptri2s_config->pMMAPTxBufPtr[i]==NULL)
1456 + ptri2s_config->pMMAPTxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
1457 +#endif
1458 + memset(ptri2s_config->pMMAPTxBufPtr[i], 0, I2S_PAGE_SIZE);
1459 + }
1460 +
1461 + return 0;
1462 +}
1463 +
1464 +int i2s_rxbuf_alloc(i2s_config_type* ptri2s_config)
1465 +{
1466 + int i;
1467 +
1468 + for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
1469 + {
1470 +#if defined(CONFIG_I2S_MMAP)
1471 + ptri2s_config->pMMAPRxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i+(ptri2s_config->mmap_index-MAX_I2S_PAGE)];
1472 +#else
1473 + if(ptri2s_config->pMMAPRxBufPtr[i]==NULL)
1474 + ptri2s_config->pMMAPRxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
1475 +#endif
1476 + memset(ptri2s_config->pMMAPRxBufPtr[i], 0, I2S_PAGE_SIZE);
1477 + }
1478 +
1479 + return 0;
1480 +}
1481 +
1482 +int i2s_txPagebuf_alloc(i2s_config_type* ptri2s_config)
1483 +{
1484 +#if defined(ARM_ARCH)
1485 + ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE , &i2s_txdma_addr0);
1486 + ptri2s_config->pPage1TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE , &i2s_txdma_addr1);
1487 + if(ptri2s_config->pPage0TxBuf8ptr==NULL)
1488 + {
1489 + MSG("Allocate Tx Page0 Buffer Failed\n");
1490 + return -1;
1491 + }
1492 + if(ptri2s_config->pPage1TxBuf8ptr==NULL)
1493 + {
1494 + MSG("Allocate Tx Page1 Buffer Failed\n");
1495 + return -1;
1496 + }
1497 +#else
1498 + ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_txdma_addr);
1499 + if(ptri2s_config->pPage0TxBuf8ptr==NULL)
1500 + {
1501 + MSG("Allocate Tx Page Buffer Failed\n");
1502 + return -1;
1503 + }
1504 + ptri2s_config->pPage1TxBuf8ptr = ptri2s_config->pPage0TxBuf8ptr + I2S_PAGE_SIZE;
1505 +#endif
1506 + return 0;
1507 +}
1508 +
1509 +int i2s_rxPagebuf_alloc(i2s_config_type* ptri2s_config)
1510 +{
1511 +#if defined(ARM_ARCH)
1512 + ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE, &i2s_rxdma_addr0);
1513 + ptri2s_config->pPage1RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE, &i2s_rxdma_addr1);
1514 + if(ptri2s_config->pPage0RxBuf8ptr==NULL)
1515 + {
1516 + MSG("Allocate Rx Page Buffer Failed\n");
1517 + return -1;
1518 + }
1519 + if(ptri2s_config->pPage1RxBuf8ptr==NULL)
1520 + {
1521 + MSG("Allocate Rx Page Buffer Failed\n");
1522 + return -1;
1523 + }
1524 +#else
1525 + ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_rxdma_addr);
1526 + if(ptri2s_config->pPage0RxBuf8ptr==NULL)
1527 + {
1528 + MSG("Allocate Rx Page Buffer Failed\n");
1529 + return -1;
1530 + }
1531 + ptri2s_config->pPage1RxBuf8ptr = ptri2s_config->pPage0RxBuf8ptr + I2S_PAGE_SIZE;
1532 +#endif
1533 + return 0;
1534 +}
1535 +
1536 +int i2s_txbuf_free(i2s_config_type* ptri2s_config)
1537 +{
1538 + int i;
1539 +
1540 + for(i = 0 ; i < MAX_I2S_PAGE ; i ++)
1541 + {
1542 + if(ptri2s_config->pMMAPTxBufPtr[i] != NULL)
1543 + {
1544 +#if defined(CONFIG_I2S_MMAP)
1545 + ptri2s_config->pMMAPTxBufPtr[i] = NULL;
1546 +#else
1547 + kfree(ptri2s_config->pMMAPTxBufPtr[i]);
1548 + ptri2s_config->pMMAPTxBufPtr[i] = NULL;
1549 +#endif
1550 + }
1551 + }
1552 + return 0;
1553 +}
1554 +
1555 +int i2s_rxbuf_free(i2s_config_type* ptri2s_config)
1556 +{
1557 + int i;
1558 +
1559 + for(i = 0 ; i < MAX_I2S_PAGE ; i ++)
1560 + {
1561 + if(ptri2s_config->pMMAPRxBufPtr[i] != NULL)
1562 + {
1563 +#if defined(CONFIG_I2S_MMAP)
1564 + ptri2s_config->pMMAPRxBufPtr[i] = NULL;
1565 +#else
1566 + kfree(ptri2s_config->pMMAPRxBufPtr[i]);
1567 + ptri2s_config->pMMAPRxBufPtr[i] = NULL;
1568 +#endif
1569 + }
1570 + }
1571 +
1572 + return 0;
1573 +}
1574 +
1575 +int i2s_txPagebuf_free(i2s_config_type* ptri2s_config)
1576 +{
1577 +#if defined(ARM_ARCH)
1578 + if (ptri2s_config->pPage0TxBuf8ptr)
1579 + {
1580 + pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr0);
1581 + ptri2s_config->pPage0TxBuf8ptr = NULL;
1582 + }
1583 +
1584 + if (ptri2s_config->pPage1TxBuf8ptr)
1585 + {
1586 + pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage1TxBuf8ptr, i2s_txdma_addr1);
1587 + ptri2s_config->pPage1TxBuf8ptr = NULL;
1588 + }
1589 + _printk("Free tx page buffer\n");
1590 +#else
1591 + if (ptri2s_config->pPage0TxBuf8ptr)
1592 + {
1593 + pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr);
1594 + ptri2s_config->pPage0TxBuf8ptr = NULL;
1595 + }
1596 +#endif
1597 + return 0;
1598 +
1599 +}
1600 +
1601 +int i2s_rxPagebuf_free(i2s_config_type* ptri2s_config)
1602 +{
1603 +#if defined(ARM_ARCH)
1604 + if (ptri2s_config->pPage0RxBuf8ptr)
1605 + {
1606 + pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr0);
1607 + ptri2s_config->pPage0RxBuf8ptr = NULL;
1608 + }
1609 + if (ptri2s_config->pPage1RxBuf8ptr)
1610 + {
1611 + pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage1RxBuf8ptr, i2s_rxdma_addr1);
1612 + ptri2s_config->pPage1RxBuf8ptr = NULL;
1613 + }
1614 + _printk("Free rx page buffer\n");
1615 +#else
1616 + if (ptri2s_config->pPage0RxBuf8ptr)
1617 + {
1618 + pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr);
1619 + ptri2s_config->pPage0RxBuf8ptr = NULL;
1620 + }
1621 +#endif
1622 + return 0;
1623 +}
1624 +
1625 +int i2s_reset_tx_param(i2s_config_type* ptri2s_config)
1626 +{
1627 + ptri2s_config->tx_isr_cnt = 0;
1628 + ptri2s_config->tx_w_idx = 0;
1629 + ptri2s_config->tx_r_idx = 0;
1630 + ptri2s_config->enLable = 0;
1631 + ptri2s_config->tx_pause_en = 0;
1632 + ptri2s_config->end_cnt = 0;
1633 + ptri2s_config->tx_stop_cnt = 0;
1634 +
1635 +#ifdef I2S_STATISTIC
1636 + pi2s_status->txbuffer_unrun = 0;
1637 + pi2s_status->txbuffer_ovrun = 0;
1638 + pi2s_status->txdmafault = 0;
1639 + pi2s_status->txovrun = 0;
1640 + pi2s_status->txunrun = 0;
1641 + pi2s_status->txthres = 0;
1642 + pi2s_status->txbuffer_len = 0;
1643 +#endif
1644 +
1645 + return 0;
1646 +}
1647 +
1648 +int i2s_reset_rx_param(i2s_config_type* ptri2s_config)
1649 +{
1650 + ptri2s_config->rx_isr_cnt = 0;
1651 + ptri2s_config->rx_w_idx = 0;
1652 + ptri2s_config->rx_r_idx = 0;
1653 + ptri2s_config->enLable = 0;
1654 + ptri2s_config->rx_pause_en = 0;
1655 + ptri2s_config->rx_stop_cnt = 0;
1656 +
1657 +#ifdef I2S_STATISTIC
1658 + pi2s_status->rxbuffer_unrun = 0;
1659 + pi2s_status->rxbuffer_ovrun = 0;
1660 + pi2s_status->rxdmafault = 0;
1661 + pi2s_status->rxovrun = 0;
1662 + pi2s_status->rxunrun = 0;
1663 + pi2s_status->rxthres = 0;
1664 + pi2s_status->rxbuffer_len = 0;
1665 +#endif
1666 +
1667 + return 0;
1668 +}
1669 +#ifdef MT7621_ASIC_BOARD
1670 +int i2s_pll_config_mt7621(unsigned long index)
1671 +{
1672 + unsigned long data;
1673 + unsigned long regValue;
1674 + bool xtal_20M_en = 0;
1675 +// bool xtal_25M_en = 0;
1676 + bool xtal_40M_en = 0;
1677 +
1678 + regValue = i2s_inw(RALINK_SYSCTL_BASE + 0x10);
1679 + regValue = (regValue >> 6) & 0x7;
1680 + if (regValue < 3)
1681 + {
1682 + xtal_20M_en = 1;
1683 + MSG("Xtal is 20MHz. \n");
1684 + }
1685 + else if (regValue < 6)
1686 + {
1687 + xtal_40M_en = 1;
1688 + MSG("Xtal is 40M.\n");
1689 + }
1690 + else
1691 + {
1692 + //xtal_25M_en = 1;
1693 + MSG("Xtal is 25M.\n");
1694 + }
1695 +
1696 +#if defined (CONFIG_I2S_MCLK_12P288MHZ)
1697 + _printk("MT7621 provide 12.288M/11.298MHz REFCLK\n");
1698 + /* Firstly, reset all required register to default value */
1699 + i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008000);
1700 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, 0x01001d61);//0x01401d61);
1701 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
1702 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, 0x80100004);//0x80120004);
1703 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48);
1704 +
1705 + /* toggle RG_XPTL_CHG */
1706 + i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008800);
1707 + i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008c00);
1708 +
1709 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1710 + data &= ~(0x0000ffc0);
1711 + if ((xtal_40M_en) || (xtal_20M_en))
1712 + {
1713 + data |= REGBIT(0x1d, 8); /* for 40M or 20M */
1714 + }
1715 + else
1716 + {
1717 + data |= REGBIT(0x17, 8); /* for 25M */
1718 + }
1719 +
1720 + if (xtal_40M_en)
1721 + {
1722 + data |= REGBIT(0x1, 6); /* for 40M */
1723 + }
1724 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1725 +
1726 +
1727 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1728 + data &= ~(0xf0773f00);
1729 + data |= REGBIT(0x3, 28);
1730 + data |= REGBIT(0x2, 20);
1731 + if ((xtal_40M_en) || (xtal_20M_en))
1732 + {
1733 + data |= REGBIT(0x3, 16); /* for 40M or 20M */
1734 + }
1735 + else
1736 + {
1737 + data |= REGBIT(0x2, 16); /* for 25M */
1738 + }
1739 + data |= REGBIT(0x3, 12);
1740 + if ((xtal_40M_en) || (xtal_20M_en))
1741 + {
1742 + data |= REGBIT(0xd, 8); /* for 40M or 20M */
1743 + }
1744 + else
1745 + {
1746 + data |= REGBIT(0x7, 8); /* for 25M */
1747 + }
1748 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1749 +
1750 + if((index==1)|(index==4)|(index==7)|(index==9))// 270 MHz for 22.05K, 44.1K, 88.2K, 176.4K
1751 + {
1752 + if ((xtal_40M_en) || (xtal_20M_en))
1753 + {
1754 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1a18548a); /* for 40M or 20M */
1755 + }
1756 + else
1757 + {
1758 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x14ad106e); /* for 25M */
1759 + }
1760 + }
1761 + else if ((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10))// 294 MHZ for 24K, 48K, 96K, 192K
1762 + {
1763 + if ((xtal_40M_en) || (xtal_20M_en))
1764 + {
1765 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48); /* for 40M or 20M */
1766 + }
1767 + else
1768 + {
1769 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1697cc39); /* for 25M */
1770 + }
1771 + }
1772 + else if (index==2)
1773 + {
1774 + _printk("Not support 12KHz sampling rate!\n");
1775 + return -1;
1776 + }
1777 + else
1778 + {
1779 + _printk("Wrong sampling rate!\n");
1780 + return -1;
1781 + }
1782 +
1783 + //*Common setting - Set PLLGP_CTRL_4 *//
1784 + /* 1. Bit 31 */
1785 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1786 + data &= ~(REGBIT(0x1, 31));
1787 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1788 + ndelay(10);
1789 +
1790 + /* 2. Bit 0 */
1791 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1792 + data |= REGBIT(0x1, 0);
1793 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1794 + udelay(200);
1795 +
1796 + /* 3. Bit 3 */
1797 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1798 + data |= REGBIT(0x1, 3);
1799 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1800 + udelay(1);
1801 +
1802 + /* 4. Bit 8 */
1803 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1804 + data |= REGBIT(0x1, 8);
1805 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1806 + ndelay(40);
1807 +
1808 + /* 5. Bit 6 */
1809 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1810 + data |= REGBIT(0x1, 6);
1811 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1812 + ndelay(40);
1813 +
1814 + /* 6. Bit 5 & Bit 7*/
1815 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1816 + data |= REGBIT(0x1, 5);
1817 + data |= REGBIT(0x1, 7);
1818 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1819 + udelay(1);
1820 +
1821 + /* 7. Bit 17 */
1822 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1823 + data |= REGBIT(0x1, 17);
1824 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1825 +
1826 +#elif defined(CONFIG_I2S_MCLK_12MHZ)
1827 + _printk("MT7621 provide 12MHz REFCLK\n");
1828 + /* Firstly, reset all required register to default value */
1829 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, 0x01401d61);//0x01401d61);
1830 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, 0x80120004);//0x80100004);
1831 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
1832 +
1833 + if (xtal_40M_en)
1834 + {
1835 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1836 + data &= ~REGBIT(0x1, 17);
1837 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1838 +
1839 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1840 + data &= ~REGBIT(0x3, 4);
1841 + data |= REGBIT(0x1, 4);
1842 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1843 +
1844 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1845 + data &= ~REGBIT(0x1, 31);
1846 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1847 + }
1848 + else if (xtal_20M_en)
1849 + {
1850 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1851 + data &= ~REGBIT(0x1, 17);
1852 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1853 +
1854 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1855 + data &= ~REGBIT(0x3, 6);
1856 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1857 +
1858 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1859 + data &= ~REGBIT(0x3, 4);
1860 + data |= REGBIT(0x1, 4);
1861 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1862 +
1863 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1864 + data &= ~REGBIT(0x1, 31);
1865 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1866 + }
1867 + else
1868 + {
1869 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1870 + data &= ~REGBIT(0x1, 17);
1871 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1872 +
1873 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1874 + data &= ~REGBIT(0x7f, 8);
1875 + data |= REGBIT(0x17, 8);
1876 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1877 +
1878 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1879 + data &= ~REGBIT(0x3, 6);
1880 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1881 +
1882 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1883 + data &= ~REGBIT(0x7, 16);
1884 + data |= REGBIT(0x2, 16);
1885 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1886 +
1887 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1888 + data &= ~REGBIT(0xf, 8);
1889 + data |= REGBIT(0x7, 8);
1890 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1891 +
1892 +
1893 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1894 + data &= ~REGBIT(0x3, 4);
1895 + data |= REGBIT(0x1, 4);
1896 + i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1897 +
1898 + data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1899 + data &= ~REGBIT(0x1, 31);
1900 + i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1901 +
1902 + }
1903 +#endif
1904 + return 0;
1905 +}
1906 +#if defined(CONFIG_I2S_IN_MCLK)
1907 +int i2s_pll_refclk_set(void)
1908 +{
1909 + unsigned long data;
1910 +
1911 + /* Set APLL register for REFCLK */
1912 + data = i2s_inw(RALINK_SYSCTL_BASE+0x90);
1913 + data &= ~(0x0000f000);
1914 + data |= REGBIT(0x1, 12);
1915 + i2s_outw(RALINK_SYSCTL_BASE+0x0090, data);
1916 +
1917 + data = i2s_inw(RALINK_SYSCTL_BASE+0x0090);
1918 + data &= ~(0x00000300);
1919 + i2s_outw(RALINK_SYSCTL_BASE+0x0090, data);
1920 + MSG("Set 0x90 register\n");
1921 +
1922 + return 0;
1923 +}
1924 +#endif
1925 +#endif
1926 +
1927 +#ifdef MT7623_ASIC_BOARD
1928 +int i2s_pll_config_mt7623(unsigned long index)
1929 +{
1930 + unsigned long data;
1931 +
1932 + /* xPLL PWR ON */
1933 + data = i2s_inw(AUD2PLL_PWR_CON0);
1934 + data |= 0x1;
1935 + i2s_outw(AUD2PLL_PWR_CON0, data);
1936 + udelay(5);
1937 +
1938 + /* xPLL ISO Disable */
1939 + data = i2s_inw(AUD2PLL_PWR_CON0);
1940 + data &= ~(0x2);
1941 + i2s_outw(AUD2PLL_PWR_CON0, data);
1942 +
1943 + /* xPLL Frequency Set */
1944 + data = i2s_inw(AUD2PLL_CON0);
1945 + data |= 0x1;
1946 + i2s_outw(AUD2PLL_CON0, data);
1947 +
1948 + /* AUD1PLL Frequency Set(change from 98.304MHz to 294.912MHz) */
1949 + i2s_outw(AUD1PLL_CON0, 0x121);
1950 + i2s_outw(AUD1PLL_CON1, 0xad5efee6);
1951 + udelay(40);
1952 +
1953 + /* Audio clock setting */
1954 + if((index==1)|(index==4)|(index==7)|(index==9)|(index==11))// for 22.05K, 44.1K, 88.2K, 176.4K
1955 + {
1956 + _printk("\n*****%s:index=%d(270MHz)*****\n", __func__, (int)index);
1957 + data = i2s_inw(0xFB00002c);
1958 + //data &= ~REGBIT(0x8, 1);
1959 + data &= ~(0x80);
1960 + i2s_outw(0xFB00002C, data); /* AUD1PLL 270.9204MHz */
1961 + }
1962 + else if ((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10)|(index==12)) //for 24K, 48K, 96K, 192K
1963 + {
1964 + _printk("\n*****%s:index=%d(294MHz)*****\n", __func__, (int)index);
1965 + data = i2s_inw(0xFB00002c);
1966 + //data |= REGBIT(0x8, 1);
1967 + data |= (0x80);
1968 + i2s_outw(0xFB00002c, data); /* AUD1PLL 294.912MHz */
1969 + }
1970 + else if (index==2)
1971 + {
1972 + _printk("Not support 12KHz sampling rate!\n");
1973 + return -1;
1974 + }
1975 + else
1976 + {
1977 + _printk("Wrong sampling rate!\n");
1978 + return -1;
1979 + }
1980 + return 0;
1981 +}
1982 +#endif
1983 +
1984 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
1985 +int i2s_driving_strength_adjust(void)
1986 +{
1987 +#if defined(MT7628_ASIC_BOARD)
1988 + unsigned long data;
1989 +
1990 + MSG("Adjust MT7628 current's driving strngth\n");
1991 + /* Adjust REFCLK0's driving strength of current which can avoid
1992 + * the glitch of REFCKL0
1993 + * E4 = 0xb0001354[5]; E8 = 0xb0001364[5]
1994 + * (E4,E8)=(0,0)-> 4 mA;
1995 + * =(1,0)-> 8 mA;
1996 + * =(0,1)-> 12 mA;
1997 + * =(1,1)-> 16 mA*/
1998 +
1999 + /* Set to 12mA */
2000 + data = i2s_inw(0xb0001354);
2001 + data &= ~(0x1<<5);
2002 + i2s_outw(0xb0001354, data);
2003 +
2004 + data = i2s_inw(0xb0001364);
2005 + data |= (0x1<<5);
2006 + i2s_outw(0xb0001364, data);
2007 +#endif
2008 +#if defined(CONFIG_ARCH_MT7623)
2009 + MSG("Adjust MT7623 current's driving strngth\n");
2010 +
2011 + i2s_outw(0xF0005F80, 0x7777);
2012 +#endif
2013 +
2014 + return 0;
2015 +}
2016 +#endif
2017 +
2018 +#if defined(CONFIG_I2S_IN_MCLK)
2019 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2020 +int i2s_refclk_12m_enable(void)
2021 +{
2022 + unsigned long data;
2023 +
2024 + MSG("Enable SoC MCLK 12Mhz\n");
2025 +
2026 +#if defined(CONFIG_RALINK_RT6855A)
2027 + data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2028 + data |= (0x1<<17);
2029 + data &= ~(0x7<<18);
2030 + data |= (0x1<<18);
2031 + i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2032 +#elif defined(CONFIG_RALINK_RT3350)
2033 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2034 + data |= (0x1<<8);
2035 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2036 +#elif defined(CONFIG_RALINK_RT3883)
2037 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2038 + data &= ~(0x03<<13);
2039 + data |= (0x1<<13);
2040 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2041 +#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
2042 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2043 + data &= ~(0x0F<<8);
2044 + data |= (0x3<<8);
2045 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2046 +#elif defined(CONFIG_RALINK_MT7620)
2047 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2048 + data &= ~(0x07<<9);
2049 + data |= (1<<9);
2050 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2051 +#elif defined(CONFIG_RALINK_MT7621)
2052 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2053 + data &= ~(0x1f<<18);
2054 + data |= REGBIT(0x19, 18);
2055 + data &= ~(0x1f<<12);
2056 + data |= REGBIT(0x1, 12);
2057 + data &= ~(0x7<<9);
2058 + data |= REGBIT(0x5, 9);
2059 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2060 +#elif defined(CONFIG_RALINK_MT7628)
2061 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2062 + MSG("turn on REFCLK output for MCLK1\n");
2063 + data &= ~(0x7<<9);
2064 + data |= (0x1<<9); /* output for MCLK */
2065 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2066 +#else
2067 + #error "This SoC does not provide 12MHz clock to audio codec\n");
2068 +#endif
2069 + i2s_refclk_gpio_out_config();
2070 +
2071 + return 0;
2072 +}
2073 +#endif
2074 +
2075 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
2076 +int i2s_refclk_12p288m_enable(void)
2077 +{
2078 + unsigned long data;
2079 + MSG("Enable SoC MCLK 12.288Mhz\n");
2080 +
2081 +#if defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
2082 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2083 + data &= ~(0x01F<<18);
2084 + data |= 31<<18;
2085 + data &= ~(0x01F<<12);
2086 + data |= 1<<12;
2087 + data |= (0xF<<8);
2088 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2089 +#elif defined(CONFIG_RALINK_MT7621)
2090 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2091 + data &= ~(0x1f<<18);
2092 + data |= REGBIT(0xc, 18);
2093 + data &= ~(0x1f<<12);
2094 + data |= REGBIT(0x1, 12);
2095 + data &= ~(0x7<<9);
2096 + data |= REGBIT(0x5, 9);
2097 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2098 + _printk("MT7621 provide REFCLK 12.288MHz/11.289MHz\n");
2099 +#elif defined(CONFIG_ARCH_MT7623)
2100 + /* MT7623 does not need to set divider for REFCLK */
2101 + /* GPIO126 - I2S0_MCLK */
2102 + data = i2s_inw(0xF00058F0);
2103 + data &= ~(0x7<<3);
2104 + data |= (0x6<<3);
2105 + i2s_outw(0xF00058F0, data);
2106 + /* GPIO_DIR8: OUT */
2107 + data = i2s_inw(0xF0005070);
2108 + data |= (0x1<<14);
2109 + i2s_outw(0xF0005070, data);
2110 +#else
2111 + #error "This SoC does not provide 12.288Mhz clock to audio codec\n");
2112 +#endif
2113 +
2114 + return 0;
2115 +}
2116 +#endif
2117 +
2118 +#if defined(CONFIG_I2S_MCLK_18P432MHZ)
2119 +int i2s_refclk_18p432m_enable(unsigned long index)
2120 +{
2121 + unsigned long data;
2122 + MSG("Enable SoC MCLK 18.432MHz/16.934MHz");
2123 +
2124 + if((index==1)|(index==4)|(index==7)|(index==9))// 16.934MHz for 22.05K, 44.1K, 88.2K, 176.4K
2125 + {
2126 + data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x2c);
2127 + data &= ~(0x1<<7);
2128 + i2s_outw(ETHDMASYS_SYSCTL_BASE+0x2c, data);
2129 + }
2130 + else if((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10))// 18.432MHZ for 24K, 48K, 96K, 192K
2131 + {
2132 + data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x2c);
2133 + data |= (0x1<<7);
2134 + i2s_outw(ETHDMASYS_SYSCTL_BASE+0x2c, data);
2135 + }
2136 +
2137 + data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x30);
2138 + data |= (0x1<<17);
2139 + i2s_outw(ETHDMASYS_SYSCTL_BASE+0x30, data);
2140 +
2141 + return 0;
2142 +}
2143 +#endif
2144 +#endif
2145 +
2146 +int i2s_refclk_disable(void)
2147 +{
2148 + unsigned long data;
2149 +
2150 +#if defined(CONFIG_RALINK_RT6855A)
2151 + data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2152 + data &= ~(1<<17);
2153 + i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2154 +#elif defined(CONFIG_RALINK_RT3350)
2155 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2156 + data &= ~(0x1<<8);
2157 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2158 +#elif defined(CONFIG_RALINK_RT3883)
2159 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2160 + data &= ~(0x0F<<13);
2161 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2162 +#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)||defined (CONFIG_RALINK_RT6855)
2163 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2164 + data &= ~(0x0F<<8);
2165 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2166 +#elif defined (CONFIG_RALINK_MT7620)||defined (CONFIG_RALINK_MT7621)||defined (CONFIG_RALINK_MT7628)
2167 + _printk("turn off REFCLK output from internal CLK\n");
2168 + data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2169 + data &= ~(0x07<<9);
2170 + i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2171 +#elif defined (CONFIG_ARCH_MT7623) /*FIXME:2*/
2172 +#ifdef MT7623_ASIC_BOARD
2173 + _printk("turn off REFCLK output from internal CLK\n");
2174 + /* GPIO126 - I2S0_MCLK */
2175 + data = i2s_inw(0xF00058F0);
2176 + data &= ~(0x7<<3);
2177 + //data |= (0x2<<3);
2178 + i2s_outw(0xF00058F0, data);
2179 + /* GPIO126 => GPIO_DIR8: IN */
2180 + data = i2s_inw(0xF0005070);
2181 + data &= ~(0x1<<14);
2182 + i2s_outw(0xF0005070, data);
2183 +#else
2184 + _printk("turn off REFCLK output from internal CLK\n");
2185 + data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x30);
2186 + data &= ~(0x1<<17);
2187 + i2s_outw(ETHDMASYS_SYSCTL_BASE+0x30, data);
2188 +#endif
2189 +#endif
2190 + return 0;
2191 +}
2192 +
2193 +int i2s_refclk_gpio_out_config(void)
2194 +{
2195 +#ifndef CONFIG_ARCH_MT7623
2196 + unsigned long data; /* FIXME */
2197 +#endif
2198 +
2199 + /* Set REFCLK GPIO pin as REFCLK mode*/
2200 +#if defined(CONFIG_RALINK_MT7620)
2201 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2202 + data &= ~(0x03<<21); /* WDT */
2203 + data |= (1<<21);
2204 + //data &= ~(0x03<<16); /* PERST */
2205 + //data |= (1<<16);
2206 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2207 +#endif
2208 +#if defined(CONFIG_RALINK_MT7621)
2209 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2210 + //data &= ~(0x3<<10); /* PERST */
2211 + //data |= (0x2<<10);
2212 + data &= ~(0x3<<8); /* WDT */
2213 + data |= (0x2<<8);
2214 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2215 + MSG("Set 0x60 register\n");
2216 +#endif
2217 +#if defined(CONFIG_RALINK_MT7628)
2218 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2219 + data &= ~(0x1<<18);
2220 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2221 +#endif
2222 +
2223 + return 0;
2224 +}
2225 +
2226 +int i2s_refclk_gpio_in_config(void)
2227 +{
2228 +#ifndef CONFIG_ARCH_MT7623
2229 + unsigned long data; /* FIXME */
2230 +#endif
2231 +
2232 +#if defined (CONFIG_RALINK_MT7620)
2233 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2234 + data &= ~(0x03<<21); /* WDT */
2235 + data |= (1<<21);
2236 + //data &= ~(0x03<<16); /* PERST */
2237 + //data |= (1<<16);
2238 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2239 +
2240 + data = i2s_inw(RALINK_PIO_BASE);
2241 + data &= ~(0x1<<17); /* GPIO share ping 17 for WDT */
2242 + i2s_outw(RALINK_PIO_BASE, data);
2243 +
2244 + //data = i2s_inw(RALINK_PIO_BASE+0x04);
2245 + //data &= ~(0x1<<4); /* GPIO share ping 36 for PERST */
2246 + //i2s_outw(RALINK_PIO_BASE+0x04, data);
2247 +#endif
2248 +#if defined (CONFIG_RALINK_MT7621)
2249 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2250 + //data &= ~(0x3<<10); /* PERST */
2251 + //data |= (0x1<<10);
2252 + data &= ~(0x3<<8); /* WDT */
2253 + data |= (0x1<<8);
2254 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2255 +
2256 + data = i2s_inw(RALINK_PIO_BASE);
2257 + //data &= ~(0x1<<19); /* GPIO share ping 19 for RERST */
2258 + data &= ~(0x1<<18); /* GPIO share ping 18 for WDT */
2259 + i2s_outw(RALINK_PIO_BASE, data);
2260 +#endif
2261 +#if defined (CONFIG_RALINK_MT7628)
2262 + /* To use external OSC, set REFCLK_GPIO ping as GPIO mode and set it as input direction */
2263 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2264 + data |= (0x1<<18);
2265 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2266 +
2267 + data = i2s_inw(RALINK_PIO_BASE+0x04);
2268 + data &= ~(0x1<<5); /* GPIO share ping 37*/
2269 + i2s_outw(RALINK_PIO_BASE+0x04, data);
2270 +#endif
2271 +
2272 + return 0;
2273 +}
2274 +
2275 +int i2s_slave_clock_gpio_in_mt7623(void)
2276 +{
2277 + unsigned long data;
2278 +
2279 + /* GPIO74(I2S0_BCLK)=>GPIO_DIR5: IN */
2280 + data = i2s_inw(0xF0005040);
2281 + data &= ~(0x1<<10);
2282 + i2s_outw(0xF0005040, data);
2283 +
2284 + /* GPIO73(I2S0_LRCK)=>GPIO_DIR5: IN */
2285 + data = i2s_inw(0xF0005040);
2286 + data &= ~(0x1<<9);
2287 + i2s_outw(0xF0005040, data);
2288 +
2289 + _printk("i2s_slave_clock_gpio_in_mt7623\n");
2290 +
2291 + return 0;
2292 +}
2293 +
2294 +int i2s_master_clock_gpio_out_mt7623(void)
2295 +{
2296 + unsigned long data;
2297 +
2298 + /* GPIO74(I2S0_BCLK)=>GPIO_DIR5: OUT */
2299 + data = i2s_inw(0xF0005040);
2300 + data |= (0x1<<10);
2301 + i2s_outw(0xF0005040, data);
2302 +
2303 + /* GPIO73(I2S0_LRCK)=>GPIO_DIR5: OUT */
2304 + data = i2s_inw(0xF0005040);
2305 + data |= (0x1<<9);
2306 + i2s_outw(0xF0005040, data);
2307 +
2308 + _printk("i2s_master_clock_gpio_out_mt7623\n");
2309 +
2310 + return 0;
2311 +}
2312 +
2313 +int i2s_share_pin_mt7623(i2s_config_type* ptri2s_config)
2314 +{
2315 + unsigned long data;
2316 +
2317 + _printk("\nConfig MT7623 I2S pinmux\n");
2318 + /* GPIO74 - I2S0_BCLK */
2319 + data = i2s_inw(0xF0005840);
2320 + data &= ~(0x7<<12);
2321 + data |= (0x6<<12);
2322 + i2s_outw(0xF0005840, data);
2323 +
2324 + /* GPIO73 - I2S0_LRCK */
2325 + data = i2s_inw(0xF0005840);
2326 + data &= ~(0x7<<9);
2327 + data |= (0x6<<9);
2328 + i2s_outw(0xF0005840, data);
2329 +
2330 + if(ptri2s_config->slave_en==0)
2331 + i2s_master_clock_gpio_out_mt7623();
2332 + else
2333 + i2s_slave_clock_gpio_in_mt7623();
2334 +
2335 + /* GPIO49 - I2S0_DATA */
2336 + data = i2s_inw(0xF00057F0);
2337 + data &= ~(0x7<<12);
2338 + data |= (0x6<<12);
2339 + i2s_outw(0xF00057F0, data);
2340 + /* GPIO_DIR4: OUT */
2341 + data = i2s_inw(0xF0005030);
2342 + data |= (0x1<<1);
2343 + i2s_outw(0xF0005030, data);
2344 +
2345 + /* GPIO72 - I2S0_DATA_IN */
2346 + data = i2s_inw(0xF0005840);
2347 + data &= ~(0x7<<6);
2348 + data |= (0x6<<6);
2349 + i2s_outw(0xF0005840, data);
2350 + /* GPIO_DIR5: IN */
2351 + data = i2s_inw(0xF0005040);
2352 + data &= ~(0x1<<8);
2353 + i2s_outw(0xF0005040, data);
2354 +
2355 + return 0;
2356 +}
2357 +
2358 +int i2s_share_pin_config(i2s_config_type* ptri2s_config)
2359 +{
2360 +#ifndef CONFIG_ARCH_MT7623
2361 + unsigned long data; /*FIXME*/
2362 +#endif
2363 +
2364 + /* set share pins to i2s/gpio mode and i2c mode */
2365 +#if defined(CONFIG_RALINK_RT6855A)
2366 + data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2367 + data |= 0x00008080;
2368 + i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2369 +#elif defined(CONFIG_RALINK_MT7621)
2370 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2371 + data &= 0xFFFFFFE3;
2372 + data |= 0x00000010;
2373 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2374 +#elif defined(CONFIG_RALINK_MT7628)
2375 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2376 + data &= ~(0x3<<6); /* I2S_MODE */
2377 + data &= ~(0x3<<20); /* I2C_MODE */
2378 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2379 +#elif defined(CONFIG_ARCH_MT7623)
2380 + i2s_share_pin_mt7623(ptri2s_config);
2381 +#else
2382 + data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2383 + data &= 0xFFFFFFE2;
2384 + data |= 0x00000018;
2385 + i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2386 +#endif
2387 + return 0;
2388 +}
2389 +
2390 +int i2s_ws_config(i2s_config_type* ptri2s_config, unsigned long index)
2391 +{
2392 + unsigned long data;
2393 + unsigned long* pTable;
2394 +
2395 +#if defined(CONFIG_I2S_IN_CLK)
2396 + /* REFCLK is 15.625Mhz or 40Mhz(fractional division) */
2397 +#if defined(CONFIG_I2S_FRAC_DIV)
2398 + MSG("Internal REFCLK with fractional division\n");
2399 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2400 + if (ptri2s_config->wordlen_24b == 1)
2401 + {
2402 + MSG("24 bit int table\n");
2403 + pTable = i2s_inclk_int_24bit;
2404 + }
2405 + else
2406 + {
2407 + MSG("16 bit int table\n");
2408 + pTable = i2s_inclk_int_16bit;
2409 + }
2410 +#else
2411 + pTable = i2s_inclk_int;
2412 +#endif /* CONFIG_RALINK_MT7628 */
2413 +
2414 + data = (unsigned long)(pTable[index]);
2415 + i2s_outw(I2S_DIVINT_CFG, data);
2416 +
2417 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2418 + if (ptri2s_config->wordlen_24b == 1)
2419 + {
2420 + MSG("24 bit comp table\n");
2421 + pTable = i2s_inclk_comp_24bit;
2422 + }
2423 + else
2424 + {
2425 + MSG("16 bit comp table\n");
2426 + pTable = i2s_inclk_comp_16bit;
2427 + }
2428 +#else
2429 + pTable = i2s_inclk_comp;
2430 +#endif /* CONFIG_RALINK_MT7628 */
2431 +
2432 + data = (unsigned long)(pTable[index]);
2433 + data |= REGBIT(1, I2S_CLKDIV_EN);
2434 + i2s_outw(I2S_DIVCOMP_CFG, data);
2435 +#else
2436 + MSG("Internal REFCLK 15.625Mhz \n");
2437 + pTable = i2s_inclk_15p625Mhz;
2438 + data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2439 + data &= 0xFFFF00FF;
2440 + data |= (unsigned long)(pTable[index]);
2441 + data |= 0x00008000;
2442 + i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2443 +#endif /* CONFIG_I2S_FRAC_DIV */
2444 +#else
2445 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2446 + /* REFCLK = MCLK = 12Mhz */
2447 + MSG("External REFCLK 12Mhz \n");
2448 + pTable = i2s_exclk_12Mhz;
2449 + data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2450 + data &= 0xFFFF00FF;
2451 + data |= (unsigned long)(pTable[index]);
2452 + data |= 0x0000C000;
2453 + i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2454 +#else
2455 + /* REFCLK = MCLK = 12.288Mhz */
2456 + pTable = i2s_exclk_12p288Mhz;
2457 + MSG("External REFCLK 12.288Mhz \n");
2458 + data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2459 + data &= 0xFFFF00FF;
2460 + data |= (unsigned long)(pTable[index]);
2461 + data |= 0x0000C000;
2462 + i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2463 +#endif /* CONFIG_I2S_MCLK_12MHZ */
2464 +#endif /* Not CONFIG_I2S_IN_CLK */
2465 +
2466 +#if defined(CONFIG_I2S_WS_EDGE)
2467 + data = i2s_inw(I2S_I2SCFG);
2468 + data |= REGBIT(0x1, I2S_WS_INV);
2469 + i2s_outw(I2S_I2SCFG, data);
2470 +#endif
2471 +
2472 + return 0;
2473 +}
2474 +
2475 +int i2s_mode_config(u32 slave_en)
2476 +{
2477 + unsigned long data;
2478 +
2479 + if(slave_en==0)
2480 + {
2481 + /* Master mode*/
2482 + _printk("This SoC is in Master mode\n");
2483 +#if defined(CONFIG_RALINK_RT3052)
2484 + data = i2s_inw(I2S_I2SCFG);
2485 + data &= ~REGBIT(0x1, I2S_SLAVE_EN);
2486 + data &= ~REGBIT(0x1, I2S_CLK_OUT_DIS);
2487 + i2s_outw(I2S_I2SCFG, data);
2488 +#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||\
2489 + defined(CONFIG_RALINK_RT5350)||defined(CONFIG_RALINK_RT6855)||\
2490 + defined(CONFIG_RALINK_MT7620)||defined(CONFIG_RALINK_RT6855A)||\
2491 + defined(CONFIG_RALINK_MT7621)||defined(CONFIG_RALINK_MT7628)||\
2492 + defined(CONFIG_ARCH_MT7623)
2493 + data = i2s_inw(I2S_I2SCFG);
2494 + data &= ~REGBIT(0x1, I2S_SLAVE_MODE);
2495 + i2s_outw(I2S_I2SCFG, data);
2496 +#else
2497 + #error "a strange clock mode"
2498 +#endif
2499 + }
2500 + else
2501 + {
2502 + /* Slave mode */
2503 + _printk("This SoC is in Slave mode\n");
2504 +#if defined(CONFIG_RALINK_RT3052)
2505 + data = i2s_inw(I2S_I2SCFG);
2506 + data |= REGBIT(0x1, I2S_SLAVE_EN);
2507 + data |= REGBIT(0x1, I2S_CLK_OUT_DIS);
2508 + i2s_outw(I2S_I2SCFG, data);
2509 +#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||\
2510 + defined(CONFIG_RALINK_RT5350)||defined(CONFIG_RALINK_RT6855)||\
2511 + defined(CONFIG_RALINK_MT7620)||defined(CONFIG_RALINK_RT6855A)||\
2512 + defined(CONFIG_RALINK_MT7621)||defined(CONFIG_RALINK_MT7628)||\
2513 + defined(CONFIG_ARCH_MT7623)
2514 + data = i2s_inw(I2S_I2SCFG);
2515 + data |= REGBIT(0x1, I2S_SLAVE_MODE);
2516 + i2s_outw(I2S_I2SCFG, data);
2517 +#else
2518 + #error "a strange clock mode "
2519 +#endif
2520 + }
2521 +
2522 + return 0;
2523 +}
2524 +
2525 +int i2s_codec_frequency_config(i2s_config_type* ptri2s_config, unsigned long index)
2526 +{
2527 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2528 + unsigned long data;
2529 + unsigned long* pTable;
2530 +#endif
2531 +
2532 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2533 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2534 + pTable = i2s_codec_12Mhz;
2535 + data = pTable[index];
2536 +#endif
2537 +#if defined(CONFIG_I2S_WM8960)
2538 + audiohw_set_frequency(data, ptri2s_config->codec_pll_en);
2539 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2540 + audiohw_set_frequency(data|0x01);
2541 +#endif
2542 +#else
2543 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2544 +#if defined(MT7623_FPGA_BOARD) && defined(CONFIG_I2S_WM8750)
2545 + pTable = i2s_codec_18p432Mhz;
2546 +#else
2547 + pTable = i2s_codec_12p288Mhz;
2548 +#endif
2549 + data = pTable[index];
2550 +#endif
2551 +#if defined(CONFIG_I2S_WM8960)
2552 + audiohw_set_frequency(data, ptri2s_config->codec_pll_en);
2553 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2554 + audiohw_set_frequency(data);
2555 +#endif
2556 +#endif
2557 + return 0;
2558 +}
2559 +
2560 +/*
2561 + * Ralink Audio System Clock Enable
2562 + *
2563 + * I2S_WS : signal direction opposite to/same as I2S_CLK
2564 + *
2565 + * I2S_CLK : Integer division or fractional division
2566 + * REFCLK from Internal or External (external REFCLK not support for fractional division)
2567 + * Suppose external REFCLK always be the same as external MCLK
2568 + *
2569 + * MCLK : External OSC or internal generation
2570 + *
2571 + */
2572 +int i2s_clock_enable(i2s_config_type* ptri2s_config)
2573 +{
2574 + unsigned long index;
2575 + /* audio sampling rate decision */
2576 + switch(ptri2s_config->srate)
2577 + {
2578 + case 8000:
2579 + index = 0;
2580 + break;
2581 + case 11025:
2582 + index = 1;
2583 + break;
2584 + case 12000:
2585 + index = 2;
2586 + break;
2587 + case 16000:
2588 + index = 3;
2589 + break;
2590 + case 22050:
2591 + index = 4;
2592 + break;
2593 + case 24000:
2594 + index = 5;
2595 + break;
2596 + case 32000:
2597 + index = 6;
2598 + break;
2599 + case 44100:
2600 + index = 7;
2601 + break;
2602 + case 48000:
2603 + index = 8;
2604 + break;
2605 + case 88200:
2606 + index = 9;
2607 + break;
2608 + case 96000:
2609 + index = 10;
2610 + break;
2611 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2612 + case 176000:
2613 + index = 11;
2614 + break;
2615 + case 192000:
2616 + index = 12;
2617 + break;
2618 +#endif
2619 + default:
2620 + index = 7;
2621 + }
2622 +#ifdef MT7621_ASIC_BOARD
2623 + /* Set pll config */
2624 + i2s_pll_config_mt7621(index);
2625 +#endif
2626 +#ifdef MT7623_ASIC_BOARD
2627 + /* Set pll config */
2628 + i2s_pll_config_mt7623(index);
2629 +#endif
2630 +
2631 + /* enable internal MCLK */
2632 +#if defined(CONFIG_I2S_IN_MCLK)
2633 +#if defined(CONFIG_RALINK_MT7621)
2634 + i2s_pll_refclk_set();
2635 +#endif
2636 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2637 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
2638 + i2s_driving_strength_adjust();
2639 +#endif
2640 + i2s_refclk_12m_enable();
2641 +#endif /* MCLK_12MHZ */
2642 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
2643 + i2s_refclk_12p288m_enable();
2644 +#endif /* MCLK_12P288MHZ */
2645 +#if defined(CONFIG_I2S_MCLK_18P432MHZ)
2646 + i2s_refclk_18p432m_enable(index);
2647 +#endif
2648 + i2s_refclk_gpio_out_config();
2649 +
2650 +#else
2651 + MSG("Disable SoC MCLK, use external OSC\n");
2652 + i2s_refclk_disable();
2653 + i2s_refclk_gpio_in_config();
2654 +#endif /* CONFIG_I2S_IN_MCLK */
2655 +
2656 + i2s_share_pin_config(ptri2s_config);
2657 +
2658 + if(ptri2s_config->slave_en==0)
2659 + {
2660 + /* Setup I2S_WS and I2S_CLK */
2661 + i2s_ws_config(ptri2s_config, index);
2662 + }
2663 +
2664 + i2s_mode_config(ptri2s_config->slave_en);
2665 +
2666 + if(!ptri2s_config->bALSAEnable)
2667 + {
2668 +#if defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)|| defined(CONFIG_I2S_WM8960)
2669 + i2s_codec_enable(ptri2s_config);
2670 +#endif
2671 + i2s_codec_frequency_config(ptri2s_config,index);
2672 + }
2673 +
2674 + return 0;
2675 +}
2676 +
2677 +int i2s_clock_disable(i2s_config_type* ptri2s_config)
2678 +{
2679 + if(!ptri2s_config->bALSAEnable)
2680 + {
2681 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2682 + i2s_codec_disable(ptri2s_config);
2683 +#endif
2684 + }
2685 +
2686 + /* disable internal MCLK */
2687 +#if defined(CONFIG_I2S_IN_MCLK)
2688 + i2s_refclk_disable();
2689 + i2s_refclk_gpio_in_config();
2690 +#endif
2691 + return 0;
2692 +}
2693 +
2694 +
2695 +int i2s_codec_enable(i2s_config_type* ptri2s_config)
2696 +{
2697 +
2698 + int AIn = 0, AOut = 0;
2699 +#if 1
2700 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2701 + /* Codec initialization */
2702 + audiohw_preinit();
2703 +#endif
2704 +#endif
2705 +
2706 +#if defined(CONFIG_I2S_WM8960)
2707 + if(ptri2s_config->codec_pll_en)
2708 + {
2709 + MSG("Codec PLL EN = %d\n", pi2s_config->codec_pll_en);
2710 + audiohw_set_apll(ptri2s_config->srate);
2711 + }
2712 +#endif
2713 +
2714 +#if defined(CONFIG_I2S_TXRX)
2715 + if((ptri2s_config->bTxDMAEnable) || (ptri2s_config->txrx_coexist))
2716 + AOut = 1;
2717 + if((ptri2s_config->bRxDMAEnable) || (ptri2s_config->txrx_coexist))
2718 + AIn = 1;
2719 +#if defined(CONFIG_I2S_WM8960)
2720 + audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut, ptri2s_config->codec_pll_en, ptri2s_config->wordlen_24b);
2721 + audiohw_micboost(ptri2s_config->micboost);
2722 + audiohw_micin(ptri2s_config->micin);
2723 +#elif defined(CONFIG_I2S_WM8750)
2724 + audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut, ptri2s_config->wordlen_24b);
2725 +#endif
2726 + MSG("AOut=%d, AIn=%d\n", AOut, AIn);
2727 +#else
2728 +#if defined(CONFIG_I2S_WM8750)
2729 + audiohw_postinit(!(ptri2s_config->slave_en), 0, 1);
2730 +#elif defined(CONFIG_I2S_WM8960)
2731 + audiohw_postinit(!(ptri2s_config->slave_en), 1, 1, ptri2s_config->codec_pll_en);
2732 +#elif defined(CONFIG_I2S_WM8751)
2733 + if(ptri2s_config->slave_en==0)
2734 + audiohw_postinit(1,1);
2735 + else
2736 + audiohw_postinit(0,1);
2737 +#endif
2738 +#endif
2739 + return 0;
2740 +}
2741 +
2742 +int i2s_codec_disable(i2s_config_type* ptri2s_config)
2743 +{
2744 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2745 + audiohw_close();
2746 +#endif
2747 + return 0;
2748 +}
2749 +
2750 +int i2s_reset_config(i2s_config_type* ptri2s_config)
2751 +{
2752 + unsigned long data;
2753 +
2754 + /* RESET bit: write 1 clear */
2755 +#if defined(CONFIG_RALINK_RT6855A)
2756 + data = i2s_inw(RALINK_SYSCTL_BASE+0x834);
2757 + data |= (1<<17);
2758 + i2s_outw(RALINK_SYSCTL_BASE+0x834, data);
2759 +
2760 + data = i2s_inw(RALINK_SYSCTL_BASE+0x834);
2761 + data &= ~(1<<17);
2762 + i2s_outw(RALINK_SYSCTL_BASE+0x834, data);
2763 +#elif defined(CONFIG_ARCH_MT7623)
2764 + data = i2s_inw(0xFB000000+0x34);
2765 + data |= (1<<17);
2766 + i2s_outw(0xFB000000+0x34, data);
2767 +
2768 + data = i2s_inw(0xFB000000+0x34);
2769 + data &= ~(1<<17);
2770 + i2s_outw(0xFB000000+0x34, data);
2771 +#else
2772 + data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2773 + data |= (1<<17);
2774 + i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2775 +
2776 + data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2777 + data &= ~(1<<17);
2778 + i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2779 +
2780 +#if 0 /* Reset GDMA */
2781 + data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2782 + data |= (1<<14);
2783 + i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2784 +
2785 + data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2786 + data &= ~(1<<14);
2787 + i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2788 +#endif
2789 +#endif
2790 + _printk("I2S reset complete!!\n");
2791 + return 0;
2792 +}
2793 +
2794 +int i2s_tx_config(i2s_config_type* ptri2s_config)
2795 +{
2796 + unsigned long data;
2797 + /* set I2S_I2SCFG */
2798 + data = i2s_inw(I2S_I2SCFG);
2799 + data &= 0xFFFFFF81;
2800 + data |= REGBIT(ptri2s_config->tx_ff_thres, I2S_TX_FF_THRES);
2801 + data |= REGBIT(ptri2s_config->tx_ch_swap, I2S_TX_CH_SWAP);
2802 +#if defined(CONFIG_RALINK_RT6855A)
2803 + data |= REGBIT(1, I2S_BYTE_SWAP);
2804 +#endif
2805 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2806 + MSG("TX:wordLen=%d, sysEndian=%d\n", ptri2s_config->wordlen_24b, ptri2s_config->sys_endian);
2807 + data |= REGBIT(ptri2s_config->wordlen_24b, I2S_DATA_24BIT);
2808 + data |= REGBIT(ptri2s_config->sys_endian, I2S_SYS_ENDIAN);
2809 + data |= REGBIT(ptri2s_config->little_edn, I2S_LITTLE_ENDIAN);
2810 +#endif
2811 + data &= ~REGBIT(1, I2S_TX_CH0_OFF);
2812 + data &= ~REGBIT(1, I2S_TX_CH1_OFF);
2813 + i2s_outw(I2S_I2SCFG, data);
2814 +
2815 + /* set I2S_I2SCFG1 */
2816 + MSG("internal loopback: %d\n", ptri2s_config->lbk);
2817 + data = i2s_inw(I2S_I2SCFG1);
2818 + data |= REGBIT(ptri2s_config->lbk, I2S_LBK_EN);
2819 + data |= REGBIT(ptri2s_config->extlbk, I2S_EXT_LBK_EN);
2820 + data &= 0xFFFFFFFC;
2821 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2822 + data |= REGBIT(ptri2s_config->fmt, I2S_DATA_FMT);
2823 +#endif
2824 + i2s_outw(I2S_I2SCFG1, data);
2825 +
2826 + return 0;
2827 +}
2828 +
2829 +int i2s_rx_config(i2s_config_type* ptri2s_config)
2830 +{
2831 + unsigned long data;
2832 + /* set I2S_I2SCFG */
2833 + data = i2s_inw(I2S_I2SCFG);
2834 + data &= 0xFFFF81FF;
2835 + data |= REGBIT(ptri2s_config->rx_ff_thres, I2S_RX_FF_THRES);
2836 + data |= REGBIT(ptri2s_config->rx_ch_swap, I2S_RX_CH_SWAP);
2837 + data &= ~REGBIT(1, I2S_RX_CH0_OFF);
2838 + data &= ~REGBIT(1, I2S_RX_CH1_OFF);
2839 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2840 + MSG("RX:wordLen=%d, sysEndian=%d\n", ptri2s_config->wordlen_24b, ptri2s_config->sys_endian);
2841 + data |= REGBIT(ptri2s_config->wordlen_24b, I2S_DATA_24BIT);
2842 + data |= REGBIT(ptri2s_config->sys_endian, I2S_SYS_ENDIAN);
2843 + data |= REGBIT(ptri2s_config->little_edn, I2S_LITTLE_ENDIAN);
2844 +#endif
2845 + i2s_outw(I2S_I2SCFG, data);
2846 +
2847 + /* set I2S_I2SCFG1 */
2848 + data = i2s_inw(I2S_I2SCFG1);
2849 + data |= REGBIT(ptri2s_config->lbk, I2S_LBK_EN);
2850 + data |= REGBIT(ptri2s_config->extlbk, I2S_EXT_LBK_EN);
2851 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2852 + data &= 0xFFFFFFFC;
2853 + data |= REGBIT(ptri2s_config->fmt, I2S_DATA_FMT);
2854 +#endif
2855 + i2s_outw(I2S_I2SCFG1, data);
2856 +
2857 + return 0;
2858 +}
2859 +
2860 +/* Turn On Tx DMA and INT */
2861 +int i2s_tx_enable(i2s_config_type* ptri2s_config)
2862 +{
2863 + unsigned long data;
2864 +
2865 +#if defined(I2S_HW_INTERRUPT_EN)
2866 + data = i2s_inw(I2S_INT_EN);
2867 + data |= REGBIT(0x1, I2S_TX_INT3_EN); /* FIFO DMA fault */
2868 + data |= REGBIT(0x1, I2S_TX_INT2_EN); /* FIFO overrun */
2869 + data |= REGBIT(0x1, I2S_TX_INT1_EN); /* FIFO underrun */
2870 + data |= REGBIT(0x1, I2S_TX_INT0_EN); /* FIFO below threshold */
2871 + i2s_outw(I2S_INT_EN, data);
2872 +#endif
2873 +
2874 + data = i2s_inw(I2S_I2SCFG);
2875 +#if defined(CONFIG_I2S_TXRX)
2876 + data |= REGBIT(0x1, I2S_TX_EN);
2877 +#endif
2878 + data |= REGBIT(0x1, I2S_DMA_EN);
2879 + i2s_outw(I2S_I2SCFG, data);
2880 +
2881 + data = i2s_inw(I2S_I2SCFG);
2882 + data |= REGBIT(0x1, I2S_EN);
2883 + i2s_outw(I2S_I2SCFG, data);
2884 +
2885 + MSG("i2s_tx_enable done\n");
2886 + return I2S_OK;
2887 +}
2888 +
2889 +/* Turn On Rx DMA and INT */
2890 +int i2s_rx_enable(i2s_config_type* ptri2s_config)
2891 +{
2892 + unsigned long data;
2893 +
2894 +#if defined(I2S_HW_INTERRUPT_EN)
2895 + data = i2s_inw(I2S_INT_EN);
2896 + data |= REGBIT(0x1, I2S_RX_INT3_EN); /* FIFO DMA fault */
2897 + data |= REGBIT(0x1, I2S_RX_INT2_EN); /* FIFO overrun */
2898 + data |= REGBIT(0x1, I2S_RX_INT1_EN); /* FIFO underrun */
2899 + data |= REGBIT(0x1, I2S_RX_INT0_EN); /* FIFO below threshold */
2900 + i2s_outw(I2S_INT_EN, data);
2901 +#endif
2902 +
2903 + data = i2s_inw(I2S_I2SCFG);
2904 +#if defined(CONFIG_I2S_TXRX)
2905 + data |= REGBIT(0x1, I2S_RX_EN);
2906 +#endif
2907 + data |= REGBIT(0x1, I2S_DMA_EN);
2908 + i2s_outw(I2S_I2SCFG, data);
2909 +
2910 + data = i2s_inw(I2S_I2SCFG);
2911 + data |= REGBIT(0x1, I2S_EN);
2912 + i2s_outw(I2S_I2SCFG, data);
2913 +
2914 + MSG("i2s_rx_enable done\n");
2915 + return I2S_OK;
2916 +}
2917 +/* Turn Off Tx DMA and INT */
2918 +int i2s_tx_disable(i2s_config_type* ptri2s_config)
2919 +{
2920 + unsigned long data;
2921 +
2922 +#if defined(I2S_HW_INTERRUPT_EN)
2923 + data = i2s_inw(I2S_INT_EN);
2924 + data &= ~REGBIT(0x1, I2S_TX_INT3_EN);
2925 + data &= ~REGBIT(0x1, I2S_TX_INT2_EN);
2926 + data &= ~REGBIT(0x1, I2S_TX_INT1_EN);
2927 + data &= ~REGBIT(0x1, I2S_TX_INT0_EN);
2928 + i2s_outw(I2S_INT_EN, data);
2929 +#endif
2930 +
2931 + data = i2s_inw(I2S_I2SCFG);
2932 +#if defined(CONFIG_I2S_TXRX)
2933 + data &= ~REGBIT(0x1, I2S_TX_EN);
2934 +#endif
2935 + if(ptri2s_config->bRxDMAEnable==0)
2936 + {
2937 + ptri2s_config->bTxDMAEnable = 0;
2938 + data &= ~REGBIT(0x1, I2S_DMA_EN);
2939 + data &= ~REGBIT(0x1, I2S_EN);
2940 + }
2941 + i2s_outw(I2S_I2SCFG, data);
2942 + return I2S_OK;
2943 +}
2944 +/* Turn Off Rx DMA and INT */
2945 +int i2s_rx_disable(i2s_config_type* ptri2s_config)
2946 +{
2947 + unsigned long data;
2948 +
2949 +#if defined(I2S_HW_INTERRUPT_EN)
2950 + data = i2s_inw(I2S_INT_EN);
2951 + data &= ~REGBIT(0x1, I2S_RX_INT3_EN);
2952 + data &= ~REGBIT(0x1, I2S_RX_INT2_EN);
2953 + data &= ~REGBIT(0x1, I2S_RX_INT1_EN);
2954 + data &= ~REGBIT(0x1, I2S_RX_INT0_EN);
2955 + i2s_outw(I2S_INT_EN, data);
2956 +#endif
2957 +
2958 + data = i2s_inw(I2S_I2SCFG);
2959 +#if defined(CONFIG_I2S_TXRX)
2960 + data &= ~REGBIT(0x1, I2S_RX_EN);
2961 +#endif
2962 + if(ptri2s_config->bTxDMAEnable==0)
2963 + {
2964 + ptri2s_config->bRxDMAEnable = 0;
2965 + data &= ~REGBIT(0x1, I2S_DMA_EN);
2966 + data &= ~REGBIT(0x1, I2S_EN);
2967 + }
2968 + i2s_outw(I2S_I2SCFG, data);
2969 + return I2S_OK;
2970 +}
2971 +
2972 +int i2s_dma_tx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch)
2973 +{
2974 + int tx_r_idx;
2975 +
2976 + if ((pi2s_config->bALSAEnable==1) && (pi2s_config->bALSAMMAPEnable==1))
2977 + tx_r_idx = (pi2s_config->tx_r_idx + ALSA_MMAP_IDX_SHIFT)%MAX_I2S_PAGE;
2978 + else
2979 + tx_r_idx = pi2s_config->tx_r_idx;
2980 +
2981 + if(dma_ch==GDMA_I2S_TX0)
2982 + {
2983 +#if defined(CONFIG_I2S_MMAP)
2984 + dma_sync_single_for_device(NULL, i2s_mmap_addr[tx_r_idx], I2S_PAGE_SIZE, DMA_TO_DEVICE);
2985 +#if defined(ARM_ARCH)
2986 + GdmaI2sTx(i2s_mmap_addr[tx_r_idx], I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2987 +#else
2988 + GdmaI2sTx((u32)(pi2s_config->pMMAPTxBufPtr[tx_r_idx]), I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2989 +#endif
2990 +#else
2991 + memcpy(pi2s_config->pPage0TxBuf8ptr, pi2s_config->pMMAPTxBufPtr[tx_r_idx], I2S_PAGE_SIZE);
2992 +#if defined(ARM_ARCH)
2993 + GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2994 +#else
2995 + GdmaI2sTx((u32)(pi2s_config->pPage0TxBuf8ptr), I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2996 +#endif
2997 +#endif
2998 + pi2s_config->dmach = GDMA_I2S_TX0;
2999 + pi2s_config->tx_r_idx = (pi2s_config->tx_r_idx+1)%MAX_I2S_PAGE;
3000 + }
3001 + else
3002 + {
3003 +#if defined(CONFIG_I2S_MMAP)
3004 + dma_sync_single_for_device(NULL, i2s_mmap_addr[tx_r_idx], I2S_PAGE_SIZE, DMA_TO_DEVICE);
3005 +#if defined(ARM_ARCH)
3006 + GdmaI2sTx(i2s_mmap_addr[tx_r_idx], I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3007 +#else
3008 + GdmaI2sTx((u32)(pi2s_config->pMMAPTxBufPtr[tx_r_idx]), I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3009 +#endif
3010 +#else
3011 + memcpy(pi2s_config->pPage1TxBuf8ptr, pi2s_config->pMMAPTxBufPtr[tx_r_idx], I2S_PAGE_SIZE);
3012 +#if defined(ARM_ARCH)
3013 + GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3014 +#else
3015 + GdmaI2sTx((u32)(pi2s_config->pPage1TxBuf8ptr), I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3016 +#endif
3017 +#endif
3018 + pi2s_config->dmach = GDMA_I2S_TX1;
3019 + pi2s_config->tx_r_idx = (pi2s_config->tx_r_idx+1)%MAX_I2S_PAGE;
3020 + }
3021 +#if defined(CONFIG_I2S_WITH_AEC)
3022 + if(aecFuncP->AECFeEnq){
3023 + aecFuncP->AECFeEnq(0,pi2s_config->pMMAPTxBufPtr[pi2s_config->tx_r_idx],I2S_PAGE_SIZE);
3024 + }
3025 +#endif
3026 + return 0;
3027 +}
3028 +
3029 +int i2s_dma_tx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch)
3030 +{
3031 + if(dma_ch==GDMA_I2S_TX0)
3032 + {
3033 + memset(pi2s_config->pPage0TxBuf8ptr, 0, I2S_PAGE_SIZE);
3034 +#if defined(ARM_ARCH)
3035 + GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3036 +#else
3037 + GdmaI2sTx((u32)pi2s_config->pPage0TxBuf8ptr, I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3038 +#endif
3039 + }
3040 + else
3041 + {
3042 + memset(pi2s_config->pPage1TxBuf8ptr, 0, I2S_PAGE_SIZE);
3043 +#if defined(ARM_ARCH)
3044 + GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3045 +#else
3046 + GdmaI2sTx((u32)pi2s_config->pPage1TxBuf8ptr, I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3047 +#endif
3048 + }
3049 + return 0;
3050 +}
3051 +
3052 +int i2s_dma_rx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch)
3053 +{
3054 + int rx_w_idx;
3055 +
3056 + pi2s_config->rx_w_idx = (pi2s_config->rx_w_idx+1)%MAX_I2S_PAGE;
3057 +
3058 + if ((pi2s_config->bALSAEnable==1) && (pi2s_config->bALSAMMAPEnable==1))
3059 + rx_w_idx = (pi2s_config->rx_w_idx+ALSA_MMAP_IDX_SHIFT)%MAX_I2S_PAGE;
3060 + else
3061 + rx_w_idx = (pi2s_config->rx_w_idx)%MAX_I2S_PAGE;
3062 +
3063 + if(dma_ch==GDMA_I2S_RX0)
3064 + {
3065 +
3066 +#ifdef CONFIG_I2S_MMAP
3067 + dma_sync_single_for_device(NULL, i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], I2S_PAGE_SIZE, DMA_FROM_DEVICE);
3068 +#if defined(ARM_ARCH)
3069 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, (u32)i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3070 +#else
3071 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pMMAPRxBufPtr[rx_w_idx]), 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3072 +#endif
3073 +#else
3074 + memcpy(pi2s_config->pMMAPRxBufPtr[rx_w_idx], pi2s_config->pPage0RxBuf8ptr, I2S_PAGE_SIZE);
3075 +#if defined(ARM_ARCH)
3076 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3077 +#else
3078 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pPage0RxBuf8ptr), 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3079 +#endif
3080 +#endif
3081 + pi2s_config->dmach = GDMA_I2S_RX0;
3082 + }
3083 + else
3084 + {
3085 +
3086 +#ifdef CONFIG_I2S_MMAP
3087 + dma_sync_single_for_device(NULL, i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], I2S_PAGE_SIZE, DMA_FROM_DEVICE);
3088 +#if defined(ARM_ARCH)
3089 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, (u32)i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3090 +#else
3091 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pMMAPRxBufPtr[rx_w_idx]), 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3092 +#endif
3093 +#else
3094 + memcpy(pi2s_config->pMMAPRxBufPtr[rx_w_idx], pi2s_config->pPage1RxBuf8ptr, I2S_PAGE_SIZE);
3095 +#if defined(ARM_ARCH)
3096 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3097 +#else
3098 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pPage1RxBuf8ptr), 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3099 +#endif
3100 +#endif
3101 + pi2s_config->dmach = GDMA_I2S_RX1;
3102 +
3103 + }
3104 +#if defined(CONFIG_I2S_WITH_AEC)
3105 + if(aecFuncP->AECNeEnq){
3106 + aecFuncP->AECNeEnq(0,pi2s_config->pMMAPRxBufPtr[rx_w_idx],I2S_PAGE_SIZE);
3107 + }
3108 +#endif
3109 + return 0;
3110 +}
3111 +
3112 +int i2s_dma_rx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch)
3113 +{
3114 + if(dma_ch==GDMA_I2S_RX0)
3115 + {
3116 + memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3117 +#if defined(ARM_ARCH)
3118 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3119 +#else
3120 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3121 +#endif
3122 + }
3123 + else
3124 + {
3125 + memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3126 +#if defined(ARM_ARCH)
3127 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3128 +#else
3129 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3130 +#endif
3131 + }
3132 + return 0;
3133 +}
3134 +
3135 +void i2s_dma_tx_handler(u32 dma_ch)
3136 +{
3137 + pi2s_config->enLable = 1; /* TX:enLabel=1; RX:enLabel=2 */
3138 +
3139 + if(pi2s_config->bTxDMAEnable==0)
3140 + {
3141 + if(pi2s_config->end_cnt != 0)
3142 + {
3143 + i2s_dma_tx_transf_data(pi2s_config, dma_ch);
3144 + pi2s_config->end_cnt --;
3145 + MSG("end_cnt = %d, r_idx = %d\n", pi2s_config->end_cnt, pi2s_config->tx_r_idx);
3146 + }
3147 + else
3148 + {
3149 + pi2s_config->tx_stop_cnt++;
3150 + i2s_dma_tx_soft_stop(pi2s_config, dma_ch);
3151 + MSG("tx_stop=%d, ch=%d\n", pi2s_config->tx_stop_cnt, dma_ch);
3152 + if (pi2s_config->tx_stop_cnt == 3)
3153 + {
3154 + wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3155 + _printk("T:wake up!!\n");
3156 + }
3157 + }
3158 + return;
3159 + }
3160 +
3161 + pi2s_config->tx_isr_cnt++;
3162 +
3163 +#ifdef I2S_STATISTIC
3164 + i2s_int_status(dma_ch);
3165 +#endif
3166 + /* FIXME */
3167 + if(pi2s_config->bALSAEnable)
3168 + {
3169 + if(pi2s_config->dmaStat[STREAM_PLAYBACK])
3170 + {
3171 + if(!pi2s_config->bTrigger[STREAM_PLAYBACK]){
3172 + //_printk("trigger stop: rIdx:%d widx:%d\n", pi2s_config->tx_r_idx,pi2s_config->tx_w_idx);
3173 + i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3174 + if(pi2s_config->bPreTrigger[STREAM_PLAYBACK]){
3175 + /* mtk04880 commented:
3176 + * for corner case, there are cases which ALSA Trigger stop before disabling DMA.
3177 + * For which case, it needs to keep call snd_pcm_elapased to keep ALSA hw ptr updating.
3178 + * It is so called post stop handlment.
3179 + */
3180 + //_printk("post-stop\n");
3181 + goto EXIT;
3182 + }
3183 + else{
3184 + //_printk("pre-stop\n");
3185 + wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3186 + return;
3187 + }
3188 + }
3189 + else{
3190 + if(!pi2s_config->bPreTrigger[STREAM_PLAYBACK])
3191 + pi2s_config->bPreTrigger[STREAM_PLAYBACK] = 1;
3192 +
3193 + }
3194 + }
3195 + }
3196 + else
3197 + {
3198 + if(pi2s_config->tx_r_idx==pi2s_config->tx_w_idx)
3199 + {
3200 + /* Buffer Empty */
3201 + MSG("TXBE r=%d w=%d[i=%u,c=%u]\n",pi2s_config->tx_r_idx,pi2s_config->tx_w_idx,pi2s_config->tx_isr_cnt,dma_ch);
3202 +#ifdef I2S_STATISTIC
3203 + pi2s_status->txbuffer_unrun++;
3204 +#endif
3205 + i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3206 + goto EXIT;
3207 + }
3208 + }
3209 +
3210 + if(pi2s_config->pMMAPTxBufPtr[pi2s_config->tx_r_idx]==NULL)
3211 + {
3212 + MSG("mmap buf NULL [%d]\n",pi2s_config->tx_r_idx);
3213 + i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3214 +
3215 + goto EXIT;
3216 + }
3217 +
3218 + if(pi2s_config->tx_pause_en == 1)
3219 + {
3220 + /* Enable PAUSE */
3221 + MSG("TX pause now\n");
3222 + i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3223 +
3224 + goto EXIT;
3225 + }
3226 +
3227 +#ifdef I2S_STATISTIC
3228 + pi2s_status->txbuffer_len--;
3229 +#endif
3230 + i2s_dma_tx_transf_data(pi2s_config, dma_ch);
3231 +
3232 +EXIT:
3233 +#if defined(CONFIG_SND_MT76XX_SOC)
3234 + if(pi2s_config->bALSAEnable == 1){
3235 + if(pi2s_config->pss[STREAM_PLAYBACK])
3236 + snd_pcm_period_elapsed(pi2s_config->pss[STREAM_PLAYBACK]);
3237 + }
3238 +#endif
3239 + wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3240 + return;
3241 +}
3242 +
3243 +void i2s_dma_rx_handler(u32 dma_ch)
3244 +{
3245 + pi2s_config->enLable = 2; /* TX:enLabel=1; RX:enLabel=2 */
3246 +#if defined(CONFIG_I2S_TXRX)
3247 + if(pi2s_config->rx_isr_cnt==0)
3248 + {
3249 + pi2s_config->next_p0_idx = 0;
3250 + pi2s_config->next_p1_idx = 1;
3251 + }
3252 + pi2s_config->rx_isr_cnt++;
3253 +
3254 +#ifdef I2S_STATISTIC
3255 + i2s_int_status(dma_ch);
3256 +#endif
3257 +
3258 + if (pi2s_config->bRxDMAEnable==0)
3259 + {
3260 + pi2s_config->rx_stop_cnt++;
3261 + i2s_dma_rx_soft_stop(pi2s_config, dma_ch);
3262 + MSG("rx_stop=%d\n", pi2s_config->rx_stop_cnt);
3263 +
3264 + if(pi2s_config->rx_stop_cnt == 2)
3265 + {
3266 + wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3267 + _printk("R:wake up!!\n");
3268 + }
3269 + return;
3270 + }
3271 +
3272 + if(pi2s_config->bALSAEnable)
3273 + {
3274 + if(pi2s_config->dmaStat[STREAM_CAPTURE]){
3275 + if(!pi2s_config->bTrigger[STREAM_CAPTURE]){
3276 + MSG("trigger stop: rIdx:%d widx:%d\n", pi2s_config->rx_r_idx,pi2s_config->rx_w_idx);
3277 + i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3278 + wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3279 + return;
3280 + }
3281 + }
3282 + }
3283 + else
3284 + {
3285 + if(((pi2s_config->rx_w_idx+1)%MAX_I2S_PAGE)==pi2s_config->rx_r_idx){
3286 + /* Buffer Full */
3287 + MSG("RXBF r=%d w=%d[i=%u,c=%u]\n",pi2s_config->rx_r_idx,pi2s_config->rx_w_idx,pi2s_config->rx_isr_cnt,dma_ch);
3288 +#ifdef I2S_STATISTIC
3289 + pi2s_status->rxbuffer_unrun++;
3290 +#endif
3291 + i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3292 + goto EXIT;
3293 + }
3294 + }
3295 +
3296 + if(pi2s_config->rx_pause_en == 1)
3297 + {
3298 + /* Enable PAUSE */
3299 + i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3300 +
3301 + goto EXIT;
3302 + }
3303 +
3304 +#ifdef I2S_STATISTIC
3305 + pi2s_status->rxbuffer_len++;
3306 +#endif
3307 + i2s_dma_rx_transf_data(pi2s_config, dma_ch);
3308 +
3309 +EXIT:
3310 +#if defined(CONFIG_SND_MT76XX_SOC)
3311 + if(pi2s_config->bALSAEnable == 1){
3312 + if(pi2s_config->pss[STREAM_CAPTURE])
3313 + snd_pcm_period_elapsed(pi2s_config->pss[STREAM_CAPTURE]);
3314 + }
3315 +#endif
3316 + wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3317 +#endif
3318 + return;
3319 +}
3320 +
3321 +#ifdef I2S_STATISTIC
3322 +void i2s_int_status(u32 dma_ch)
3323 +{
3324 + u32 i2s_status;
3325 +
3326 + if((pi2s_config->tx_isr_cnt>0)||(pi2s_config->rx_isr_cnt>0))
3327 + {
3328 + i2s_status = i2s_inw(I2S_INT_STATUS);
3329 +
3330 + if(i2s_status&REGBIT(1, I2S_TX_DMA_FAULT))
3331 + {
3332 + pi2s_status->txdmafault++;
3333 + }
3334 + if(i2s_status&REGBIT(1, I2S_TX_OVRUN))
3335 + {
3336 + pi2s_status->txovrun++;
3337 + }
3338 + if(i2s_status&REGBIT(1, I2S_TX_UNRUN))
3339 + {
3340 + pi2s_status->txunrun++;
3341 + }
3342 + if(i2s_status&REGBIT(1, I2S_TX_THRES))
3343 + {
3344 + pi2s_status->txthres++;
3345 + }
3346 + if(i2s_status&REGBIT(1, I2S_RX_DMA_FAULT))
3347 + {
3348 + pi2s_status->rxdmafault++;
3349 + }
3350 + if(i2s_status&REGBIT(1, I2S_RX_OVRUN))
3351 + {
3352 + pi2s_status->rxovrun++;
3353 + }
3354 + if(i2s_status&REGBIT(1, I2S_RX_UNRUN))
3355 + {
3356 + pi2s_status->rxunrun++;
3357 + }
3358 + if(i2s_status&REGBIT(1, I2S_RX_THRES))
3359 + {
3360 + pi2s_status->rxthres++;
3361 + }
3362 + }
3363 +#if 0
3364 + if(pi2s_config->enLable == 1)
3365 + {
3366 + if((pi2s_config->tx_isr_cnt>0) && (pi2s_config->tx_isr_cnt%40==0))
3367 + {
3368 + MSG("tisr i=%u,ch=%u,o=%u,u=%d,s=%X [r=%d,w=%d]\n",\
3369 + pi2s_config->tx_isr_cnt,dma_ch,pi2s_status->txovrun,pi2s_status->txunrun,\
3370 + i2s_inw(I2S_INT_STATUS),pi2s_config->tx_r_idx,pi2s_config->tx_w_idx);
3371 + }
3372 + }
3373 +
3374 + if(pi2s_config->enLable == 2)
3375 + {
3376 + if((pi2s_config->rx_isr_cnt>0) && (pi2s_config->rx_isr_cnt%40==0))
3377 + {
3378 + MSG("risr i=%u,ch=%u,o=%u,u=%d,s=%X [r=%d,w=%d]\n",\
3379 + pi2s_config->rx_isr_cnt,dma_ch,pi2s_status->rxovrun,pi2s_status->rxunrun,\
3380 + i2s_inw(I2S_INT_STATUS),pi2s_config->rx_r_idx,pi2s_config->rx_w_idx);
3381 + }
3382 + }
3383 +#endif
3384 +
3385 + *(unsigned long*)(I2S_INT_STATUS) = 0xFFFFFFFF;
3386 +}
3387 +#endif
3388 +
3389 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
3390 +irqreturn_t i2s_irq_isr(int irq, void *irqaction)
3391 +{
3392 + u32 i2s_status;
3393 +
3394 + //MSG("i2s_irq_isr [0x%08X]\n",i2s_inw(I2S_INT_STATUS));
3395 + if((pi2s_config->tx_isr_cnt>0)||(pi2s_config->rx_isr_cnt>0))
3396 + {
3397 + i2s_status = i2s_inw(I2S_INT_STATUS);
3398 + MSG("i2s_irq_isr [0x%08X]\n",i2s_status);
3399 + }
3400 + else
3401 + return IRQ_HANDLED;
3402 +
3403 + if(i2s_status&REGBIT(1, I2S_TX_DMA_FAULT))
3404 + {
3405 +#ifdef I2S_STATISTIC
3406 + pi2s_status->txdmafault++;
3407 +#endif
3408 + }
3409 + if(i2s_status&REGBIT(1, I2S_TX_OVRUN))
3410 + {
3411 +#ifdef I2S_STATISTIC
3412 + pi2s_status->txovrun++;
3413 +#endif
3414 + }
3415 + if(i2s_status&REGBIT(1, I2S_TX_UNRUN))
3416 + {
3417 +#ifdef I2S_STATISTIC
3418 + pi2s_status->txunrun++;
3419 +#endif
3420 + }
3421 + if(i2s_status&REGBIT(1, I2S_TX_THRES))
3422 + {
3423 +#ifdef I2S_STATISTIC
3424 + pi2s_status->txthres++;
3425 +#endif
3426 + }
3427 + if(i2s_status&REGBIT(1, I2S_RX_DMA_FAULT))
3428 + {
3429 +#ifdef I2S_STATISTIC
3430 + pi2s_status->rxdmafault++;
3431 +#endif
3432 + }
3433 + if(i2s_status&REGBIT(1, I2S_RX_OVRUN))
3434 + {
3435 +#ifdef I2S_STATISTIC
3436 + pi2s_status->rxovrun++;
3437 +#endif
3438 + }
3439 + if(i2s_status&REGBIT(1, I2S_RX_UNRUN))
3440 + {
3441 +#ifdef I2S_STATISTIC
3442 + pi2s_status->rxunrun++;
3443 +#endif
3444 + }
3445 + if(i2s_status&REGBIT(1, I2S_RX_THRES))
3446 + {
3447 +#ifdef I2S_STATISTIC
3448 + pi2s_status->rxthres++;
3449 +#endif
3450 + }
3451 + i2s_outw(I2S_INT_STATUS, 0xFFFFFFFF);
3452 + return IRQ_HANDLED;
3453 +}
3454 +#endif
3455 +
3456 +void i2s_tx_task(unsigned long pData)
3457 +{
3458 + unsigned long flags;
3459 + spin_lock_irqsave(&pi2s_config->lock, flags);
3460 + //if (pi2s_config->bTxDMAEnable!=0)
3461 + {
3462 + if (pi2s_config->tx_unmask_ch!=0)
3463 + {
3464 + u32 dmach = pi2s_config->tx_unmask_ch;
3465 + u32 ch;
3466 + for (ch = 0; ch < 16; ch++)
3467 + {
3468 + if (dmach& (1<<ch))
3469 + {
3470 + MSG("do unmask ch%d tisr=%d in tx_isr\n",ch,pi2s_config->tx_isr_cnt);
3471 + GdmaUnMaskChannel(ch);
3472 + }
3473 + }
3474 + pi2s_config->tx_unmask_ch = 0;
3475 + }
3476 + }
3477 + spin_unlock_irqrestore(&pi2s_config->lock, flags);
3478 +}
3479 +
3480 +void i2s_rx_task(unsigned long pData)
3481 +{
3482 + unsigned long flags;
3483 + spin_lock_irqsave(&pi2s_config->lock, flags);
3484 + //if (pi2s_config->bRxDMAEnable!=0)
3485 + {
3486 + if (pi2s_config->rx_unmask_ch!=0)
3487 + {
3488 + u32 dmach = pi2s_config->rx_unmask_ch;
3489 + u32 ch;
3490 + for (ch = 0; ch < 16; ch++)
3491 + {
3492 + if (dmach& (1<<ch))
3493 + {
3494 + MSG("do unmask ch%d risr=%d in rx_isr\n",ch,pi2s_config->rx_isr_cnt);
3495 + GdmaUnMaskChannel(ch);
3496 + }
3497 + }
3498 + pi2s_config->rx_unmask_ch = 0;
3499 +
3500 + }
3501 + }
3502 + spin_unlock_irqrestore(&pi2s_config->lock, flags);
3503 +}
3504 +
3505 +
3506 +void i2s_dma_unmask_handler(u32 dma_ch)
3507 +{
3508 + MSG("i2s_dma_unmask_handler ch=%d\n",dma_ch);
3509 +
3510 + GdmaUnMaskChannel(dma_ch);
3511 +
3512 + return;
3513 +}
3514 +
3515 +void i2s_dma_tx_unmask_handler(u32 dma_ch)
3516 +{
3517 + MSG("i2s_dma_tx_unmask_handler ch=%d\n",dma_ch);
3518 + pi2s_config->tx_unmask_ch |= (1<<dma_ch);
3519 + tasklet_hi_schedule(&i2s_tx_tasklet);
3520 + return;
3521 +}
3522 +
3523 +void i2s_dma_rx_unmask_handler(u32 dma_ch)
3524 +{
3525 + MSG("i2s_dma_rx_unmask_handler ch=%d\n",dma_ch);
3526 + pi2s_config->rx_unmask_ch |= (1<<dma_ch);
3527 + tasklet_hi_schedule(&i2s_rx_tasklet);
3528 + return;
3529 +}
3530 +
3531 +void i2s_dma_mask_handler(u32 dma_ch)
3532 +{
3533 + MSG("i2s_dma_mask_handler ch=%d\n", dma_ch);
3534 + GdmaMaskChannel(dma_ch);
3535 + return;
3536 +}
3537 +
3538 +void i2s_dma_tx_init(i2s_config_type* ptri2s_config)
3539 +{
3540 + memset(pi2s_config->pPage0TxBuf8ptr, 0, I2S_PAGE_SIZE);
3541 + memset(pi2s_config->pPage1TxBuf8ptr, 0, I2S_PAGE_SIZE);
3542 +#if defined(ARM_ARCH)
3543 + GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3544 + GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3545 +#else
3546 + GdmaI2sTx((u32)ptri2s_config->pPage0TxBuf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3547 + GdmaI2sTx((u32)ptri2s_config->pPage1TxBuf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3548 +#endif
3549 +
3550 + return;
3551 +}
3552 +
3553 +void i2s_dma_rx_init(i2s_config_type* ptri2s_config)
3554 +{
3555 + memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3556 + memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3557 +
3558 +#if defined(ARM_ARCH)
3559 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3560 + GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3561 +#else
3562 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3563 + GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3564 +#endif
3565 +
3566 + return;
3567 +}
3568 +
3569 +void i2s_dma_tx_end_handle(i2s_config_type* ptri2s_config)
3570 +{
3571 + if (ptri2s_config->tx_w_idx < ptri2s_config->tx_r_idx)
3572 + {
3573 + ptri2s_config->end_cnt = (ptri2s_config->tx_w_idx + MAX_I2S_PAGE)-ptri2s_config->tx_r_idx;
3574 + _printk("case1: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3575 + }
3576 + else if (ptri2s_config->tx_w_idx > ptri2s_config->tx_r_idx)
3577 + {
3578 + ptri2s_config->end_cnt = ptri2s_config->tx_w_idx-ptri2s_config->tx_r_idx;
3579 + _printk("case2: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3580 + }
3581 + else
3582 + {
3583 + _printk("case3: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3584 +
3585 + }
3586 +
3587 + if (ptri2s_config->end_cnt > 0)
3588 + {
3589 + interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3590 + }
3591 +
3592 + return;
3593 +}
3594 +
3595 +void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config)
3596 +{
3597 + while(ptri2s_config->tx_stop_cnt<3)
3598 + interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3599 +
3600 + return;
3601 +}
3602 +
3603 +void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config)
3604 +{
3605 + while(ptri2s_config->rx_stop_cnt<2)
3606 + interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
3607 + return;
3608 +}
3609 +
3610 +int i2s_dma_tx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch)
3611</