target/linux/ramips/patches-3.8/0107-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch

   1 From f63a0ea6c115e7b78bce70d78aaa813615e3d434 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jan 2013 09:17:20 +0100
   4 Subject: [PATCH 107/121] MIPS: ralink: adds support for RT2880 SoC family
   5
   6 Add support code for rt2880 SOC.
   7
   8 The code detects the SoC and registers the clk / pinmux settings.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 ---
  12  arch/mips/Kconfig                          |    2 +-
  13  arch/mips/include/asm/mach-ralink/rt288x.h |   49 ++++++++++
  14  arch/mips/ralink/Kconfig                   |    3 +
  15  arch/mips/ralink/Makefile                  |    1 +
  16  arch/mips/ralink/Platform                  |    5 +
  17  arch/mips/ralink/rt288x.c                  |  141 ++++++++++++++++++++++++++++
  18  6 files changed, 200 insertions(+), 1 deletion(-)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
  20  create mode 100644 arch/mips/ralink/rt288x.c
  21
  22 --- a/arch/mips/Kconfig
  23 +++ b/arch/mips/Kconfig
  24 @@ -1189,7 +1189,7 @@ config BOOT_ELF32
  25
  26  config MIPS_L1_CACHE_SHIFT
  27         int
  28 -       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
  29 +       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
  30         default "6" if MIPS_CPU_SCACHE
  31         default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
  32         default "5"
  33 --- /dev/null
  34 +++ b/arch/mips/include/asm/mach-ralink/rt288x.h
  35 @@ -0,0 +1,49 @@
  36 +/*
  37 + * This program is free software; you can redistribute it and/or modify it
  38 + * under the terms of the GNU General Public License version 2 as published
  39 + * by the Free Software Foundation.
  40 + *
  41 + * Parts of this file are based on Ralink's 2.6.21 BSP
  42 + *
  43 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  44 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  45 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  46 + */
  47 +
  48 +#ifndef _RT288X_REGS_H_
  49 +#define _RT288X_REGS_H_
  50 +
  51 +#define RT2880_SYSC_BASE               0x00300000
  52 +
  53 +#define SYSC_REG_CHIP_NAME0            0x00
  54 +#define SYSC_REG_CHIP_NAME1            0x04
  55 +#define SYSC_REG_CHIP_ID               0x0c
  56 +#define SYSC_REG_SYSTEM_CONFIG         0x10
  57 +#define SYSC_REG_CLKCFG                        0x30
  58 +
  59 +#define RT2880_CHIP_NAME0              0x38325452
  60 +#define RT2880_CHIP_NAME1              0x20203038
  61 +
  62 +#define CHIP_ID_ID_MASK                        0xff
  63 +#define CHIP_ID_ID_SHIFT               8
  64 +#define CHIP_ID_REV_MASK               0xff
  65 +
  66 +#define SYSTEM_CONFIG_CPUCLK_SHIFT     20
  67 +#define SYSTEM_CONFIG_CPUCLK_MASK      0x3
  68 +#define SYSTEM_CONFIG_CPUCLK_250       0x0
  69 +#define SYSTEM_CONFIG_CPUCLK_266       0x1
  70 +#define SYSTEM_CONFIG_CPUCLK_280       0x2
  71 +#define SYSTEM_CONFIG_CPUCLK_300       0x3
  72 +
  73 +#define RT2880_GPIO_MODE_I2C           BIT(0)
  74 +#define RT2880_GPIO_MODE_UART0         BIT(1)
  75 +#define RT2880_GPIO_MODE_SPI           BIT(2)
  76 +#define RT2880_GPIO_MODE_UART1         BIT(3)
  77 +#define RT2880_GPIO_MODE_JTAG          BIT(4)
  78 +#define RT2880_GPIO_MODE_MDIO          BIT(5)
  79 +#define RT2880_GPIO_MODE_SDRAM         BIT(6)
  80 +#define RT2880_GPIO_MODE_PCI           BIT(7)
  81 +
  82 +#define CLKCFG_SRAM_CS_N_WDT           BIT(9)
  83 +
  84 +#endif
  85 --- a/arch/mips/ralink/Kconfig
  86 +++ b/arch/mips/ralink/Kconfig
  87 @@ -6,6 +6,9 @@ choice
  88         help
  89           Select Ralink MIPS SoC type.
  90
  91 +       config SOC_RT288X
  92 +               bool "RT288x"
  93 +
  94         config SOC_RT305X
  95                 bool "RT305x"
  96                 select USB_ARCH_HAS_HCD
  97 --- a/arch/mips/ralink/Makefile
  98 +++ b/arch/mips/ralink/Makefile
  99 @@ -8,6 +8,7 @@
 100
 101  obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
 102
 103 +obj-$(CONFIG_SOC_RT288X) += rt288x.o
 104  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 105
 106  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 107 --- a/arch/mips/ralink/Platform
 108 +++ b/arch/mips/ralink/Platform
 109 @@ -5,6 +5,11 @@ core-$(CONFIG_RALINK)          += arch/mips/rali
 110  cflags-$(CONFIG_RALINK)                += -I$(srctree)/arch/mips/include/asm/mach-ralink
 111
 112  #
 113 +# Ralink RT288x
 114 +#
 115 +load-$(CONFIG_SOC_RT288X)      += 0xffffffff88000000
 116 +
 117 +#
 118  # Ralink RT305x
 119  #
 120  load-$(CONFIG_SOC_RT305X)      += 0xffffffff80000000
 121 --- /dev/null
 122 +++ b/arch/mips/ralink/rt288x.c
 123 @@ -0,0 +1,141 @@
 124 +/*
 125 + * This program is free software; you can redistribute it and/or modify it
 126 + * under the terms of the GNU General Public License version 2 as published
 127 + * by the Free Software Foundation.
 128 + *
 129 + * Parts of this file are based on Ralink's 2.6.21 BSP
 130 + *
 131 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 132 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 133 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 134 + */
 135 +
 136 +#include <linux/kernel.h>
 137 +#include <linux/init.h>
 138 +#include <linux/module.h>
 139 +
 140 +#include <asm/mipsregs.h>
 141 +#include <asm/mach-ralink/ralink_regs.h>
 142 +#include <asm/mach-ralink/rt288x.h>
 143 +
 144 +#include "common.h"
 145 +
 146 +struct ralink_pinmux_grp mode_mux[] = {
 147 +       {
 148 +               .name = "i2c",
 149 +               .mask = RT2880_GPIO_MODE_I2C,
 150 +               .gpio_first = 1,
 151 +               .gpio_last = 2,
 152 +       }, {
 153 +               .name = "spi",
 154 +               .mask = RT2880_GPIO_MODE_SPI,
 155 +               .gpio_first = 3,
 156 +               .gpio_last = 6,
 157 +       }, {
 158 +               .name = "uartlite",
 159 +               .mask = RT2880_GPIO_MODE_UART0,
 160 +               .gpio_first = 7,
 161 +               .gpio_last = 14,
 162 +       }, {
 163 +               .name = "jtag",
 164 +               .mask = RT2880_GPIO_MODE_JTAG,
 165 +               .gpio_first = 17,
 166 +               .gpio_last = 21,
 167 +       }, {
 168 +               .name = "mdio",
 169 +               .mask = RT2880_GPIO_MODE_MDIO,
 170 +               .gpio_first = 22,
 171 +               .gpio_last = 23,
 172 +       }, {
 173 +               .name = "sdram",
 174 +               .mask = RT2880_GPIO_MODE_SDRAM,
 175 +               .gpio_first = 24,
 176 +               .gpio_last = 39,
 177 +       }, {
 178 +               .name = "pci",
 179 +               .mask = RT2880_GPIO_MODE_PCI,
 180 +               .gpio_first = 40,
 181 +               .gpio_last = 71,
 182 +       }, {0}
 183 +};
 184 +
 185 +void rt288x_wdt_reset(void)
 186 +{
 187 +       u32 t;
 188 +
 189 +       /* enable WDT reset output on pin SRAM_CS_N */
 190 +       t = rt_sysc_r32(SYSC_REG_CLKCFG);
 191 +       t |= CLKCFG_SRAM_CS_N_WDT;
 192 +       rt_sysc_w32(t, SYSC_REG_CLKCFG);
 193 +}
 194 +
 195 +struct ralink_pinmux rt_pinmux = {
 196 +       .mode = mode_mux,
 197 +       .wdt_reset = rt288x_wdt_reset,
 198 +};
 199 +
 200 +void ralink_usb_platform(void)
 201 +{
 202 +}
 203 +
 204 +void __init ralink_clk_init(void)
 205 +{
 206 +       unsigned long cpu_rate;
 207 +       u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 208 +       t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
 209 +
 210 +       switch (t) {
 211 +       case SYSTEM_CONFIG_CPUCLK_250:
 212 +               cpu_rate = 250000000;
 213 +               break;
 214 +       case SYSTEM_CONFIG_CPUCLK_266:
 215 +               cpu_rate = 266666667;
 216 +               break;
 217 +       case SYSTEM_CONFIG_CPUCLK_280:
 218 +               cpu_rate = 280000000;
 219 +               break;
 220 +       case SYSTEM_CONFIG_CPUCLK_300:
 221 +               cpu_rate = 300000000;
 222 +               break;
 223 +       }
 224 +
 225 +       ralink_clk_add("cpu", cpu_rate);
 226 +       ralink_clk_add("10000100.timer", cpu_rate / 2);
 227 +       ralink_clk_add("10000500.uart", cpu_rate / 2);
 228 +       ralink_clk_add("10000c00.uartlite", cpu_rate / 2);
 229 +}
 230 +
 231 +void __init ralink_of_remap(void)
 232 +{
 233 +       rt_sysc_membase = plat_of_remap_node("ralink,rt288x-sysc");
 234 +       rt_memc_membase = plat_of_remap_node("ralink,rt288x-memc");
 235 +
 236 +       if (!rt_sysc_membase || !rt_memc_membase)
 237 +               panic("Failed to remap core resources");
 238 +}
 239 +
 240 +void prom_soc_init(struct ralink_soc_info *soc_info)
 241 +{
 242 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
 243 +       const char *name;
 244 +       u32 n0;
 245 +       u32 n1;
 246 +       u32 id;
 247 +
 248 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 249 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 250 +       id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 251 +
 252 +       if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
 253 +               soc_info->compatible = "ralink,r2880-soc";
 254 +               name = "RT2880";
 255 +       } else {
 256 +               panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 257 +       }
 258 +
 259 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 260 +               "Ralink %s id:%u rev:%u",
 261 +               name,
 262 +               (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 263 +               (id & CHIP_ID_REV_MASK));
 264 +}