target/linux/ramips/patches-3.8/0108-MIPS-add-rt2880-dts-files.patch

   1 From b72ae753b73cbc4b488dcdbf997faec199c8bb3f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 18:29:02 +0100
   4 Subject: [PATCH 108/121] MIPS: add rt2880 dts files
   5
   6 Add a dtsi file for RT2880 SoC and a sample dts file. This SoC is first one that
   7 was released in this SoC family.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/ralink/Kconfig             |    4 ++
  12  arch/mips/ralink/dts/Makefile        |    1 +
  13  arch/mips/ralink/dts/rt2880.dtsi     |  116 ++++++++++++++++++++++++++++++++++
  14  arch/mips/ralink/dts/rt2880_eval.dts |   52 +++++++++++++++
  15  4 files changed, 173 insertions(+)
  16  create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
  17  create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
  18
  19 --- a/arch/mips/ralink/Kconfig
  20 +++ b/arch/mips/ralink/Kconfig
  21 @@ -26,6 +26,10 @@ choice
  22         config DTB_RT_NONE
  23                 bool "None"
  24
  25 +       config DTB_RT2880_EVAL
  26 +               bool "RT2880 eval kit"
  27 +               depends on SOC_RT288X
  28 +
  29         config DTB_RT305X_EVAL
  30                 bool "RT305x eval kit"
  31                 depends on SOC_RT305X
  32 --- a/arch/mips/ralink/dts/Makefile
  33 +++ b/arch/mips/ralink/dts/Makefile
  34 @@ -1 +1,2 @@
  35 +obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
  36  obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
  37 --- /dev/null
  38 +++ b/arch/mips/ralink/dts/rt2880.dtsi
  39 @@ -0,0 +1,116 @@
  40 +/ {
  41 +       #address-cells = <1>;
  42 +       #size-cells = <1>;
  43 +       compatible = "ralink,rt2880-soc";
  44 +
  45 +       cpus {
  46 +               cpu@0 {
  47 +                       compatible = "mips,mips24KEc";
  48 +               };
  49 +       };
  50 +
  51 +       chosen {
  52 +               bootargs = "console=ttyS0,57600 init=/init";
  53 +       };
  54 +
  55 +       cpuintc: cpuintc@0 {
  56 +               #address-cells = <0>;
  57 +               #interrupt-cells = <1>;
  58 +               interrupt-controller;
  59 +               compatible = "mti,cpu-interrupt-controller";
  60 +       };
  61 +
  62 +       palmbus@10000000 {
  63 +               compatible = "palmbus";
  64 +               reg = <0x10000000 0x200000>;
  65 +                ranges = <0x0 0x10000000 0x1FFFFF>;
  66 +
  67 +               #address-cells = <1>;
  68 +               #size-cells = <1>;
  69 +
  70 +               sysc@300000 {
  71 +                       compatible = "ralink,rt2880-sysc";
  72 +                       reg = <0x300000 0x100>;
  73 +               };
  74 +
  75 +               timer@300100 {
  76 +                       compatible = "ralink,rt2880-timer";
  77 +                       reg = <0x300100 0x20>;
  78 +
  79 +                       interrupt-parent = <&intc>;
  80 +                       interrupts = <1>;
  81 +
  82 +                       status = "disabled";
  83 +               };
  84 +
  85 +               watchdog@300120 {
  86 +                       compatible = "ralink,rt2880-wdt";
  87 +                       reg = <0x300120 0x10>;
  88 +               };
  89 +
  90 +               intc: intc@300200 {
  91 +                       compatible = "ralink,rt2880-intc";
  92 +                       reg = <0x300200 0x100>;
  93 +
  94 +                       interrupt-controller;
  95 +                       #interrupt-cells = <1>;
  96 +
  97 +                       interrupt-parent = <&cpuintc>;
  98 +                       interrupts = <2>;
  99 +               };
 100 +
 101 +               memc@300300 {
 102 +                       compatible = "ralink,rt2880-memc";
 103 +                       reg = <0x300300 0x100>;
 104 +               };
 105 +
 106 +               gpio0: gpio@300600 {
 107 +                       compatible = "ralink,rt2880-gpio";
 108 +                       reg = <0x300600 0x34>;
 109 +
 110 +                       gpio-controller;
 111 +                       #gpio-cells = <2>;
 112 +
 113 +                       ralink,num-gpios = <24>;
 114 +                       ralink,register-map = [ 00 04 08 0c
 115 +                                               20 24 28 2c
 116 +                                               30 34 ];
 117 +               };
 118 +
 119 +               gpio1: gpio@300638 {
 120 +                       compatible = "ralink,rt2880-gpio";
 121 +                       reg = <0x300638 0x24>;
 122 +
 123 +                       gpio-controller;
 124 +                       #gpio-cells = <2>;
 125 +
 126 +                       ralink,num-gpios = <16>;
 127 +                       ralink,register-map = [ 00 04 08 0c
 128 +                                               10 14 18 1c
 129 +                                               20 24 ];
 130 +               };
 131 +
 132 +               gpio2: gpio@300660 {
 133 +                       compatible = "ralink,rt2880-gpio";
 134 +                       reg = <0x300660 0x24>;
 135 +
 136 +                       gpio-controller;
 137 +                       #gpio-cells = <2>;
 138 +
 139 +                       ralink,num-gpios = <32>;
 140 +                       ralink,register-map = [ 00 04 08 0c
 141 +                                               10 14 18 1c
 142 +                                               20 24 ];
 143 +               };
 144 +
 145 +               uartlite@300c00 {
 146 +                       compatible = "ralink,rt2880-uart", "ns16550a";
 147 +                       reg = <0x300c00 0x100>;
 148 +
 149 +                       interrupt-parent = <&intc>;
 150 +                       interrupts = <12>;
 151 +
 152 +                       reg-shift = <2>;
 153 +               };
 154 +       };
 155 +};
 156 --- /dev/null
 157 +++ b/arch/mips/ralink/dts/rt2880_eval.dts
 158 @@ -0,0 +1,52 @@
 159 +/dts-v1/;
 160 +
 161 +/include/ "rt2880.dtsi"
 162 +
 163 +/ {
 164 +       #address-cells = <1>;
 165 +       #size-cells = <1>;
 166 +       compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
 167 +       model = "Ralink RT2880 evaluation board";
 168 +
 169 +       memory@8000000 {
 170 +               reg = <0x0 0x2000000>;
 171 +       };
 172 +
 173 +       palmbus@10000000 {
 174 +               sysc@300000 {
 175 +                       ralink,pinmmux = "uartlite", "spi";
 176 +                       ralink,uartmux = "gpio";
 177 +                       ralink,wdtmux = <0>;
 178 +               };
 179 +       };
 180 +
 181 +       cfi@1f000000 {
 182 +               compatible = "cfi-flash";
 183 +               reg = <0x1f000000 0x800000>;
 184 +
 185 +               bank-width = <2>;
 186 +               device-width = <2>;
 187 +               #address-cells = <1>;
 188 +               #size-cells = <1>;
 189 +
 190 +               partition@0 {
 191 +                       label = "uboot";
 192 +                       reg = <0x0 0x30000>;
 193 +                       read-only;
 194 +               };
 195 +               partition@30000 {
 196 +                       label = "uboot-env";
 197 +                       reg = <0x30000 0x10000>;
 198 +                       read-only;
 199 +               };
 200 +               partition@40000 {
 201 +                       label = "calibration";
 202 +                       reg = <0x40000 0x10000>;
 203 +                       read-only;
 204 +               };
 205 +               partition@50000 {
 206 +                       label = "linux";
 207 +                       reg = <0x50000 0x7b0000>;
 208 +               };
 209 +       };
 210 +};