projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update linux 3.8 to 3.8.7
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.8 / 0120-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From 1c31c288bc1e853e3226ba593a13a0492b39c9e8 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 15 Mar 2013 19:07:05 +0100
4 Subject: [PATCH 120/121] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ramips/Kconfig | 18 +
15 drivers/net/ethernet/ramips/Makefile | 9 +
16 drivers/net/ethernet/ramips/ramips_debugfs.c | 127 ++
17 drivers/net/ethernet/ramips/ramips_esw.c | 1220 +++++++++++++++++++
18 drivers/net/ethernet/ramips/ramips_eth.h | 375 ++++++
19 drivers/net/ethernet/ramips/ramips_main.c | 1285 ++++++++++++++++++++
20 10 files changed, 3064 insertions(+)
21 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
22 create mode 100644 drivers/net/ethernet/ramips/Kconfig
23 create mode 100644 drivers/net/ethernet/ramips/Makefile
24 create mode 100644 drivers/net/ethernet/ramips/ramips_debugfs.c
25 create mode 100644 drivers/net/ethernet/ramips/ramips_esw.c
26 create mode 100644 drivers/net/ethernet/ramips/ramips_eth.h
27 create mode 100644 drivers/net/ethernet/ramips/ramips_main.c
28
29 --- /dev/null
30 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
31 @@ -0,0 +1,27 @@
32 +/*
33 + * Ralink RT305x SoC platform device registration
34 + *
35 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
36 + *
37 + * This program is free software; you can redistribute it and/or modify it
38 + * under the terms of the GNU General Public License version 2 as published
39 + * by the Free Software Foundation.
40 + */
41 +
42 +#ifndef _RT305X_ESW_PLATFORM_H
43 +#define _RT305X_ESW_PLATFORM_H
44 +
45 +enum {
46 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
47 + RT305X_ESW_VLAN_CONFIG_LLLLW,
48 + RT305X_ESW_VLAN_CONFIG_WLLLL,
49 +};
50 +
51 +struct rt305x_esw_platform_data
52 +{
53 + u8 vlan_config;
54 + u32 reg_initval_fct2;
55 + u32 reg_initval_fpa2;
56 +};
57 +
58 +#endif /* _RT305X_ESW_PLATFORM_H */
59 --- a/arch/mips/ralink/rt305x.c
60 +++ b/arch/mips/ralink/rt305x.c
61 @@ -182,6 +182,7 @@ void __init ralink_clk_init(void)
62 }
63
64 ralink_clk_add("cpu", cpu_rate);
65 + ralink_clk_add("sys", sys_rate);
66 ralink_clk_add("10000b00.spi", sys_rate);
67 ralink_clk_add("10000100.timer", wdt_rate);
68 ralink_clk_add("10000120.watchdog", wdt_rate);
69 --- a/drivers/net/ethernet/Kconfig
70 +++ b/drivers/net/ethernet/Kconfig
71 @@ -136,6 +136,7 @@ source "drivers/net/ethernet/packetengin
72 source "drivers/net/ethernet/pasemi/Kconfig"
73 source "drivers/net/ethernet/qlogic/Kconfig"
74 source "drivers/net/ethernet/racal/Kconfig"
75 +source "drivers/net/ethernet/ramips/Kconfig"
76 source "drivers/net/ethernet/realtek/Kconfig"
77 source "drivers/net/ethernet/renesas/Kconfig"
78 source "drivers/net/ethernet/rdc/Kconfig"
79 --- a/drivers/net/ethernet/Makefile
80 +++ b/drivers/net/ethernet/Makefile
81 @@ -54,6 +54,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe
82 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
83 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
84 obj-$(CONFIG_NET_VENDOR_RACAL) += racal/
85 +obj-$(CONFIG_NET_RAMIPS) += ramips/
86 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
87 obj-$(CONFIG_SH_ETH) += renesas/
88 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
89 --- /dev/null
90 +++ b/drivers/net/ethernet/ramips/Kconfig
91 @@ -0,0 +1,18 @@
92 +config NET_RAMIPS
93 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883 ethernet driver"
94 + depends on RALINK
95 + select PHYLIB if (SOC_RT288X || SOC_RT3883)
96 + select SWCONFIG if SOC_RT305X
97 + help
98 + This driver supports the etehrnet mac inside the ralink wisocs
99 +
100 +if NET_RAMIPS
101 +
102 +config NET_RAMIPS_DEBUG
103 + bool "Enable debug messages in the Ralink ethernet driver"
104 +
105 +config NET_RAMIPS_DEBUG_FS
106 + bool "Enable debugfs support for the Ralink ethernet driver"
107 + depends on DEBUG_FS
108 +
109 +endif
110 --- /dev/null
111 +++ b/drivers/net/ethernet/ramips/Makefile
112 @@ -0,0 +1,9 @@
113 +#
114 +# Makefile for the Ramips SoCs built-in ethernet macs
115 +#
116 +
117 +ramips-y += ramips_main.o
118 +
119 +ramips-$(CONFIG_NET_RAMIPS_DEBUG_FS) += ramips_debugfs.o
120 +
121 +obj-$(CONFIG_NET_RAMIPS) += ramips.o
122 --- /dev/null
123 +++ b/drivers/net/ethernet/ramips/ramips_debugfs.c
124 @@ -0,0 +1,127 @@
125 +/*
126 + * Ralink SoC ethernet driver debugfs code
127 + *
128 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
129 + *
130 + * This program is free software; you can redistribute it and/or modify it
131 + * under the terms of the GNU General Public License version 2 as published
132 + * by the Free Software Foundation.
133 + */
134 +
135 +#include <linux/debugfs.h>
136 +#include <linux/module.h>
137 +#include <linux/phy.h>
138 +
139 +#include "ramips_eth.h"
140 +
141 +static struct dentry *raeth_debugfs_root;
142 +
143 +static int raeth_debugfs_generic_open(struct inode *inode, struct file *file)
144 +{
145 + file->private_data = inode->i_private;
146 + return 0;
147 +}
148 +
149 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status)
150 +{
151 + re->debug.int_stats.total += !!status;
152 +
153 + re->debug.int_stats.rx_delayed += !!(status & RAMIPS_RX_DLY_INT);
154 + re->debug.int_stats.rx_done0 += !!(status & RAMIPS_RX_DONE_INT0);
155 + re->debug.int_stats.rx_coherent += !!(status & RAMIPS_RX_COHERENT);
156 +
157 + re->debug.int_stats.tx_delayed += !!(status & RAMIPS_TX_DLY_INT);
158 + re->debug.int_stats.tx_done0 += !!(status & RAMIPS_TX_DONE_INT0);
159 + re->debug.int_stats.tx_done1 += !!(status & RAMIPS_TX_DONE_INT1);
160 + re->debug.int_stats.tx_done2 += !!(status & RAMIPS_TX_DONE_INT2);
161 + re->debug.int_stats.tx_done3 += !!(status & RAMIPS_TX_DONE_INT3);
162 + re->debug.int_stats.tx_coherent += !!(status & RAMIPS_TX_COHERENT);
163 +
164 + re->debug.int_stats.pse_fq_empty += !!(status & RAMIPS_PSE_FQ_EMPTY);
165 + re->debug.int_stats.pse_p0_fc += !!(status & RAMIPS_PSE_P0_FC);
166 + re->debug.int_stats.pse_p1_fc += !!(status & RAMIPS_PSE_P1_FC);
167 + re->debug.int_stats.pse_p2_fc += !!(status & RAMIPS_PSE_P2_FC);
168 + re->debug.int_stats.pse_buf_drop += !!(status & RAMIPS_PSE_BUF_DROP);
169 +}
170 +
171 +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
172 + size_t count, loff_t *ppos)
173 +{
174 +#define PR_INT_STAT(_label, _field) \
175 + len += snprintf(buf + len, sizeof(buf) - len, \
176 + "%-18s: %10lu\n", _label, re->debug.int_stats._field);
177 +
178 + struct raeth_priv *re = file->private_data;
179 + char buf[512];
180 + unsigned int len = 0;
181 + unsigned long flags;
182 +
183 + spin_lock_irqsave(&re->page_lock, flags);
184 +
185 + PR_INT_STAT("RX Delayed", rx_delayed);
186 + PR_INT_STAT("RX Done 0", rx_done0);
187 + PR_INT_STAT("RX Coherent", rx_coherent);
188 +
189 + PR_INT_STAT("TX Delayed", tx_delayed);
190 + PR_INT_STAT("TX Done 0", tx_done0);
191 + PR_INT_STAT("TX Done 1", tx_done1);
192 + PR_INT_STAT("TX Done 2", tx_done2);
193 + PR_INT_STAT("TX Done 3", tx_done3);
194 + PR_INT_STAT("TX Coherent", tx_coherent);
195 +
196 + PR_INT_STAT("PSE FQ empty", pse_fq_empty);
197 + PR_INT_STAT("CDMA Flow control", pse_p0_fc);
198 + PR_INT_STAT("GDMA1 Flow control", pse_p1_fc);
199 + PR_INT_STAT("GDMA2 Flow control", pse_p2_fc);
200 + PR_INT_STAT("PSE discard", pse_buf_drop);
201 +
202 + len += snprintf(buf + len, sizeof(buf) - len, "\n");
203 + PR_INT_STAT("Total", total);
204 +
205 + spin_unlock_irqrestore(&re->page_lock, flags);
206 +
207 + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
208 +#undef PR_INT_STAT
209 +}
210 +
211 +static const struct file_operations raeth_fops_int_stats = {
212 + .open = raeth_debugfs_generic_open,
213 + .read = read_file_int_stats,
214 + .owner = THIS_MODULE
215 +};
216 +
217 +void raeth_debugfs_exit(struct raeth_priv *re)
218 +{
219 + debugfs_remove_recursive(re->debug.debugfs_dir);
220 +}
221 +
222 +int raeth_debugfs_init(struct raeth_priv *re)
223 +{
224 + re->debug.debugfs_dir = debugfs_create_dir(re->netdev->name,
225 + raeth_debugfs_root);
226 + if (!re->debug.debugfs_dir)
227 + return -ENOMEM;
228 +
229 + debugfs_create_file("int_stats", S_IRUGO, re->debug.debugfs_dir,
230 + re, &raeth_fops_int_stats);
231 +
232 + return 0;
233 +}
234 +
235 +int raeth_debugfs_root_init(void)
236 +{
237 + if (raeth_debugfs_root)
238 + return -EBUSY;
239 +
240 + raeth_debugfs_root = debugfs_create_dir("raeth", NULL);
241 + if (!raeth_debugfs_root)
242 + return -ENOENT;
243 +
244 + return 0;
245 +}
246 +
247 +void raeth_debugfs_root_exit(void)
248 +{
249 + debugfs_remove(raeth_debugfs_root);
250 + raeth_debugfs_root = NULL;
251 +}
252 --- /dev/null
253 +++ b/drivers/net/ethernet/ramips/ramips_esw.c
254 @@ -0,0 +1,1221 @@
255 +#include <linux/ioport.h>
256 +#include <linux/switch.h>
257 +#include <linux/mii.h>
258 +
259 +#include <ralink_regs.h>
260 +#include <rt305x.h>
261 +#include <rt305x_esw_platform.h>
262 +
263 +/*
264 + * HW limitations for this switch:
265 + * - No large frame support (PKT_MAX_LEN at most 1536)
266 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
267 + * though this might be possible using the undocumented PPE.
268 + */
269 +
270 +#define RT305X_ESW_REG_ISR 0x00
271 +#define RT305X_ESW_REG_IMR 0x04
272 +#define RT305X_ESW_REG_FCT0 0x08
273 +#define RT305X_ESW_REG_PFC1 0x14
274 +#define RT305X_ESW_REG_ATS 0x24
275 +#define RT305X_ESW_REG_ATS0 0x28
276 +#define RT305X_ESW_REG_ATS1 0x2c
277 +#define RT305X_ESW_REG_ATS2 0x30
278 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
279 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
280 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
281 +#define RT305X_ESW_REG_POA 0x80
282 +#define RT305X_ESW_REG_FPA 0x84
283 +#define RT305X_ESW_REG_SOCPC 0x8c
284 +#define RT305X_ESW_REG_POC0 0x90
285 +#define RT305X_ESW_REG_POC1 0x94
286 +#define RT305X_ESW_REG_POC2 0x98
287 +#define RT305X_ESW_REG_SGC 0x9c
288 +#define RT305X_ESW_REG_STRT 0xa0
289 +#define RT305X_ESW_REG_PCR0 0xc0
290 +#define RT305X_ESW_REG_PCR1 0xc4
291 +#define RT305X_ESW_REG_FPA2 0xc8
292 +#define RT305X_ESW_REG_FCT2 0xcc
293 +#define RT305X_ESW_REG_SGC2 0xe4
294 +#define RT305X_ESW_REG_P0LED 0xa4
295 +#define RT305X_ESW_REG_P1LED 0xa8
296 +#define RT305X_ESW_REG_P2LED 0xac
297 +#define RT305X_ESW_REG_P3LED 0xb0
298 +#define RT305X_ESW_REG_P4LED 0xb4
299 +#define RT305X_ESW_REG_P0PC 0xe8
300 +#define RT305X_ESW_REG_P1PC 0xec
301 +#define RT305X_ESW_REG_P2PC 0xf0
302 +#define RT305X_ESW_REG_P3PC 0xf4
303 +#define RT305X_ESW_REG_P4PC 0xf8
304 +#define RT305X_ESW_REG_P5PC 0xfc
305 +
306 +#define RT305X_ESW_LED_LINK 0
307 +#define RT305X_ESW_LED_100M 1
308 +#define RT305X_ESW_LED_DUPLEX 2
309 +#define RT305X_ESW_LED_ACTIVITY 3
310 +#define RT305X_ESW_LED_COLLISION 4
311 +#define RT305X_ESW_LED_LINKACT 5
312 +#define RT305X_ESW_LED_DUPLCOLL 6
313 +#define RT305X_ESW_LED_10MACT 7
314 +#define RT305X_ESW_LED_100MACT 8
315 +/* Additional led states not in datasheet: */
316 +#define RT305X_ESW_LED_BLINK 10
317 +#define RT305X_ESW_LED_ON 12
318 +
319 +#define RT305X_ESW_LINK_S 25
320 +#define RT305X_ESW_DUPLEX_S 9
321 +#define RT305X_ESW_SPD_S 0
322 +
323 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
324 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
325 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
326 +
327 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
328 +
329 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
330 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
331 +
332 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
333 +#define RT305X_ESW_PVIDC_PVID_S 12
334 +
335 +#define RT305X_ESW_VLANI_VID_M 0xfff
336 +#define RT305X_ESW_VLANI_VID_S 12
337 +
338 +#define RT305X_ESW_VMSC_MSC_M 0xff
339 +#define RT305X_ESW_VMSC_MSC_S 8
340 +
341 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
342 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
343 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
344 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
345 +
346 +#define RT305X_ESW_POC0_EN_BP_S 0
347 +#define RT305X_ESW_POC0_EN_FC_S 8
348 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
349 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
350 +#define RT305X_ESW_POC0_DIS_PORT_S 23
351 +
352 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
353 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
354 +#define RT305X_ESW_POC2_ENAGING_S 8
355 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
356 +
357 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
358 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
359 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
360 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
361 +
362 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
363 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
364 +#define RT305X_ESW_PFC1_EN_TOS_S 24
365 +
366 +#define RT305X_ESW_VLAN_NONE 0xfff
367 +
368 +#define RT305X_ESW_POA_LINK_MASK 0x1f
369 +#define RT305X_ESW_POA_LINK_SHIFT 25
370 +
371 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
372 +#define RT305X_ESW_PORT0 0
373 +#define RT305X_ESW_PORT1 1
374 +#define RT305X_ESW_PORT2 2
375 +#define RT305X_ESW_PORT3 3
376 +#define RT305X_ESW_PORT4 4
377 +#define RT305X_ESW_PORT5 5
378 +#define RT305X_ESW_PORT6 6
379 +
380 +#define RT305X_ESW_PORTS_NONE 0
381 +
382 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
383 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
384 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
385 +
386 +#define RT305X_ESW_PORTS_INTERNAL \
387 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
388 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
389 + BIT(RT305X_ESW_PORT4))
390 +
391 +#define RT305X_ESW_PORTS_NOCPU \
392 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
393 +
394 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
395 +
396 +#define RT305X_ESW_PORTS_ALL \
397 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
398 +
399 +#define RT305X_ESW_NUM_VLANS 16
400 +#define RT305X_ESW_NUM_VIDS 4096
401 +#define RT305X_ESW_NUM_PORTS 7
402 +#define RT305X_ESW_NUM_LANWAN 6
403 +#define RT305X_ESW_NUM_LEDS 5
404 +
405 +enum {
406 + /* Global attributes. */
407 + RT305X_ESW_ATTR_ENABLE_VLAN,
408 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
409 + /* Port attributes. */
410 + RT305X_ESW_ATTR_PORT_DISABLE,
411 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
412 + RT305X_ESW_ATTR_PORT_UNTAG,
413 + RT305X_ESW_ATTR_PORT_LED,
414 + RT305X_ESW_ATTR_PORT_LAN,
415 + RT305X_ESW_ATTR_PORT_RECV_BAD,
416 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
417 +};
418 +
419 +struct rt305x_esw_port {
420 + bool disable;
421 + bool doubletag;
422 + bool untag;
423 + u8 led;
424 + u16 pvid;
425 +};
426 +
427 +struct rt305x_esw_vlan {
428 + u8 ports;
429 + u16 vid;
430 +};
431 +
432 +struct rt305x_esw {
433 + struct device *dev;
434 + void __iomem *base;
435 + int irq;
436 + const struct rt305x_esw_platform_data *pdata;
437 + /* Protects against concurrent register rmw operations. */
438 + spinlock_t reg_rw_lock;
439 +
440 + unsigned char port_map;
441 + unsigned int reg_initval_fct2;
442 + unsigned int reg_initval_fpa2;
443 +
444 +
445 + struct switch_dev swdev;
446 + bool global_vlan_enable;
447 + bool alt_vlan_disable;
448 + struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS];
449 + struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS];
450 +
451 +};
452 +
453 +static inline void
454 +rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
455 +{
456 + __raw_writel(val, esw->base + reg);
457 +}
458 +
459 +static inline u32
460 +rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
461 +{
462 + return __raw_readl(esw->base + reg);
463 +}
464 +
465 +static inline void
466 +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
467 + unsigned long val)
468 +{
469 + unsigned long t;
470 +
471 + t = __raw_readl(esw->base + reg) & ~mask;
472 + __raw_writel(t | val, esw->base + reg);
473 +}
474 +
475 +static void
476 +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
477 + unsigned long val)
478 +{
479 + unsigned long flags;
480 +
481 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
482 + rt305x_esw_rmw_raw(esw, reg, mask, val);
483 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
484 +}
485 +
486 +static u32
487 +rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
488 + u32 write_data)
489 +{
490 + unsigned long t_start = jiffies;
491 + int ret = 0;
492 +
493 + while (1) {
494 + if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
495 + RT305X_ESW_PCR1_WT_DONE))
496 + break;
497 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
498 + ret = 1;
499 + goto out;
500 + }
501 + }
502 +
503 + write_data &= 0xffff;
504 + rt305x_esw_wr(esw,
505 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
506 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
507 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
508 + RT305X_ESW_REG_PCR0);
509 +
510 + t_start = jiffies;
511 + while (1) {
512 + if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
513 + RT305X_ESW_PCR1_WT_DONE)
514 + break;
515 +
516 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
517 + ret = 1;
518 + break;
519 + }
520 + }
521 +out:
522 + if (ret)
523 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
524 + return ret;
525 +}
526 +
527 +static unsigned
528 +rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
529 +{
530 + unsigned s;
531 + unsigned val;
532 +
533 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
534 + val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2));
535 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
536 +
537 + return val;
538 +}
539 +
540 +static void
541 +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
542 +{
543 + unsigned s;
544 +
545 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
546 + rt305x_esw_rmw(esw,
547 + RT305X_ESW_REG_VLANI(vlan / 2),
548 + RT305X_ESW_VLANI_VID_M << s,
549 + (vid & RT305X_ESW_VLANI_VID_M) << s);
550 +}
551 +
552 +static unsigned
553 +rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port)
554 +{
555 + unsigned s, val;
556 +
557 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
558 + val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2));
559 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
560 +}
561 +
562 +static void
563 +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
564 +{
565 + unsigned s;
566 +
567 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
568 + rt305x_esw_rmw(esw,
569 + RT305X_ESW_REG_PVIDC(port / 2),
570 + RT305X_ESW_PVIDC_PVID_M << s,
571 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
572 +}
573 +
574 +static unsigned
575 +rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
576 +{
577 + unsigned s, val;
578 +
579 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
580 + val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4));
581 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
582 +
583 + return val;
584 +}
585 +
586 +static void
587 +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
588 +{
589 + unsigned s;
590 +
591 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
592 + rt305x_esw_rmw(esw,
593 + RT305X_ESW_REG_VMSC(vlan / 4),
594 + RT305X_ESW_VMSC_MSC_M << s,
595 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
596 +}
597 +
598 +static unsigned
599 +rt305x_esw_get_port_disable(struct rt305x_esw *esw)
600 +{
601 + unsigned reg;
602 + reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0);
603 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
604 + RT305X_ESW_POC0_DIS_PORT_M;
605 +}
606 +
607 +static void
608 +rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
609 +{
610 + unsigned old_mask;
611 + unsigned enable_mask;
612 + unsigned changed;
613 + int i;
614 +
615 + old_mask = rt305x_esw_get_port_disable(esw);
616 + changed = old_mask ^ disable_mask;
617 + enable_mask = old_mask & disable_mask;
618 +
619 + /* enable before writing to MII */
620 + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
621 + (RT305X_ESW_POC0_DIS_PORT_M <<
622 + RT305X_ESW_POC0_DIS_PORT_S),
623 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
624 +
625 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
626 + if (!(changed & (1 << i)))
627 + continue;
628 + if (disable_mask & (1 << i)) {
629 + /* disable */
630 + rt305x_mii_write(esw, i, MII_BMCR,
631 + BMCR_PDOWN);
632 + } else {
633 + /* enable */
634 + rt305x_mii_write(esw, i, MII_BMCR,
635 + BMCR_FULLDPLX |
636 + BMCR_ANENABLE |
637 + BMCR_ANRESTART |
638 + BMCR_SPEED100);
639 + }
640 + }
641 +
642 + /* disable after writing to MII */
643 + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
644 + (RT305X_ESW_POC0_DIS_PORT_M <<
645 + RT305X_ESW_POC0_DIS_PORT_S),
646 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
647 +}
648 +
649 +static int
650 +rt305x_esw_apply_config(struct switch_dev *dev);
651 +
652 +static void
653 +rt305x_esw_hw_init(struct rt305x_esw *esw)
654 +{
655 + int i;
656 + u8 port_disable = 0;
657 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
658 +
659 + /* vodoo from original driver */
660 + rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
661 + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
662 + /* Port priority 1 for all ports, vlan enabled. */
663 + rt305x_esw_wr(esw, 0x00005555 |
664 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
665 + RT305X_ESW_REG_PFC1);
666 +
667 + /* Enable Back Pressure, and Flow Control */
668 + rt305x_esw_wr(esw,
669 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
670 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
671 + RT305X_ESW_REG_POC0);
672 +
673 + /* Enable Aging, and VLAN TAG removal */
674 + rt305x_esw_wr(esw,
675 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
676 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
677 + RT305X_ESW_REG_POC2);
678 +
679 + if (esw->reg_initval_fct2)
680 + rt305x_esw_wr(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
681 + else
682 + rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
683 +
684 + /*
685 + * 300s aging timer, max packet len 1536, broadcast storm prevention
686 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
687 + * pressure jam, GMII disable was_transmit, back pressure disabled,
688 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
689 + * ports.
690 + */
691 + rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
692 +
693 + /* Setup SoC Port control register */
694 + rt305x_esw_wr(esw,
695 + (RT305X_ESW_SOCPC_CRC_PADDING |
696 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
697 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
698 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
699 + RT305X_ESW_REG_SOCPC);
700 +
701 + if (esw->reg_initval_fpa2)
702 + rt305x_esw_wr(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
703 + else
704 + rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
705 + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
706 +
707 + /* Force Link/Activity on ports */
708 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
709 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
710 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
711 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
712 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
713 +
714 + /* Copy disabled port configuration from bootloader setup */
715 + port_disable = rt305x_esw_get_port_disable(esw);
716 + for (i = 0; i < 6; i++)
717 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
718 +
719 + rt305x_mii_write(esw, 0, 31, 0x8000);
720 + for (i = 0; i < 5; i++) {
721 + if (esw->ports[i].disable) {
722 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
723 + } else {
724 + rt305x_mii_write(esw, i, MII_BMCR,
725 + BMCR_FULLDPLX |
726 + BMCR_ANENABLE |
727 + BMCR_SPEED100);
728 + }
729 + /* TX10 waveform coefficient */
730 + rt305x_mii_write(esw, i, 26, 0x1601);
731 + /* TX100/TX10 AD/DA current bias */
732 + rt305x_mii_write(esw, i, 29, 0x7058);
733 + /* TX100 slew rate control */
734 + rt305x_mii_write(esw, i, 30, 0x0018);
735 + }
736 +
737 + /* PHY IOT */
738 + /* select global register */
739 + rt305x_mii_write(esw, 0, 31, 0x0);
740 + /* tune TP_IDL tail and head waveform */
741 + rt305x_mii_write(esw, 0, 22, 0x052f);
742 + /* set TX10 signal amplitude threshold to minimum */
743 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
744 + /* set squelch amplitude to higher threshold */
745 + rt305x_mii_write(esw, 0, 18, 0x40ba);
746 + /* longer TP_IDL tail length */
747 + rt305x_mii_write(esw, 0, 14, 0x65);
748 + /* select local register */
749 + rt305x_mii_write(esw, 0, 31, 0x8000);
750 +
751 + if (esw->port_map)
752 + port_map = esw->port_map;
753 + else
754 + port_map = RT305X_ESW_PMAP_LLLLLL;
755 +
756 + /*
757 + * Unused HW feature, but still nice to be consistent here...
758 + * This is also exported to userspace ('lan' attribute) so it's
759 + * conveniently usable to decide which ports go into the wan vlan by
760 + * default.
761 + */
762 + rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
763 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
764 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
765 +
766 + /* make the switch leds blink */
767 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
768 + esw->ports[i].led = 0x05;
769 +
770 + /* Apply the empty config. */
771 + rt305x_esw_apply_config(&esw->swdev);
772 +}
773 +
774 +static irqreturn_t
775 +rt305x_esw_interrupt(int irq, void *_esw)
776 +{
777 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
778 + u32 status;
779 +
780 + status = rt305x_esw_rr(esw, RT305X_ESW_REG_ISR);
781 + if (status & RT305X_ESW_PORT_ST_CHG) {
782 + u32 link = rt305x_esw_rr(esw, RT305X_ESW_REG_POA);
783 + link >>= RT305X_ESW_POA_LINK_SHIFT;
784 + link &= RT305X_ESW_POA_LINK_MASK;
785 + dev_info(esw->dev, "link changed 0x%02X\n", link);
786 + }
787 + rt305x_esw_wr(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
788 +
789 + return IRQ_HANDLED;
790 +}
791 +
792 +static void
793 +rt305x_esw_request_irq(struct rt305x_esw *esw)
794 +{
795 + /* Only unmask the port change interrupt */
796 + rt305x_esw_wr(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
797 +
798 + /* request the irq handler */
799 + request_irq(esw->irq, rt305x_esw_interrupt, 0, "esw", esw);
800 +}
801 +
802 +static int
803 +rt305x_esw_apply_config(struct switch_dev *dev)
804 +{
805 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
806 + int i;
807 + u8 disable = 0;
808 + u8 doubletag = 0;
809 + u8 en_vlan = 0;
810 + u8 untag = 0;
811 +
812 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
813 + u32 vid, vmsc;
814 + if (esw->global_vlan_enable) {
815 + vid = esw->vlans[i].vid;
816 + vmsc = esw->vlans[i].ports;
817 + } else {
818 + vid = RT305X_ESW_VLAN_NONE;
819 + vmsc = RT305X_ESW_PORTS_NONE;
820 + }
821 + rt305x_esw_set_vlan_id(esw, i, vid);
822 + rt305x_esw_set_vmsc(esw, i, vmsc);
823 + }
824 +
825 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
826 + u32 pvid;
827 + disable |= esw->ports[i].disable << i;
828 + if (esw->global_vlan_enable) {
829 + doubletag |= esw->ports[i].doubletag << i;
830 + en_vlan |= 1 << i;
831 + untag |= esw->ports[i].untag << i;
832 + pvid = esw->ports[i].pvid;
833 + } else {
834 + int x = esw->alt_vlan_disable ? 0 : 1;
835 + doubletag |= x << i;
836 + en_vlan |= x << i;
837 + untag |= x << i;
838 + pvid = 0;
839 + }
840 + rt305x_esw_set_pvid(esw, i, pvid);
841 + if (i < RT305X_ESW_NUM_LEDS)
842 + rt305x_esw_wr(esw, esw->ports[i].led,
843 + RT305X_ESW_REG_P0LED + 4*i);
844 + }
845 +
846 + rt305x_esw_set_port_disable(esw, disable);
847 + rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
848 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
849 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
850 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
851 + rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
852 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
853 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
854 + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
855 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
856 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
857 +
858 + if (!esw->global_vlan_enable) {
859 + /*
860 + * Still need to put all ports into vlan 0 or they'll be
861 + * isolated.
862 + * NOTE: vlan 0 is special, no vlan tag is prepended
863 + */
864 + rt305x_esw_set_vlan_id(esw, 0, 0);
865 + rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
866 + }
867 +
868 + return 0;
869 +}
870 +
871 +static int
872 +rt305x_esw_reset_switch(struct switch_dev *dev)
873 +{
874 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
875 + esw->global_vlan_enable = 0;
876 + memset(esw->ports, 0, sizeof(esw->ports));
877 + memset(esw->vlans, 0, sizeof(esw->vlans));
878 + rt305x_esw_hw_init(esw);
879 +
880 + return 0;
881 +}
882 +
883 +static int
884 +rt305x_esw_get_vlan_enable(struct switch_dev *dev,
885 + const struct switch_attr *attr,
886 + struct switch_val *val)
887 +{
888 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
889 +
890 + val->value.i = esw->global_vlan_enable;
891 +
892 + return 0;
893 +}
894 +
895 +static int
896 +rt305x_esw_set_vlan_enable(struct switch_dev *dev,
897 + const struct switch_attr *attr,
898 + struct switch_val *val)
899 +{
900 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
901 +
902 + esw->global_vlan_enable = val->value.i != 0;
903 +
904 + return 0;
905 +}
906 +
907 +static int
908 +rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev,
909 + const struct switch_attr *attr,
910 + struct switch_val *val)
911 +{
912 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
913 +
914 + val->value.i = esw->alt_vlan_disable;
915 +
916 + return 0;
917 +}
918 +
919 +static int
920 +rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev,
921 + const struct switch_attr *attr,
922 + struct switch_val *val)
923 +{
924 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
925 +
926 + esw->alt_vlan_disable = val->value.i != 0;
927 +
928 + return 0;
929 +}
930 +
931 +static int
932 +rt305x_esw_get_port_link(struct switch_dev *dev,
933 + int port,
934 + struct switch_port_link *link)
935 +{
936 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
937 + u32 speed, poa;
938 +
939 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
940 + return -EINVAL;
941 +
942 + poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port;
943 +
944 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
945 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
946 + if (port < RT305X_ESW_NUM_LEDS) {
947 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
948 + } else {
949 + if (port == RT305X_ESW_NUM_PORTS - 1)
950 + poa >>= 1;
951 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
952 + }
953 + switch (speed) {
954 + case 0:
955 + link->speed = SWITCH_PORT_SPEED_10;
956 + break;
957 + case 1:
958 + link->speed = SWITCH_PORT_SPEED_100;
959 + break;
960 + case 2:
961 + case 3: /* forced gige speed can be 2 or 3 */
962 + link->speed = SWITCH_PORT_SPEED_1000;
963 + break;
964 + default:
965 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
966 + break;
967 + }
968 +
969 + return 0;
970 +}
971 +
972 +static int
973 +rt305x_esw_get_port_bool(struct switch_dev *dev,
974 + const struct switch_attr *attr,
975 + struct switch_val *val)
976 +{
977 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
978 + int idx = val->port_vlan;
979 + u32 x, reg, shift;
980 +
981 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
982 + return -EINVAL;
983 +
984 + switch (attr->id) {
985 + case RT305X_ESW_ATTR_PORT_DISABLE:
986 + reg = RT305X_ESW_REG_POC0;
987 + shift = RT305X_ESW_POC0_DIS_PORT_S;
988 + break;
989 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
990 + reg = RT305X_ESW_REG_SGC2;
991 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
992 + break;
993 + case RT305X_ESW_ATTR_PORT_UNTAG:
994 + reg = RT305X_ESW_REG_POC2;
995 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
996 + break;
997 + case RT305X_ESW_ATTR_PORT_LAN:
998 + reg = RT305X_ESW_REG_SGC2;
999 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1000 + if (idx >= RT305X_ESW_NUM_LANWAN)
1001 + return -EINVAL;
1002 + break;
1003 + default:
1004 + return -EINVAL;
1005 + }
1006 +
1007 + x = rt305x_esw_rr(esw, reg);
1008 + val->value.i = (x >> (idx + shift)) & 1;
1009 +
1010 + return 0;
1011 +}
1012 +
1013 +static int
1014 +rt305x_esw_set_port_bool(struct switch_dev *dev,
1015 + const struct switch_attr *attr,
1016 + struct switch_val *val)
1017 +{
1018 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1019 + int idx = val->port_vlan;
1020 +
1021 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1022 + val->value.i < 0 || val->value.i > 1)
1023 + return -EINVAL;
1024 +
1025 + switch (attr->id) {
1026 + case RT305X_ESW_ATTR_PORT_DISABLE:
1027 + esw->ports[idx].disable = val->value.i;
1028 + break;
1029 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1030 + esw->ports[idx].doubletag = val->value.i;
1031 + break;
1032 + case RT305X_ESW_ATTR_PORT_UNTAG:
1033 + esw->ports[idx].untag = val->value.i;
1034 + break;
1035 + default:
1036 + return -EINVAL;
1037 + }
1038 +
1039 + return 0;
1040 +}
1041 +
1042 +static int
1043 +rt305x_esw_get_port_recv_badgood(struct switch_dev *dev,
1044 + const struct switch_attr *attr,
1045 + struct switch_val *val)
1046 +{
1047 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1048 + int idx = val->port_vlan;
1049 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1050 + u32 reg;
1051 +
1052 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1053 + return -EINVAL;
1054 +
1055 + reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx);
1056 + val->value.i = (reg >> shift) & 0xffff;
1057 +
1058 + return 0;
1059 +}
1060 +
1061 +static int
1062 +rt305x_esw_get_port_led(struct switch_dev *dev,
1063 + const struct switch_attr *attr,
1064 + struct switch_val *val)
1065 +{
1066 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1067 + int idx = val->port_vlan;
1068 +
1069 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1070 + idx >= RT305X_ESW_NUM_LEDS)
1071 + return -EINVAL;
1072 +
1073 + val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx);
1074 +
1075 + return 0;
1076 +}
1077 +
1078 +static int
1079 +rt305x_esw_set_port_led(struct switch_dev *dev,
1080 + const struct switch_attr *attr,
1081 + struct switch_val *val)
1082 +{
1083 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1084 + int idx = val->port_vlan;
1085 +
1086 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1087 + return -EINVAL;
1088 +
1089 + esw->ports[idx].led = val->value.i;
1090 +
1091 + return 0;
1092 +}
1093 +
1094 +static int
1095 +rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1096 +{
1097 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1098 +
1099 + if (port >= RT305X_ESW_NUM_PORTS)
1100 + return -EINVAL;
1101 +
1102 + *val = rt305x_esw_get_pvid(esw, port);
1103 +
1104 + return 0;
1105 +}
1106 +
1107 +static int
1108 +rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1109 +{
1110 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1111 +
1112 + if (port >= RT305X_ESW_NUM_PORTS)
1113 + return -EINVAL;
1114 +
1115 + esw->ports[port].pvid = val;
1116 +
1117 + return 0;
1118 +}
1119 +
1120 +static int
1121 +rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1122 +{
1123 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1124 + u32 vmsc, poc2;
1125 + int vlan_idx = -1;
1126 + int i;
1127 +
1128 + val->len = 0;
1129 +
1130 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1131 + return -EINVAL;
1132 +
1133 + /* valid vlan? */
1134 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1135 + if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan &&
1136 + rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1137 + vlan_idx = i;
1138 + break;
1139 + }
1140 + }
1141 +
1142 + if (vlan_idx == -1)
1143 + return -EINVAL;
1144 +
1145 + vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
1146 + poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
1147 +
1148 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1149 + struct switch_port *p;
1150 + int port_mask = 1 << i;
1151 +
1152 + if (!(vmsc & port_mask))
1153 + continue;
1154 +
1155 + p = &val->value.ports[val->len++];
1156 + p->id = i;
1157 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1158 + p->flags = 0;
1159 + else
1160 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1161 + }
1162 +
1163 + return 0;
1164 +}
1165 +
1166 +static int
1167 +rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1168 +{
1169 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1170 + int ports;
1171 + int vlan_idx = -1;
1172 + int i;
1173 +
1174 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1175 + val->len > RT305X_ESW_NUM_PORTS)
1176 + return -EINVAL;
1177 +
1178 + /* one of the already defined vlans? */
1179 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1180 + if (esw->vlans[i].vid == val->port_vlan &&
1181 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1182 + vlan_idx = i;
1183 + break;
1184 + }
1185 + }
1186 +
1187 + /* select a free slot */
1188 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1189 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1190 + vlan_idx = i;
1191 + }
1192 +
1193 + /* bail if all slots are in use */
1194 + if (vlan_idx == -1)
1195 + return -EINVAL;
1196 +
1197 + ports = RT305X_ESW_PORTS_NONE;
1198 + for (i = 0; i < val->len; i++) {
1199 + struct switch_port *p = &val->value.ports[i];
1200 + int port_mask = 1 << p->id;
1201 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1202 +
1203 + if (p->id >= RT305X_ESW_NUM_PORTS)
1204 + return -EINVAL;
1205 +
1206 + ports |= port_mask;
1207 + esw->ports[p->id].untag = untagged;
1208 + }
1209 + esw->vlans[vlan_idx].ports = ports;
1210 + if (ports == RT305X_ESW_PORTS_NONE)
1211 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1212 + else
1213 + esw->vlans[vlan_idx].vid = val->port_vlan;
1214 +
1215 + return 0;
1216 +}
1217 +
1218 +static const struct switch_attr rt305x_esw_global[] = {
1219 + {
1220 + .type = SWITCH_TYPE_INT,
1221 + .name = "enable_vlan",
1222 + .description = "VLAN mode (1:enabled)",
1223 + .max = 1,
1224 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1225 + .get = rt305x_esw_get_vlan_enable,
1226 + .set = rt305x_esw_set_vlan_enable,
1227 + },
1228 + {
1229 + .type = SWITCH_TYPE_INT,
1230 + .name = "alternate_vlan_disable",
1231 + .description = "Use en_vlan instead of doubletag to disable"
1232 + " VLAN mode",
1233 + .max = 1,
1234 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1235 + .get = rt305x_esw_get_alt_vlan_disable,
1236 + .set = rt305x_esw_set_alt_vlan_disable,
1237 + },
1238 +};
1239 +
1240 +static const struct switch_attr rt305x_esw_port[] = {
1241 + {
1242 + .type = SWITCH_TYPE_INT,
1243 + .name = "disable",
1244 + .description = "Port state (1:disabled)",
1245 + .max = 1,
1246 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1247 + .get = rt305x_esw_get_port_bool,
1248 + .set = rt305x_esw_set_port_bool,
1249 + },
1250 + {
1251 + .type = SWITCH_TYPE_INT,
1252 + .name = "doubletag",
1253 + .description = "Double tagging for incoming vlan packets "
1254 + "(1:enabled)",
1255 + .max = 1,
1256 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1257 + .get = rt305x_esw_get_port_bool,
1258 + .set = rt305x_esw_set_port_bool,
1259 + },
1260 + {
1261 + .type = SWITCH_TYPE_INT,
1262 + .name = "untag",
1263 + .description = "Untag (1:strip outgoing vlan tag)",
1264 + .max = 1,
1265 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1266 + .get = rt305x_esw_get_port_bool,
1267 + .set = rt305x_esw_set_port_bool,
1268 + },
1269 + {
1270 + .type = SWITCH_TYPE_INT,
1271 + .name = "led",
1272 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1273 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1274 + " 8:100mact, 10:blink, 12:on)",
1275 + .max = 15,
1276 + .id = RT305X_ESW_ATTR_PORT_LED,
1277 + .get = rt305x_esw_get_port_led,
1278 + .set = rt305x_esw_set_port_led,
1279 + },
1280 + {
1281 + .type = SWITCH_TYPE_INT,
1282 + .name = "lan",
1283 + .description = "HW port group (0:wan, 1:lan)",
1284 + .max = 1,
1285 + .id = RT305X_ESW_ATTR_PORT_LAN,
1286 + .get = rt305x_esw_get_port_bool,
1287 + },
1288 + {
1289 + .type = SWITCH_TYPE_INT,
1290 + .name = "recv_bad",
1291 + .description = "Receive bad packet counter",
1292 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1293 + .get = rt305x_esw_get_port_recv_badgood,
1294 + },
1295 + {
1296 + .type = SWITCH_TYPE_INT,
1297 + .name = "recv_good",
1298 + .description = "Receive good packet counter",
1299 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1300 + .get = rt305x_esw_get_port_recv_badgood,
1301 + },
1302 +};
1303 +
1304 +static const struct switch_attr rt305x_esw_vlan[] = {
1305 +};
1306 +
1307 +static const struct switch_dev_ops rt305x_esw_ops = {
1308 + .attr_global = {
1309 + .attr = rt305x_esw_global,
1310 + .n_attr = ARRAY_SIZE(rt305x_esw_global),
1311 + },
1312 + .attr_port = {
1313 + .attr = rt305x_esw_port,
1314 + .n_attr = ARRAY_SIZE(rt305x_esw_port),
1315 + },
1316 + .attr_vlan = {
1317 + .attr = rt305x_esw_vlan,
1318 + .n_attr = ARRAY_SIZE(rt305x_esw_vlan),
1319 + },
1320 + .get_vlan_ports = rt305x_esw_get_vlan_ports,
1321 + .set_vlan_ports = rt305x_esw_set_vlan_ports,
1322 + .get_port_pvid = rt305x_esw_get_port_pvid,
1323 + .set_port_pvid = rt305x_esw_set_port_pvid,
1324 + .get_port_link = rt305x_esw_get_port_link,
1325 + .apply_config = rt305x_esw_apply_config,
1326 + .reset_switch = rt305x_esw_reset_switch,
1327 +};
1328 +
1329 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1330 + /* All ports are LAN ports. */
1331 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1332 + .reg_initval_fct2 = 0x00d6500c,
1333 + /*
1334 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1335 + * turbo mii off, rgmi 3.3v off
1336 + * port5: disabled
1337 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1338 + */
1339 + .reg_initval_fpa2 = 0x3f502b28,
1340 +};
1341 +
1342 +static const struct of_device_id ralink_esw_match[] = {
1343 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1344 + {},
1345 +};
1346 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1347 +
1348 +static int
1349 +rt305x_esw_probe(struct platform_device *pdev)
1350 +{
1351 + struct device_node *np = pdev->dev.of_node;
1352 + const struct rt305x_esw_platform_data *pdata;
1353 + const __be32 *port_map, *reg_init;
1354 + struct rt305x_esw *esw;
1355 + struct switch_dev *swdev;
1356 + struct resource *res, *irq;
1357 + int err;
1358 +
1359 + pdata = pdev->dev.platform_data;
1360 + if (!pdata) {
1361 + const struct of_device_id *match;
1362 + match = of_match_device(ralink_esw_match, &pdev->dev);
1363 + if (match)
1364 + pdata = (struct rt305x_esw_platform_data *) match->data;
1365 + }
1366 + if (!pdata)
1367 + return -EINVAL;
1368 +
1369 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 + if (!res) {
1371 + dev_err(&pdev->dev, "no memory resource found\n");
1372 + return -ENOMEM;
1373 + }
1374 +
1375 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1376 + if (!irq) {
1377 + dev_err(&pdev->dev, "no irq resource found\n");
1378 + return -ENOMEM;
1379 + }
1380 +
1381 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1382 + if (!esw) {
1383 + dev_err(&pdev->dev, "no memory for private data\n");
1384 + return -ENOMEM;
1385 + }
1386 +
1387 + esw->dev = &pdev->dev;
1388 + esw->irq = irq->start;
1389 + esw->base = ioremap(res->start, resource_size(res));
1390 + if (!esw->base) {
1391 + dev_err(&pdev->dev, "ioremap failed\n");
1392 + err = -ENOMEM;
1393 + goto free_esw;
1394 + }
1395 +
1396 + port_map = of_get_property(np, "ralink,portmap", NULL);
1397 + if (port_map)
1398 + esw->port_map = be32_to_cpu(*port_map);
1399 +
1400 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1401 + if (reg_init)
1402 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1403 +
1404 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1405 + if (reg_init)
1406 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1407 +
1408 + swdev = &esw->swdev;
1409 + swdev->of_node = pdev->dev.of_node;
1410 + swdev->name = "rt305x-esw";
1411 + swdev->alias = "rt305x";
1412 + swdev->cpu_port = RT305X_ESW_PORT6;
1413 + swdev->ports = RT305X_ESW_NUM_PORTS;
1414 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1415 + swdev->ops = &rt305x_esw_ops;
1416 +
1417 + err = register_switch(swdev, NULL);
1418 + if (err < 0) {
1419 + dev_err(&pdev->dev, "register_switch failed\n");
1420 + goto unmap_base;
1421 + }
1422 +
1423 + platform_set_drvdata(pdev, esw);
1424 +
1425 + esw->pdata = pdata;
1426 + spin_lock_init(&esw->reg_rw_lock);
1427 + rt305x_esw_hw_init(esw);
1428 + rt305x_esw_request_irq(esw);
1429 +
1430 + return 0;
1431 +
1432 +unmap_base:
1433 + iounmap(esw->base);
1434 +free_esw:
1435 + kfree(esw);
1436 + return err;
1437 +}
1438 +
1439 +static int
1440 +rt305x_esw_remove(struct platform_device *pdev)
1441 +{
1442 + struct rt305x_esw *esw;
1443 +
1444 + esw = platform_get_drvdata(pdev);
1445 + if (esw) {
1446 + unregister_switch(&esw->swdev);
1447 + platform_set_drvdata(pdev, NULL);
1448 + iounmap(esw->base);
1449 + kfree(esw);
1450 + }
1451 +
1452 + return 0;
1453 +}
1454 +
1455 +static struct platform_driver rt305x_esw_driver = {
1456 + .probe = rt305x_esw_probe,
1457 + .remove = rt305x_esw_remove,
1458 + .driver = {
1459 + .name = "rt305x-esw",
1460 + .owner = THIS_MODULE,
1461 + .of_match_table = ralink_esw_match,
1462 + },
1463 +};
1464 +
1465 +static int __init
1466 +rt305x_esw_init(void)
1467 +{
1468 + return platform_driver_register(&rt305x_esw_driver);
1469 +}
1470 +
1471 +static void
1472 +rt305x_esw_exit(void)
1473 +{
1474 + platform_driver_unregister(&rt305x_esw_driver);
1475 +}
1476 --- /dev/null
1477 +++ b/drivers/net/ethernet/ramips/ramips_eth.h
1478 @@ -0,0 +1,375 @@
1479 +/*
1480 + * This program is free software; you can redistribute it and/or modify
1481 + * it under the terms of the GNU General Public License as published by
1482 + * the Free Software Foundation; version 2 of the License
1483 + *
1484 + * This program is distributed in the hope that it will be useful,
1485 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1486 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1487 + * GNU General Public License for more details.
1488 + *
1489 + * You should have received a copy of the GNU General Public License
1490 + * along with this program; if not, write to the Free Software
1491 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1492 + *
1493 + * based on Ralink SDK3.3
1494 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1495 + */
1496 +
1497 +#ifndef RAMIPS_ETH_H
1498 +#define RAMIPS_ETH_H
1499 +
1500 +#include <linux/mii.h>
1501 +#include <linux/interrupt.h>
1502 +#include <linux/netdevice.h>
1503 +#include <linux/dma-mapping.h>
1504 +
1505 +#define NUM_RX_DESC 256
1506 +#define NUM_TX_DESC 256
1507 +
1508 +#define RAMIPS_DELAY_EN_INT 0x80
1509 +#define RAMIPS_DELAY_MAX_INT 0x04
1510 +#define RAMIPS_DELAY_MAX_TOUT 0x04
1511 +#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
1512 +#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
1513 +#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000
1514 +
1515 +/* interrupt bits */
1516 +#define RAMIPS_CNT_PPE_AF BIT(31)
1517 +#define RAMIPS_CNT_GDM_AF BIT(29)
1518 +#define RAMIPS_PSE_P2_FC BIT(26)
1519 +#define RAMIPS_PSE_BUF_DROP BIT(24)
1520 +#define RAMIPS_GDM_OTHER_DROP BIT(23)
1521 +#define RAMIPS_PSE_P1_FC BIT(22)
1522 +#define RAMIPS_PSE_P0_FC BIT(21)
1523 +#define RAMIPS_PSE_FQ_EMPTY BIT(20)
1524 +#define RAMIPS_GE1_STA_CHG BIT(18)
1525 +#define RAMIPS_TX_COHERENT BIT(17)
1526 +#define RAMIPS_RX_COHERENT BIT(16)
1527 +#define RAMIPS_TX_DONE_INT3 BIT(11)
1528 +#define RAMIPS_TX_DONE_INT2 BIT(10)
1529 +#define RAMIPS_TX_DONE_INT1 BIT(9)
1530 +#define RAMIPS_TX_DONE_INT0 BIT(8)
1531 +#define RAMIPS_RX_DONE_INT0 BIT(2)
1532 +#define RAMIPS_TX_DLY_INT BIT(1)
1533 +#define RAMIPS_RX_DLY_INT BIT(0)
1534 +
1535 +#define RT5350_RX_DLY_INT BIT(30)
1536 +#define RT5350_TX_DLY_INT BIT(28)
1537 +
1538 +/* registers */
1539 +#define RAMIPS_FE_OFFSET 0x0000
1540 +#define RAMIPS_GDMA_OFFSET 0x0020
1541 +#define RAMIPS_PSE_OFFSET 0x0040
1542 +#define RAMIPS_GDMA2_OFFSET 0x0060
1543 +#define RAMIPS_CDMA_OFFSET 0x0080
1544 +#define RAMIPS_PDMA_OFFSET 0x0100
1545 +#define RAMIPS_PPE_OFFSET 0x0200
1546 +#define RAMIPS_CMTABLE_OFFSET 0x0400
1547 +#define RAMIPS_POLICYTABLE_OFFSET 0x1000
1548 +
1549 +#define RT5350_PDMA_OFFSET 0x0800
1550 +#define RT5350_SDM_OFFSET 0x0c00
1551 +
1552 +#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00)
1553 +#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04)
1554 +#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08)
1555 +#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C)
1556 +#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10)
1557 +#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14)
1558 +#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18)
1559 +#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C)
1560 +
1561 +#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00)
1562 +#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04)
1563 +#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08)
1564 +#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C)
1565 +#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10)
1566 +
1567 +#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00)
1568 +#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04)
1569 +#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08)
1570 +#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C)
1571 +#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10)
1572 +
1573 +#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00)
1574 +#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04)
1575 +#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08)
1576 +#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C)
1577 +
1578 +#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00)
1579 +#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04)
1580 +
1581 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
1582 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
1583 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
1584 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
1585 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
1586 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
1587 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
1588 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
1589 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
1590 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
1591 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
1592 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
1593 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
1594 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
1595 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
1596 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
1597 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
1598 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
1599 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
1600 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
1601 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
1602 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
1603 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
1604 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
1605 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
1606 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
1607 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
1608 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
1609 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
1610 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
1611 +
1612 +
1613 +#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00)
1614 +#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04)
1615 +#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08)
1616 +#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C)
1617 +#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10)
1618 +#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14)
1619 +#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18)
1620 +#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C)
1621 +#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20)
1622 +#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24)
1623 +#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28)
1624 +#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C)
1625 +#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30)
1626 +#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34)
1627 +#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38)
1628 +#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C)
1629 +#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40)
1630 +#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44)
1631 +#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48)
1632 +#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C)
1633 +#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50)
1634 +#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54)
1635 +#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58)
1636 +#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C)
1637 +#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x60)
1638 +#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x64)
1639 +#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
1640 +#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
1641 +
1642 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
1643 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
1644 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
1645 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
1646 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
1647 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
1648 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
1649 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
1650 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
1651 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
1652 +
1653 +#define RT5350_SDM_ICS_EN BIT(16)
1654 +#define RT5350_SDM_TCS_EN BIT(17)
1655 +#define RT5350_SDM_UCS_EN BIT(18)
1656 +
1657 +
1658 +/* MDIO_CFG register bits */
1659 +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
1660 +#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
1661 +#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15)
1662 +#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13)
1663 +#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13)
1664 +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
1665 +#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12)
1666 +#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11)
1667 +#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10)
1668 +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9)
1669 +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8)
1670 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
1671 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
1672 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
1673 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
1674 +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
1675 +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
1676 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
1677 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
1678 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
1679 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
1680 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0
1681 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
1682 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
1683 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
1684 +
1685 +/* uni-cast port */
1686 +#define RAMIPS_GDM1_ICS_EN BIT(22)
1687 +#define RAMIPS_GDM1_TCS_EN BIT(21)
1688 +#define RAMIPS_GDM1_UCS_EN BIT(20)
1689 +#define RAMIPS_GDM1_JMB_EN BIT(19)
1690 +#define RAMIPS_GDM1_STRPCRC BIT(16)
1691 +#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12)
1692 +#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12)
1693 +#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12)
1694 +
1695 +/* checksums */
1696 +#define RAMIPS_ICS_GEN_EN BIT(2)
1697 +#define RAMIPS_UCS_GEN_EN BIT(1)
1698 +#define RAMIPS_TCS_GEN_EN BIT(0)
1699 +
1700 +/* dma ring */
1701 +#define RAMIPS_PST_DRX_IDX0 BIT(16)
1702 +#define RAMIPS_PST_DTX_IDX3 BIT(3)
1703 +#define RAMIPS_PST_DTX_IDX2 BIT(2)
1704 +#define RAMIPS_PST_DTX_IDX1 BIT(1)
1705 +#define RAMIPS_PST_DTX_IDX0 BIT(0)
1706 +
1707 +#define RAMIPS_TX_WB_DDONE BIT(6)
1708 +#define RAMIPS_RX_DMA_BUSY BIT(3)
1709 +#define RAMIPS_TX_DMA_BUSY BIT(1)
1710 +#define RAMIPS_RX_DMA_EN BIT(2)
1711 +#define RAMIPS_TX_DMA_EN BIT(0)
1712 +
1713 +#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4)
1714 +#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4)
1715 +#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4)
1716 +
1717 +#define RAMIPS_US_CYC_CNT_MASK 0xff
1718 +#define RAMIPS_US_CYC_CNT_SHIFT 0x8
1719 +#define RAMIPS_US_CYC_CNT_DIVISOR 1000000
1720 +
1721 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
1722 +#define RX_DMA_LSO BIT(30)
1723 +#define RX_DMA_DONE BIT(31)
1724 +
1725 +struct ramips_rx_dma {
1726 + unsigned int rxd1;
1727 + unsigned int rxd2;
1728 + unsigned int rxd3;
1729 + unsigned int rxd4;
1730 +} __packed __aligned(4);
1731 +
1732 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
1733 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
1734 +#define TX_DMA_LSO BIT(30)
1735 +#define TX_DMA_DONE BIT(31)
1736 +#define TX_DMA_QN(_x) ((_x) << 16)
1737 +#define TX_DMA_PN(_x) ((_x) << 24)
1738 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
1739 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
1740 +
1741 +struct ramips_tx_dma {
1742 + unsigned int txd1;
1743 + unsigned int txd2;
1744 + unsigned int txd3;
1745 + unsigned int txd4;
1746 +} __packed __aligned(4);
1747 +
1748 +struct raeth_tx_info {
1749 + struct ramips_tx_dma *tx_desc;
1750 + struct sk_buff *tx_skb;
1751 +};
1752 +
1753 +struct raeth_rx_info {
1754 + struct ramips_rx_dma *rx_desc;
1755 + struct sk_buff *rx_skb;
1756 + dma_addr_t rx_dma;
1757 + unsigned int pad;
1758 +};
1759 +
1760 +struct raeth_int_stats {
1761 + unsigned long rx_delayed;
1762 + unsigned long tx_delayed;
1763 + unsigned long rx_done0;
1764 + unsigned long tx_done0;
1765 + unsigned long tx_done1;
1766 + unsigned long tx_done2;
1767 + unsigned long tx_done3;
1768 + unsigned long rx_coherent;
1769 + unsigned long tx_coherent;
1770 +
1771 + unsigned long pse_fq_empty;
1772 + unsigned long pse_p0_fc;
1773 + unsigned long pse_p1_fc;
1774 + unsigned long pse_p2_fc;
1775 + unsigned long pse_buf_drop;
1776 +
1777 + unsigned long total;
1778 +};
1779 +
1780 +struct raeth_debug {
1781 + struct dentry *debugfs_dir;
1782 +
1783 + struct raeth_int_stats int_stats;
1784 +};
1785 +
1786 +struct raeth_priv
1787 +{
1788 + struct device_node *of_node;
1789 +
1790 + struct raeth_rx_info *rx_info;
1791 + dma_addr_t rx_desc_dma;
1792 + struct tasklet_struct rx_tasklet;
1793 + struct ramips_rx_dma *rx;
1794 +
1795 + struct raeth_tx_info *tx_info;
1796 + dma_addr_t tx_desc_dma;
1797 + struct tasklet_struct tx_housekeeping_tasklet;
1798 + struct ramips_tx_dma *tx;
1799 +
1800 + unsigned int skb_free_idx;
1801 +
1802 + spinlock_t page_lock;
1803 + struct net_device *netdev;
1804 + struct device *parent;
1805 +
1806 + int link;
1807 + int speed;
1808 + int duplex;
1809 + int tx_fc;
1810 + int rx_fc;
1811 +
1812 + struct mii_bus *mii_bus;
1813 + int mii_irq[PHY_MAX_ADDR];
1814 + struct phy_device *phy_dev;
1815 + spinlock_t phy_lock;
1816 + unsigned long sys_freq;
1817 +
1818 + unsigned char mac[6];
1819 + void (*reset_fe)(void);
1820 + int min_pkt_len;
1821 +
1822 + u32 phy_mask;
1823 + phy_interface_t phy_if_mode;
1824 +
1825 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1826 + struct raeth_debug debug;
1827 +#endif
1828 +};
1829 +
1830 +struct ramips_soc_data
1831 +{
1832 + unsigned char mac[6];
1833 + void (*reset_fe)(void);
1834 + int min_pkt_len;
1835 +};
1836 +
1837 +
1838 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1839 +int raeth_debugfs_root_init(void);
1840 +void raeth_debugfs_root_exit(void);
1841 +int raeth_debugfs_init(struct raeth_priv *re);
1842 +void raeth_debugfs_exit(struct raeth_priv *re);
1843 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status);
1844 +#else
1845 +static inline int raeth_debugfs_root_init(void) { return 0; }
1846 +static inline void raeth_debugfs_root_exit(void) {}
1847 +static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; }
1848 +static inline void raeth_debugfs_exit(struct raeth_priv *re) {}
1849 +static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re,
1850 + u32 status) {}
1851 +#endif /* CONFIG_NET_RAMIPS_DEBUG_FS */
1852 +
1853 +#endif /* RAMIPS_ETH_H */
1854 --- /dev/null
1855 +++ b/drivers/net/ethernet/ramips/ramips_main.c
1856 @@ -0,0 +1,1285 @@
1857 +/*
1858 + * This program is free software; you can redistribute it and/or modify
1859 + * it under the terms of the GNU General Public License as published by
1860 + * the Free Software Foundation; version 2 of the License
1861 + *
1862 + * This program is distributed in the hope that it will be useful,
1863 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1864 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1865 + * GNU General Public License for more details.
1866 + *
1867 + * You should have received a copy of the GNU General Public License
1868 + * along with this program; if not, write to the Free Software
1869 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1870 + *
1871 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1872 + */
1873 +
1874 +#include <linux/module.h>
1875 +#include <linux/kernel.h>
1876 +#include <linux/types.h>
1877 +#include <linux/dma-mapping.h>
1878 +#include <linux/init.h>
1879 +#include <linux/skbuff.h>
1880 +#include <linux/etherdevice.h>
1881 +#include <linux/ethtool.h>
1882 +#include <linux/platform_device.h>
1883 +#include <linux/phy.h>
1884 +#include <linux/of_device.h>
1885 +#include <linux/clk.h>
1886 +#include <linux/of_net.h>
1887 +
1888 +#include "ramips_eth.h"
1889 +
1890 +#define TX_TIMEOUT (20 * HZ / 100)
1891 +#define MAX_RX_LENGTH 1600
1892 +
1893 +#ifdef CONFIG_SOC_RT305X
1894 +#include <rt305x.h>
1895 +#include "ramips_esw.c"
1896 +#else
1897 +#include <asm/mach-ralink/ralink_regs.h>
1898 +static inline int rt305x_esw_init(void) { return 0; }
1899 +static inline void rt305x_esw_exit(void) { }
1900 +static inline int soc_is_rt5350(void) { return 0; }
1901 +#endif
1902 +
1903 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
1904 +
1905 +#ifdef CONFIG_NET_RAMIPS_DEBUG
1906 +#define RADEBUG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
1907 +#else
1908 +#define RADEBUG(fmt, args...) do {} while (0)
1909 +#endif
1910 +
1911 +#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT))
1912 +#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT))
1913 +
1914 +enum raeth_reg {
1915 + RAETH_REG_PDMA_GLO_CFG = 0,
1916 + RAETH_REG_PDMA_RST_CFG,
1917 + RAETH_REG_DLY_INT_CFG,
1918 + RAETH_REG_TX_BASE_PTR0,
1919 + RAETH_REG_TX_MAX_CNT0,
1920 + RAETH_REG_TX_CTX_IDX0,
1921 + RAETH_REG_RX_BASE_PTR0,
1922 + RAETH_REG_RX_MAX_CNT0,
1923 + RAETH_REG_RX_CALC_IDX0,
1924 + RAETH_REG_FE_INT_ENABLE,
1925 + RAETH_REG_FE_INT_STATUS,
1926 + RAETH_REG_COUNT
1927 +};
1928 +
1929 +static const u32 ramips_reg_table[RAETH_REG_COUNT] = {
1930 + [RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG,
1931 + [RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG,
1932 + [RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG,
1933 + [RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0,
1934 + [RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0,
1935 + [RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0,
1936 + [RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0,
1937 + [RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0,
1938 + [RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0,
1939 + [RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE,
1940 + [RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS,
1941 +};
1942 +
1943 +static const u32 rt5350_reg_table[RAETH_REG_COUNT] = {
1944 + [RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
1945 + [RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
1946 + [RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
1947 + [RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
1948 + [RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
1949 + [RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
1950 + [RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
1951 + [RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
1952 + [RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
1953 + [RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
1954 + [RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
1955 +};
1956 +
1957 +static struct net_device * ramips_dev;
1958 +static void __iomem *ramips_fe_base = 0;
1959 +
1960 +static inline u32 get_reg_offset(enum raeth_reg reg)
1961 +{
1962 + const u32 *table;
1963 +
1964 + if (soc_is_rt5350())
1965 + table = rt5350_reg_table;
1966 + else
1967 + table = ramips_reg_table;
1968 +
1969 + return table[reg];
1970 +}
1971 +
1972 +static inline void
1973 +ramips_fe_wr(u32 val, unsigned reg)
1974 +{
1975 + __raw_writel(val, ramips_fe_base + reg);
1976 +}
1977 +
1978 +static inline u32
1979 +ramips_fe_rr(unsigned reg)
1980 +{
1981 + return __raw_readl(ramips_fe_base + reg);
1982 +}
1983 +
1984 +static inline void
1985 +ramips_fe_twr(u32 val, enum raeth_reg reg)
1986 +{
1987 + ramips_fe_wr(val, get_reg_offset(reg));
1988 +}
1989 +
1990 +static inline u32
1991 +ramips_fe_trr(enum raeth_reg reg)
1992 +{
1993 + return ramips_fe_rr(get_reg_offset(reg));
1994 +}
1995 +
1996 +static inline void
1997 +ramips_fe_int_disable(u32 mask)
1998 +{
1999 + ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask,
2000 + RAETH_REG_FE_INT_ENABLE);
2001 + /* flush write */
2002 + ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2003 +}
2004 +
2005 +static inline void
2006 +ramips_fe_int_enable(u32 mask)
2007 +{
2008 + ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask,
2009 + RAETH_REG_FE_INT_ENABLE);
2010 + /* flush write */
2011 + ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2012 +}
2013 +
2014 +static inline void
2015 +ramips_hw_set_macaddr(unsigned char *mac)
2016 +{
2017 + if (soc_is_rt5350()) {
2018 + ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
2019 + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2020 + RT5350_SDM_MAC_ADRL);
2021 + } else {
2022 + ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
2023 + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2024 + RAMIPS_GDMA1_MAC_ADRL);
2025 + }
2026 +}
2027 +
2028 +static struct sk_buff *
2029 +ramips_alloc_skb(struct raeth_priv *re)
2030 +{
2031 + struct sk_buff *skb;
2032 +
2033 + skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2034 + if (!skb)
2035 + return NULL;
2036 +
2037 + skb_reserve(skb, NET_IP_ALIGN);
2038 +
2039 + return skb;
2040 +}
2041 +
2042 +static void
2043 +ramips_ring_setup(struct raeth_priv *re)
2044 +{
2045 + int len;
2046 + int i;
2047 +
2048 + memset(re->tx_info, 0, NUM_TX_DESC * sizeof(struct raeth_tx_info));
2049 +
2050 + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2051 + memset(re->tx, 0, len);
2052 +
2053 + for (i = 0; i < NUM_TX_DESC; i++) {
2054 + struct raeth_tx_info *txi;
2055 + struct ramips_tx_dma *txd;
2056 +
2057 + txd = &re->tx[i];
2058 + txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
2059 + txd->txd2 = TX_DMA_LSO | TX_DMA_DONE;
2060 +
2061 + txi = &re->tx_info[i];
2062 + txi->tx_desc = txd;
2063 + if (txi->tx_skb != NULL) {
2064 + netdev_warn(re->netdev,
2065 + "dirty skb for TX desc %d\n", i);
2066 + txi->tx_skb = NULL;
2067 + }
2068 + }
2069 +
2070 + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2071 + memset(re->rx, 0, len);
2072 +
2073 + for (i = 0; i < NUM_RX_DESC; i++) {
2074 + struct raeth_rx_info *rxi;
2075 + struct ramips_rx_dma *rxd;
2076 + dma_addr_t dma_addr;
2077 +
2078 + rxd = &re->rx[i];
2079 + rxi = &re->rx_info[i];
2080 + BUG_ON(rxi->rx_skb == NULL);
2081 + dma_addr = dma_map_single(&re->netdev->dev, rxi->rx_skb->data,
2082 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
2083 + rxi->rx_dma = dma_addr;
2084 + rxi->rx_desc = rxd;
2085 +
2086 + rxd->rxd1 = (unsigned int) dma_addr;
2087 + rxd->rxd2 = RX_DMA_LSO;
2088 + }
2089 +
2090 + /* flush descriptors */
2091 + wmb();
2092 +}
2093 +
2094 +static void
2095 +ramips_ring_cleanup(struct raeth_priv *re)
2096 +{
2097 + int i;
2098 +
2099 + for (i = 0; i < NUM_RX_DESC; i++) {
2100 + struct raeth_rx_info *rxi;
2101 +
2102 + rxi = &re->rx_info[i];
2103 + if (rxi->rx_skb)
2104 + dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2105 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
2106 + }
2107 +
2108 + for (i = 0; i < NUM_TX_DESC; i++) {
2109 + struct raeth_tx_info *txi;
2110 +
2111 + txi = &re->tx_info[i];
2112 + if (txi->tx_skb) {
2113 + dev_kfree_skb_any(txi->tx_skb);
2114 + txi->tx_skb = NULL;
2115 + }
2116 + }
2117 +
2118 + netdev_reset_queue(re->netdev);
2119 +}
2120 +
2121 +#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT3883)
2122 +
2123 +#define RAMIPS_MDIO_RETRY 1000
2124 +
2125 +static unsigned char *ramips_speed_str(struct raeth_priv *re)
2126 +{
2127 + switch (re->speed) {
2128 + case SPEED_1000:
2129 + return "1000";
2130 + case SPEED_100:
2131 + return "100";
2132 + case SPEED_10:
2133 + return "10";
2134 + }
2135 +
2136 + return "?";
2137 +}
2138 +
2139 +static void ramips_link_adjust(struct raeth_priv *re)
2140 +{
2141 + u32 mdio_cfg;
2142 +
2143 + if (!re->link) {
2144 + netif_carrier_off(re->netdev);
2145 + netdev_info(re->netdev, "link down\n");
2146 + return;
2147 + }
2148 +
2149 + mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
2150 + RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
2151 + RAMIPS_MDIO_CFG_GP1_FRC_EN;
2152 +
2153 + if (re->duplex == DUPLEX_FULL)
2154 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
2155 +
2156 + if (re->tx_fc)
2157 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
2158 +
2159 + if (re->rx_fc)
2160 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
2161 +
2162 + switch (re->speed) {
2163 + case SPEED_10:
2164 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
2165 + break;
2166 + case SPEED_100:
2167 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
2168 + break;
2169 + case SPEED_1000:
2170 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
2171 + break;
2172 + default:
2173 + BUG();
2174 + }
2175 +
2176 + ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
2177 +
2178 + netif_carrier_on(re->netdev);
2179 + netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n",
2180 + ramips_speed_str(re),
2181 + (DUPLEX_FULL == re->duplex) ? "Full" : "Half");
2182 +}
2183 +
2184 +static int
2185 +ramips_mdio_wait_ready(struct raeth_priv *re)
2186 +{
2187 + int retries;
2188 +
2189 + retries = RAMIPS_MDIO_RETRY;
2190 + while (1) {
2191 + u32 t;
2192 +
2193 + t = ramips_fe_rr(RAMIPS_MDIO_ACCESS);
2194 + if ((t & (0x1 << 31)) == 0)
2195 + return 0;
2196 +
2197 + if (retries-- == 0)
2198 + break;
2199 +
2200 + udelay(1);
2201 + }
2202 +
2203 + dev_err(re->parent, "MDIO operation timed out\n");
2204 + return -ETIMEDOUT;
2205 +}
2206 +
2207 +static int
2208 +ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2209 +{
2210 + struct raeth_priv *re = bus->priv;
2211 + int err;
2212 + u32 t;
2213 +
2214 + err = ramips_mdio_wait_ready(re);
2215 + if (err)
2216 + return 0xffff;
2217 +
2218 + t = (phy_addr << 24) | (phy_reg << 16);
2219 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2220 + t |= (1 << 31);
2221 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2222 +
2223 + err = ramips_mdio_wait_ready(re);
2224 + if (err)
2225 + return 0xffff;
2226 +
2227 + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2228 + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2229 +
2230 + return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff;
2231 +}
2232 +
2233 +static int
2234 +ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2235 +{
2236 + struct raeth_priv *re = bus->priv;
2237 + int err;
2238 + u32 t;
2239 +
2240 + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2241 + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2242 +
2243 + err = ramips_mdio_wait_ready(re);
2244 + if (err)
2245 + return err;
2246 +
2247 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2248 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2249 + t |= (1 << 31);
2250 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2251 +
2252 + return ramips_mdio_wait_ready(re);
2253 +}
2254 +
2255 +static int
2256 +ramips_mdio_reset(struct mii_bus *bus)
2257 +{
2258 + /* TODO */
2259 + return 0;
2260 +}
2261 +
2262 +static int
2263 +ramips_mdio_init(struct raeth_priv *re)
2264 +{
2265 + int err;
2266 + int i;
2267 +
2268 + re->mii_bus = mdiobus_alloc();
2269 + if (re->mii_bus == NULL)
2270 + return -ENOMEM;
2271 +
2272 + re->mii_bus->name = "ramips_mdio";
2273 + re->mii_bus->read = ramips_mdio_read;
2274 + re->mii_bus->write = ramips_mdio_write;
2275 + re->mii_bus->reset = ramips_mdio_reset;
2276 + re->mii_bus->irq = re->mii_irq;
2277 + re->mii_bus->priv = re;
2278 + re->mii_bus->parent = re->parent;
2279 +
2280 + snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
2281 + re->mii_bus->phy_mask = 0;
2282 +
2283 + for (i = 0; i < PHY_MAX_ADDR; i++)
2284 + re->mii_irq[i] = PHY_POLL;
2285 +
2286 + err = mdiobus_register(re->mii_bus);
2287 + if (err)
2288 + goto err_free_bus;
2289 +
2290 + return 0;
2291 +
2292 +err_free_bus:
2293 + kfree(re->mii_bus);
2294 + return err;
2295 +}
2296 +
2297 +static void
2298 +ramips_mdio_cleanup(struct raeth_priv *re)
2299 +{
2300 + mdiobus_unregister(re->mii_bus);
2301 + kfree(re->mii_bus);
2302 +}
2303 +
2304 +static void
2305 +ramips_phy_link_adjust(struct net_device *dev)
2306 +{
2307 + struct raeth_priv *re = netdev_priv(dev);
2308 + struct phy_device *phydev = re->phy_dev;
2309 + unsigned long flags;
2310 + int status_change = 0;
2311 +
2312 + spin_lock_irqsave(&re->phy_lock, flags);
2313 +
2314 + if (phydev->link)
2315 + if (re->duplex != phydev->duplex ||
2316 + re->speed != phydev->speed)
2317 + status_change = 1;
2318 +
2319 + if (phydev->link != re->link)
2320 + status_change = 1;
2321 +
2322 + re->link = phydev->link;
2323 + re->duplex = phydev->duplex;
2324 + re->speed = phydev->speed;
2325 +
2326 + if (status_change)
2327 + ramips_link_adjust(re);
2328 +
2329 + spin_unlock_irqrestore(&re->phy_lock, flags);
2330 +}
2331 +
2332 +static int
2333 +ramips_phy_connect_multi(struct raeth_priv *re)
2334 +{
2335 + struct net_device *netdev = re->netdev;
2336 + struct phy_device *phydev = NULL;
2337 + int phy_addr;
2338 + int ret = 0;
2339 +
2340 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2341 + if (!(re->phy_mask & (1 << phy_addr)))
2342 + continue;
2343 +
2344 + if (re->mii_bus->phy_map[phy_addr] == NULL)
2345 + continue;
2346 +
2347 + RADEBUG("%s: PHY found at %s, uid=%08x\n",
2348 + netdev->name,
2349 + dev_name(&re->mii_bus->phy_map[phy_addr]->dev),
2350 + re->mii_bus->phy_map[phy_addr]->phy_id);
2351 +
2352 + if (phydev == NULL)
2353 + phydev = re->mii_bus->phy_map[phy_addr];
2354 + }
2355 +
2356 + if (!phydev) {
2357 + netdev_err(netdev, "no PHY found with phy_mask=%08x\n",
2358 + re->phy_mask);
2359 + return -ENODEV;
2360 + }
2361 +
2362 + re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev),
2363 + ramips_phy_link_adjust, 0, re->phy_if_mode);
2364 +
2365 + if (IS_ERR(re->phy_dev)) {
2366 + netdev_err(netdev, "could not connect to PHY at %s\n",
2367 + dev_name(&phydev->dev));
2368 + return PTR_ERR(re->phy_dev);
2369 + }
2370 +
2371 + phydev->supported &= PHY_GBIT_FEATURES;
2372 + phydev->advertising = phydev->supported;
2373 +
2374 + RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n",
2375 + netdev->name, dev_name(&phydev->dev),
2376 + phydev->phy_id, phydev->drv->name);
2377 +
2378 + re->link = 0;
2379 + re->speed = 0;
2380 + re->duplex = -1;
2381 + re->rx_fc = 0;
2382 + re->tx_fc = 0;
2383 +
2384 + return ret;
2385 +}
2386 +
2387 +static int
2388 +ramips_phy_connect_fixed(struct raeth_priv *re)
2389 +{
2390 + if (!re->speed) {
2391 + const __be32 *link;
2392 + int size;
2393 +
2394 + link = of_get_property(re->of_node,
2395 + "ralink,fixed-link", &size);
2396 + if (!link || size != (4 * sizeof(*link)))
2397 + return -ENOENT;
2398 +
2399 + re->speed = be32_to_cpup(link++);
2400 + re->duplex = be32_to_cpup(link++);
2401 + re->tx_fc = be32_to_cpup(link++);
2402 + re->rx_fc = be32_to_cpup(link++);
2403 + }
2404 +
2405 + switch (re->speed) {
2406 + case SPEED_10:
2407 + case SPEED_100:
2408 + case SPEED_1000:
2409 + break;
2410 + default:
2411 + netdev_err(re->netdev, "invalid speed specified\n");
2412 + return -EINVAL;
2413 + }
2414 +
2415 + pr_info("%s: using fixed link parameters\n", re->netdev->name);
2416 + return 0;
2417 +}
2418 +
2419 +static int
2420 +ramips_phy_connect(struct raeth_priv *re)
2421 +{
2422 + const __be32 *mask;
2423 +
2424 + mask = of_get_property(re->of_node, "ralink,phy-mask", NULL);
2425 + re->phy_if_mode = of_get_phy_mode(re->of_node);
2426 +
2427 + if (!re->phy_if_mode || !mask)
2428 + return ramips_phy_connect_fixed(re);
2429 +
2430 + re->phy_mask = be32_to_cpup(mask);
2431 + return ramips_phy_connect_multi(re);
2432 +
2433 +}
2434 +
2435 +static void
2436 +ramips_phy_disconnect(struct raeth_priv *re)
2437 +{
2438 + if (re->phy_dev)
2439 + phy_disconnect(re->phy_dev);
2440 +}
2441 +
2442 +static void
2443 +ramips_phy_start(struct raeth_priv *re)
2444 +{
2445 + unsigned long flags;
2446 +
2447 + if (re->phy_dev) {
2448 + phy_start(re->phy_dev);
2449 + } else {
2450 + spin_lock_irqsave(&re->phy_lock, flags);
2451 + re->link = 1;
2452 + ramips_link_adjust(re);
2453 + spin_unlock_irqrestore(&re->phy_lock, flags);
2454 + }
2455 +}
2456 +
2457 +static void
2458 +ramips_phy_stop(struct raeth_priv *re)
2459 +{
2460 + unsigned long flags;
2461 +
2462 + if (re->phy_dev)
2463 + phy_stop(re->phy_dev);
2464 +
2465 + spin_lock_irqsave(&re->phy_lock, flags);
2466 + re->link = 0;
2467 + ramips_link_adjust(re);
2468 + spin_unlock_irqrestore(&re->phy_lock, flags);
2469 +}
2470 +#else
2471 +static inline int
2472 +ramips_mdio_init(struct raeth_priv *re)
2473 +{
2474 + return 0;
2475 +}
2476 +
2477 +static inline void
2478 +ramips_mdio_cleanup(struct raeth_priv *re)
2479 +{
2480 +}
2481 +
2482 +static inline int
2483 +ramips_phy_connect(struct raeth_priv *re)
2484 +{
2485 + return 0;
2486 +}
2487 +
2488 +static inline void
2489 +ramips_phy_disconnect(struct raeth_priv *re)
2490 +{
2491 +}
2492 +
2493 +static inline void
2494 +ramips_phy_start(struct raeth_priv *re)
2495 +{
2496 +}
2497 +
2498 +static inline void
2499 +ramips_phy_stop(struct raeth_priv *re)
2500 +{
2501 +}
2502 +#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT3883 */
2503 +
2504 +static void
2505 +ramips_ring_free(struct raeth_priv *re)
2506 +{
2507 + int len;
2508 + int i;
2509 +
2510 + if (re->rx_info) {
2511 + for (i = 0; i < NUM_RX_DESC; i++) {
2512 + struct raeth_rx_info *rxi;
2513 +
2514 + rxi = &re->rx_info[i];
2515 + if (rxi->rx_skb)
2516 + dev_kfree_skb_any(rxi->rx_skb);
2517 + }
2518 + kfree(re->rx_info);
2519 + }
2520 +
2521 + if (re->rx) {
2522 + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2523 + dma_free_coherent(&re->netdev->dev, len, re->rx,
2524 + re->rx_desc_dma);
2525 + }
2526 +
2527 + if (re->tx) {
2528 + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2529 + dma_free_coherent(&re->netdev->dev, len, re->tx,
2530 + re->tx_desc_dma);
2531 + }
2532 +
2533 + kfree(re->tx_info);
2534 +}
2535 +
2536 +static int
2537 +ramips_ring_alloc(struct raeth_priv *re)
2538 +{
2539 + int len;
2540 + int err = -ENOMEM;
2541 + int i;
2542 +
2543 + re->tx_info = kzalloc(NUM_TX_DESC * sizeof(struct raeth_tx_info),
2544 + GFP_ATOMIC);
2545 + if (!re->tx_info)
2546 + goto err_cleanup;
2547 +
2548 + re->rx_info = kzalloc(NUM_RX_DESC * sizeof(struct raeth_rx_info),
2549 + GFP_ATOMIC);
2550 + if (!re->rx_info)
2551 + goto err_cleanup;
2552 +
2553 + /* allocate tx ring */
2554 + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2555 + re->tx = dma_alloc_coherent(&re->netdev->dev, len,
2556 + &re->tx_desc_dma, GFP_ATOMIC);
2557 + if (!re->tx)
2558 + goto err_cleanup;
2559 +
2560 + /* allocate rx ring */
2561 + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2562 + re->rx = dma_alloc_coherent(&re->netdev->dev, len,
2563 + &re->rx_desc_dma, GFP_ATOMIC);
2564 + if (!re->rx)
2565 + goto err_cleanup;
2566 +
2567 + for (i = 0; i < NUM_RX_DESC; i++) {
2568 + struct sk_buff *skb;
2569 +
2570 + skb = ramips_alloc_skb(re);
2571 + if (!skb)
2572 + goto err_cleanup;
2573 +
2574 + re->rx_info[i].rx_skb = skb;
2575 + }
2576 +
2577 + return 0;
2578 +
2579 +err_cleanup:
2580 + ramips_ring_free(re);
2581 + return err;
2582 +}
2583 +
2584 +static void
2585 +ramips_setup_dma(struct raeth_priv *re)
2586 +{
2587 + ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0);
2588 + ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0);
2589 + ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0);
2590 + ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG);
2591 +
2592 + ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0);
2593 + ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0);
2594 + ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0);
2595 + ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG);
2596 +}
2597 +
2598 +static int
2599 +ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
2600 +{
2601 + struct raeth_priv *re = netdev_priv(dev);
2602 + struct raeth_tx_info *txi, *txi_next;
2603 + struct ramips_tx_dma *txd, *txd_next;
2604 + unsigned long tx;
2605 + unsigned int tx_next;
2606 + dma_addr_t mapped_addr;
2607 +
2608 + if (re->min_pkt_len) {
2609 + if (skb->len < re->min_pkt_len) {
2610 + if (skb_padto(skb, re->min_pkt_len)) {
2611 + printk(KERN_ERR
2612 + "ramips_eth: skb_padto failed\n");
2613 + kfree_skb(skb);
2614 + return 0;
2615 + }
2616 + skb_put(skb, re->min_pkt_len - skb->len);
2617 + }
2618 + }
2619 +
2620 + dev->trans_start = jiffies;
2621 + mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len,
2622 + DMA_TO_DEVICE);
2623 +
2624 + spin_lock(&re->page_lock);
2625 + tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0);
2626 + tx_next = (tx + 1) % NUM_TX_DESC;
2627 +
2628 + txi = &re->tx_info[tx];
2629 + txd = txi->tx_desc;
2630 + txi_next = &re->tx_info[tx_next];
2631 + txd_next = txi_next->tx_desc;
2632 +
2633 + if ((txi->tx_skb) || (txi_next->tx_skb) ||
2634 + !(txd->txd2 & TX_DMA_DONE) ||
2635 + !(txd_next->txd2 & TX_DMA_DONE))
2636 + goto out;
2637 +
2638 + txi->tx_skb = skb;
2639 +
2640 + txd->txd1 = (unsigned int) mapped_addr;
2641 + wmb();
2642 + txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
2643 + dev->stats.tx_packets++;
2644 + dev->stats.tx_bytes += skb->len;
2645 + ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0);
2646 + netdev_sent_queue(dev, skb->len);
2647 + spin_unlock(&re->page_lock);
2648 + return NETDEV_TX_OK;
2649 +
2650 + out:
2651 + spin_unlock(&re->page_lock);
2652 + dev->stats.tx_dropped++;
2653 + kfree_skb(skb);
2654 + return NETDEV_TX_OK;
2655 +}
2656 +
2657 +static void
2658 +ramips_eth_rx_hw(unsigned long ptr)
2659 +{
2660 + struct net_device *dev = (struct net_device *) ptr;
2661 + struct raeth_priv *re = netdev_priv(dev);
2662 + int rx;
2663 + int max_rx = 16;
2664 +
2665 + rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0);
2666 +
2667 + while (max_rx) {
2668 + struct raeth_rx_info *rxi;
2669 + struct ramips_rx_dma *rxd;
2670 + struct sk_buff *rx_skb, *new_skb;
2671 + int pktlen;
2672 +
2673 + rx = (rx + 1) % NUM_RX_DESC;
2674 +
2675 + rxi = &re->rx_info[rx];
2676 + rxd = rxi->rx_desc;
2677 + if (!(rxd->rxd2 & RX_DMA_DONE))
2678 + break;
2679 +
2680 + rx_skb = rxi->rx_skb;
2681 + pktlen = RX_DMA_PLEN0(rxd->rxd2);
2682 +
2683 + new_skb = ramips_alloc_skb(re);
2684 + /* Reuse the buffer on allocation failures */
2685 + if (new_skb) {
2686 + dma_addr_t dma_addr;
2687 +
2688 + dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2689 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
2690 +
2691 + skb_put(rx_skb, pktlen);
2692 + rx_skb->dev = dev;
2693 + rx_skb->protocol = eth_type_trans(rx_skb, dev);
2694 + rx_skb->ip_summed = CHECKSUM_NONE;
2695 + dev->stats.rx_packets++;
2696 + dev->stats.rx_bytes += pktlen;
2697 + netif_rx(rx_skb);
2698 +
2699 + rxi->rx_skb = new_skb;
2700 +
2701 + dma_addr = dma_map_single(&re->netdev->dev,
2702 + new_skb->data,
2703 + MAX_RX_LENGTH,
2704 + DMA_FROM_DEVICE);
2705 + rxi->rx_dma = dma_addr;
2706 + rxd->rxd1 = (unsigned int) dma_addr;
2707 + wmb();
2708 + } else {
2709 + dev->stats.rx_dropped++;
2710 + }
2711 +
2712 + rxd->rxd2 = RX_DMA_LSO;
2713 + ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0);
2714 + max_rx--;
2715 + }
2716 +
2717 + if (max_rx == 0)
2718 + tasklet_schedule(&re->rx_tasklet);
2719 + else
2720 + ramips_fe_int_enable(RX_DLY_INT);
2721 +}
2722 +
2723 +static void
2724 +ramips_eth_tx_housekeeping(unsigned long ptr)
2725 +{
2726 + struct net_device *dev = (struct net_device*)ptr;
2727 + struct raeth_priv *re = netdev_priv(dev);
2728 + unsigned int bytes_compl = 0, pkts_compl = 0;
2729 +
2730 + spin_lock(&re->page_lock);
2731 + while (1) {
2732 + struct raeth_tx_info *txi;
2733 + struct ramips_tx_dma *txd;
2734 +
2735 + txi = &re->tx_info[re->skb_free_idx];
2736 + txd = txi->tx_desc;
2737 +
2738 + if (!(txd->txd2 & TX_DMA_DONE) || !(txi->tx_skb))
2739 + break;
2740 +
2741 + pkts_compl++;
2742 + bytes_compl += txi->tx_skb->len;
2743 +
2744 + dev_kfree_skb_irq(txi->tx_skb);
2745 + txi->tx_skb = NULL;
2746 + re->skb_free_idx++;
2747 + if (re->skb_free_idx >= NUM_TX_DESC)
2748 + re->skb_free_idx = 0;
2749 + }
2750 + netdev_completed_queue(dev, pkts_compl, bytes_compl);
2751 + spin_unlock(&re->page_lock);
2752 +
2753 + ramips_fe_int_enable(TX_DLY_INT);
2754 +}
2755 +
2756 +static void
2757 +ramips_eth_timeout(struct net_device *dev)
2758 +{
2759 + struct raeth_priv *re = netdev_priv(dev);
2760 +
2761 + tasklet_schedule(&re->tx_housekeeping_tasklet);
2762 +}
2763 +
2764 +static irqreturn_t
2765 +ramips_eth_irq(int irq, void *dev)
2766 +{
2767 + struct raeth_priv *re = netdev_priv(dev);
2768 + unsigned int status;
2769 +
2770 + status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS);
2771 + status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2772 +
2773 + if (!status)
2774 + return IRQ_NONE;
2775 +
2776 + ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS);
2777 +
2778 + if (status & RX_DLY_INT) {
2779 + ramips_fe_int_disable(RX_DLY_INT);
2780 + tasklet_schedule(&re->rx_tasklet);
2781 + }
2782 +
2783 + if (status & TX_DLY_INT) {
2784 + ramips_fe_int_disable(TX_DLY_INT);
2785 + tasklet_schedule(&re->tx_housekeeping_tasklet);
2786 + }
2787 +
2788 + raeth_debugfs_update_int_stats(re, status);
2789 +
2790 + return IRQ_HANDLED;
2791 +}
2792 +
2793 +static int
2794 +ramips_eth_hw_init(struct net_device *dev)
2795 +{
2796 + struct raeth_priv *re = netdev_priv(dev);
2797 + int err;
2798 +
2799 + err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED,
2800 + dev_name(re->parent), dev);
2801 + if (err)
2802 + return err;
2803 +
2804 + err = ramips_ring_alloc(re);
2805 + if (err)
2806 + goto err_free_irq;
2807 +
2808 + ramips_ring_setup(re);
2809 + ramips_hw_set_macaddr(dev->dev_addr);
2810 +
2811 + ramips_setup_dma(re);
2812 + ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) &
2813 + ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) |
2814 + ((re->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT),
2815 + RAMIPS_FE_GLO_CFG);
2816 +
2817 + tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping,
2818 + (unsigned long)dev);
2819 + tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
2820 +
2821 +
2822 + ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG);
2823 + ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
2824 + if (soc_is_rt5350()) {
2825 + ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) &
2826 + ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff),
2827 + RT5350_SDM_CFG);
2828 + } else {
2829 + ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
2830 + ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
2831 + RAMIPS_GDMA1_FWD_CFG);
2832 + ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
2833 + ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
2834 + RAMIPS_CDMA_CSG_CFG);
2835 + ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
2836 + }
2837 + ramips_fe_wr(1, RAMIPS_FE_RST_GL);
2838 + ramips_fe_wr(0, RAMIPS_FE_RST_GL);
2839 +
2840 + return 0;
2841 +
2842 +err_free_irq:
2843 + free_irq(dev->irq, dev);
2844 + return err;
2845 +}
2846 +
2847 +static int
2848 +ramips_eth_open(struct net_device *dev)
2849 +{
2850 + struct raeth_priv *re = netdev_priv(dev);
2851 +
2852 + ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) |
2853 + (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN |
2854 + RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS),
2855 + RAETH_REG_PDMA_GLO_CFG);
2856 + ramips_phy_start(re);
2857 + netif_start_queue(dev);
2858 + return 0;
2859 +}
2860 +
2861 +static int
2862 +ramips_eth_stop(struct net_device *dev)
2863 +{
2864 + struct raeth_priv *re = netdev_priv(dev);
2865 +
2866 + ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) &
2867 + ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN),
2868 + RAETH_REG_PDMA_GLO_CFG);
2869 +
2870 + netif_stop_queue(dev);
2871 + ramips_phy_stop(re);
2872 + RADEBUG("ramips_eth: stopped\n");
2873 + return 0;
2874 +}
2875 +
2876 +static int __init
2877 +ramips_eth_probe(struct net_device *dev)
2878 +{
2879 + struct raeth_priv *re = netdev_priv(dev);
2880 + int err;
2881 +
2882 + BUG_ON(!re->reset_fe);
2883 + re->reset_fe();
2884 + net_srandom(jiffies);
2885 + memcpy(dev->dev_addr, re->mac, ETH_ALEN);
2886 + of_get_mac_address_mtd(re->of_node, dev->dev_addr);
2887 + ether_setup(dev);
2888 + dev->mtu = 1500;
2889 + dev->watchdog_timeo = TX_TIMEOUT;
2890 + spin_lock_init(&re->page_lock);
2891 + spin_lock_init(&re->phy_lock);
2892 +
2893 + err = ramips_mdio_init(re);
2894 + if (err)
2895 + return err;
2896 +
2897 + err = ramips_phy_connect(re);
2898 + if (err)
2899 + goto err_mdio_cleanup;
2900 +
2901 + err = raeth_debugfs_init(re);
2902 + if (err)
2903 + goto err_phy_disconnect;
2904 +
2905 + err = ramips_eth_hw_init(dev);
2906 + if (err)
2907 + goto err_debugfs;
2908 +
2909 + return 0;
2910 +
2911 +err_debugfs:
2912 + raeth_debugfs_exit(re);
2913 +err_phy_disconnect:
2914 + ramips_phy_disconnect(re);
2915 +err_mdio_cleanup:
2916 + ramips_mdio_cleanup(re);
2917 + return err;
2918 +}
2919 +
2920 +static void
2921 +ramips_eth_uninit(struct net_device *dev)
2922 +{
2923 + struct raeth_priv *re = netdev_priv(dev);
2924 +
2925 + raeth_debugfs_exit(re);
2926 + ramips_phy_disconnect(re);
2927 + ramips_mdio_cleanup(re);
2928 + ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE);
2929 + free_irq(dev->irq, dev);
2930 + tasklet_kill(&re->tx_housekeeping_tasklet);
2931 + tasklet_kill(&re->rx_tasklet);
2932 + ramips_ring_cleanup(re);
2933 + ramips_ring_free(re);
2934 +}
2935 +
2936 +static const struct net_device_ops ramips_eth_netdev_ops = {
2937 + .ndo_init = ramips_eth_probe,
2938 + .ndo_uninit = ramips_eth_uninit,
2939 + .ndo_open = ramips_eth_open,
2940 + .ndo_stop = ramips_eth_stop,
2941 + .ndo_start_xmit = ramips_eth_hard_start_xmit,
2942 + .ndo_tx_timeout = ramips_eth_timeout,
2943 + .ndo_change_mtu = eth_change_mtu,
2944 + .ndo_set_mac_address = eth_mac_addr,
2945 + .ndo_validate_addr = eth_validate_addr,
2946 +};
2947 +
2948 +#ifdef CONFIG_SOC_RT305X
2949 +static void rt305x_fe_reset(void)
2950 +{
2951 +#define RT305X_RESET_FE BIT(21)
2952 +#define RT305X_RESET_ESW BIT(23)
2953 +#define SYSC_REG_RESET_CTRL 0x034
2954 + u32 reset_bits = RT305X_RESET_FE;
2955 +
2956 + if (soc_is_rt5350())
2957 + reset_bits |= RT305X_RESET_ESW;
2958 + rt_sysc_w32(reset_bits, SYSC_REG_RESET_CTRL);
2959 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
2960 +}
2961 +
2962 +struct ramips_soc_data rt3050_data = {
2963 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
2964 + .reset_fe = rt305x_fe_reset,
2965 + .min_pkt_len = 64,
2966 +};
2967 +
2968 +static const struct of_device_id ralink_eth_match[] = {
2969 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
2970 + {},
2971 +};
2972 +#else
2973 +static void rt3883_fe_reset(void)
2974 +{
2975 +#define RT3883_SYSC_REG_RSTCTRL 0x34
2976 +#define RT3883_RSTCTRL_FE BIT(21)
2977 + u32 t;
2978 +
2979 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
2980 + t |= RT3883_RSTCTRL_FE;
2981 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
2982 +
2983 + t &= ~RT3883_RSTCTRL_FE;
2984 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
2985 +}
2986 +
2987 +struct ramips_soc_data rt3883_data = {
2988 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
2989 + .reset_fe = rt3883_fe_reset,
2990 + .min_pkt_len = 64,
2991 +};
2992 +
2993 +static const struct of_device_id ralink_eth_match[] = {
2994 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
2995 + {},
2996 +};
2997 +#endif
2998 +MODULE_DEVICE_TABLE(of, ralink_eth_match);
2999 +
3000 +static int
3001 +ramips_eth_plat_probe(struct platform_device *plat)
3002 +{
3003 + struct raeth_priv *re;
3004 + struct resource *res;
3005 + struct clk *clk;
3006 + int err;
3007 + const struct of_device_id *match;
3008 + const struct ramips_soc_data *soc = NULL;
3009 +
3010 + match = of_match_device(ralink_eth_match, &plat->dev);
3011 + if (match)
3012 + soc = (const struct ramips_soc_data *) match->data;
3013 +
3014 + if (!soc) {
3015 + dev_err(&plat->dev, "no platform data specified\n");
3016 + return -EINVAL;
3017 + }
3018 +
3019 + res = platform_get_resource(plat, IORESOURCE_MEM, 0);
3020 + if (!res) {
3021 + dev_err(&plat->dev, "no memory resource found\n");
3022 + return -ENXIO;
3023 + }
3024 +
3025 + ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1);
3026 + if (!ramips_fe_base)
3027 + return -ENOMEM;
3028 +
3029 + ramips_dev = alloc_etherdev(sizeof(struct raeth_priv));
3030 + if (!ramips_dev) {
3031 + dev_err(&plat->dev, "alloc_etherdev failed\n");
3032 + err = -ENOMEM;
3033 + goto err_unmap;
3034 + }
3035 +
3036 + strcpy(ramips_dev->name, "eth%d");
3037 + ramips_dev->irq = platform_get_irq(plat, 0);
3038 + if (ramips_dev->irq < 0) {
3039 + dev_err(&plat->dev, "no IRQ resource found\n");
3040 + err = -ENXIO;
3041 + goto err_free_dev;
3042 + }
3043 + ramips_dev->addr_len = ETH_ALEN;
3044 + ramips_dev->base_addr = (unsigned long)ramips_fe_base;
3045 + ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
3046 +
3047 + re = netdev_priv(ramips_dev);
3048 +
3049 + clk = clk_get(&plat->dev, NULL);
3050 + if (IS_ERR(clk))
3051 + panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
3052 + re->sys_freq = clk_get_rate(clk);
3053 +
3054 + re->netdev = ramips_dev;
3055 + re->of_node = plat->dev.of_node;
3056 + re->parent = &plat->dev;
3057 + memcpy(re->mac, soc->mac, 6);
3058 + re->reset_fe = soc->reset_fe;
3059 + re->min_pkt_len = soc->min_pkt_len;
3060 +
3061 + err = register_netdev(ramips_dev);
3062 + if (err) {
3063 + dev_err(&plat->dev, "error bringing up device\n");
3064 + goto err_free_dev;
3065 + }
3066 +
3067 + netdev_info(ramips_dev, "done loading\n");
3068 + return 0;
3069 +
3070 + err_free_dev:
3071 + kfree(ramips_dev);
3072 + err_unmap:
3073 + iounmap(ramips_fe_base);
3074 + return err;
3075 +}
3076 +
3077 +static int
3078 +ramips_eth_plat_remove(struct platform_device *plat)
3079 +{
3080 + unregister_netdev(ramips_dev);
3081 + free_netdev(ramips_dev);
3082 + RADEBUG("ramips_eth: unloaded\n");
3083 + return 0;
3084 +}
3085 +
3086 +
3087 +
3088 +static struct platform_driver ramips_eth_driver = {
3089 + .probe = ramips_eth_plat_probe,
3090 + .remove = ramips_eth_plat_remove,
3091 + .driver = {
3092 + .name = "ramips_eth",
3093 + .owner = THIS_MODULE,
3094 + .of_match_table = ralink_eth_match
3095 + },
3096 +};
3097 +
3098 +static int __init
3099 +ramips_eth_init(void)
3100 +{
3101 + int ret;
3102 +
3103 + ret = raeth_debugfs_root_init();
3104 + if (ret)
3105 + goto err_out;
3106 +
3107 + ret = rt305x_esw_init();
3108 + if (ret)
3109 + goto err_debugfs_exit;
3110 +
3111 + ret = platform_driver_register(&ramips_eth_driver);
3112 + if (ret) {
3113 + printk(KERN_ERR
3114 + "ramips_eth: Error registering platfom driver!\n");
3115 + goto esw_cleanup;
3116 + }
3117 +
3118 + return 0;
3119 +
3120 +esw_cleanup:
3121 + rt305x_esw_exit();
3122 +err_debugfs_exit:
3123 + raeth_debugfs_root_exit();
3124 +err_out:
3125 + return ret;
3126 +}
3127 +
3128 +static void __exit
3129 +ramips_eth_cleanup(void)
3130 +{
3131 + platform_driver_unregister(&ramips_eth_driver);
3132 + rt305x_esw_exit();
3133 + raeth_debugfs_root_exit();
3134 +}
3135 +
3136 +module_init(ramips_eth_init);
3137 +module_exit(ramips_eth_cleanup);
3138 +
3139 +MODULE_LICENSE("GPL");
3140 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3141 +MODULE_DESCRIPTION("ethernet driver for ramips boards");
OpenWrt SVN history