target/linux/ramips/patches-3.8/0130-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch

   1 From 007ab7fe49bfcaa220372260eedeb4eed51f1631 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 22 Jan 2013 18:24:34 +0100
   4 Subject: [PATCH 130/137] GPIO: MIPS: ralink: adds ralink gpio support
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/Kconfig                        |    1 +
  12  arch/mips/include/asm/mach-ralink/gpio.h |   24 ++++
  13  drivers/gpio/Kconfig                     |    6 +
  14  drivers/gpio/Makefile                    |    1 +
  15  drivers/gpio/gpio-ralink.c               |  176 ++++++++++++++++++++++++++++++
  16  5 files changed, 208 insertions(+)
  17  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  18  create mode 100644 drivers/gpio/gpio-ralink.c
  19
  20 --- a/arch/mips/Kconfig
  21 +++ b/arch/mips/Kconfig
  22 @@ -449,6 +449,7 @@ config RALINK
  23         select SYS_HAS_EARLY_PRINTK
  24         select HAVE_MACH_CLKDEV
  25         select CLKDEV_LOOKUP
  26 +       select ARCH_REQUIRE_GPIOLIB
  27
  28  config SGI_IP22
  29         bool "SGI IP22 (Indy/Indigo2)"
  30 --- /dev/null
  31 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
  32 @@ -0,0 +1,24 @@
  33 +/*
  34 + *  Ralink SoC GPIO API support
  35 + *
  36 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  37 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  38 + *
  39 + *  This program is free software; you can redistribute it and/or modify it
  40 + *  under the terms of the GNU General Public License version 2 as published
  41 + *  by the Free Software Foundation.
  42 + *
  43 + */
  44 +
  45 +#ifndef __ASM_MACH_RALINK_GPIO_H
  46 +#define __ASM_MACH_RALINK_GPIO_H
  47 +
  48 +#define ARCH_NR_GPIOS  128
  49 +#include <asm-generic/gpio.h>
  50 +
  51 +#define gpio_get_value __gpio_get_value
  52 +#define gpio_set_value __gpio_set_value
  53 +#define gpio_cansleep  __gpio_cansleep
  54 +#define gpio_to_irq    __gpio_to_irq
  55 +
  56 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  57 --- a/drivers/gpio/Kconfig
  58 +++ b/drivers/gpio/Kconfig
  59 @@ -201,6 +201,12 @@ config GPIO_PXA
  60         help
  61           Say yes here to support the PXA GPIO device
  62
  63 +config GPIO_RALINK
  64 +       bool "Ralink GPIO Support"
  65 +       depends on RALINK
  66 +       help
  67 +         Say yes here to support the Ralink SoC GPIO device
  68 +
  69  config GPIO_SPEAR_SPICS
  70         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  71         depends on PLAT_SPEAR
  72 --- a/drivers/gpio/Makefile
  73 +++ b/drivers/gpio/Makefile
  74 @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_PCF857X)    += gpio-pcf85
  75  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  76  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  77  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  78 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  79  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  80  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  81  obj-$(CONFIG_PLAT_SAMSUNG)     += gpio-samsung.o
  82 --- /dev/null
  83 +++ b/drivers/gpio/gpio-ralink.c
  84 @@ -0,0 +1,176 @@
  85 +/*
  86 + * This program is free software; you can redistribute it and/or modify it
  87 + * under the terms of the GNU General Public License version 2 as published
  88 + * by the Free Software Foundation.
  89 + *
  90 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  91 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  92 + */
  93 +
  94 +#include <linux/module.h>
  95 +#include <linux/io.h>
  96 +#include <linux/gpio.h>
  97 +#include <linux/spinlock.h>
  98 +#include <linux/platform_device.h>
  99 +
 100 +enum ralink_gpio_reg {
 101 +       GPIO_REG_INT = 0,
 102 +       GPIO_REG_EDGE,
 103 +       GPIO_REG_RENA,
 104 +       GPIO_REG_FENA,
 105 +       GPIO_REG_DATA,
 106 +       GPIO_REG_DIR,
 107 +       GPIO_REG_POL,
 108 +       GPIO_REG_SET,
 109 +       GPIO_REG_RESET,
 110 +       GPIO_REG_TOGGLE,
 111 +       GPIO_REG_MAX
 112 +};
 113 +
 114 +struct ralink_gpio_chip {
 115 +       struct gpio_chip chip;
 116 +       u8 regs[GPIO_REG_MAX];
 117 +
 118 +       spinlock_t lock;
 119 +       void __iomem *membase;
 120 +};
 121 +
 122 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 123 +{
 124 +       struct ralink_gpio_chip *rg;
 125 +
 126 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 127 +       return rg;
 128 +}
 129 +
 130 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 131 +{
 132 +       iowrite32(val, rg->membase + rg->regs[reg]);
 133 +}
 134 +
 135 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 136 +{
 137 +       return ioread32(rg->membase + rg->regs[reg]);
 138 +}
 139 +
 140 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 141 +{
 142 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 143 +
 144 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 145 +}
 146 +
 147 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 148 +{
 149 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 150 +
 151 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 152 +}
 153 +
 154 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 155 +{
 156 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 157 +       unsigned long flags;
 158 +       u32 t;
 159 +
 160 +       spin_lock_irqsave(&rg->lock, flags);
 161 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 162 +       t &= ~BIT(offset);
 163 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 164 +       spin_unlock_irqrestore(&rg->lock, flags);
 165 +
 166 +       return 0;
 167 +}
 168 +
 169 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 170 +                                       unsigned offset, int value)
 171 +{
 172 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 173 +       unsigned long flags;
 174 +       u32 t;
 175 +
 176 +       spin_lock_irqsave(&rg->lock, flags);
 177 +       ralink_gpio_set(chip, offset, value);
 178 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 179 +       t |= BIT(offset);
 180 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 181 +       spin_unlock_irqrestore(&rg->lock, flags);
 182 +
 183 +       return 0;
 184 +}
 185 +
 186 +static int ralink_gpio_probe(struct platform_device *pdev)
 187 +{
 188 +       struct device_node *np = pdev->dev.of_node;
 189 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 190 +       struct ralink_gpio_chip *gc;
 191 +       const __be32 *ngpio;
 192 +
 193 +       if (!res) {
 194 +               dev_err(&pdev->dev, "failed to find resource\n");
 195 +               return -ENOMEM;
 196 +       }
 197 +
 198 +       gc = devm_kzalloc(&pdev->dev,
 199 +                               sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 200 +       if (!gc)
 201 +               return -ENOMEM;
 202 +
 203 +       gc->membase = devm_request_and_ioremap(&pdev->dev, res);
 204 +       if (!gc->membase) {
 205 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 206 +               return -ENOMEM;
 207 +       }
 208 +
 209 +       if (of_property_read_u8_array(np, "ralink,register-map",
 210 +                       gc->regs, GPIO_REG_MAX)) {
 211 +               dev_err(&pdev->dev, "failed to read register definition\n");
 212 +               return -EINVAL;
 213 +       }
 214 +
 215 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 216 +       if (!ngpio) {
 217 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 218 +               return -EINVAL;
 219 +       }
 220 +
 221 +       spin_lock_init(&gc->lock);
 222 +
 223 +       gc->chip.label = dev_name(&pdev->dev);
 224 +       gc->chip.of_node = np;
 225 +       gc->chip.base = -1;
 226 +       gc->chip.ngpio = be32_to_cpu(*ngpio);
 227 +       gc->chip.direction_input = ralink_gpio_direction_input;
 228 +       gc->chip.direction_output = ralink_gpio_direction_output;
 229 +       gc->chip.get = ralink_gpio_get;
 230 +       gc->chip.set = ralink_gpio_set;
 231 +
 232 +       /* set polarity to low for all lines */
 233 +       rt_gpio_w32(gc, GPIO_REG_POL, 0);
 234 +
 235 +       dev_info(&pdev->dev, "registering %d gpios\n", gc->chip.ngpio);
 236 +
 237 +       return gpiochip_add(&gc->chip);
 238 +}
 239 +
 240 +static const struct of_device_id ralink_gpio_match[] = {
 241 +       { .compatible = "ralink,rt2880-gpio" },
 242 +       {},
 243 +};
 244 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 245 +
 246 +static struct platform_driver ralink_gpio_driver = {
 247 +       .probe = ralink_gpio_probe,
 248 +       .driver = {
 249 +               .name = "rt2880_gpio",
 250 +               .owner = THIS_MODULE,
 251 +               .of_match_table = ralink_gpio_match,
 252 +       },
 253 +};
 254 +
 255 +static int __init ralink_gpio_init(void)
 256 +{
 257 +       return platform_driver_register(&ralink_gpio_driver);
 258 +}
 259 +
 260 +subsys_initcall(ralink_gpio_init);