target/linux/ramips/patches-3.8/0131-MIPS-pci-rt3883-rewrite.patch

   1 --- a/arch/mips/pci/pci-rt3883.c
   2 +++ b/arch/mips/pci/pci-rt3883.c
   3 @@ -1,7 +1,7 @@
   4  /*
   5 - *  Ralink RT3883 SoC PCI support
   6 + *  Ralink RT3662/RT3883 SoC PCI support
   7   *
   8 - *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   9 + *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  10   *
  11   *  Parts of this file are based on Ralink's 2.6.21 BSP
  12   *
  13 @@ -16,52 +16,82 @@
  14  #include <linux/init.h>
  15  #include <linux/delay.h>
  16  #include <linux/interrupt.h>
  17 +#include <linux/module.h>
  18 +#include <linux/of.h>
  19 +#include <linux/of_irq.h>
  20 +#include <linux/of_pci.h>
  21 +#include <linux/platform_device.h>
  22
  23  #include <asm/mach-ralink/rt3883.h>
  24 -#include <asm/mach-ralink/rt3883_regs.h>
  25 +#include <asm/mach-ralink/ralink_regs.h>
  26
  27  #define RT3883_MEMORY_BASE             0x00000000
  28  #define RT3883_MEMORY_SIZE             0x02000000
  29
  30 -#define RT3883_PCI_MEM_BASE            0x20000000
  31 -#define RT3883_PCI_MEM_SIZE            0x10000000
  32 -#define RT3883_PCI_IO_BASE             0x10160000
  33 -#define RT3883_PCI_IO_SIZE             0x00010000
  34 -
  35 -#define RT3883_PCI_REG_PCICFG_ADDR     0x00
  36 -#define RT3883_PCI_REG_PCIRAW_ADDR     0x04
  37 -#define RT3883_PCI_REG_PCIINT_ADDR     0x08
  38 -#define RT3883_PCI_REG_PCIMSK_ADDR     0x0c
  39 -#define   RT3833_PCI_PCIINT_PCIE       BIT(20)
  40 -#define   RT3833_PCI_PCIINT_PCI1       BIT(19)
  41 -#define   RT3833_PCI_PCIINT_PCI0       BIT(18)
  42 +#define RT3883_PCI_REG_PCICFG          0x00
  43 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  44 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  45 +#define   RT3883_PCICFG_PCIRST         BIT(1)
  46 +#define RT3883_PCI_REG_PCIRAW          0x04
  47 +#define RT3883_PCI_REG_PCIINT          0x08
  48 +#define RT3883_PCI_REG_PCIENA          0x0c
  49
  50 -#define RT3883_PCI_REG_CONFIG_ADDR     0x20
  51 -#define RT3883_PCI_REG_CONFIG_DATA     0x24
  52 +#define RT3883_PCI_REG_CFGADDR         0x20
  53 +#define RT3883_PCI_REG_CFGDATA         0x24
  54  #define RT3883_PCI_REG_MEMBASE         0x28
  55  #define RT3883_PCI_REG_IOBASE          0x2c
  56  #define RT3883_PCI_REG_ARBCTL          0x80
  57
  58  #define RT3883_PCI_REG_BASE(_x)                (0x1000 + (_x) * 0x1000)
  59 -#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
  60 -#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
  61 +#define RT3883_PCI_REG_BAR0SETUP(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x10)
  62 +#define RT3883_PCI_REG_IMBASEBAR0(_x)  (RT3883_PCI_REG_BASE((_x)) + 0x18)
  63  #define RT3883_PCI_REG_ID(_x)          (RT3883_PCI_REG_BASE((_x)) + 0x30)
  64  #define RT3883_PCI_REG_CLASS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x34)
  65  #define RT3883_PCI_REG_SUBID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x38)
  66  #define RT3883_PCI_REG_STATUS(_x)      (RT3883_PCI_REG_BASE((_x)) + 0x50)
  67
  68 -static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
  69 -static void __iomem *rt3883_pci_base;
  70 -static DEFINE_SPINLOCK(rt3883_pci_lock);
  71 +#define RT3883_PCI_MODE_NONE   0
  72 +#define RT3883_PCI_MODE_PCI    BIT(0)
  73 +#define RT3883_PCI_MODE_PCIE   BIT(1)
  74 +#define RT3883_PCI_MODE_BOTH   (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  75
  76 -static inline u32 rt3883_pci_rr(unsigned reg)
  77 +#define RT3883_PCI_IRQ_COUNT   32
  78 +
  79 +#define RT3883_P2P_BR_DEVNUM   1
  80 +
  81 +struct rt3883_pci_controller {
  82 +       void __iomem *base;
  83 +       spinlock_t lock;
  84 +
  85 +       struct irq_domain *irq_domain;
  86 +
  87 +       struct pci_controller pci_controller;
  88 +       struct resource io_res;
  89 +       struct resource mem_res;
  90 +
  91 +       bool pcie_ready;
  92 +       unsigned char p2p_devnum;
  93 +};
  94 +
  95 +static inline struct rt3883_pci_controller *
  96 +pci_bus_to_rt3883_controller(struct pci_bus *bus)
  97  {
  98 -       return readl(rt3883_pci_base + reg);
  99 +       struct pci_controller *hose;
 100 +
 101 +       hose = (struct pci_controller *) bus->sysdata;
 102 +       return container_of(hose, struct rt3883_pci_controller, pci_controller);
 103 +}
 104 +
 105 +static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
 106 +                                unsigned reg)
 107 +{
 108 +       return ioread32(rpc->base + reg);
 109  }
 110
 111 -static inline void rt3883_pci_wr(u32 val, unsigned reg)
 112 +static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
 113 +                                 u32 val, unsigned reg)
 114  {
 115 -       writel(val, rt3883_pci_base + reg);
 116 +       iowrite32(val, rpc->base + reg);
 117  }
 118
 119  static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 120 @@ -71,7 +101,8 @@ static inline u32 rt3883_pci_get_cfgaddr
 121                 0x80000000);
 122  }
 123
 124 -static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
 125 +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 126 +                              unsigned bus, unsigned slot,
 127                                unsigned func, unsigned reg)
 128  {
 129         unsigned long flags;
 130 @@ -80,15 +111,16 @@ static u32 rt3883_pci_read_u32(unsigned
 131
 132         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 133
 134 -       spin_lock_irqsave(&rt3883_pci_lock, flags);
 135 -       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 136 -       ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 137 -       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 138 +       spin_lock_irqsave(&rpc->lock, flags);
 139 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 140 +       ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 141 +       spin_unlock_irqrestore(&rpc->lock, flags);
 142
 143         return ret;
 144  }
 145
 146 -static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
 147 +static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 148 +                                unsigned bus, unsigned slot,
 149                                  unsigned func, unsigned reg, u32 val)
 150  {
 151         unsigned long flags;
 152 @@ -96,84 +128,61 @@ static void rt3883_pci_write_u32(unsigne
 153
 154         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 155
 156 -       spin_lock_irqsave(&rt3883_pci_lock, flags);
 157 -       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 158 -       rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
 159 -       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 160 +       spin_lock_irqsave(&rpc->lock, flags);
 161 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 162 +       rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
 163 +       spin_unlock_irqrestore(&rpc->lock, flags);
 164  }
 165
 166  static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 167  {
 168 +       struct rt3883_pci_controller *rpc;
 169         u32 pending;
 170
 171 -       pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
 172 -                 rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 173 +       rpc = irq_get_handler_data(irq);
 174 +
 175 +       pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
 176 +                 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 177
 178         if (!pending) {
 179                 spurious_interrupt();
 180                 return;
 181         }
 182
 183 -       if (pending & RT3833_PCI_PCIINT_PCI0)
 184 -               generic_handle_irq(RT3883_PCI_IRQ_PCI0);
 185 +       while (pending) {
 186 +               unsigned bit = __ffs(pending);
 187
 188 -       if (pending & RT3833_PCI_PCIINT_PCI1)
 189 -               generic_handle_irq(RT3883_PCI_IRQ_PCI1);
 190 +               irq = irq_find_mapping(rpc->irq_domain, bit);
 191 +               generic_handle_irq(irq);
 192
 193 -       if (pending & RT3833_PCI_PCIINT_PCIE)
 194 -               generic_handle_irq(RT3883_PCI_IRQ_PCIE);
 195 +               pending &= ~BIT(bit);
 196 +       }
 197  }
 198
 199  static void rt3883_pci_irq_unmask(struct irq_data *d)
 200  {
 201 -       int irq = d->irq;
 202 -       u32 mask;
 203 +       struct rt3883_pci_controller *rpc;
 204         u32 t;
 205
 206 -       switch (irq) {
 207 -       case RT3883_PCI_IRQ_PCI0:
 208 -               mask = RT3833_PCI_PCIINT_PCI0;
 209 -               break;
 210 -       case RT3883_PCI_IRQ_PCI1:
 211 -               mask = RT3833_PCI_PCIINT_PCI1;
 212 -               break;
 213 -       case RT3883_PCI_IRQ_PCIE:
 214 -               mask = RT3833_PCI_PCIINT_PCIE;
 215 -               break;
 216 -       default:
 217 -               BUG();
 218 -       }
 219 +       rpc = irq_data_get_irq_chip_data(d);
 220
 221 -       t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 222 -       rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
 223 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 224 +       rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 225         /* flush write */
 226 -       rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 227 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 228  }
 229
 230  static void rt3883_pci_irq_mask(struct irq_data *d)
 231  {
 232 -       int irq = d->irq;
 233 -       u32 mask;
 234 +       struct rt3883_pci_controller *rpc;
 235         u32 t;
 236
 237 -       switch (irq) {
 238 -       case RT3883_PCI_IRQ_PCI0:
 239 -               mask = RT3833_PCI_PCIINT_PCI0;
 240 -               break;
 241 -       case RT3883_PCI_IRQ_PCI1:
 242 -               mask = RT3833_PCI_PCIINT_PCI1;
 243 -               break;
 244 -       case RT3883_PCI_IRQ_PCIE:
 245 -               mask = RT3833_PCI_PCIINT_PCIE;
 246 -               break;
 247 -       default:
 248 -               BUG();
 249 -       }
 250 +       rpc = irq_data_get_irq_chip_data(d);
 251
 252 -       t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 253 -       rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
 254 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 255 +       rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 256         /* flush write */
 257 -       rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 258 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 259  }
 260
 261  static struct irq_chip rt3883_pci_irq_chip = {
 262 @@ -183,36 +192,84 @@ static struct irq_chip rt3883_pci_irq_ch
 263         .irq_mask_ack   = rt3883_pci_irq_mask,
 264  };
 265
 266 -static void __init rt3883_pci_irq_init(void)
 267 +static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
 268 +                             irq_hw_number_t hw)
 269  {
 270 -       int i;
 271 +       irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
 272 +       irq_set_chip_data(irq, d->host_data);
 273 +
 274 +       return 0;
 275 +}
 276 +
 277 +static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
 278 +       .map = rt3883_pci_irq_map,
 279 +       .xlate = irq_domain_xlate_onecell,
 280 +};
 281 +
 282 +static int rt3883_pci_irq_init(struct device *dev,
 283 +                              struct rt3883_pci_controller *rpc)
 284 +{
 285 +       struct device_node *np = dev->of_node;
 286 +       struct device_node *intc_np;
 287 +       int irq;
 288 +       int err;
 289 +
 290 +       intc_np = of_get_child_by_name(np, "interrupt-controller");
 291 +       if (!intc_np) {
 292 +               dev_err(dev, "no %s child node found", "interrupt-controller");
 293 +               return -ENODEV;
 294 +       }
 295 +
 296 +       irq = irq_of_parse_and_map(intc_np, 0);
 297 +       if (irq == 0) {
 298 +               dev_err(dev, "%s has no IRQ", of_node_full_name(intc_np));
 299 +               err = -EINVAL;
 300 +               goto err_put_intc;
 301 +       }
 302
 303         /* disable all interrupts */
 304 -       rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
 305 +       rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 306
 307 -       for (i = RT3883_PCI_IRQ_BASE;
 308 -            i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
 309 -               irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
 310 -                                        handle_level_irq);
 311 +       rpc->irq_domain =
 312 +               irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
 313 +                                     &rt3883_pci_irq_domain_ops,
 314 +                                     rpc);
 315 +       if (!rpc->irq_domain) {
 316 +               dev_err(dev, "unable to add IRQ domain\n");
 317 +               err = -ENODEV;
 318 +               goto err_put_intc;
 319         }
 320
 321 -       irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
 322 +       irq_set_handler_data(irq, rpc);
 323 +       irq_set_chained_handler(irq, rt3883_pci_irq_handler);
 324 +
 325 +       return 0;
 326 +
 327 +err_put_intc:
 328 +       of_node_put(intc_np);
 329 +       return err;
 330  }
 331
 332  static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 333                                   int where, int size, u32 *val)
 334  {
 335 +       struct rt3883_pci_controller *rpc;
 336         unsigned long flags;
 337         u32 address;
 338         u32 data;
 339
 340 +       rpc = pci_bus_to_rt3883_controller(bus);
 341 +
 342 +       if (!rpc->pcie_ready && bus->number == 1)
 343 +               return PCIBIOS_DEVICE_NOT_FOUND;
 344 +
 345         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 346                                          PCI_FUNC(devfn), where);
 347
 348 -       spin_lock_irqsave(&rt3883_pci_lock, flags);
 349 -       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 350 -       data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 351 -       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 352 +       spin_lock_irqsave(&rpc->lock, flags);
 353 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 354 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 355 +       spin_unlock_irqrestore(&rpc->lock, flags);
 356
 357         switch (size) {
 358         case 1:
 359 @@ -232,16 +289,22 @@ static int rt3883_pci_config_read(struct
 360  static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 361                                    int where, int size, u32 val)
 362  {
 363 +       struct rt3883_pci_controller *rpc;
 364         unsigned long flags;
 365         u32 address;
 366         u32 data;
 367
 368 +       rpc = pci_bus_to_rt3883_controller(bus);
 369 +
 370 +       if (!rpc->pcie_ready && bus->number == 1)
 371 +               return PCIBIOS_DEVICE_NOT_FOUND;
 372 +
 373         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 374                                          PCI_FUNC(devfn), where);
 375
 376 -       spin_lock_irqsave(&rt3883_pci_lock, flags);
 377 -       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 378 -       data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 379 +       spin_lock_irqsave(&rpc->lock, flags);
 380 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 381 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 382
 383         switch (size) {
 384         case 1:
 385 @@ -257,8 +320,8 @@ static int rt3883_pci_config_write(struc
 386                 break;
 387         }
 388
 389 -       rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
 390 -       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 391 +       rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
 392 +       spin_unlock_irqrestore(&rpc->lock, flags);
 393
 394         return PCIBIOS_SUCCESSFUL;
 395  }
 396 @@ -268,220 +331,310 @@ static struct pci_ops rt3883_pci_ops = {
 397         .write  = rt3883_pci_config_write,
 398  };
 399
 400 -static struct resource rt3883_pci_mem_resource = {
 401 -       .name   = "PCI MEM space",
 402 -       .start  = RT3883_PCI_MEM_BASE,
 403 -       .end    = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
 404 -       .flags  = IORESOURCE_MEM,
 405 -};
 406 -
 407 -static struct resource rt3883_pci_io_resource = {
 408 -       .name   = "PCI IO space",
 409 -       .start  = RT3883_PCI_IO_BASE,
 410 -       .end    = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
 411 -       .flags  = IORESOURCE_IO,
 412 -};
 413 -
 414 -static struct pci_controller rt3883_pci_controller = {
 415 -       .pci_ops        = &rt3883_pci_ops,
 416 -       .mem_resource   = &rt3883_pci_mem_resource,
 417 -       .io_resource    = &rt3883_pci_io_resource,
 418 -};
 419 -
 420 -static void rt3883_pci_preinit(unsigned mode)
 421 +static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
 422  {
 423         u32 syscfg1;
 424         u32 rstctrl;
 425         u32 clkcfg1;
 426 +       u32 t;
 427 +
 428 +       rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 429 +       syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 430 +       clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 431
 432         if (mode & RT3883_PCI_MODE_PCIE) {
 433 -               u32 val;
 434 +               rstctrl |= RT3883_RSTCTRL_PCIE;
 435 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 436
 437 -               val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
 438 -               val &= ~(0x30);
 439 -               val |= (2 << 4);
 440 -               rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
 441 -
 442 -               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 443 -               val &= ~BIT(31);
 444 -               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 445 -
 446 -               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 447 -               val &= 0x80ffffff;
 448 -               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 449 -
 450 -               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 451 -               val |= 0xa << 24;
 452 -               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 453 -
 454 -               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 455 -               val |= BIT(31);
 456 -               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 457 +               /* setup PCI PAD drive mode */
 458 +               syscfg1 &= ~(0x30);
 459 +               syscfg1 |= (2 << 4);
 460 +               rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 461 +
 462 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 463 +               t &= ~BIT(31);
 464 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 465 +
 466 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 467 +               t &= 0x80ffffff;
 468 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 469 +
 470 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 471 +               t |= 0xa << 24;
 472 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 473 +
 474 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 475 +               t |= BIT(31);
 476 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 477
 478                 msleep(50);
 479 +
 480 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 481 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 482         }
 483
 484 -       syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
 485 -       syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
 486 -                    RT3883_SYSCFG1_PCI_HOST_MODE);
 487 -
 488 -       rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
 489 -       rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
 490 -
 491 -       clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
 492 -       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
 493 -                    RT3883_CLKCFG1_PCIE_CLK_EN);
 494 +       syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
 495 +
 496 +       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
 497
 498         if (mode & RT3883_PCI_MODE_PCI) {
 499 -               syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
 500                 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 501                 rstctrl &= ~RT3883_RSTCTRL_PCI;
 502         }
 503 +
 504         if (mode & RT3883_PCI_MODE_PCIE) {
 505 -               syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
 506 -                          RT3883_SYSCFG1_PCIE_RC_MODE;
 507                 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 508                 rstctrl &= ~RT3883_RSTCTRL_PCIE;
 509         }
 510
 511 -       rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 512 -       rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 513 -       rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 514 +       rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 515 +       rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 516 +       rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 517
 518         msleep(500);
 519 -}
 520
 521 -static int rt3883_pcie_ready(void)
 522 -{
 523 -       u32 status;
 524 +       /*
 525 +        * setup the device number of the P2P bridge
 526 +        * and de-assert the reset line
 527 +        */
 528 +       t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
 529 +       rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
 530
 531 +       /* flush write */
 532 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
 533         msleep(500);
 534
 535 -       status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
 536 -       if (status & BIT(0))
 537 -               return 0;
 538 +       if (mode & RT3883_PCI_MODE_PCIE) {
 539 +               msleep(500);
 540 +
 541 +               t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
 542 +
 543 +               rpc->pcie_ready = t & BIT(0);
 544 +
 545 +               if (!rpc->pcie_ready) {
 546 +                       /* reset the PCIe block */
 547 +                       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 548 +                       t |= RT3883_RSTCTRL_PCIE;
 549 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 550 +                       t &= ~RT3883_RSTCTRL_PCIE;
 551 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 552 +
 553 +                       /* turn off PCIe clock */
 554 +                       t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 555 +                       t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
 556 +                       rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 557 +
 558 +                       t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 559 +                       t &= ~0xf000c080;
 560 +                       rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 561 +               }
 562 +       }
 563 +
 564 +       /* enable PCI arbiter */
 565 +       rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 566 +}
 567
 568 -       /* TODO: reset PCIe and turn off PCIe clock */
 569 +static inline void
 570 +rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
 571 +                      int bus, int slot)
 572 +{
 573 +       int i;
 574 +
 575 +       for (i = 0; i < 16; i++) {
 576 +               u32 val;
 577
 578 -       return -ENODEV;
 579 +               val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
 580 +               pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
 581 +                       bus, slot, i << 2, val);
 582 +       }
 583  }
 584
 585 -void __init rt3883_pci_init(unsigned mode)
 586 +static int rt3883_pci_probe(struct platform_device *pdev)
 587  {
 588 +       struct rt3883_pci_controller *rpc;
 589 +       struct device *dev = &pdev->dev;
 590 +       struct device_node *np = dev->of_node;
 591 +       struct resource *res;
 592 +       struct device_node *child;
 593         u32 val;
 594         int err;
 595 +       int mode;
 596
 597 -       rt3883_pci_preinit(mode);
 598 +       rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 599 +       if (!rpc)
 600 +               return -ENOMEM;
 601 +
 602 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 603 +       if (!res)
 604 +               return -EINVAL;
 605 +
 606 +       rpc->base = devm_ioremap_resource(dev, res);
 607 +       if (IS_ERR(rpc->base))
 608 +               return PTR_ERR(rpc->base);
 609 +
 610 +       rpc->pci_controller.of_node = of_get_child_by_name(np, "host-bridge");
 611 +       if (!rpc->pci_controller.of_node) {
 612 +               dev_err(dev, "no %s child node found", "host-bridge");
 613 +               return -ENODEV;
 614 +       }
 615 +
 616 +       mode = RT3883_PCI_MODE_NONE;
 617 +       for_each_child_of_node(rpc->pci_controller.of_node, child) {
 618 +               u32 slot;
 619 +
 620 +               if (!of_device_is_available(child))
 621 +                       continue;
 622 +
 623 +               if (of_property_read_u32(child, "ralink,pci-slot",
 624 +                                        &slot)) {
 625 +                       dev_err(dev, "no '%s' property found for %s\n",
 626 +                               "ralink,pci-slot",
 627 +                               of_node_full_name(child));
 628 +                       continue;
 629 +               }
 630
 631 -       rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
 632 -       if (rt3883_pci_base == NULL) {
 633 -               pr_err("failed to ioremap PCI registers\n");
 634 -               return;
 635 +               switch (slot) {
 636 +               case 1:
 637 +                       mode |= RT3883_PCI_MODE_PCIE;
 638 +                       break;
 639 +
 640 +               case 17:
 641 +               case 18:
 642 +                       mode |= RT3883_PCI_MODE_PCI;
 643 +                       break;
 644 +               }
 645         }
 646
 647 -       rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
 648 -       if (mode & RT3883_PCI_MODE_PCI)
 649 -               rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
 650 +       if (mode == RT3883_PCI_MODE_NONE) {
 651 +               dev_err(dev, "unable to determine PCI mode\n");
 652 +               err = -EINVAL;
 653 +               goto err_put_hb_node;
 654 +       }
 655
 656 -       msleep(500);
 657 +       dev_info(dev, "mode:%s%s\n",
 658 +                (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
 659 +                (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
 660
 661 -       if (mode & RT3883_PCI_MODE_PCIE) {
 662 -               err = rt3883_pcie_ready();
 663 -               if (err)
 664 -                       return;
 665 -       }
 666 +       rt3883_pci_preinit(rpc, mode);
 667
 668 -       if (mode & RT3883_PCI_MODE_PCI)
 669 -               rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
 670 +       rpc->pci_controller.pci_ops = &rt3883_pci_ops;
 671 +       rpc->pci_controller.io_resource = &rpc->io_res;
 672 +       rpc->pci_controller.mem_resource = &rpc->mem_res;
 673
 674 -       rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
 675 -       rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
 676 +       /* Load PCI I/O and memory resources from DT */
 677 +       pci_load_of_ranges(&rpc->pci_controller,
 678 +                          rpc->pci_controller.of_node);
 679 +
 680 +       rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
 681 +       rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
 682 +
 683 +       ioport_resource.start = rpc->io_res.start;
 684 +       ioport_resource.end = rpc->io_res.end;
 685
 686         /* PCI */
 687 -       rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
 688 -       rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
 689 -       rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
 690 -       rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
 691 -       rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
 692 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
 693 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
 694 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
 695 +       rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
 696 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
 697
 698         /* PCIe */
 699 -       rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
 700 -       rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
 701 -       rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
 702 -       rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
 703 -       rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
 704 -
 705 -       rt3883_pci_irq_init();
 706 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
 707 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
 708 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
 709 +       rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
 710 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
 711 +
 712 +       err = rt3883_pci_irq_init(dev, rpc);
 713 +       if (err)
 714 +               goto err_put_hb_node;
 715
 716         /* PCIe */
 717 -       val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
 718 -       val |= 0x7;
 719 -       rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
 720 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
 721 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 722 +       rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
 723
 724         /* PCI */
 725 -       val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
 726 -       val |= 0x7;
 727 -       rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
 728 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
 729 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 730 +       rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
 731 +
 732 +       if (mode == RT3883_PCI_MODE_PCIE) {
 733 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
 734 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
 735 +
 736 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 737 +                                      PCI_BASE_ADDRESS_0,
 738 +                                      RT3883_MEMORY_BASE);
 739 +               /* flush write */
 740 +               rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 741 +                                     PCI_BASE_ADDRESS_0);
 742 +       } else {
 743 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 744 +                                      PCI_IO_BASE, 0x00000101);
 745 +       }
 746 +
 747 +       register_pci_controller(&rpc->pci_controller);
 748
 749 -       ioport_resource.start = rt3883_pci_io_resource.start;
 750 -       ioport_resource.end = rt3883_pci_io_resource.end;
 751 +       return 0;
 752
 753 -       register_pci_controller(&rt3883_pci_controller);
 754 +err_put_hb_node:
 755 +       of_node_put(rpc->pci_controller.of_node);
 756 +       return err;
 757  }
 758
 759  int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 760  {
 761 -       int irq = -1;
 762 -
 763 -       switch (dev->bus->number) {
 764 -       case 0:
 765 -               switch (PCI_SLOT(dev->devfn)) {
 766 -               case 0x00:
 767 -                       rt3883_pci_wr(0x03ff0001,
 768 -                                            RT3883_PCI_REG_BAR0SETUP_ADDR(0));
 769 -                       rt3883_pci_wr(0x03ff0001,
 770 -                                            RT3883_PCI_REG_BAR0SETUP_ADDR(1));
 771 -
 772 -                       rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
 773 -                                            RT3883_MEMORY_BASE);
 774 -                       rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
 775 -
 776 -                       irq = RT3883_CPU_IRQ_PCI;
 777 -                       break;
 778 -               case 0x01:
 779 -                       rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
 780 -                                            0x00000101);
 781 -                       break;
 782 -               case 0x11:
 783 -                       irq = RT3883_PCI_IRQ_PCI0;
 784 -                       break;
 785 -               case 0x12:
 786 -                       irq = RT3883_PCI_IRQ_PCI1;
 787 -                       break;
 788 -               }
 789 -               break;
 790 -
 791 -       case 1:
 792 -               irq = RT3883_PCI_IRQ_PCIE;
 793 -               break;
 794 +       struct rt3883_pci_controller *rpc;
 795 +       struct of_irq dev_irq;
 796 +       int err;
 797 +       int irq;
 798
 799 -       default:
 800 -               dev_err(&dev->dev, "no IRQ specified\n");
 801 -               return irq;
 802 +       rpc = pci_bus_to_rt3883_controller(dev->bus);
 803 +       err = of_irq_map_pci(dev, &dev_irq);
 804 +       if (err) {
 805 +               pr_err("pci %s: unable to get irq map, err=%d\n",
 806 +                      pci_name((struct pci_dev *) dev), err);
 807 +               return 0;
 808         }
 809
 810 +       irq = irq_create_of_mapping(dev_irq.controller,
 811 +                                   dev_irq.specifier,
 812 +                                   dev_irq.size);
 813 +
 814 +       if (irq == 0)
 815 +               pr_crit("pci %s: no irq found for pin %u\n",
 816 +                       pci_name((struct pci_dev *) dev), pin);
 817 +       else
 818 +               pr_info("pci %s: using irq %d for pin %u\n",
 819 +                       pci_name((struct pci_dev *) dev), irq, pin);
 820 +
 821         return irq;
 822  }
 823
 824 -void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
 825 +int pcibios_plat_dev_init(struct pci_dev *dev)
 826  {
 827 -       rt3883_pci_plat_dev_init = f;
 828 +       return 0;
 829  }
 830
 831 -int pcibios_plat_dev_init(struct pci_dev *dev)
 832 -{
 833 -       if (rt3883_pci_plat_dev_init)
 834 -               return rt3883_pci_plat_dev_init(dev);
 835 +static const struct of_device_id rt3883_pci_ids[] = {
 836 +       { .compatible = "ralink,rt3883-pci" },
 837 +       {},
 838 +};
 839 +MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
 840
 841 -       return 0;
 842 +static struct platform_driver rt3883_pci_driver = {
 843 +       .probe = rt3883_pci_probe,
 844 +       .driver = {
 845 +               .name = "rt3883-pci",
 846 +               .owner = THIS_MODULE,
 847 +               .of_match_table = of_match_ptr(rt3883_pci_ids),
 848 +       },
 849 +};
 850 +
 851 +static int __init rt3883_pci_init(void)
 852 +{
 853 +       return platform_driver_register(&rt3883_pci_driver);
 854  }
 855 +
 856 +postcore_initcall(rt3883_pci_init);