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[ramips] add patches for v3.8
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.8 / 0202-owrt-USB-adds-dwc_otg.patch
1 From 1a44a003bdaf917193114d0d40534496c39644ba Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 15 Mar 2013 20:58:18 +0100
4 Subject: [PATCH 202/208] owrt: USB: adds dwc_otg
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/usb/Kconfig | 2 +
9 drivers/usb/Makefile | 1 +
10 drivers/usb/dwc_otg/Kconfig | 24 +
11 drivers/usb/dwc_otg/Makefile | 25 +
12 drivers/usb/dwc_otg/dummy_audio.c | 1575 +++++++++++++
13 drivers/usb/dwc_otg/dwc_otg_attr.c | 966 ++++++++
14 drivers/usb/dwc_otg/dwc_otg_attr.h | 67 +
15 drivers/usb/dwc_otg/dwc_otg_cil.c | 3692 ++++++++++++++++++++++++++++++
16 drivers/usb/dwc_otg/dwc_otg_cil.h | 1098 +++++++++
17 drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 750 ++++++
18 drivers/usb/dwc_otg/dwc_otg_driver.c | 1273 ++++++++++
19 drivers/usb/dwc_otg/dwc_otg_driver.h | 83 +
20 drivers/usb/dwc_otg/dwc_otg_hcd.c | 2852 +++++++++++++++++++++++
21 drivers/usb/dwc_otg/dwc_otg_hcd.h | 668 ++++++
22 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1873 +++++++++++++++
23 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 684 ++++++
24 drivers/usb/dwc_otg/dwc_otg_pcd.c | 2523 ++++++++++++++++++++
25 drivers/usb/dwc_otg/dwc_otg_pcd.h | 248 ++
26 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 3654 +++++++++++++++++++++++++++++
27 drivers/usb/dwc_otg/dwc_otg_regs.h | 2075 +++++++++++++++++
28 drivers/usb/dwc_otg/linux/dwc_otg_plat.h | 260 +++
29 21 files changed, 24393 insertions(+)
30 create mode 100644 drivers/usb/dwc_otg/Kconfig
31 create mode 100644 drivers/usb/dwc_otg/Makefile
32 create mode 100644 drivers/usb/dwc_otg/dummy_audio.c
33 create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c
34 create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h
35 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c
36 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h
37 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c
38 create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c
39 create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
40 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c
41 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h
42 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
43 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
44 create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c
45 create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h
46 create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
47 create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
48 create mode 100644 drivers/usb/dwc_otg/linux/dwc_otg_plat.h
49
50 diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
51 index 640ae6c..20a629a 100644
52 --- a/drivers/usb/Kconfig
53 +++ b/drivers/usb/Kconfig
54 @@ -126,6 +126,8 @@ source "drivers/usb/core/Kconfig"
55
56 source "drivers/usb/dwc3/Kconfig"
57
58 +source "drivers/usb/dwc_otg/Kconfig"
59 +
60 source "drivers/usb/mon/Kconfig"
61
62 source "drivers/usb/wusbcore/Kconfig"
63 diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
64 index 8f5ebce..4bcfe6d 100644
65 --- a/drivers/usb/Makefile
66 +++ b/drivers/usb/Makefile
67 @@ -9,6 +9,7 @@ obj-$(CONFIG_USB) += core/
68 obj-$(CONFIG_USB_OTG_UTILS) += otg/
69
70 obj-$(CONFIG_USB_DWC3) += dwc3/
71 +obj-$(CONFIG_DWC_OTG) += dwc_otg/
72
73 obj-$(CONFIG_USB_MON) += mon/
74
75 diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig
76 new file mode 100644
77 index 0000000..6dd75f1
78 --- /dev/null
79 +++ b/drivers/usb/dwc_otg/Kconfig
80 @@ -0,0 +1,24 @@
81 +config DWC_OTG
82 + tristate "Ralink RT305X DWC_OTG support"
83 + depends on SOC_RT305X
84 + ---help---
85 + This driver supports Ralink DWC_OTG
86 +
87 +choice
88 + prompt "USB Operation Mode"
89 + depends on DWC_OTG
90 + default DWC_OTG_HOST_ONLY
91 +
92 +config DWC_OTG_HOST_ONLY
93 + bool "HOST ONLY MODE"
94 + depends on DWC_OTG
95 +
96 +config DWC_OTG_DEVICE_ONLY
97 + bool "DEVICE ONLY MODE"
98 + depends on DWC_OTG
99 +
100 +endchoice
101 +
102 +config DWC_OTG_DEBUG
103 + bool "Enable debug mode"
104 + depends on DWC_OTG
105 diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile
106 new file mode 100644
107 index 0000000..95c5b66
108 --- /dev/null
109 +++ b/drivers/usb/dwc_otg/Makefile
110 @@ -0,0 +1,25 @@
111 +#
112 +# Makefile for DWC_otg Highspeed USB controller driver
113 +#
114 +
115 +ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
116 +EXTRA_CFLAGS += -DDEBUG
117 +endif
118 +
119 +# Use one of the following flags to compile the software in host-only or
120 +# device-only mode.
121 +ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
122 +EXTRA_CFLAGS += -DDWC_HOST_ONLY
123 +EXTRA_CFLAGS += -DDWC_EN_ISOC
124 +endif
125 +
126 +ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
127 +EXTRA_CFLAGS += -DDWC_DEVICE_ONLY
128 +endif
129 +
130 +obj-$(CONFIG_DWC_OTG) := dwc_otg.o
131 +
132 +dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
133 +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
134 +dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
135 +dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
136 diff --git a/drivers/usb/dwc_otg/dummy_audio.c b/drivers/usb/dwc_otg/dummy_audio.c
137 new file mode 100644
138 index 0000000..225decf
139 --- /dev/null
140 +++ b/drivers/usb/dwc_otg/dummy_audio.c
141 @@ -0,0 +1,1575 @@
142 +/*
143 + * zero.c -- Gadget Zero, for USB development
144 + *
145 + * Copyright (C) 2003-2004 David Brownell
146 + * All rights reserved.
147 + *
148 + * Redistribution and use in source and binary forms, with or without
149 + * modification, are permitted provided that the following conditions
150 + * are met:
151 + * 1. Redistributions of source code must retain the above copyright
152 + * notice, this list of conditions, and the following disclaimer,
153 + * without modification.
154 + * 2. Redistributions in binary form must reproduce the above copyright
155 + * notice, this list of conditions and the following disclaimer in the
156 + * documentation and/or other materials provided with the distribution.
157 + * 3. The names of the above-listed copyright holders may not be used
158 + * to endorse or promote products derived from this software without
159 + * specific prior written permission.
160 + *
161 + * ALTERNATIVELY, this software may be distributed under the terms of the
162 + * GNU General Public License ("GPL") as published by the Free Software
163 + * Foundation, either version 2 of that License or (at your option) any
164 + * later version.
165 + *
166 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
167 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
168 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
169 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
170 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
171 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
172 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
173 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
174 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
175 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
176 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
177 + */
178 +
179 +
180 +/*
181 + * Gadget Zero only needs two bulk endpoints, and is an example of how you
182 + * can write a hardware-agnostic gadget driver running inside a USB device.
183 + *
184 + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
185 + * affect most of the driver.
186 + *
187 + * Use it with the Linux host/master side "usbtest" driver to get a basic
188 + * functional test of your device-side usb stack, or with "usb-skeleton".
189 + *
190 + * It supports two similar configurations. One sinks whatever the usb host
191 + * writes, and in return sources zeroes. The other loops whatever the host
192 + * writes back, so the host can read it. Module options include:
193 + *
194 + * buflen=N default N=4096, buffer size used
195 + * qlen=N default N=32, how many buffers in the loopback queue
196 + * loopdefault default false, list loopback config first
197 + *
198 + * Many drivers will only have one configuration, letting them be much
199 + * simpler if they also don't support high speed operation (like this
200 + * driver does).
201 + */
202 +
203 +#include <linux/config.h>
204 +#include <linux/module.h>
205 +#include <linux/kernel.h>
206 +#include <linux/delay.h>
207 +#include <linux/ioport.h>
208 +#include <linux/sched.h>
209 +#include <linux/slab.h>
210 +#include <linux/smp_lock.h>
211 +#include <linux/errno.h>
212 +#include <linux/init.h>
213 +#include <linux/timer.h>
214 +#include <linux/list.h>
215 +#include <linux/interrupt.h>
216 +#include <linux/uts.h>
217 +#include <linux/version.h>
218 +#include <linux/device.h>
219 +#include <linux/moduleparam.h>
220 +#include <linux/proc_fs.h>
221 +
222 +#include <asm/byteorder.h>
223 +#include <asm/io.h>
224 +#include <asm/irq.h>
225 +#include <asm/system.h>
226 +#include <asm/unaligned.h>
227 +
228 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
229 +# include <linux/usb/ch9.h>
230 +#else
231 +# include <linux/usb_ch9.h>
232 +#endif
233 +
234 +#include <linux/usb_gadget.h>
235 +
236 +
237 +/*-------------------------------------------------------------------------*/
238 +/*-------------------------------------------------------------------------*/
239 +
240 +
241 +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
242 +{
243 + int count = 0;
244 + u8 c;
245 + u16 uchar;
246 +
247 + /* this insists on correct encodings, though not minimal ones.
248 + * BUT it currently rejects legit 4-byte UTF-8 code points,
249 + * which need surrogate pairs. (Unicode 3.1 can use them.)
250 + */
251 + while (len != 0 && (c = (u8) *s++) != 0) {
252 + if (unlikely(c & 0x80)) {
253 + // 2-byte sequence:
254 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
255 + if ((c & 0xe0) == 0xc0) {
256 + uchar = (c & 0x1f) << 6;
257 +
258 + c = (u8) *s++;
259 + if ((c & 0xc0) != 0xc0)
260 + goto fail;
261 + c &= 0x3f;
262 + uchar |= c;
263 +
264 + // 3-byte sequence (most CJKV characters):
265 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
266 + } else if ((c & 0xf0) == 0xe0) {
267 + uchar = (c & 0x0f) << 12;
268 +
269 + c = (u8) *s++;
270 + if ((c & 0xc0) != 0xc0)
271 + goto fail;
272 + c &= 0x3f;
273 + uchar |= c << 6;
274 +
275 + c = (u8) *s++;
276 + if ((c & 0xc0) != 0xc0)
277 + goto fail;
278 + c &= 0x3f;
279 + uchar |= c;
280 +
281 + /* no bogus surrogates */
282 + if (0xd800 <= uchar && uchar <= 0xdfff)
283 + goto fail;
284 +
285 + // 4-byte sequence (surrogate pairs, currently rare):
286 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
287 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
288 + // (uuuuu = wwww + 1)
289 + // FIXME accept the surrogate code points (only)
290 +
291 + } else
292 + goto fail;
293 + } else
294 + uchar = c;
295 + put_unaligned (cpu_to_le16 (uchar), cp++);
296 + count++;
297 + len--;
298 + }
299 + return count;
300 +fail:
301 + return -1;
302 +}
303 +
304 +
305 +/**
306 + * usb_gadget_get_string - fill out a string descriptor
307 + * @table: of c strings encoded using UTF-8
308 + * @id: string id, from low byte of wValue in get string descriptor
309 + * @buf: at least 256 bytes
310 + *
311 + * Finds the UTF-8 string matching the ID, and converts it into a
312 + * string descriptor in utf16-le.
313 + * Returns length of descriptor (always even) or negative errno
314 + *
315 + * If your driver needs stings in multiple languages, you'll probably
316 + * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
317 + * using this routine after choosing which set of UTF-8 strings to use.
318 + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
319 + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
320 + * characters (which are also widely used in C strings).
321 + */
322 +int
323 +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
324 +{
325 + struct usb_string *s;
326 + int len;
327 +
328 + /* descriptor 0 has the language id */
329 + if (id == 0) {
330 + buf [0] = 4;
331 + buf [1] = USB_DT_STRING;
332 + buf [2] = (u8) table->language;
333 + buf [3] = (u8) (table->language >> 8);
334 + return 4;
335 + }
336 + for (s = table->strings; s && s->s; s++)
337 + if (s->id == id)
338 + break;
339 +
340 + /* unrecognized: stall. */
341 + if (!s || !s->s)
342 + return -EINVAL;
343 +
344 + /* string descriptors have length, tag, then UTF16-LE text */
345 + len = min ((size_t) 126, strlen (s->s));
346 + memset (buf + 2, 0, 2 * len); /* zero all the bytes */
347 + len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
348 + if (len < 0)
349 + return -EINVAL;
350 + buf [0] = (len + 1) * 2;
351 + buf [1] = USB_DT_STRING;
352 + return buf [0];
353 +}
354 +
355 +
356 +/*-------------------------------------------------------------------------*/
357 +/*-------------------------------------------------------------------------*/
358 +
359 +
360 +/**
361 + * usb_descriptor_fillbuf - fill buffer with descriptors
362 + * @buf: Buffer to be filled
363 + * @buflen: Size of buf
364 + * @src: Array of descriptor pointers, terminated by null pointer.
365 + *
366 + * Copies descriptors into the buffer, returning the length or a
367 + * negative error code if they can't all be copied. Useful when
368 + * assembling descriptors for an associated set of interfaces used
369 + * as part of configuring a composite device; or in other cases where
370 + * sets of descriptors need to be marshaled.
371 + */
372 +int
373 +usb_descriptor_fillbuf(void *buf, unsigned buflen,
374 + const struct usb_descriptor_header **src)
375 +{
376 + u8 *dest = buf;
377 +
378 + if (!src)
379 + return -EINVAL;
380 +
381 + /* fill buffer from src[] until null descriptor ptr */
382 + for (; 0 != *src; src++) {
383 + unsigned len = (*src)->bLength;
384 +
385 + if (len > buflen)
386 + return -EINVAL;
387 + memcpy(dest, *src, len);
388 + buflen -= len;
389 + dest += len;
390 + }
391 + return dest - (u8 *)buf;
392 +}
393 +
394 +
395 +/**
396 + * usb_gadget_config_buf - builts a complete configuration descriptor
397 + * @config: Header for the descriptor, including characteristics such
398 + * as power requirements and number of interfaces.
399 + * @desc: Null-terminated vector of pointers to the descriptors (interface,
400 + * endpoint, etc) defining all functions in this device configuration.
401 + * @buf: Buffer for the resulting configuration descriptor.
402 + * @length: Length of buffer. If this is not big enough to hold the
403 + * entire configuration descriptor, an error code will be returned.
404 + *
405 + * This copies descriptors into the response buffer, building a descriptor
406 + * for that configuration. It returns the buffer length or a negative
407 + * status code. The config.wTotalLength field is set to match the length
408 + * of the result, but other descriptor fields (including power usage and
409 + * interface count) must be set by the caller.
410 + *
411 + * Gadget drivers could use this when constructing a config descriptor
412 + * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
413 + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
414 + */
415 +int usb_gadget_config_buf(
416 + const struct usb_config_descriptor *config,
417 + void *buf,
418 + unsigned length,
419 + const struct usb_descriptor_header **desc
420 +)
421 +{
422 + struct usb_config_descriptor *cp = buf;
423 + int len;
424 +
425 + /* config descriptor first */
426 + if (length < USB_DT_CONFIG_SIZE || !desc)
427 + return -EINVAL;
428 + *cp = *config;
429 +
430 + /* then interface/endpoint/class/vendor/... */
431 + len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
432 + length - USB_DT_CONFIG_SIZE, desc);
433 + if (len < 0)
434 + return len;
435 + len += USB_DT_CONFIG_SIZE;
436 + if (len > 0xffff)
437 + return -EINVAL;
438 +
439 + /* patch up the config descriptor */
440 + cp->bLength = USB_DT_CONFIG_SIZE;
441 + cp->bDescriptorType = USB_DT_CONFIG;
442 + cp->wTotalLength = cpu_to_le16(len);
443 + cp->bmAttributes |= USB_CONFIG_ATT_ONE;
444 + return len;
445 +}
446 +
447 +/*-------------------------------------------------------------------------*/
448 +/*-------------------------------------------------------------------------*/
449 +
450 +
451 +#define RBUF_LEN (1024*1024)
452 +static int rbuf_start;
453 +static int rbuf_len;
454 +static __u8 rbuf[RBUF_LEN];
455 +
456 +/*-------------------------------------------------------------------------*/
457 +
458 +#define DRIVER_VERSION "St Patrick's Day 2004"
459 +
460 +static const char shortname [] = "zero";
461 +static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
462 +
463 +static const char source_sink [] = "source and sink data";
464 +static const char loopback [] = "loop input to output";
465 +
466 +/*-------------------------------------------------------------------------*/
467 +
468 +/*
469 + * driver assumes self-powered hardware, and
470 + * has no way for users to trigger remote wakeup.
471 + *
472 + * this version autoconfigures as much as possible,
473 + * which is reasonable for most "bulk-only" drivers.
474 + */
475 +static const char *EP_IN_NAME; /* source */
476 +static const char *EP_OUT_NAME; /* sink */
477 +
478 +/*-------------------------------------------------------------------------*/
479 +
480 +/* big enough to hold our biggest descriptor */
481 +#define USB_BUFSIZ 512
482 +
483 +struct zero_dev {
484 + spinlock_t lock;
485 + struct usb_gadget *gadget;
486 + struct usb_request *req; /* for control responses */
487 +
488 + /* when configured, we have one of two configs:
489 + * - source data (in to host) and sink it (out from host)
490 + * - or loop it back (out from host back in to host)
491 + */
492 + u8 config;
493 + struct usb_ep *in_ep, *out_ep;
494 +
495 + /* autoresume timer */
496 + struct timer_list resume;
497 +};
498 +
499 +#define xprintk(d,level,fmt,args...) \
500 + dev_printk(level , &(d)->gadget->dev , fmt , ## args)
501 +
502 +#ifdef DEBUG
503 +#define DBG(dev,fmt,args...) \
504 + xprintk(dev , KERN_DEBUG , fmt , ## args)
505 +#else
506 +#define DBG(dev,fmt,args...) \
507 + do { } while (0)
508 +#endif /* DEBUG */
509 +
510 +#ifdef VERBOSE
511 +#define VDBG DBG
512 +#else
513 +#define VDBG(dev,fmt,args...) \
514 + do { } while (0)
515 +#endif /* VERBOSE */
516 +
517 +#define ERROR(dev,fmt,args...) \
518 + xprintk(dev , KERN_ERR , fmt , ## args)
519 +#define WARN(dev,fmt,args...) \
520 + xprintk(dev , KERN_WARNING , fmt , ## args)
521 +#define INFO(dev,fmt,args...) \
522 + xprintk(dev , KERN_INFO , fmt , ## args)
523 +
524 +/*-------------------------------------------------------------------------*/
525 +
526 +static unsigned buflen = 4096;
527 +static unsigned qlen = 32;
528 +static unsigned pattern = 0;
529 +
530 +module_param (buflen, uint, S_IRUGO|S_IWUSR);
531 +module_param (qlen, uint, S_IRUGO|S_IWUSR);
532 +module_param (pattern, uint, S_IRUGO|S_IWUSR);
533 +
534 +/*
535 + * if it's nonzero, autoresume says how many seconds to wait
536 + * before trying to wake up the host after suspend.
537 + */
538 +static unsigned autoresume = 0;
539 +module_param (autoresume, uint, 0);
540 +
541 +/*
542 + * Normally the "loopback" configuration is second (index 1) so
543 + * it's not the default. Here's where to change that order, to
544 + * work better with hosts where config changes are problematic.
545 + * Or controllers (like superh) that only support one config.
546 + */
547 +static int loopdefault = 0;
548 +
549 +module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
550 +
551 +/*-------------------------------------------------------------------------*/
552 +
553 +/* Thanks to NetChip Technologies for donating this product ID.
554 + *
555 + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
556 + * Instead: allocate your own, using normal USB-IF procedures.
557 + */
558 +#ifndef CONFIG_USB_ZERO_HNPTEST
559 +#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
560 +#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
561 +#else
562 +#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
563 +#define DRIVER_PRODUCT_NUM 0xbadd
564 +#endif
565 +
566 +/*-------------------------------------------------------------------------*/
567 +
568 +/*
569 + * DESCRIPTORS ... most are static, but strings and (full)
570 + * configuration descriptors are built on demand.
571 + */
572 +
573 +/*
574 +#define STRING_MANUFACTURER 25
575 +#define STRING_PRODUCT 42
576 +#define STRING_SERIAL 101
577 +*/
578 +#define STRING_MANUFACTURER 1
579 +#define STRING_PRODUCT 2
580 +#define STRING_SERIAL 3
581 +
582 +#define STRING_SOURCE_SINK 250
583 +#define STRING_LOOPBACK 251
584 +
585 +/*
586 + * This device advertises two configurations; these numbers work
587 + * on a pxa250 as well as more flexible hardware.
588 + */
589 +#define CONFIG_SOURCE_SINK 3
590 +#define CONFIG_LOOPBACK 2
591 +
592 +/*
593 +static struct usb_device_descriptor
594 +device_desc = {
595 + .bLength = sizeof device_desc,
596 + .bDescriptorType = USB_DT_DEVICE,
597 +
598 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
599 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
600 +
601 + .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
602 + .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
603 + .iManufacturer = STRING_MANUFACTURER,
604 + .iProduct = STRING_PRODUCT,
605 + .iSerialNumber = STRING_SERIAL,
606 + .bNumConfigurations = 2,
607 +};
608 +*/
609 +static struct usb_device_descriptor
610 +device_desc = {
611 + .bLength = sizeof device_desc,
612 + .bDescriptorType = USB_DT_DEVICE,
613 + .bcdUSB = __constant_cpu_to_le16 (0x0100),
614 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
615 + .bDeviceSubClass = 0,
616 + .bDeviceProtocol = 0,
617 + .bMaxPacketSize0 = 64,
618 + .bcdDevice = __constant_cpu_to_le16 (0x0100),
619 + .idVendor = __constant_cpu_to_le16 (0x0499),
620 + .idProduct = __constant_cpu_to_le16 (0x3002),
621 + .iManufacturer = STRING_MANUFACTURER,
622 + .iProduct = STRING_PRODUCT,
623 + .iSerialNumber = STRING_SERIAL,
624 + .bNumConfigurations = 1,
625 +};
626 +
627 +static struct usb_config_descriptor
628 +z_config = {
629 + .bLength = sizeof z_config,
630 + .bDescriptorType = USB_DT_CONFIG,
631 +
632 + /* compute wTotalLength on the fly */
633 + .bNumInterfaces = 2,
634 + .bConfigurationValue = 1,
635 + .iConfiguration = 0,
636 + .bmAttributes = 0x40,
637 + .bMaxPower = 0, /* self-powered */
638 +};
639 +
640 +
641 +static struct usb_otg_descriptor
642 +otg_descriptor = {
643 + .bLength = sizeof otg_descriptor,
644 + .bDescriptorType = USB_DT_OTG,
645 +
646 + .bmAttributes = USB_OTG_SRP,
647 +};
648 +
649 +/* one interface in each configuration */
650 +#ifdef CONFIG_USB_GADGET_DUALSPEED
651 +
652 +/*
653 + * usb 2.0 devices need to expose both high speed and full speed
654 + * descriptors, unless they only run at full speed.
655 + *
656 + * that means alternate endpoint descriptors (bigger packets)
657 + * and a "device qualifier" ... plus more construction options
658 + * for the config descriptor.
659 + */
660 +
661 +static struct usb_qualifier_descriptor
662 +dev_qualifier = {
663 + .bLength = sizeof dev_qualifier,
664 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
665 +
666 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
667 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
668 +
669 + .bNumConfigurations = 2,
670 +};
671 +
672 +
673 +struct usb_cs_as_general_descriptor {
674 + __u8 bLength;
675 + __u8 bDescriptorType;
676 +
677 + __u8 bDescriptorSubType;
678 + __u8 bTerminalLink;
679 + __u8 bDelay;
680 + __u16 wFormatTag;
681 +} __attribute__ ((packed));
682 +
683 +struct usb_cs_as_format_descriptor {
684 + __u8 bLength;
685 + __u8 bDescriptorType;
686 +
687 + __u8 bDescriptorSubType;
688 + __u8 bFormatType;
689 + __u8 bNrChannels;
690 + __u8 bSubframeSize;
691 + __u8 bBitResolution;
692 + __u8 bSamfreqType;
693 + __u8 tLowerSamFreq[3];
694 + __u8 tUpperSamFreq[3];
695 +} __attribute__ ((packed));
696 +
697 +static const struct usb_interface_descriptor
698 +z_audio_control_if_desc = {
699 + .bLength = sizeof z_audio_control_if_desc,
700 + .bDescriptorType = USB_DT_INTERFACE,
701 + .bInterfaceNumber = 0,
702 + .bAlternateSetting = 0,
703 + .bNumEndpoints = 0,
704 + .bInterfaceClass = USB_CLASS_AUDIO,
705 + .bInterfaceSubClass = 0x1,
706 + .bInterfaceProtocol = 0,
707 + .iInterface = 0,
708 +};
709 +
710 +static const struct usb_interface_descriptor
711 +z_audio_if_desc = {
712 + .bLength = sizeof z_audio_if_desc,
713 + .bDescriptorType = USB_DT_INTERFACE,
714 + .bInterfaceNumber = 1,
715 + .bAlternateSetting = 0,
716 + .bNumEndpoints = 0,
717 + .bInterfaceClass = USB_CLASS_AUDIO,
718 + .bInterfaceSubClass = 0x2,
719 + .bInterfaceProtocol = 0,
720 + .iInterface = 0,
721 +};
722 +
723 +static const struct usb_interface_descriptor
724 +z_audio_if_desc2 = {
725 + .bLength = sizeof z_audio_if_desc,
726 + .bDescriptorType = USB_DT_INTERFACE,
727 + .bInterfaceNumber = 1,
728 + .bAlternateSetting = 1,
729 + .bNumEndpoints = 1,
730 + .bInterfaceClass = USB_CLASS_AUDIO,
731 + .bInterfaceSubClass = 0x2,
732 + .bInterfaceProtocol = 0,
733 + .iInterface = 0,
734 +};
735 +
736 +static const struct usb_cs_as_general_descriptor
737 +z_audio_cs_as_if_desc = {
738 + .bLength = 7,
739 + .bDescriptorType = 0x24,
740 +
741 + .bDescriptorSubType = 0x01,
742 + .bTerminalLink = 0x01,
743 + .bDelay = 0x0,
744 + .wFormatTag = __constant_cpu_to_le16 (0x0001)
745 +};
746 +
747 +
748 +static const struct usb_cs_as_format_descriptor
749 +z_audio_cs_as_format_desc = {
750 + .bLength = 0xe,
751 + .bDescriptorType = 0x24,
752 +
753 + .bDescriptorSubType = 2,
754 + .bFormatType = 1,
755 + .bNrChannels = 1,
756 + .bSubframeSize = 1,
757 + .bBitResolution = 8,
758 + .bSamfreqType = 0,
759 + .tLowerSamFreq = {0x7e, 0x13, 0x00},
760 + .tUpperSamFreq = {0xe2, 0xd6, 0x00},
761 +};
762 +
763 +static const struct usb_endpoint_descriptor
764 +z_iso_ep = {
765 + .bLength = 0x09,
766 + .bDescriptorType = 0x05,
767 + .bEndpointAddress = 0x04,
768 + .bmAttributes = 0x09,
769 + .wMaxPacketSize = 0x0038,
770 + .bInterval = 0x01,
771 + .bRefresh = 0x00,
772 + .bSynchAddress = 0x00,
773 +};
774 +
775 +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
776 +
777 +// 9 bytes
778 +static char z_ac_interface_header_desc[] =
779 +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
780 +
781 +// 12 bytes
782 +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
783 + 0x03, 0x00, 0x00, 0x00};
784 +// 13 bytes
785 +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
786 + 0x02, 0x00, 0x02, 0x00, 0x00};
787 +// 9 bytes
788 +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
789 + 0x00};
790 +
791 +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
792 + 0x00};
793 +
794 +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
795 +
796 +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
797 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
798 +
799 +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
800 + 0x00};
801 +
802 +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
803 +
804 +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
805 + 0x00};
806 +
807 +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
808 +
809 +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
810 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
811 +
812 +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
813 + 0x00};
814 +
815 +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
816 +
817 +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
818 + 0x00};
819 +
820 +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
821 +
822 +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
823 + 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
824 +
825 +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
826 + 0x00};
827 +
828 +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
829 +
830 +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
831 + 0x00};
832 +
833 +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
834 +
835 +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
836 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
837 +
838 +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
839 + 0x00};
840 +
841 +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
842 +
843 +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
844 + 0x00};
845 +
846 +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
847 +
848 +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
849 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
850 +
851 +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
852 + 0x00};
853 +
854 +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
855 +
856 +
857 +
858 +static const struct usb_descriptor_header *z_function [] = {
859 + (struct usb_descriptor_header *) &z_audio_control_if_desc,
860 + (struct usb_descriptor_header *) &z_ac_interface_header_desc,
861 + (struct usb_descriptor_header *) &z_0,
862 + (struct usb_descriptor_header *) &z_1,
863 + (struct usb_descriptor_header *) &z_2,
864 + (struct usb_descriptor_header *) &z_audio_if_desc,
865 + (struct usb_descriptor_header *) &z_audio_if_desc2,
866 + (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
867 + (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
868 + (struct usb_descriptor_header *) &z_iso_ep,
869 + (struct usb_descriptor_header *) &z_iso_ep2,
870 + (struct usb_descriptor_header *) &za_0,
871 + (struct usb_descriptor_header *) &za_1,
872 + (struct usb_descriptor_header *) &za_2,
873 + (struct usb_descriptor_header *) &za_3,
874 + (struct usb_descriptor_header *) &za_4,
875 + (struct usb_descriptor_header *) &za_5,
876 + (struct usb_descriptor_header *) &za_6,
877 + (struct usb_descriptor_header *) &za_7,
878 + (struct usb_descriptor_header *) &za_8,
879 + (struct usb_descriptor_header *) &za_9,
880 + (struct usb_descriptor_header *) &za_10,
881 + (struct usb_descriptor_header *) &za_11,
882 + (struct usb_descriptor_header *) &za_12,
883 + (struct usb_descriptor_header *) &za_13,
884 + (struct usb_descriptor_header *) &za_14,
885 + (struct usb_descriptor_header *) &za_15,
886 + (struct usb_descriptor_header *) &za_16,
887 + (struct usb_descriptor_header *) &za_17,
888 + (struct usb_descriptor_header *) &za_18,
889 + (struct usb_descriptor_header *) &za_19,
890 + (struct usb_descriptor_header *) &za_20,
891 + (struct usb_descriptor_header *) &za_21,
892 + (struct usb_descriptor_header *) &za_22,
893 + (struct usb_descriptor_header *) &za_23,
894 + (struct usb_descriptor_header *) &za_24,
895 + NULL,
896 +};
897 +
898 +/* maxpacket and other transfer characteristics vary by speed. */
899 +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
900 +
901 +#else
902 +
903 +/* if there's no high speed support, maxpacket doesn't change. */
904 +#define ep_desc(g,hs,fs) fs
905 +
906 +#endif /* !CONFIG_USB_GADGET_DUALSPEED */
907 +
908 +static char manufacturer [40];
909 +//static char serial [40];
910 +static char serial [] = "Ser 00 em";
911 +
912 +/* static strings, in UTF-8 */
913 +static struct usb_string strings [] = {
914 + { STRING_MANUFACTURER, manufacturer, },
915 + { STRING_PRODUCT, longname, },
916 + { STRING_SERIAL, serial, },
917 + { STRING_LOOPBACK, loopback, },
918 + { STRING_SOURCE_SINK, source_sink, },
919 + { } /* end of list */
920 +};
921 +
922 +static struct usb_gadget_strings stringtab = {
923 + .language = 0x0409, /* en-us */
924 + .strings = strings,
925 +};
926 +
927 +/*
928 + * config descriptors are also handcrafted. these must agree with code
929 + * that sets configurations, and with code managing interfaces and their
930 + * altsettings. other complexity may come from:
931 + *
932 + * - high speed support, including "other speed config" rules
933 + * - multiple configurations
934 + * - interfaces with alternate settings
935 + * - embedded class or vendor-specific descriptors
936 + *
937 + * this handles high speed, and has a second config that could as easily
938 + * have been an alternate interface setting (on most hardware).
939 + *
940 + * NOTE: to demonstrate (and test) more USB capabilities, this driver
941 + * should include an altsetting to test interrupt transfers, including
942 + * high bandwidth modes at high speed. (Maybe work like Intel's test
943 + * device?)
944 + */
945 +static int
946 +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
947 +{
948 + int len;
949 + const struct usb_descriptor_header **function;
950 +
951 + function = z_function;
952 + len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
953 + if (len < 0)
954 + return len;
955 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
956 + return len;
957 +}
958 +
959 +/*-------------------------------------------------------------------------*/
960 +
961 +static struct usb_request *
962 +alloc_ep_req (struct usb_ep *ep, unsigned length)
963 +{
964 + struct usb_request *req;
965 +
966 + req = usb_ep_alloc_request (ep, GFP_ATOMIC);
967 + if (req) {
968 + req->length = length;
969 + req->buf = usb_ep_alloc_buffer (ep, length,
970 + &req->dma, GFP_ATOMIC);
971 + if (!req->buf) {
972 + usb_ep_free_request (ep, req);
973 + req = NULL;
974 + }
975 + }
976 + return req;
977 +}
978 +
979 +static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
980 +{
981 + if (req->buf)
982 + usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
983 + usb_ep_free_request (ep, req);
984 +}
985 +
986 +/*-------------------------------------------------------------------------*/
987 +
988 +/* optionally require specific source/sink data patterns */
989 +
990 +static int
991 +check_read_data (
992 + struct zero_dev *dev,
993 + struct usb_ep *ep,
994 + struct usb_request *req
995 +)
996 +{
997 + unsigned i;
998 + u8 *buf = req->buf;
999 +
1000 + for (i = 0; i < req->actual; i++, buf++) {
1001 + switch (pattern) {
1002 + /* all-zeroes has no synchronization issues */
1003 + case 0:
1004 + if (*buf == 0)
1005 + continue;
1006 + break;
1007 + /* mod63 stays in sync with short-terminated transfers,
1008 + * or otherwise when host and gadget agree on how large
1009 + * each usb transfer request should be. resync is done
1010 + * with set_interface or set_config.
1011 + */
1012 + case 1:
1013 + if (*buf == (u8)(i % 63))
1014 + continue;
1015 + break;
1016 + }
1017 + ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
1018 + usb_ep_set_halt (ep);
1019 + return -EINVAL;
1020 + }
1021 + return 0;
1022 +}
1023 +
1024 +/*-------------------------------------------------------------------------*/
1025 +
1026 +static void zero_reset_config (struct zero_dev *dev)
1027 +{
1028 + if (dev->config == 0)
1029 + return;
1030 +
1031 + DBG (dev, "reset config\n");
1032 +
1033 + /* just disable endpoints, forcing completion of pending i/o.
1034 + * all our completion handlers free their requests in this case.
1035 + */
1036 + if (dev->in_ep) {
1037 + usb_ep_disable (dev->in_ep);
1038 + dev->in_ep = NULL;
1039 + }
1040 + if (dev->out_ep) {
1041 + usb_ep_disable (dev->out_ep);
1042 + dev->out_ep = NULL;
1043 + }
1044 + dev->config = 0;
1045 + del_timer (&dev->resume);
1046 +}
1047 +
1048 +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
1049 +
1050 +static void
1051 +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
1052 +{
1053 + struct zero_dev *dev = ep->driver_data;
1054 + int status = req->status;
1055 + int i, j;
1056 +
1057 + switch (status) {
1058 +
1059 + case 0: /* normal completion? */
1060 + //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
1061 + for (i=0, j=rbuf_start; i<req->actual; i++) {
1062 + //printk ("%02x ", ((__u8*)req->buf)[i]);
1063 + rbuf[j] = ((__u8*)req->buf)[i];
1064 + j++;
1065 + if (j >= RBUF_LEN) j=0;
1066 + }
1067 + rbuf_start = j;
1068 + //printk ("\n\n");
1069 +
1070 + if (rbuf_len < RBUF_LEN) {
1071 + rbuf_len += req->actual;
1072 + if (rbuf_len > RBUF_LEN) {
1073 + rbuf_len = RBUF_LEN;
1074 + }
1075 + }
1076 +
1077 + break;
1078 +
1079 + /* this endpoint is normally active while we're configured */
1080 + case -ECONNABORTED: /* hardware forced ep reset */
1081 + case -ECONNRESET: /* request dequeued */
1082 + case -ESHUTDOWN: /* disconnect from host */
1083 + VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
1084 + req->actual, req->length);
1085 + if (ep == dev->out_ep)
1086 + check_read_data (dev, ep, req);
1087 + free_ep_req (ep, req);
1088 + return;
1089 +
1090 + case -EOVERFLOW: /* buffer overrun on read means that
1091 + * we didn't provide a big enough
1092 + * buffer.
1093 + */
1094 + default:
1095 +#if 1
1096 + DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
1097 + status, req->actual, req->length);
1098 +#endif
1099 + case -EREMOTEIO: /* short read */
1100 + break;
1101 + }
1102 +
1103 + status = usb_ep_queue (ep, req, GFP_ATOMIC);
1104 + if (status) {
1105 + ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
1106 + ep->name, req->length, status);
1107 + usb_ep_set_halt (ep);
1108 + /* FIXME recover later ... somehow */
1109 + }
1110 +}
1111 +
1112 +static struct usb_request *
1113 +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
1114 +{
1115 + struct usb_request *req;
1116 + int status;
1117 +
1118 + req = alloc_ep_req (ep, 512);
1119 + if (!req)
1120 + return NULL;
1121 +
1122 + req->complete = zero_isoc_complete;
1123 +
1124 + status = usb_ep_queue (ep, req, gfp_flags);
1125 + if (status) {
1126 + struct zero_dev *dev = ep->driver_data;
1127 +
1128 + ERROR (dev, "start %s --> %d\n", ep->name, status);
1129 + free_ep_req (ep, req);
1130 + req = NULL;
1131 + }
1132 +
1133 + return req;
1134 +}
1135 +
1136 +/* change our operational config. this code must agree with the code
1137 + * that returns config descriptors, and altsetting code.
1138 + *
1139 + * it's also responsible for power management interactions. some
1140 + * configurations might not work with our current power sources.
1141 + *
1142 + * note that some device controller hardware will constrain what this
1143 + * code can do, perhaps by disallowing more than one configuration or
1144 + * by limiting configuration choices (like the pxa2xx).
1145 + */
1146 +static int
1147 +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
1148 +{
1149 + int result = 0;
1150 + struct usb_gadget *gadget = dev->gadget;
1151 + const struct usb_endpoint_descriptor *d;
1152 + struct usb_ep *ep;
1153 +
1154 + if (number == dev->config)
1155 + return 0;
1156 +
1157 + zero_reset_config (dev);
1158 +
1159 + gadget_for_each_ep (ep, gadget) {
1160 +
1161 + if (strcmp (ep->name, "ep4") == 0) {
1162 +
1163 + d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
1164 + result = usb_ep_enable (ep, d);
1165 +
1166 + if (result == 0) {
1167 + ep->driver_data = dev;
1168 + dev->in_ep = ep;
1169 +
1170 + if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
1171 +
1172 + dev->in_ep = ep;
1173 + continue;
1174 + }
1175 +
1176 + usb_ep_disable (ep);
1177 + result = -EIO;
1178 + }
1179 + }
1180 +
1181 + }
1182 +
1183 + dev->config = number;
1184 + return result;
1185 +}
1186 +
1187 +/*-------------------------------------------------------------------------*/
1188 +
1189 +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
1190 +{
1191 + if (req->status || req->actual != req->length)
1192 + DBG ((struct zero_dev *) ep->driver_data,
1193 + "setup complete --> %d, %d/%d\n",
1194 + req->status, req->actual, req->length);
1195 +}
1196 +
1197 +/*
1198 + * The setup() callback implements all the ep0 functionality that's
1199 + * not handled lower down, in hardware or the hardware driver (like
1200 + * device and endpoint feature flags, and their status). It's all
1201 + * housekeeping for the gadget function we're implementing. Most of
1202 + * the work is in config-specific setup.
1203 + */
1204 +static int
1205 +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
1206 +{
1207 + struct zero_dev *dev = get_gadget_data (gadget);
1208 + struct usb_request *req = dev->req;
1209 + int value = -EOPNOTSUPP;
1210 +
1211 + /* usually this stores reply data in the pre-allocated ep0 buffer,
1212 + * but config change events will reconfigure hardware.
1213 + */
1214 + req->zero = 0;
1215 + switch (ctrl->bRequest) {
1216 +
1217 + case USB_REQ_GET_DESCRIPTOR:
1218 +
1219 + switch (ctrl->wValue >> 8) {
1220 +
1221 + case USB_DT_DEVICE:
1222 + value = min (ctrl->wLength, (u16) sizeof device_desc);
1223 + memcpy (req->buf, &device_desc, value);
1224 + break;
1225 +#ifdef CONFIG_USB_GADGET_DUALSPEED
1226 + case USB_DT_DEVICE_QUALIFIER:
1227 + if (!gadget->is_dualspeed)
1228 + break;
1229 + value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
1230 + memcpy (req->buf, &dev_qualifier, value);
1231 + break;
1232 +
1233 + case USB_DT_OTHER_SPEED_CONFIG:
1234 + if (!gadget->is_dualspeed)
1235 + break;
1236 + // FALLTHROUGH
1237 +#endif /* CONFIG_USB_GADGET_DUALSPEED */
1238 + case USB_DT_CONFIG:
1239 + value = config_buf (gadget, req->buf,
1240 + ctrl->wValue >> 8,
1241 + ctrl->wValue & 0xff);
1242 + if (value >= 0)
1243 + value = min (ctrl->wLength, (u16) value);
1244 + break;
1245 +
1246 + case USB_DT_STRING:
1247 + /* wIndex == language code.
1248 + * this driver only handles one language, you can
1249 + * add string tables for other languages, using
1250 + * any UTF-8 characters
1251 + */
1252 + value = usb_gadget_get_string (&stringtab,
1253 + ctrl->wValue & 0xff, req->buf);
1254 + if (value >= 0) {
1255 + value = min (ctrl->wLength, (u16) value);
1256 + }
1257 + break;
1258 + }
1259 + break;
1260 +
1261 + /* currently two configs, two speeds */
1262 + case USB_REQ_SET_CONFIGURATION:
1263 + if (ctrl->bRequestType != 0)
1264 + goto unknown;
1265 +
1266 + spin_lock (&dev->lock);
1267 + value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
1268 + spin_unlock (&dev->lock);
1269 + break;
1270 + case USB_REQ_GET_CONFIGURATION:
1271 + if (ctrl->bRequestType != USB_DIR_IN)
1272 + goto unknown;
1273 + *(u8 *)req->buf = dev->config;
1274 + value = min (ctrl->wLength, (u16) 1);
1275 + break;
1276 +
1277 + /* until we add altsetting support, or other interfaces,
1278 + * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
1279 + * and already killed pending endpoint I/O.
1280 + */
1281 + case USB_REQ_SET_INTERFACE:
1282 +
1283 + if (ctrl->bRequestType != USB_RECIP_INTERFACE)
1284 + goto unknown;
1285 + spin_lock (&dev->lock);
1286 + if (dev->config) {
1287 + u8 config = dev->config;
1288 +
1289 + /* resets interface configuration, forgets about
1290 + * previous transaction state (queued bufs, etc)
1291 + * and re-inits endpoint state (toggle etc)
1292 + * no response queued, just zero status == success.
1293 + * if we had more than one interface we couldn't
1294 + * use this "reset the config" shortcut.
1295 + */
1296 + zero_reset_config (dev);
1297 + zero_set_config (dev, config, GFP_ATOMIC);
1298 + value = 0;
1299 + }
1300 + spin_unlock (&dev->lock);
1301 + break;
1302 + case USB_REQ_GET_INTERFACE:
1303 + if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
1304 + value = ctrl->wLength;
1305 + break;
1306 + }
1307 + else {
1308 + if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
1309 + goto unknown;
1310 + if (!dev->config)
1311 + break;
1312 + if (ctrl->wIndex != 0) {
1313 + value = -EDOM;
1314 + break;
1315 + }
1316 + *(u8 *)req->buf = 0;
1317 + value = min (ctrl->wLength, (u16) 1);
1318 + }
1319 + break;
1320 +
1321 + /*
1322 + * These are the same vendor-specific requests supported by
1323 + * Intel's USB 2.0 compliance test devices. We exceed that
1324 + * device spec by allowing multiple-packet requests.
1325 + */
1326 + case 0x5b: /* control WRITE test -- fill the buffer */
1327 + if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
1328 + goto unknown;
1329 + if (ctrl->wValue || ctrl->wIndex)
1330 + break;
1331 + /* just read that many bytes into the buffer */
1332 + if (ctrl->wLength > USB_BUFSIZ)
1333 + break;
1334 + value = ctrl->wLength;
1335 + break;
1336 + case 0x5c: /* control READ test -- return the buffer */
1337 + if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
1338 + goto unknown;
1339 + if (ctrl->wValue || ctrl->wIndex)
1340 + break;
1341 + /* expect those bytes are still in the buffer; send back */
1342 + if (ctrl->wLength > USB_BUFSIZ
1343 + || ctrl->wLength != req->length)
1344 + break;
1345 + value = ctrl->wLength;
1346 + break;
1347 +
1348 + case 0x01: // SET_CUR
1349 + case 0x02:
1350 + case 0x03:
1351 + case 0x04:
1352 + case 0x05:
1353 + value = ctrl->wLength;
1354 + break;
1355 + case 0x81:
1356 + switch (ctrl->wValue) {
1357 + case 0x0201:
1358 + case 0x0202:
1359 + ((u8*)req->buf)[0] = 0x00;
1360 + ((u8*)req->buf)[1] = 0xe3;
1361 + break;
1362 + case 0x0300:
1363 + case 0x0500:
1364 + ((u8*)req->buf)[0] = 0x00;
1365 + break;
1366 + }
1367 + //((u8*)req->buf)[0] = 0x81;
1368 + //((u8*)req->buf)[1] = 0x81;
1369 + value = ctrl->wLength;
1370 + break;
1371 + case 0x82:
1372 + switch (ctrl->wValue) {
1373 + case 0x0201:
1374 + case 0x0202:
1375 + ((u8*)req->buf)[0] = 0x00;
1376 + ((u8*)req->buf)[1] = 0xc3;
1377 + break;
1378 + case 0x0300:
1379 + case 0x0500:
1380 + ((u8*)req->buf)[0] = 0x00;
1381 + break;
1382 + }
1383 + //((u8*)req->buf)[0] = 0x82;
1384 + //((u8*)req->buf)[1] = 0x82;
1385 + value = ctrl->wLength;
1386 + break;
1387 + case 0x83:
1388 + switch (ctrl->wValue) {
1389 + case 0x0201:
1390 + case 0x0202:
1391 + ((u8*)req->buf)[0] = 0x00;
1392 + ((u8*)req->buf)[1] = 0x00;
1393 + break;
1394 + case 0x0300:
1395 + ((u8*)req->buf)[0] = 0x60;
1396 + break;
1397 + case 0x0500:
1398 + ((u8*)req->buf)[0] = 0x18;
1399 + break;
1400 + }
1401 + //((u8*)req->buf)[0] = 0x83;
1402 + //((u8*)req->buf)[1] = 0x83;
1403 + value = ctrl->wLength;
1404 + break;
1405 + case 0x84:
1406 + switch (ctrl->wValue) {
1407 + case 0x0201:
1408 + case 0x0202:
1409 + ((u8*)req->buf)[0] = 0x00;
1410 + ((u8*)req->buf)[1] = 0x01;
1411 + break;
1412 + case 0x0300:
1413 + case 0x0500:
1414 + ((u8*)req->buf)[0] = 0x08;
1415 + break;
1416 + }
1417 + //((u8*)req->buf)[0] = 0x84;
1418 + //((u8*)req->buf)[1] = 0x84;
1419 + value = ctrl->wLength;
1420 + break;
1421 + case 0x85:
1422 + ((u8*)req->buf)[0] = 0x85;
1423 + ((u8*)req->buf)[1] = 0x85;
1424 + value = ctrl->wLength;
1425 + break;
1426 +
1427 +
1428 + default:
1429 +unknown:
1430 + printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
1431 + ctrl->bRequestType, ctrl->bRequest,
1432 + ctrl->wValue, ctrl->wIndex, ctrl->wLength);
1433 + }
1434 +
1435 + /* respond with data transfer before status phase? */
1436 + if (value >= 0) {
1437 + req->length = value;
1438 + req->zero = value < ctrl->wLength
1439 + && (value % gadget->ep0->maxpacket) == 0;
1440 + value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
1441 + if (value < 0) {
1442 + DBG (dev, "ep_queue < 0 --> %d\n", value);
1443 + req->status = 0;
1444 + zero_setup_complete (gadget->ep0, req);
1445 + }
1446 + }
1447 +
1448 + /* device either stalls (value < 0) or reports success */
1449 + return value;
1450 +}
1451 +
1452 +static void
1453 +zero_disconnect (struct usb_gadget *gadget)
1454 +{
1455 + struct zero_dev *dev = get_gadget_data (gadget);
1456 + unsigned long flags;
1457 +
1458 + spin_lock_irqsave (&dev->lock, flags);
1459 + zero_reset_config (dev);
1460 +
1461 + /* a more significant application might have some non-usb
1462 + * activities to quiesce here, saving resources like power
1463 + * or pushing the notification up a network stack.
1464 + */
1465 + spin_unlock_irqrestore (&dev->lock, flags);
1466 +
1467 + /* next we may get setup() calls to enumerate new connections;
1468 + * or an unbind() during shutdown (including removing module).
1469 + */
1470 +}
1471 +
1472 +static void
1473 +zero_autoresume (unsigned long _dev)
1474 +{
1475 + struct zero_dev *dev = (struct zero_dev *) _dev;
1476 + int status;
1477 +
1478 + /* normally the host would be woken up for something
1479 + * more significant than just a timer firing...
1480 + */
1481 + if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
1482 + status = usb_gadget_wakeup (dev->gadget);
1483 + DBG (dev, "wakeup --> %d\n", status);
1484 + }
1485 +}
1486 +
1487 +/*-------------------------------------------------------------------------*/
1488 +
1489 +static void
1490 +zero_unbind (struct usb_gadget *gadget)
1491 +{
1492 + struct zero_dev *dev = get_gadget_data (gadget);
1493 +
1494 + DBG (dev, "unbind\n");
1495 +
1496 + /* we've already been disconnected ... no i/o is active */
1497 + if (dev->req)
1498 + free_ep_req (gadget->ep0, dev->req);
1499 + del_timer_sync (&dev->resume);
1500 + kfree (dev);
1501 + set_gadget_data (gadget, NULL);
1502 +}
1503 +
1504 +static int
1505 +zero_bind (struct usb_gadget *gadget)
1506 +{
1507 + struct zero_dev *dev;
1508 + //struct usb_ep *ep;
1509 +
1510 + printk("binding\n");
1511 + /*
1512 + * DRIVER POLICY CHOICE: you may want to do this differently.
1513 + * One thing to avoid is reusing a bcdDevice revision code
1514 + * with different host-visible configurations or behavior
1515 + * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
1516 + */
1517 + //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
1518 +
1519 +
1520 + /* ok, we made sense of the hardware ... */
1521 + dev = kmalloc (sizeof *dev, SLAB_KERNEL);
1522 + if (!dev)
1523 + return -ENOMEM;
1524 + memset (dev, 0, sizeof *dev);
1525 + spin_lock_init (&dev->lock);
1526 + dev->gadget = gadget;
1527 + set_gadget_data (gadget, dev);
1528 +
1529 + /* preallocate control response and buffer */
1530 + dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
1531 + if (!dev->req)
1532 + goto enomem;
1533 + dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
1534 + &dev->req->dma, GFP_KERNEL);
1535 + if (!dev->req->buf)
1536 + goto enomem;
1537 +
1538 + dev->req->complete = zero_setup_complete;
1539 +
1540 + device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
1541 +
1542 +#ifdef CONFIG_USB_GADGET_DUALSPEED
1543 + /* assume ep0 uses the same value for both speeds ... */
1544 + dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
1545 +
1546 + /* and that all endpoints are dual-speed */
1547 + //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
1548 + //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
1549 +#endif
1550 +
1551 + usb_gadget_set_selfpowered (gadget);
1552 +
1553 + init_timer (&dev->resume);
1554 + dev->resume.function = zero_autoresume;
1555 + dev->resume.data = (unsigned long) dev;
1556 +
1557 + gadget->ep0->driver_data = dev;
1558 +
1559 + INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
1560 + INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
1561 + EP_OUT_NAME, EP_IN_NAME);
1562 +
1563 + snprintf (manufacturer, sizeof manufacturer,
1564 + UTS_SYSNAME " " UTS_RELEASE " with %s",
1565 + gadget->name);
1566 +
1567 + return 0;
1568 +
1569 +enomem:
1570 + zero_unbind (gadget);
1571 + return -ENOMEM;
1572 +}
1573 +
1574 +/*-------------------------------------------------------------------------*/
1575 +
1576 +static void
1577 +zero_suspend (struct usb_gadget *gadget)
1578 +{
1579 + struct zero_dev *dev = get_gadget_data (gadget);
1580 +
1581 + if (gadget->speed == USB_SPEED_UNKNOWN)
1582 + return;
1583 +
1584 + if (autoresume) {
1585 + mod_timer (&dev->resume, jiffies + (HZ * autoresume));
1586 + DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
1587 + } else
1588 + DBG (dev, "suspend\n");
1589 +}
1590 +
1591 +static void
1592 +zero_resume (struct usb_gadget *gadget)
1593 +{
1594 + struct zero_dev *dev = get_gadget_data (gadget);
1595 +
1596 + DBG (dev, "resume\n");
1597 + del_timer (&dev->resume);
1598 +}
1599 +
1600 +
1601 +/*-------------------------------------------------------------------------*/
1602 +
1603 +static struct usb_gadget_driver zero_driver = {
1604 +#ifdef CONFIG_USB_GADGET_DUALSPEED
1605 + .speed = USB_SPEED_HIGH,
1606 +#else
1607 + .speed = USB_SPEED_FULL,
1608 +#endif
1609 + .function = (char *) longname,
1610 + .bind = zero_bind,
1611 + .unbind = zero_unbind,
1612 +
1613 + .setup = zero_setup,
1614 + .disconnect = zero_disconnect,
1615 +
1616 + .suspend = zero_suspend,
1617 + .resume = zero_resume,
1618 +
1619 + .driver = {
1620 + .name = (char *) shortname,
1621 + // .shutdown = ...
1622 + // .suspend = ...
1623 + // .resume = ...
1624 + },
1625 +};
1626 +
1627 +MODULE_AUTHOR ("David Brownell");
1628 +MODULE_LICENSE ("Dual BSD/GPL");
1629 +
1630 +static struct proc_dir_entry *pdir, *pfile;
1631 +
1632 +static int isoc_read_data (char *page, char **start,
1633 + off_t off, int count,
1634 + int *eof, void *data)
1635 +{
1636 + int i;
1637 + static int c = 0;
1638 + static int done = 0;
1639 + static int s = 0;
1640 +
1641 +/*
1642 + printk ("\ncount: %d\n", count);
1643 + printk ("rbuf_start: %d\n", rbuf_start);
1644 + printk ("rbuf_len: %d\n", rbuf_len);
1645 + printk ("off: %d\n", off);
1646 + printk ("start: %p\n\n", *start);
1647 +*/
1648 + if (done) {
1649 + c = 0;
1650 + done = 0;
1651 + *eof = 1;
1652 + return 0;
1653 + }
1654 +
1655 + if (c == 0) {
1656 + if (rbuf_len == RBUF_LEN)
1657 + s = rbuf_start;
1658 + else s = 0;
1659 + }
1660 +
1661 + for (i=0; i<count && c<rbuf_len; i++, c++) {
1662 + page[i] = rbuf[(c+s) % RBUF_LEN];
1663 + }
1664 + *start = page;
1665 +
1666 + if (c >= rbuf_len) {
1667 + *eof = 1;
1668 + done = 1;
1669 + }
1670 +
1671 +
1672 + return i;
1673 +}
1674 +
1675 +static int __init init (void)
1676 +{
1677 +
1678 + int retval = 0;
1679 +
1680 + pdir = proc_mkdir("isoc_test", NULL);
1681 + if(pdir == NULL) {
1682 + retval = -ENOMEM;
1683 + printk("Error creating dir\n");
1684 + goto done;
1685 + }
1686 + pdir->owner = THIS_MODULE;
1687 +
1688 + pfile = create_proc_read_entry("isoc_data",
1689 + 0444, pdir,
1690 + isoc_read_data,
1691 + NULL);
1692 + if (pfile == NULL) {
1693 + retval = -ENOMEM;
1694 + printk("Error creating file\n");
1695 + goto no_file;
1696 + }
1697 + pfile->owner = THIS_MODULE;
1698 +
1699 + return usb_gadget_register_driver (&zero_driver);
1700 +
1701 + no_file:
1702 + remove_proc_entry("isoc_data", NULL);
1703 + done:
1704 + return retval;
1705 +}
1706 +module_init (init);
1707 +
1708 +static void __exit cleanup (void)
1709 +{
1710 +
1711 + usb_gadget_unregister_driver (&zero_driver);
1712 +
1713 + remove_proc_entry("isoc_data", pdir);
1714 + remove_proc_entry("isoc_test", NULL);
1715 +}
1716 +module_exit (cleanup);
1717 diff --git a/drivers/usb/dwc_otg/dwc_otg_attr.c b/drivers/usb/dwc_otg/dwc_otg_attr.c
1718 new file mode 100644
1719 index 0000000..8543537
1720 --- /dev/null
1721 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
1722 @@ -0,0 +1,966 @@
1723 +/* ==========================================================================
1724 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
1725 + * $Revision: 1.2 $
1726 + * $Date: 2008-11-21 05:39:15 $
1727 + * $Change: 1064918 $
1728 + *
1729 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
1730 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
1731 + * otherwise expressly agreed to in writing between Synopsys and you.
1732 + *
1733 + * The Software IS NOT an item of Licensed Software or Licensed Product under
1734 + * any End User Software License Agreement or Agreement for Licensed Product
1735 + * with Synopsys or any supplement thereto. You are permitted to use and
1736 + * redistribute this Software in source and binary forms, with or without
1737 + * modification, provided that redistributions of source code must retain this
1738 + * notice. You may not view, use, disclose, copy or distribute this file or
1739 + * any information contained herein except pursuant to this license grant from
1740 + * Synopsys. If you do not agree with this notice, including the disclaimer
1741 + * below, then you are not authorized to use the Software.
1742 + *
1743 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1744 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1745 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1746 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1747 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1748 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1749 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1750 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1751 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1752 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1753 + * DAMAGE.
1754 + * ========================================================================== */
1755 +
1756 +/** @file
1757 + *
1758 + * The diagnostic interface will provide access to the controller for
1759 + * bringing up the hardware and testing. The Linux driver attributes
1760 + * feature will be used to provide the Linux Diagnostic
1761 + * Interface. These attributes are accessed through sysfs.
1762 + */
1763 +
1764 +/** @page "Linux Module Attributes"
1765 + *
1766 + * The Linux module attributes feature is used to provide the Linux
1767 + * Diagnostic Interface. These attributes are accessed through sysfs.
1768 + * The diagnostic interface will provide access to the controller for
1769 + * bringing up the hardware and testing.
1770 +
1771 +
1772 + The following table shows the attributes.
1773 + <table>
1774 + <tr>
1775 + <td><b> Name</b></td>
1776 + <td><b> Description</b></td>
1777 + <td><b> Access</b></td>
1778 + </tr>
1779 +
1780 + <tr>
1781 + <td> mode </td>
1782 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
1783 + <td> Read</td>
1784 + </tr>
1785 +
1786 + <tr>
1787 + <td> hnpcapable </td>
1788 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
1789 + Read returns the current value.</td>
1790 + <td> Read/Write</td>
1791 + </tr>
1792 +
1793 + <tr>
1794 + <td> srpcapable </td>
1795 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
1796 + Read returns the current value.</td>
1797 + <td> Read/Write</td>
1798 + </tr>
1799 +
1800 + <tr>
1801 + <td> hnp </td>
1802 + <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
1803 + <td> Read/Write</td>
1804 + </tr>
1805 +
1806 + <tr>
1807 + <td> srp </td>
1808 + <td> Initiates the Session Request Protocol. Read returns the status.</td>
1809 + <td> Read/Write</td>
1810 + </tr>
1811 +
1812 + <tr>
1813 + <td> buspower </td>
1814 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
1815 + <td> Read/Write</td>
1816 + </tr>
1817 +
1818 + <tr>
1819 + <td> bussuspend </td>
1820 + <td> Suspends the USB bus.</td>
1821 + <td> Read/Write</td>
1822 + </tr>
1823 +
1824 + <tr>
1825 + <td> busconnected </td>
1826 + <td> Gets the connection status of the bus</td>
1827 + <td> Read</td>
1828 + </tr>
1829 +
1830 + <tr>
1831 + <td> gotgctl </td>
1832 + <td> Gets or sets the Core Control Status Register.</td>
1833 + <td> Read/Write</td>
1834 + </tr>
1835 +
1836 + <tr>
1837 + <td> gusbcfg </td>
1838 + <td> Gets or sets the Core USB Configuration Register</td>
1839 + <td> Read/Write</td>
1840 + </tr>
1841 +
1842 + <tr>
1843 + <td> grxfsiz </td>
1844 + <td> Gets or sets the Receive FIFO Size Register</td>
1845 + <td> Read/Write</td>
1846 + </tr>
1847 +
1848 + <tr>
1849 + <td> gnptxfsiz </td>
1850 + <td> Gets or sets the non-periodic Transmit Size Register</td>
1851 + <td> Read/Write</td>
1852 + </tr>
1853 +
1854 + <tr>
1855 + <td> gpvndctl </td>
1856 + <td> Gets or sets the PHY Vendor Control Register</td>
1857 + <td> Read/Write</td>
1858 + </tr>
1859 +
1860 + <tr>
1861 + <td> ggpio </td>
1862 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
1863 + or sets the upper 16 bits.</td>
1864 + <td> Read/Write</td>
1865 + </tr>
1866 +
1867 + <tr>
1868 + <td> guid </td>
1869 + <td> Gets or sets the value of the User ID Register</td>
1870 + <td> Read/Write</td>
1871 + </tr>
1872 +
1873 + <tr>
1874 + <td> gsnpsid </td>
1875 + <td> Gets the value of the Synopsys ID Regester</td>
1876 + <td> Read</td>
1877 + </tr>
1878 +
1879 + <tr>
1880 + <td> devspeed </td>
1881 + <td> Gets or sets the device speed setting in the DCFG register</td>
1882 + <td> Read/Write</td>
1883 + </tr>
1884 +
1885 + <tr>
1886 + <td> enumspeed </td>
1887 + <td> Gets the device enumeration Speed.</td>
1888 + <td> Read</td>
1889 + </tr>
1890 +
1891 + <tr>
1892 + <td> hptxfsiz </td>
1893 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
1894 + <td> Read</td>
1895 + </tr>
1896 +
1897 + <tr>
1898 + <td> hprt0 </td>
1899 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
1900 + <td> Read/Write</td>
1901 + </tr>
1902 +
1903 + <tr>
1904 + <td> regoffset </td>
1905 + <td> Sets the register offset for the next Register Access</td>
1906 + <td> Read/Write</td>
1907 + </tr>
1908 +
1909 + <tr>
1910 + <td> regvalue </td>
1911 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
1912 + <td> Read/Write</td>
1913 + </tr>
1914 +
1915 + <tr>
1916 + <td> remote_wakeup </td>
1917 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
1918 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
1919 + Wakeup signalling bit in the Device Control Register is set for 1
1920 + milli-second.</td>
1921 + <td> Read/Write</td>
1922 + </tr>
1923 +
1924 + <tr>
1925 + <td> regdump </td>
1926 + <td> Dumps the contents of core registers.</td>
1927 + <td> Read</td>
1928 + </tr>
1929 +
1930 + <tr>
1931 + <td> spramdump </td>
1932 + <td> Dumps the contents of core registers.</td>
1933 + <td> Read</td>
1934 + </tr>
1935 +
1936 + <tr>
1937 + <td> hcddump </td>
1938 + <td> Dumps the current HCD state.</td>
1939 + <td> Read</td>
1940 + </tr>
1941 +
1942 + <tr>
1943 + <td> hcd_frrem </td>
1944 + <td> Shows the average value of the Frame Remaining
1945 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
1946 + occurs. This can be used to determine the average interrupt latency. Also
1947 + shows the average Frame Remaining value for start_transfer and the "a" and
1948 + "b" sample points. The "a" and "b" sample points may be used during debugging
1949 + bto determine how long it takes to execute a section of the HCD code.</td>
1950 + <td> Read</td>
1951 + </tr>
1952 +
1953 + <tr>
1954 + <td> rd_reg_test </td>
1955 + <td> Displays the time required to read the GNPTXFSIZ register many times
1956 + (the output shows the number of times the register is read).
1957 + <td> Read</td>
1958 + </tr>
1959 +
1960 + <tr>
1961 + <td> wr_reg_test </td>
1962 + <td> Displays the time required to write the GNPTXFSIZ register many times
1963 + (the output shows the number of times the register is written).
1964 + <td> Read</td>
1965 + </tr>
1966 +
1967 + </table>
1968 +
1969 + Example usage:
1970 + To get the current mode:
1971 + cat /sys/devices/lm0/mode
1972 +
1973 + To power down the USB:
1974 + echo 0 > /sys/devices/lm0/buspower
1975 + */
1976 +
1977 +#include <linux/kernel.h>
1978 +#include <linux/module.h>
1979 +#include <linux/moduleparam.h>
1980 +#include <linux/init.h>
1981 +#include <linux/device.h>
1982 +#include <linux/errno.h>
1983 +#include <linux/types.h>
1984 +#include <linux/stat.h> /* permission constants */
1985 +#include <linux/version.h>
1986 +
1987 +#include <asm/io.h>
1988 +
1989 +#include "linux/dwc_otg_plat.h"
1990 +#include "dwc_otg_attr.h"
1991 +#include "dwc_otg_driver.h"
1992 +#include "dwc_otg_pcd.h"
1993 +#include "dwc_otg_hcd.h"
1994 +
1995 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1996 +/*
1997 + * MACROs for defining sysfs attribute
1998 + */
1999 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2000 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
2001 +{ \
2002 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
2003 + uint32_t val; \
2004 + val = dwc_read_reg32 (_addr_); \
2005 + val = (val & (_mask_)) >> _shift_; \
2006 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
2007 +}
2008 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2009 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
2010 + const char *buf, size_t count) \
2011 +{ \
2012 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
2013 + uint32_t set = simple_strtoul(buf, NULL, 16); \
2014 + uint32_t clear = set; \
2015 + clear = ((~clear) << _shift_) & _mask_; \
2016 + set = (set << _shift_) & _mask_; \
2017 + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
2018 + dwc_modify_reg32(_addr_, clear, set); \
2019 + return count; \
2020 +}
2021 +
2022 +/*
2023 + * MACROs for defining sysfs attribute for 32-bit registers
2024 + */
2025 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2026 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
2027 +{ \
2028 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
2029 + uint32_t val; \
2030 + val = dwc_read_reg32 (_addr_); \
2031 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
2032 +}
2033 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
2034 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
2035 + const char *buf, size_t count) \
2036 +{ \
2037 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
2038 + uint32_t val = simple_strtoul(buf, NULL, 16); \
2039 + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
2040 + dwc_write_reg32(_addr_, val); \
2041 + return count; \
2042 +}
2043 +
2044 +#else
2045 +
2046 +/*
2047 + * MACROs for defining sysfs attribute
2048 + */
2049 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2050 +static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
2051 +{ \
2052 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2053 + uint32_t val; \
2054 + val = dwc_read_reg32 (_addr_); \
2055 + val = (val & (_mask_)) >> _shift_; \
2056 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
2057 +}
2058 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2059 +static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
2060 +{ \
2061 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2062 + uint32_t set = simple_strtoul(buf, NULL, 16); \
2063 + uint32_t clear = set; \
2064 + clear = ((~clear) << _shift_) & _mask_; \
2065 + set = (set << _shift_) & _mask_; \
2066 + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
2067 + dwc_modify_reg32(_addr_, clear, set); \
2068 + return count; \
2069 +}
2070 +
2071 +/*
2072 + * MACROs for defining sysfs attribute for 32-bit registers
2073 + */
2074 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2075 +static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
2076 +{ \
2077 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2078 + uint32_t val; \
2079 + val = dwc_read_reg32 (_addr_); \
2080 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
2081 +}
2082 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
2083 +static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
2084 +{ \
2085 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
2086 + uint32_t val = simple_strtoul(buf, NULL, 16); \
2087 + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
2088 + dwc_write_reg32(_addr_, val); \
2089 + return count; \
2090 +}
2091 +
2092 +#endif
2093 +
2094 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2095 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2096 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2097 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
2098 +
2099 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2100 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
2101 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
2102 +
2103 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
2104 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2105 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
2106 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
2107 +
2108 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
2109 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
2110 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
2111 +
2112 +
2113 +/** @name Functions for Show/Store of Attributes */
2114 +/**@{*/
2115 +
2116 +/**
2117 + * Show the register offset of the Register Access.
2118 + */
2119 +static ssize_t regoffset_show( struct device *_dev,
2120 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2121 + struct device_attribute *attr,
2122 +#endif
2123 + char *buf)
2124 +{
2125 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2126 + return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
2127 +}
2128 +
2129 +/**
2130 + * Set the register offset for the next Register Access Read/Write
2131 + */
2132 +static ssize_t regoffset_store( struct device *_dev,
2133 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2134 + struct device_attribute *attr,
2135 +#endif
2136 + const char *buf,
2137 + size_t count )
2138 +{
2139 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2140 +
2141 + uint32_t offset = simple_strtoul(buf, NULL, 16);
2142 + //dev_dbg(_dev, "Offset=0x%08x\n", offset);
2143 + if (offset < 0x00040000 ) {
2144 + otg_dev->reg_offset = offset;
2145 + }
2146 + else {
2147 + dev_err( _dev, "invalid offset\n" );
2148 + }
2149 +
2150 + return count;
2151 +}
2152 +DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store);
2153 +
2154 +
2155 +/**
2156 + * Show the value of the register at the offset in the reg_offset
2157 + * attribute.
2158 + */
2159 +static ssize_t regvalue_show( struct device *_dev,
2160 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2161 + struct device_attribute *attr,
2162 +#endif
2163 + char *buf)
2164 +{
2165 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2166 +
2167 + uint32_t val;
2168 + volatile uint32_t *addr;
2169 +
2170 + if (otg_dev->reg_offset != 0xFFFFFFFF &&
2171 + 0 != otg_dev->base) {
2172 + /* Calculate the address */
2173 + addr = (uint32_t*)(otg_dev->reg_offset +
2174 + (uint8_t*)otg_dev->base);
2175 + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
2176 + val = dwc_read_reg32( addr );
2177 + return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
2178 + "Reg@0x%06x = 0x%08x\n",
2179 + otg_dev->reg_offset, val);
2180 + }
2181 + else {
2182 + dev_err(_dev, "Invalid offset (0x%0x)\n",
2183 + otg_dev->reg_offset);
2184 + return sprintf(buf, "invalid offset\n" );
2185 + }
2186 +}
2187 +
2188 +/**
2189 + * Store the value in the register at the offset in the reg_offset
2190 + * attribute.
2191 + *
2192 + */
2193 +static ssize_t regvalue_store( struct device *_dev,
2194 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2195 + struct device_attribute *attr,
2196 +#endif
2197 + const char *buf,
2198 + size_t count )
2199 +{
2200 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2201 +
2202 + volatile uint32_t * addr;
2203 + uint32_t val = simple_strtoul(buf, NULL, 16);
2204 + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
2205 + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
2206 + /* Calculate the address */
2207 + addr = (uint32_t*)(otg_dev->reg_offset +
2208 + (uint8_t*)otg_dev->base);
2209 + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
2210 + dwc_write_reg32( addr, val );
2211 + }
2212 + else {
2213 + dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
2214 + otg_dev->reg_offset);
2215 + }
2216 + return count;
2217 +}
2218 +DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
2219 +
2220 +/*
2221 + * Attributes
2222 + */
2223 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
2224 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
2225 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
2226 +
2227 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
2228 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
2229 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
2230 +
2231 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
2232 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
2233 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
2234 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
2235 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
2236 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
2237 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
2238 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
2239 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
2240 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
2241 +
2242 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
2243 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
2244 +
2245 +
2246 +/**
2247 + * @todo Add code to initiate the HNP.
2248 + */
2249 +/**
2250 + * Show the HNP status bit
2251 + */
2252 +static ssize_t hnp_show( struct device *_dev,
2253 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2254 + struct device_attribute *attr,
2255 +#endif
2256 + char *buf)
2257 +{
2258 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2259 +
2260 + gotgctl_data_t val;
2261 + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
2262 + return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
2263 +}
2264 +
2265 +/**
2266 + * Set the HNP Request bit
2267 + */
2268 +static ssize_t hnp_store( struct device *_dev,
2269 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2270 + struct device_attribute *attr,
2271 +#endif
2272 + const char *buf,
2273 + size_t count )
2274 +{
2275 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2276 +
2277 + uint32_t in = simple_strtoul(buf, NULL, 16);
2278 + uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
2279 + gotgctl_data_t mem;
2280 + mem.d32 = dwc_read_reg32(addr);
2281 + mem.b.hnpreq = in;
2282 + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
2283 + dwc_write_reg32(addr, mem.d32);
2284 + return count;
2285 +}
2286 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
2287 +
2288 +/**
2289 + * @todo Add code to initiate the SRP.
2290 + */
2291 +/**
2292 + * Show the SRP status bit
2293 + */
2294 +static ssize_t srp_show( struct device *_dev,
2295 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2296 + struct device_attribute *attr,
2297 +#endif
2298 + char *buf)
2299 +{
2300 +#ifndef DWC_HOST_ONLY
2301 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2302 +
2303 + gotgctl_data_t val;
2304 + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
2305 + return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
2306 +#else
2307 + return sprintf(buf, "Host Only Mode!\n");
2308 +#endif
2309 +}
2310 +
2311 +
2312 +
2313 +/**
2314 + * Set the SRP Request bit
2315 + */
2316 +static ssize_t srp_store( struct device *_dev,
2317 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2318 + struct device_attribute *attr,
2319 +#endif
2320 + const char *buf,
2321 + size_t count )
2322 +{
2323 +#ifndef DWC_HOST_ONLY
2324 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2325 +
2326 + dwc_otg_pcd_initiate_srp(otg_dev->pcd);
2327 +#endif
2328 + return count;
2329 +}
2330 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
2331 +
2332 +/**
2333 + * @todo Need to do more for power on/off?
2334 + */
2335 +/**
2336 + * Show the Bus Power status
2337 + */
2338 +static ssize_t buspower_show( struct device *_dev,
2339 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2340 + struct device_attribute *attr,
2341 +#endif
2342 + char *buf)
2343 +{
2344 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2345 +
2346 + hprt0_data_t val;
2347 + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
2348 + return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
2349 +}
2350 +
2351 +
2352 +/**
2353 + * Set the Bus Power status
2354 + */
2355 +static ssize_t buspower_store( struct device *_dev,
2356 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2357 + struct device_attribute *attr,
2358 +#endif
2359 + const char *buf,
2360 + size_t count )
2361 +{
2362 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2363 +
2364 + uint32_t on = simple_strtoul(buf, NULL, 16);
2365 + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
2366 + hprt0_data_t mem;
2367 +
2368 + mem.d32 = dwc_read_reg32(addr);
2369 + mem.b.prtpwr = on;
2370 +
2371 + //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
2372 + dwc_write_reg32(addr, mem.d32);
2373 +
2374 + return count;
2375 +}
2376 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
2377 +
2378 +/**
2379 + * @todo Need to do more for suspend?
2380 + */
2381 +/**
2382 + * Show the Bus Suspend status
2383 + */
2384 +static ssize_t bussuspend_show( struct device *_dev,
2385 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2386 + struct device_attribute *attr,
2387 +#endif
2388 + char *buf)
2389 +{
2390 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2391 +
2392 + hprt0_data_t val;
2393 + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
2394 + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
2395 +}
2396 +
2397 +/**
2398 + * Set the Bus Suspend status
2399 + */
2400 +static ssize_t bussuspend_store( struct device *_dev,
2401 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2402 + struct device_attribute *attr,
2403 +#endif
2404 + const char *buf,
2405 + size_t count )
2406 +{
2407 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2408 +
2409 + uint32_t in = simple_strtoul(buf, NULL, 16);
2410 + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
2411 + hprt0_data_t mem;
2412 + mem.d32 = dwc_read_reg32(addr);
2413 + mem.b.prtsusp = in;
2414 + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
2415 + dwc_write_reg32(addr, mem.d32);
2416 + return count;
2417 +}
2418 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
2419 +
2420 +/**
2421 + * Show the status of Remote Wakeup.
2422 + */
2423 +static ssize_t remote_wakeup_show( struct device *_dev,
2424 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2425 + struct device_attribute *attr,
2426 +#endif
2427 + char *buf)
2428 +{
2429 +#ifndef DWC_HOST_ONLY
2430 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2431 +
2432 + dctl_data_t val;
2433 + val.d32 =
2434 + dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
2435 + return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
2436 + val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
2437 +#else
2438 + return sprintf(buf, "Host Only Mode!\n");
2439 +#endif
2440 +}
2441 +/**
2442 + * Initiate a remote wakeup of the host. The Device control register
2443 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
2444 + * flag is set.
2445 + *
2446 + */
2447 +static ssize_t remote_wakeup_store( struct device *_dev,
2448 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2449 + struct device_attribute *attr,
2450 +#endif
2451 + const char *buf,
2452 + size_t count )
2453 +{
2454 +#ifndef DWC_HOST_ONLY
2455 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2456 +
2457 + uint32_t val = simple_strtoul(buf, NULL, 16);
2458 + if (val&1) {
2459 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
2460 + }
2461 + else {
2462 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
2463 + }
2464 +#endif
2465 + return count;
2466 +}
2467 +DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
2468 + remote_wakeup_store);
2469 +
2470 +/**
2471 + * Dump global registers and either host or device registers (depending on the
2472 + * current mode of the core).
2473 + */
2474 +static ssize_t regdump_show( struct device *_dev,
2475 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2476 + struct device_attribute *attr,
2477 +#endif
2478 + char *buf)
2479 +{
2480 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2481 +
2482 + dwc_otg_dump_global_registers( otg_dev->core_if);
2483 + if (dwc_otg_is_host_mode(otg_dev->core_if)) {
2484 + dwc_otg_dump_host_registers( otg_dev->core_if);
2485 + } else {
2486 + dwc_otg_dump_dev_registers( otg_dev->core_if);
2487 +
2488 + }
2489 + return sprintf( buf, "Register Dump\n" );
2490 +}
2491 +
2492 +DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
2493 +
2494 +/**
2495 + * Dump global registers and either host or device registers (depending on the
2496 + * current mode of the core).
2497 + */
2498 +static ssize_t spramdump_show( struct device *_dev,
2499 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2500 + struct device_attribute *attr,
2501 +#endif
2502 + char *buf)
2503 +{
2504 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2505 +
2506 + dwc_otg_dump_spram( otg_dev->core_if);
2507 +
2508 + return sprintf( buf, "SPRAM Dump\n" );
2509 +}
2510 +
2511 +DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
2512 +
2513 +/**
2514 + * Dump the current hcd state.
2515 + */
2516 +static ssize_t hcddump_show( struct device *_dev,
2517 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2518 + struct device_attribute *attr,
2519 +#endif
2520 + char *buf)
2521 +{
2522 +#ifndef DWC_DEVICE_ONLY
2523 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2524 +
2525 + dwc_otg_hcd_dump_state(otg_dev->hcd);
2526 +#endif
2527 + return sprintf( buf, "HCD Dump\n" );
2528 +}
2529 +
2530 +DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
2531 +
2532 +/**
2533 + * Dump the average frame remaining at SOF. This can be used to
2534 + * determine average interrupt latency. Frame remaining is also shown for
2535 + * start transfer and two additional sample points.
2536 + */
2537 +static ssize_t hcd_frrem_show( struct device *_dev,
2538 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2539 + struct device_attribute *attr,
2540 +#endif
2541 + char *buf)
2542 +{
2543 +#ifndef DWC_DEVICE_ONLY
2544 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2545 +
2546 + dwc_otg_hcd_dump_frrem(otg_dev->hcd);
2547 +#endif
2548 + return sprintf( buf, "HCD Dump Frame Remaining\n" );
2549 +}
2550 +
2551 +DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
2552 +
2553 +/**
2554 + * Displays the time required to read the GNPTXFSIZ register many times (the
2555 + * output shows the number of times the register is read).
2556 + */
2557 +#define RW_REG_COUNT 10000000
2558 +#define MSEC_PER_JIFFIE 1000/HZ
2559 +static ssize_t rd_reg_test_show( struct device *_dev,
2560 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2561 + struct device_attribute *attr,
2562 +#endif
2563 + char *buf)
2564 +{
2565 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2566 +
2567 + int i;
2568 + int time;
2569 + int start_jiffies;
2570 +
2571 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
2572 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
2573 + start_jiffies = jiffies;
2574 + for (i = 0; i < RW_REG_COUNT; i++) {
2575 + dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
2576 + }
2577 + time = jiffies - start_jiffies;
2578 + return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
2579 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
2580 +}
2581 +
2582 +DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
2583 +
2584 +/**
2585 + * Displays the time required to write the GNPTXFSIZ register many times (the
2586 + * output shows the number of times the register is written).
2587 + */
2588 +static ssize_t wr_reg_test_show( struct device *_dev,
2589 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2590 + struct device_attribute *attr,
2591 +#endif
2592 + char *buf)
2593 +{
2594 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
2595 +
2596 + uint32_t reg_val;
2597 + int i;
2598 + int time;
2599 + int start_jiffies;
2600 +
2601 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
2602 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
2603 + reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
2604 + start_jiffies = jiffies;
2605 + for (i = 0; i < RW_REG_COUNT; i++) {
2606 + dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
2607 + }
2608 + time = jiffies - start_jiffies;
2609 + return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
2610 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
2611 +}
2612 +
2613 +DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
2614 +/**@}*/
2615 +
2616 +/**
2617 + * Create the device files
2618 + */
2619 +void dwc_otg_attr_create (struct device *dev)
2620 +{
2621 + int error;
2622 +
2623 + error = device_create_file(dev, &dev_attr_regoffset);
2624 + error = device_create_file(dev, &dev_attr_regvalue);
2625 + error = device_create_file(dev, &dev_attr_mode);
2626 + error = device_create_file(dev, &dev_attr_hnpcapable);
2627 + error = device_create_file(dev, &dev_attr_srpcapable);
2628 + error = device_create_file(dev, &dev_attr_hnp);
2629 + error = device_create_file(dev, &dev_attr_srp);
2630 + error = device_create_file(dev, &dev_attr_buspower);
2631 + error = device_create_file(dev, &dev_attr_bussuspend);
2632 + error = device_create_file(dev, &dev_attr_busconnected);
2633 + error = device_create_file(dev, &dev_attr_gotgctl);
2634 + error = device_create_file(dev, &dev_attr_gusbcfg);
2635 + error = device_create_file(dev, &dev_attr_grxfsiz);
2636 + error = device_create_file(dev, &dev_attr_gnptxfsiz);
2637 + error = device_create_file(dev, &dev_attr_gpvndctl);
2638 + error = device_create_file(dev, &dev_attr_ggpio);
2639 + error = device_create_file(dev, &dev_attr_guid);
2640 + error = device_create_file(dev, &dev_attr_gsnpsid);
2641 + error = device_create_file(dev, &dev_attr_devspeed);
2642 + error = device_create_file(dev, &dev_attr_enumspeed);
2643 + error = device_create_file(dev, &dev_attr_hptxfsiz);
2644 + error = device_create_file(dev, &dev_attr_hprt0);
2645 + error = device_create_file(dev, &dev_attr_remote_wakeup);
2646 + error = device_create_file(dev, &dev_attr_regdump);
2647 + error = device_create_file(dev, &dev_attr_spramdump);
2648 + error = device_create_file(dev, &dev_attr_hcddump);
2649 + error = device_create_file(dev, &dev_attr_hcd_frrem);
2650 + error = device_create_file(dev, &dev_attr_rd_reg_test);
2651 + error = device_create_file(dev, &dev_attr_wr_reg_test);
2652 +}
2653 +
2654 +/**
2655 + * Remove the device files
2656 + */
2657 +void dwc_otg_attr_remove (struct device *dev)
2658 +{
2659 + device_remove_file(dev, &dev_attr_regoffset);
2660 + device_remove_file(dev, &dev_attr_regvalue);
2661 + device_remove_file(dev, &dev_attr_mode);
2662 + device_remove_file(dev, &dev_attr_hnpcapable);
2663 + device_remove_file(dev, &dev_attr_srpcapable);
2664 + device_remove_file(dev, &dev_attr_hnp);
2665 + device_remove_file(dev, &dev_attr_srp);
2666 + device_remove_file(dev, &dev_attr_buspower);
2667 + device_remove_file(dev, &dev_attr_bussuspend);
2668 + device_remove_file(dev, &dev_attr_busconnected);
2669 + device_remove_file(dev, &dev_attr_gotgctl);
2670 + device_remove_file(dev, &dev_attr_gusbcfg);
2671 + device_remove_file(dev, &dev_attr_grxfsiz);
2672 + device_remove_file(dev, &dev_attr_gnptxfsiz);
2673 + device_remove_file(dev, &dev_attr_gpvndctl);
2674 + device_remove_file(dev, &dev_attr_ggpio);
2675 + device_remove_file(dev, &dev_attr_guid);
2676 + device_remove_file(dev, &dev_attr_gsnpsid);
2677 + device_remove_file(dev, &dev_attr_devspeed);
2678 + device_remove_file(dev, &dev_attr_enumspeed);
2679 + device_remove_file(dev, &dev_attr_hptxfsiz);
2680 + device_remove_file(dev, &dev_attr_hprt0);
2681 + device_remove_file(dev, &dev_attr_remote_wakeup);
2682 + device_remove_file(dev, &dev_attr_regdump);
2683 + device_remove_file(dev, &dev_attr_spramdump);
2684 + device_remove_file(dev, &dev_attr_hcddump);
2685 + device_remove_file(dev, &dev_attr_hcd_frrem);
2686 + device_remove_file(dev, &dev_attr_rd_reg_test);
2687 + device_remove_file(dev, &dev_attr_wr_reg_test);
2688 +}
2689 diff --git a/drivers/usb/dwc_otg/dwc_otg_attr.h b/drivers/usb/dwc_otg/dwc_otg_attr.h
2690 new file mode 100644
2691 index 0000000..0862b27
2692 --- /dev/null
2693 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
2694 @@ -0,0 +1,67 @@
2695 +/* ==========================================================================
2696 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
2697 + * $Revision: 1.2 $
2698 + * $Date: 2008-11-21 05:39:15 $
2699 + * $Change: 477051 $
2700 + *
2701 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
2702 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
2703 + * otherwise expressly agreed to in writing between Synopsys and you.
2704 + *
2705 + * The Software IS NOT an item of Licensed Software or Licensed Product under
2706 + * any End User Software License Agreement or Agreement for Licensed Product
2707 + * with Synopsys or any supplement thereto. You are permitted to use and
2708 + * redistribute this Software in source and binary forms, with or without
2709 + * modification, provided that redistributions of source code must retain this
2710 + * notice. You may not view, use, disclose, copy or distribute this file or
2711 + * any information contained herein except pursuant to this license grant from
2712 + * Synopsys. If you do not agree with this notice, including the disclaimer
2713 + * below, then you are not authorized to use the Software.
2714 + *
2715 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
2716 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2717 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2718 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
2719 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2720 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
2721 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
2722 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2723 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2724 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
2725 + * DAMAGE.
2726 + * ========================================================================== */
2727 +
2728 +#if !defined(__DWC_OTG_ATTR_H__)
2729 +#define __DWC_OTG_ATTR_H__
2730 +
2731 +/** @file
2732 + * This file contains the interface to the Linux device attributes.
2733 + */
2734 +extern struct device_attribute dev_attr_regoffset;
2735 +extern struct device_attribute dev_attr_regvalue;
2736 +
2737 +extern struct device_attribute dev_attr_mode;
2738 +extern struct device_attribute dev_attr_hnpcapable;
2739 +extern struct device_attribute dev_attr_srpcapable;
2740 +extern struct device_attribute dev_attr_hnp;
2741 +extern struct device_attribute dev_attr_srp;
2742 +extern struct device_attribute dev_attr_buspower;
2743 +extern struct device_attribute dev_attr_bussuspend;
2744 +extern struct device_attribute dev_attr_busconnected;
2745 +extern struct device_attribute dev_attr_gotgctl;
2746 +extern struct device_attribute dev_attr_gusbcfg;
2747 +extern struct device_attribute dev_attr_grxfsiz;
2748 +extern struct device_attribute dev_attr_gnptxfsiz;
2749 +extern struct device_attribute dev_attr_gpvndctl;
2750 +extern struct device_attribute dev_attr_ggpio;
2751 +extern struct device_attribute dev_attr_guid;
2752 +extern struct device_attribute dev_attr_gsnpsid;
2753 +extern struct device_attribute dev_attr_devspeed;
2754 +extern struct device_attribute dev_attr_enumspeed;
2755 +extern struct device_attribute dev_attr_hptxfsiz;
2756 +extern struct device_attribute dev_attr_hprt0;
2757 +
2758 +void dwc_otg_attr_create (struct device *dev);
2759 +void dwc_otg_attr_remove (struct device *dev);
2760 +
2761 +#endif
2762 diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.c b/drivers/usb/dwc_otg/dwc_otg_cil.c
2763 new file mode 100644
2764 index 0000000..89aa83e
2765 --- /dev/null
2766 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
2767 @@ -0,0 +1,3692 @@
2768 +/* ==========================================================================
2769 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
2770 + * $Revision: 1.7 $
2771 + * $Date: 2008-12-22 11:43:05 $
2772 + * $Change: 1117667 $
2773 + *
2774 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
2775 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
2776 + * otherwise expressly agreed to in writing between Synopsys and you.
2777 + *
2778 + * The Software IS NOT an item of Licensed Software or Licensed Product under
2779 + * any End User Software License Agreement or Agreement for Licensed Product
2780 + * with Synopsys or any supplement thereto. You are permitted to use and
2781 + * redistribute this Software in source and binary forms, with or without
2782 + * modification, provided that redistributions of source code must retain this
2783 + * notice. You may not view, use, disclose, copy or distribute this file or
2784 + * any information contained herein except pursuant to this license grant from
2785 + * Synopsys. If you do not agree with this notice, including the disclaimer
2786 + * below, then you are not authorized to use the Software.
2787 + *
2788 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
2789 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2790 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2791 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
2792 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2793 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
2794 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
2795 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2796 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2797 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
2798 + * DAMAGE.
2799 + * ========================================================================== */
2800 +
2801 +/** @file
2802 + *
2803 + * The Core Interface Layer provides basic services for accessing and
2804 + * managing the DWC_otg hardware. These services are used by both the
2805 + * Host Controller Driver and the Peripheral Controller Driver.
2806 + *
2807 + * The CIL manages the memory map for the core so that the HCD and PCD
2808 + * don't have to do this separately. It also handles basic tasks like
2809 + * reading/writing the registers and data FIFOs in the controller.
2810 + * Some of the data access functions provide encapsulation of several
2811 + * operations required to perform a task, such as writing multiple
2812 + * registers to start a transfer. Finally, the CIL performs basic
2813 + * services that are not specific to either the host or device modes
2814 + * of operation. These services include management of the OTG Host
2815 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
2816 + * Diagnostic API is also provided to allow testing of the controller
2817 + * hardware.
2818 + *
2819 + * The Core Interface Layer has the following requirements:
2820 + * - Provides basic controller operations.
2821 + * - Minimal use of OS services.
2822 + * - The OS services used will be abstracted by using inline functions
2823 + * or macros.
2824 + *
2825 + */
2826 +#include <asm/unaligned.h>
2827 +#include <linux/dma-mapping.h>
2828 +#ifdef DEBUG
2829 +#include <linux/jiffies.h>
2830 +#endif
2831 +
2832 +#include "linux/dwc_otg_plat.h"
2833 +#include "dwc_otg_regs.h"
2834 +#include "dwc_otg_cil.h"
2835 +
2836 +/* Included only to access hc->qh for non-dword buffer handling
2837 + * TODO: account it
2838 + */
2839 +#include "dwc_otg_hcd.h"
2840 +
2841 +/**
2842 + * This function is called to initialize the DWC_otg CSR data
2843 + * structures. The register addresses in the device and host
2844 + * structures are initialized from the base address supplied by the
2845 + * caller. The calling function must make the OS calls to get the
2846 + * base address of the DWC_otg controller registers. The core_params
2847 + * argument holds the parameters that specify how the core should be
2848 + * configured.
2849 + *
2850 + * @param[in] reg_base_addr Base address of DWC_otg core registers
2851 + * @param[in] core_params Pointer to the core configuration parameters
2852 + *
2853 + */
2854 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr,
2855 + dwc_otg_core_params_t *core_params)
2856 +{
2857 + dwc_otg_core_if_t *core_if = 0;
2858 + dwc_otg_dev_if_t *dev_if = 0;
2859 + dwc_otg_host_if_t *host_if = 0;
2860 + uint8_t *reg_base = (uint8_t *)reg_base_addr;
2861 + int i = 0;
2862 +
2863 + DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params);
2864 +
2865 + core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL);
2866 +
2867 + if (core_if == 0) {
2868 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
2869 + return 0;
2870 + }
2871 +
2872 + memset(core_if, 0, sizeof(dwc_otg_core_if_t));
2873 +
2874 + core_if->core_params = core_params;
2875 + core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
2876 +
2877 + /*
2878 + * Allocate the Device Mode structures.
2879 + */
2880 + dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
2881 +
2882 + if (dev_if == 0) {
2883 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
2884 + kfree(core_if);
2885 + return 0;
2886 + }
2887 +
2888 + dev_if->dev_global_regs =
2889 + (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
2890 +
2891 + for (i=0; i<MAX_EPS_CHANNELS; i++)
2892 + {
2893 + dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
2894 + (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
2895 + (i * DWC_EP_REG_OFFSET));
2896 +
2897 + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
2898 + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
2899 + (i * DWC_EP_REG_OFFSET));
2900 + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
2901 + i, &dev_if->in_ep_regs[i]->diepctl);
2902 + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
2903 + i, &dev_if->out_ep_regs[i]->doepctl);
2904 + }
2905 +
2906 + dev_if->speed = 0; // unknown
2907 +
2908 + core_if->dev_if = dev_if;
2909 +
2910 + /*
2911 + * Allocate the Host Mode structures.
2912 + */
2913 + host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL);
2914 +
2915 + if (host_if == 0) {
2916 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
2917 + kfree(dev_if);
2918 + kfree(core_if);
2919 + return 0;
2920 + }
2921 +
2922 + host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
2923 + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
2924 +
2925 + host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
2926 +
2927 + for (i=0; i<MAX_EPS_CHANNELS; i++)
2928 + {
2929 + host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
2930 + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
2931 + (i * DWC_OTG_CHAN_REGS_OFFSET));
2932 + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
2933 + i, &host_if->hc_regs[i]->hcchar);
2934 + }
2935 +
2936 + host_if->num_host_channels = MAX_EPS_CHANNELS;
2937 + core_if->host_if = host_if;
2938 +
2939 + for (i=0; i<MAX_EPS_CHANNELS; i++)
2940 + {
2941 + core_if->data_fifo[i] =
2942 + (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
2943 + (i * DWC_OTG_DATA_FIFO_SIZE));
2944 + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
2945 + i, (unsigned)core_if->data_fifo[i]);
2946 + }
2947 +
2948 + core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
2949 +
2950 + /*
2951 + * Store the contents of the hardware configuration registers here for
2952 + * easy access later.
2953 + */
2954 + core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
2955 + core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
2956 + core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
2957 + core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
2958 +
2959 + DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
2960 + DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
2961 + DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
2962 + DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
2963 +
2964 + core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
2965 + core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
2966 +
2967 + DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32);
2968 + DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32);
2969 +
2970 + DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
2971 + DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
2972 + DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
2973 + DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
2974 + DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
2975 + DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
2976 + DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
2977 +
2978 + DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
2979 + DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
2980 +
2981 + /*
2982 + * Set the SRP sucess bit for FS-I2c
2983 + */
2984 + core_if->srp_success = 0;
2985 + core_if->srp_timer_started = 0;
2986 +
2987 +
2988 + /*
2989 + * Create new workqueue and init works
2990 + */
2991 + core_if->wq_otg = create_singlethread_workqueue("dwc_otg");
2992 + if(core_if->wq_otg == 0) {
2993 + DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n");
2994 + kfree(host_if);
2995 + kfree(dev_if);
2996 + kfree(core_if);
2997 + return 0 * HZ;
2998 + }
2999 +
3000 +
3001 +
3002 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
3003 +
3004 + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
3005 + INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
3006 +
3007 +#else
3008 +
3009 + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
3010 + INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
3011 +
3012 +#endif
3013 + return core_if;
3014 +}
3015 +
3016 +/**
3017 + * This function frees the structures allocated by dwc_otg_cil_init().
3018 + *
3019 + * @param[in] core_if The core interface pointer returned from
3020 + * dwc_otg_cil_init().
3021 + *
3022 + */
3023 +void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
3024 +{
3025 + /* Disable all interrupts */
3026 + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
3027 + dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
3028 +
3029 + if (core_if->wq_otg) {
3030 + destroy_workqueue(core_if->wq_otg);
3031 + }
3032 + if (core_if->dev_if) {
3033 + kfree(core_if->dev_if);
3034 + }
3035 + if (core_if->host_if) {
3036 + kfree(core_if->host_if);
3037 + }
3038 + kfree(core_if);
3039 +}
3040 +
3041 +/**
3042 + * This function enables the controller's Global Interrupt in the AHB Config
3043 + * register.
3044 + *
3045 + * @param[in] core_if Programming view of DWC_otg controller.
3046 + */
3047 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
3048 +{
3049 + gahbcfg_data_t ahbcfg = { .d32 = 0};
3050 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
3051 + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
3052 +}
3053 +
3054 +/**
3055 + * This function disables the controller's Global Interrupt in the AHB Config
3056 + * register.
3057 + *
3058 + * @param[in] core_if Programming view of DWC_otg controller.
3059 + */
3060 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
3061 +{
3062 + gahbcfg_data_t ahbcfg = { .d32 = 0};
3063 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
3064 + dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
3065 +}
3066 +
3067 +/**
3068 + * This function initializes the commmon interrupts, used in both
3069 + * device and host modes.
3070 + *
3071 + * @param[in] core_if Programming view of the DWC_otg controller
3072 + *
3073 + */
3074 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
3075 +{
3076 + dwc_otg_core_global_regs_t *global_regs =
3077 + core_if->core_global_regs;
3078 + gintmsk_data_t intr_mask = { .d32 = 0};
3079 +
3080 + /* Clear any pending OTG Interrupts */
3081 + dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
3082 +
3083 + /* Clear any pending interrupts */
3084 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
3085 +
3086 + /*
3087 + * Enable the interrupts in the GINTMSK.
3088 + */
3089 + intr_mask.b.modemismatch = 1;
3090 + intr_mask.b.otgintr = 1;
3091 +
3092 + if (!core_if->dma_enable) {
3093 + intr_mask.b.rxstsqlvl = 1;
3094 + }
3095 +
3096 + intr_mask.b.conidstschng = 1;
3097 + intr_mask.b.wkupintr = 1;
3098 + intr_mask.b.disconnect = 1;
3099 + intr_mask.b.usbsuspend = 1;
3100 + intr_mask.b.sessreqintr = 1;
3101 + dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
3102 +}
3103 +
3104 +/**
3105 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
3106 + * type.
3107 + */
3108 +static void init_fslspclksel(dwc_otg_core_if_t *core_if)
3109 +{
3110 + uint32_t val;
3111 + hcfg_data_t hcfg;
3112 +
3113 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
3114 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
3115 + (core_if->core_params->ulpi_fs_ls)) ||
3116 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
3117 + /* Full speed PHY */
3118 + val = DWC_HCFG_48_MHZ;
3119 + }
3120 + else {
3121 + /* High speed PHY running at full speed or high speed */
3122 + val = DWC_HCFG_30_60_MHZ;
3123 + }
3124 +
3125 + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
3126 + hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
3127 + hcfg.b.fslspclksel = val;
3128 + dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
3129 +}
3130 +
3131 +/**
3132 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
3133 + * and the enumeration speed of the device.
3134 + */
3135 +static void init_devspd(dwc_otg_core_if_t *core_if)
3136 +{
3137 + uint32_t val;
3138 + dcfg_data_t dcfg;
3139 +
3140 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
3141 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
3142 + (core_if->core_params->ulpi_fs_ls)) ||
3143 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
3144 + /* Full speed PHY */
3145 + val = 0x3;
3146 + }
3147 + else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
3148 + /* High speed PHY running at full speed */
3149 + val = 0x1;
3150 + }
3151 + else {
3152 + /* High speed PHY running at high speed */
3153 + val = 0x0;
3154 + }
3155 +
3156 + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
3157 +
3158 + dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
3159 + dcfg.b.devspd = val;
3160 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
3161 +}
3162 +
3163 +/**
3164 + * This function calculates the number of IN EPS
3165 + * using GHWCFG1 and GHWCFG2 registers values
3166 + *
3167 + * @param core_if Programming view of the DWC_otg controller
3168 + */
3169 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
3170 +{
3171 + uint32_t num_in_eps = 0;
3172 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
3173 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
3174 + uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
3175 + int i;
3176 +
3177 +
3178 + for(i = 0; i < num_eps; ++i)
3179 + {
3180 + if(!(hwcfg1 & 0x1))
3181 + num_in_eps++;
3182 +
3183 + hwcfg1 >>= 2;
3184 + }
3185 +
3186 + if(core_if->hwcfg4.b.ded_fifo_en) {
3187 + num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
3188 + }
3189 +
3190 + return num_in_eps;
3191 +}
3192 +
3193 +
3194 +/**
3195 + * This function calculates the number of OUT EPS
3196 + * using GHWCFG1 and GHWCFG2 registers values
3197 + *
3198 + * @param core_if Programming view of the DWC_otg controller
3199 + */
3200 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
3201 +{
3202 + uint32_t num_out_eps = 0;
3203 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
3204 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
3205 + int i;
3206 +
3207 + for(i = 0; i < num_eps; ++i)
3208 + {
3209 + if(!(hwcfg1 & 0x2))
3210 + num_out_eps++;
3211 +
3212 + hwcfg1 >>= 2;
3213 + }
3214 + return num_out_eps;
3215 +}
3216 +/**
3217 + * This function initializes the DWC_otg controller registers and
3218 + * prepares the core for device mode or host mode operation.
3219 + *
3220 + * @param core_if Programming view of the DWC_otg controller
3221 + *
3222 + */
3223 +void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
3224 +{
3225 + int i = 0;
3226 + dwc_otg_core_global_regs_t *global_regs =
3227 + core_if->core_global_regs;
3228 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3229 + gahbcfg_data_t ahbcfg = { .d32 = 0 };
3230 + gusbcfg_data_t usbcfg = { .d32 = 0 };
3231 + gi2cctl_data_t i2cctl = { .d32 = 0 };
3232 +
3233 + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
3234 +
3235 + /* Common Initialization */
3236 +
3237 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3238 +
3239 +// usbcfg.b.tx_end_delay = 1;
3240 + /* Program the ULPI External VBUS bit if needed */
3241 + usbcfg.b.ulpi_ext_vbus_drv =
3242 + (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
3243 +
3244 + /* Set external TS Dline pulsing */
3245 + usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0;
3246 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
3247 +
3248 +
3249 + /* Reset the Controller */
3250 + dwc_otg_core_reset(core_if);
3251 +
3252 + /* Initialize parameters from Hardware configuration registers. */
3253 + dev_if->num_in_eps = calc_num_in_eps(core_if);
3254 + dev_if->num_out_eps = calc_num_out_eps(core_if);
3255 +
3256 +
3257 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep);
3258 +
3259 + for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
3260 + {
3261 + dev_if->perio_tx_fifo_size[i] =
3262 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
3263 + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
3264 + i, dev_if->perio_tx_fifo_size[i]);
3265 + }
3266 +
3267 + for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++)
3268 + {
3269 + dev_if->tx_fifo_size[i] =
3270 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
3271 + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
3272 + i, dev_if->perio_tx_fifo_size[i]);
3273 + }
3274 +
3275 + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
3276 + core_if->rx_fifo_size =
3277 + dwc_read_reg32(&global_regs->grxfsiz);
3278 + core_if->nperio_tx_fifo_size =
3279 + dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
3280 +
3281 + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
3282 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
3283 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size);
3284 +
3285 + /* This programming sequence needs to happen in FS mode before any other
3286 + * programming occurs */
3287 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
3288 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
3289 + /* If FS mode with FS PHY */
3290 +
3291 + /* core_init() is now called on every switch so only call the
3292 + * following for the first time through. */
3293 + if (!core_if->phy_init_done) {
3294 + core_if->phy_init_done = 1;
3295 + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
3296 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3297 + usbcfg.b.physel = 1;
3298 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
3299 +
3300 + /* Reset after a PHY select */
3301 + dwc_otg_core_reset(core_if);
3302 + }
3303 +
3304 + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
3305 + * do this on HNP Dev/Host mode switches (done in dev_init and
3306 + * host_init). */
3307 + if (dwc_otg_is_host_mode(core_if)) {
3308 + init_fslspclksel(core_if);
3309 + }
3310 + else {
3311 + init_devspd(core_if);
3312 + }
3313 +
3314 + if (core_if->core_params->i2c_enable) {
3315 + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
3316 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
3317 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3318 + usbcfg.b.otgutmifssel = 1;
3319 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
3320 +
3321 + /* Program GI2CCTL.I2CEn */
3322 + i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
3323 + i2cctl.b.i2cdevaddr = 1;
3324 + i2cctl.b.i2cen = 0;
3325 + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
3326 + i2cctl.b.i2cen = 1;
3327 + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
3328 + }
3329 +
3330 + } /* endif speed == DWC_SPEED_PARAM_FULL */
3331 +
3332 + else {
3333 + /* High speed PHY. */
3334 + if (!core_if->phy_init_done) {
3335 + core_if->phy_init_done = 1;
3336 + /* HS PHY parameters. These parameters are preserved
3337 + * during soft reset so only program the first time. Do
3338 + * a soft reset immediately after setting phyif. */
3339 + usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
3340 + if (usbcfg.b.ulpi_utmi_sel == 1) {
3341 + /* ULPI interface */
3342 + usbcfg.b.phyif = 0;
3343 + usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr;
3344 + }
3345 + else {
3346 + /* UTMI+ interface */
3347 + if (core_if->core_params->phy_utmi_width == 16) {
3348 + usbcfg.b.phyif = 1;
3349 + }
3350 + else {
3351 + usbcfg.b.phyif = 0;
3352 + }
3353 + }
3354 +
3355 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3356 +
3357 + /* Reset after setting the PHY parameters */
3358 + dwc_otg_core_reset(core_if);
3359 + }
3360 + }
3361 +
3362 + if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
3363 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
3364 + (core_if->core_params->ulpi_fs_ls)) {
3365 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
3366 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3367 + usbcfg.b.ulpi_fsls = 1;
3368 + usbcfg.b.ulpi_clk_sus_m = 1;
3369 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3370 + }
3371 + else {
3372 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3373 + usbcfg.b.ulpi_fsls = 0;
3374 + usbcfg.b.ulpi_clk_sus_m = 0;
3375 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3376 + }
3377 +
3378 + /* Program the GAHBCFG Register.*/
3379 + switch (core_if->hwcfg2.b.architecture) {
3380 +
3381 + case DWC_SLAVE_ONLY_ARCH:
3382 + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
3383 + ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
3384 + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
3385 + core_if->dma_enable = 0;
3386 + core_if->dma_desc_enable = 0;
3387 + break;
3388 +
3389 + case DWC_EXT_DMA_ARCH:
3390 + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
3391 + ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size;
3392 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
3393 + core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
3394 + break;
3395 +
3396 + case DWC_INT_DMA_ARCH:
3397 + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
3398 + ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
3399 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
3400 + core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
3401 + break;
3402 +
3403 + }
3404 + ahbcfg.b.dmaenable = core_if->dma_enable;
3405 + dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
3406 +
3407 + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
3408 +
3409 + core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
3410 + core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
3411 + DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled"));
3412 + DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled"));
3413 +
3414 + /*
3415 + * Program the GUSBCFG register.
3416 + */
3417 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
3418 +
3419 + switch (core_if->hwcfg2.b.op_mode) {
3420 + case DWC_MODE_HNP_SRP_CAPABLE:
3421 + usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
3422 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
3423 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3424 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3425 + break;
3426 +
3427 + case DWC_MODE_SRP_ONLY_CAPABLE:
3428 + usbcfg.b.hnpcap = 0;
3429 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3430 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3431 + break;
3432 +
3433 + case DWC_MODE_NO_HNP_SRP_CAPABLE:
3434 + usbcfg.b.hnpcap = 0;
3435 + usbcfg.b.srpcap = 0;
3436 + break;
3437 +
3438 + case DWC_MODE_SRP_CAPABLE_DEVICE:
3439 + usbcfg.b.hnpcap = 0;
3440 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3441 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3442 + break;
3443 +
3444 + case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
3445 + usbcfg.b.hnpcap = 0;
3446 + usbcfg.b.srpcap = 0;
3447 + break;
3448 +
3449 + case DWC_MODE_SRP_CAPABLE_HOST:
3450 + usbcfg.b.hnpcap = 0;
3451 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
3452 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
3453 + break;
3454 +
3455 + case DWC_MODE_NO_SRP_CAPABLE_HOST:
3456 + usbcfg.b.hnpcap = 0;
3457 + usbcfg.b.srpcap = 0;
3458 + break;
3459 + }
3460 +
3461 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
3462 +
3463 + /* Enable common interrupts */
3464 + dwc_otg_enable_common_interrupts(core_if);
3465 +
3466 + /* Do device or host intialization based on mode during PCD
3467 + * and HCD initialization */
3468 + if (dwc_otg_is_host_mode(core_if)) {
3469 + DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
3470 + core_if->op_state = A_HOST;
3471 + }
3472 + else {
3473 + DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
3474 + core_if->op_state = B_PERIPHERAL;
3475 +#ifdef DWC_DEVICE_ONLY
3476 + dwc_otg_core_dev_init(core_if);
3477 +#endif
3478 + }
3479 +}
3480 +
3481 +
3482 +/**
3483 + * This function enables the Device mode interrupts.
3484 + *
3485 + * @param core_if Programming view of DWC_otg controller
3486 + */
3487 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
3488 +{
3489 + gintmsk_data_t intr_mask = { .d32 = 0};
3490 + dwc_otg_core_global_regs_t *global_regs =
3491 + core_if->core_global_regs;
3492 +
3493 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
3494 +
3495 + /* Disable all interrupts. */
3496 + dwc_write_reg32(&global_regs->gintmsk, 0);
3497 +
3498 + /* Clear any pending interrupts */
3499 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
3500 +
3501 + /* Enable the common interrupts */
3502 + dwc_otg_enable_common_interrupts(core_if);
3503 +
3504 + /* Enable interrupts */
3505 + intr_mask.b.usbreset = 1;
3506 + intr_mask.b.enumdone = 1;
3507 +
3508 + if(!core_if->multiproc_int_enable) {
3509 + intr_mask.b.inepintr = 1;
3510 + intr_mask.b.outepintr = 1;
3511 + }
3512 +
3513 + intr_mask.b.erlysuspend = 1;
3514 +
3515 + if(core_if->en_multiple_tx_fifo == 0) {
3516 + intr_mask.b.epmismatch = 1;
3517 + }
3518 +
3519 +
3520 +#ifdef DWC_EN_ISOC
3521 + if(core_if->dma_enable) {
3522 + if(core_if->dma_desc_enable == 0) {
3523 + if(core_if->pti_enh_enable) {
3524 + dctl_data_t dctl = { .d32 = 0 };
3525 + dctl.b.ifrmnum = 1;
3526 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
3527 + } else {
3528 + intr_mask.b.incomplisoin = 1;
3529 + intr_mask.b.incomplisoout = 1;
3530 + }
3531 + }
3532 + } else {
3533 + intr_mask.b.incomplisoin = 1;
3534 + intr_mask.b.incomplisoout = 1;
3535 + }
3536 +#endif // DWC_EN_ISOC
3537 +
3538 +/** @todo NGS: Should this be a module parameter? */
3539 +#ifdef USE_PERIODIC_EP
3540 + intr_mask.b.isooutdrop = 1;
3541 + intr_mask.b.eopframe = 1;
3542 + intr_mask.b.incomplisoin = 1;
3543 + intr_mask.b.incomplisoout = 1;
3544 +#endif
3545 +
3546 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
3547 +
3548 + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
3549 + dwc_read_reg32(&global_regs->gintmsk));
3550 +}
3551 +
3552 +/**
3553 + * This function initializes the DWC_otg controller registers for
3554 + * device mode.
3555 + *
3556 + * @param core_if Programming view of DWC_otg controller
3557 + *
3558 + */
3559 +void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
3560 +{
3561 + int i;
3562 + dwc_otg_core_global_regs_t *global_regs =
3563 + core_if->core_global_regs;
3564 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3565 + dwc_otg_core_params_t *params = core_if->core_params;
3566 + dcfg_data_t dcfg = { .d32 = 0};
3567 + grstctl_t resetctl = { .d32 = 0 };
3568 + uint32_t rx_fifo_size;
3569 + fifosize_data_t nptxfifosize;
3570 + fifosize_data_t txfifosize;
3571 + dthrctl_data_t dthrctl;
3572 + fifosize_data_t ptxfifosize;
3573 +
3574 + /* Restart the Phy Clock */
3575 + dwc_write_reg32(core_if->pcgcctl, 0);
3576 +
3577 + /* Device configuration register */
3578 + init_devspd(core_if);
3579 + dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
3580 + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
3581 + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
3582 +
3583 + dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
3584 +
3585 + /* Configure data FIFO sizes */
3586 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
3587 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size);
3588 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
3589 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
3590 +
3591 + /* Rx FIFO */
3592 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
3593 + dwc_read_reg32(&global_regs->grxfsiz));
3594 +
3595 + rx_fifo_size = params->dev_rx_fifo_size;
3596 + dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
3597 +
3598 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
3599 + dwc_read_reg32(&global_regs->grxfsiz));
3600 +
3601 + /** Set Periodic Tx FIFO Mask all bits 0 */
3602 + core_if->p_tx_msk = 0;
3603 +
3604 + /** Set Tx FIFO Mask all bits 0 */
3605 + core_if->tx_msk = 0;
3606 +
3607 + if(core_if->en_multiple_tx_fifo == 0) {
3608 + /* Non-periodic Tx FIFO */
3609 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
3610 + dwc_read_reg32(&global_regs->gnptxfsiz));
3611 +
3612 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
3613 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
3614 +
3615 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
3616 +
3617 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
3618 + dwc_read_reg32(&global_regs->gnptxfsiz));
3619 +
3620 + /**@todo NGS: Fix Periodic FIFO Sizing! */
3621 + /*
3622 + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
3623 + * Indexes of the FIFO size module parameters in the
3624 + * dev_perio_tx_fifo_size array and the FIFO size registers in
3625 + * the dptxfsiz array run from 0 to 14.
3626 + */
3627 + /** @todo Finish debug of this */
3628 + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
3629 + for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
3630 + {
3631 + ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
3632 + DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
3633 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
3634 + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
3635 + ptxfifosize.d32);
3636 + DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
3637 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
3638 + ptxfifosize.b.startaddr += ptxfifosize.b.depth;
3639 + }
3640 + }
3641 + else {
3642 + /*
3643 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
3644 + * Indexes of the FIFO size module parameters in the
3645 + * dev_tx_fifo_size array and the FIFO size registers in
3646 + * the dptxfsiz_dieptxf array run from 0 to 14.
3647 + */
3648 +
3649 +
3650 + /* Non-periodic Tx FIFO */
3651 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
3652 + dwc_read_reg32(&global_regs->gnptxfsiz));
3653 +
3654 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
3655 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
3656 +
3657 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
3658 +
3659 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
3660 + dwc_read_reg32(&global_regs->gnptxfsiz));
3661 +
3662 + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
3663 + /*
3664 + Modify by kaiker ,for RT3052 device mode config
3665 +
3666 + In RT3052,Since the _core_if->hwcfg4.b.num_dev_perio_in_ep is
3667 + configed to 0 so these TX_FIF0 not config.IN EP will can't
3668 + more than 1 if not modify it.
3669 +
3670 + */
3671 +#if 1
3672 + for (i=1 ; i <= dev_if->num_in_eps; i++)
3673 +#else
3674 + for (i=1; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
3675 +#endif
3676 + {
3677 +
3678 + txfifosize.b.depth = params->dev_tx_fifo_size[i];
3679 +
3680 + DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
3681 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
3682 +
3683 + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i-1],
3684 + txfifosize.d32);
3685 +
3686 + DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
3687 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1]));
3688 +
3689 + txfifosize.b.startaddr += txfifosize.b.depth;
3690 + }
3691 + }
3692 + }
3693 + /* Flush the FIFOs */
3694 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
3695 + dwc_otg_flush_rx_fifo(core_if);
3696 +
3697 + /* Flush the Learning Queue. */
3698 + resetctl.b.intknqflsh = 1;
3699 + dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
3700 +
3701 + /* Clear all pending Device Interrupts */
3702 +
3703 + if(core_if->multiproc_int_enable) {
3704 + }
3705 +
3706 + /** @todo - if the condition needed to be checked
3707 + * or in any case all pending interrutps should be cleared?
3708 + */
3709 + if(core_if->multiproc_int_enable) {
3710 + for(i = 0; i < core_if->dev_if->num_in_eps; ++i) {
3711 + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0);
3712 + }
3713 +
3714 + for(i = 0; i < core_if->dev_if->num_out_eps; ++i) {
3715 + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0);
3716 + }
3717 +
3718 + dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
3719 + dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
3720 + } else {
3721 + dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
3722 + dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
3723 + dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
3724 + dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
3725 + }
3726 +
3727 + for (i=0; i <= dev_if->num_in_eps; i++)
3728 + {
3729 + depctl_data_t depctl;
3730 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
3731 + if (depctl.b.epena) {
3732 + depctl.d32 = 0;
3733 + depctl.b.epdis = 1;
3734 + depctl.b.snak = 1;
3735 + }
3736 + else {
3737 + depctl.d32 = 0;
3738 + }
3739 +
3740 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
3741 +
3742 +
3743 + dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
3744 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
3745 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
3746 + }
3747 +
3748 + for (i=0; i <= dev_if->num_out_eps; i++)
3749 + {
3750 + depctl_data_t depctl;
3751 + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
3752 + if (depctl.b.epena) {
3753 + depctl.d32 = 0;
3754 + depctl.b.epdis = 1;
3755 + depctl.b.snak = 1;
3756 + }
3757 + else {
3758 + depctl.d32 = 0;
3759 + }
3760 +
3761 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
3762 +
3763 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
3764 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
3765 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
3766 + }
3767 +
3768 + if(core_if->en_multiple_tx_fifo && core_if->dma_enable) {
3769 + dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
3770 + dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
3771 + dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
3772 +
3773 + dev_if->rx_thr_length = params->rx_thr_length;
3774 + dev_if->tx_thr_length = params->tx_thr_length;
3775 +
3776 + dev_if->setup_desc_index = 0;
3777 +
3778 + dthrctl.d32 = 0;
3779 + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
3780 + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
3781 + dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
3782 + dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
3783 + dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
3784 +
3785 + dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32);
3786 +
3787 + DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
3788 + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len);
3789 +
3790 + }
3791 +
3792 + dwc_otg_enable_device_interrupts(core_if);
3793 +
3794 + {
3795 + diepmsk_data_t msk = { .d32 = 0 };
3796 + msk.b.txfifoundrn = 1;
3797 + if(core_if->multiproc_int_enable) {
3798 + dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32);
3799 + } else {
3800 + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32);
3801 + }
3802 + }
3803 +
3804 +
3805 + if(core_if->multiproc_int_enable) {
3806 + /* Set NAK on Babble */
3807 + dctl_data_t dctl = { .d32 = 0};
3808 + dctl.b.nakonbble = 1;
3809 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
3810 + }
3811 +}
3812 +
3813 +/**
3814 + * This function enables the Host mode interrupts.
3815 + *
3816 + * @param core_if Programming view of DWC_otg controller
3817 + */
3818 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
3819 +{
3820 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
3821 + gintmsk_data_t intr_mask = { .d32 = 0 };
3822 +
3823 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
3824 +
3825 + /* Disable all interrupts. */
3826 + dwc_write_reg32(&global_regs->gintmsk, 0);
3827 +
3828 + /* Clear any pending interrupts. */
3829 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
3830 +
3831 + /* Enable the common interrupts */
3832 + dwc_otg_enable_common_interrupts(core_if);
3833 +
3834 + /*
3835 + * Enable host mode interrupts without disturbing common
3836 + * interrupts.
3837 + */
3838 + intr_mask.b.sofintr = 1;
3839 + intr_mask.b.portintr = 1;
3840 + intr_mask.b.hcintr = 1;
3841 +
3842 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
3843 +}
3844 +
3845 +/**
3846 + * This function disables the Host Mode interrupts.
3847 + *
3848 + * @param core_if Programming view of DWC_otg controller
3849 + */
3850 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
3851 +{
3852 + dwc_otg_core_global_regs_t *global_regs =
3853 + core_if->core_global_regs;
3854 + gintmsk_data_t intr_mask = { .d32 = 0 };
3855 +
3856 + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
3857 +
3858 + /*
3859 + * Disable host mode interrupts without disturbing common
3860 + * interrupts.
3861 + */
3862 + intr_mask.b.sofintr = 1;
3863 + intr_mask.b.portintr = 1;
3864 + intr_mask.b.hcintr = 1;
3865 + intr_mask.b.ptxfempty = 1;
3866 + intr_mask.b.nptxfempty = 1;
3867 +
3868 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3869 +}
3870 +
3871 +/**
3872 + * This function initializes the DWC_otg controller registers for
3873 + * host mode.
3874 + *
3875 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
3876 + * request queues. Host channels are reset to ensure that they are ready for
3877 + * performing transfers.
3878 + *
3879 + * @param core_if Programming view of DWC_otg controller
3880 + *
3881 + */
3882 +void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
3883 +{
3884 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
3885 + dwc_otg_host_if_t *host_if = core_if->host_if;
3886 + dwc_otg_core_params_t *params = core_if->core_params;
3887 + hprt0_data_t hprt0 = { .d32 = 0 };
3888 + fifosize_data_t nptxfifosize;
3889 + fifosize_data_t ptxfifosize;
3890 + int i;
3891 + hcchar_data_t hcchar;
3892 + hcfg_data_t hcfg;
3893 + dwc_otg_hc_regs_t *hc_regs;
3894 + int num_channels;
3895 + gotgctl_data_t gotgctl = { .d32 = 0 };
3896 +
3897 + DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if);
3898 +
3899 + /* Restart the Phy Clock */
3900 + dwc_write_reg32(core_if->pcgcctl, 0);
3901 +
3902 + /* Initialize Host Configuration Register */
3903 + init_fslspclksel(core_if);
3904 + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL)
3905 + {
3906 + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
3907 + hcfg.b.fslssupp = 1;
3908 + dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
3909 + }
3910 +
3911 + /* Configure data FIFO sizes */
3912 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
3913 + DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size);
3914 + DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
3915 + DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
3916 + DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
3917 +
3918 + /* Rx FIFO */
3919 + DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
3920 + dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
3921 + DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
3922 +
3923 + /* Non-periodic Tx FIFO */
3924 + DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
3925 + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
3926 + nptxfifosize.b.startaddr = params->host_rx_fifo_size;
3927 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
3928 + DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
3929 +
3930 + /* Periodic Tx FIFO */
3931 + DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
3932 + ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
3933 + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
3934 + dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
3935 + DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
3936 + }
3937 +
3938 + /* Clear Host Set HNP Enable in the OTG Control Register */
3939 + gotgctl.b.hstsethnpen = 1;
3940 + dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
3941 +
3942 + /* Make sure the FIFOs are flushed. */
3943 + dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */);
3944 + dwc_otg_flush_rx_fifo(core_if);
3945 +
3946 + /* Flush out any leftover queued requests. */
3947 + num_channels = core_if->core_params->host_channels;
3948 + for (i = 0; i < num_channels; i++)
3949 + {
3950 + hc_regs = core_if->host_if->hc_regs[i];
3951 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
3952 + hcchar.b.chen = 0;
3953 + hcchar.b.chdis = 1;
3954 + hcchar.b.epdir = 0;
3955 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
3956 + }
3957 +
3958 + /* Halt all channels to put them into a known state. */
3959 + for (i = 0; i < num_channels; i++)
3960 + {
3961 + int count = 0;
3962 + hc_regs = core_if->host_if->hc_regs[i];
3963 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
3964 + hcchar.b.chen = 1;
3965 + hcchar.b.chdis = 1;
3966 + hcchar.b.epdir = 0;
3967 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
3968 + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
3969 + do {
3970 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
3971 + if (++count > 1000)
3972 + {
3973 + DWC_ERROR("%s: Unable to clear halt on channel %d\n",
3974 + __func__, i);
3975 + break;
3976 + }
3977 + }
3978 + while (hcchar.b.chen);
3979 + }
3980 +
3981 + /* Turn on the vbus power. */
3982 + DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state);
3983 + if (core_if->op_state == A_HOST) {
3984 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
3985 + DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
3986 + if (hprt0.b.prtpwr == 0) {
3987 + hprt0.b.prtpwr = 1;
3988 + dwc_write_reg32(host_if->hprt0, hprt0.d32);
3989 + }
3990 + }
3991 +
3992 + dwc_otg_enable_host_interrupts(core_if);
3993 +}
3994 +
3995 +/**
3996 + * Prepares a host channel for transferring packets to/from a specific
3997 + * endpoint. The HCCHARn register is set up with the characteristics specified
3998 + * in _hc. Host channel interrupts that may need to be serviced while this
3999 + * transfer is in progress are enabled.
4000 + *
4001 + * @param core_if Programming view of DWC_otg controller
4002 + * @param hc Information needed to initialize the host channel
4003 + */
4004 +void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4005 +{
4006 + uint32_t intr_enable;
4007 + hcintmsk_data_t hc_intr_mask;
4008 + gintmsk_data_t gintmsk = { .d32 = 0 };
4009 + hcchar_data_t hcchar;
4010 + hcsplt_data_t hcsplt;
4011 +
4012 + uint8_t hc_num = hc->hc_num;
4013 + dwc_otg_host_if_t *host_if = core_if->host_if;
4014 + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
4015 +
4016 + /* Clear old interrupt conditions for this host channel. */
4017 + hc_intr_mask.d32 = 0xFFFFFFFF;
4018 + hc_intr_mask.b.reserved = 0;
4019 + dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
4020 +
4021 + /* Enable channel interrupts required for this transfer. */
4022 + hc_intr_mask.d32 = 0;
4023 + hc_intr_mask.b.chhltd = 1;
4024 + if (core_if->dma_enable) {
4025 + hc_intr_mask.b.ahberr = 1;
4026 + if (hc->error_state && !hc->do_split &&
4027 + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
4028 + hc_intr_mask.b.ack = 1;
4029 + if (hc->ep_is_in) {
4030 + hc_intr_mask.b.datatglerr = 1;
4031 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
4032 + hc_intr_mask.b.nak = 1;
4033 + }
4034 + }
4035 + }
4036 + }
4037 + else {
4038 + switch (hc->ep_type) {
4039 + case DWC_OTG_EP_TYPE_CONTROL:
4040 + case DWC_OTG_EP_TYPE_BULK:
4041 + hc_intr_mask.b.xfercompl = 1;
4042 + hc_intr_mask.b.stall = 1;
4043 + hc_intr_mask.b.xacterr = 1;
4044 + hc_intr_mask.b.datatglerr = 1;
4045 + if (hc->ep_is_in) {
4046 + hc_intr_mask.b.bblerr = 1;
4047 + }
4048 + else {
4049 + hc_intr_mask.b.nak = 1;
4050 + hc_intr_mask.b.nyet = 1;
4051 + if (hc->do_ping) {
4052 + hc_intr_mask.b.ack = 1;
4053 + }
4054 + }
4055 +
4056 + if (hc->do_split) {
4057 + hc_intr_mask.b.nak = 1;
4058 + if (hc->complete_split) {
4059 + hc_intr_mask.b.nyet = 1;
4060 + }
4061 + else {
4062 + hc_intr_mask.b.ack = 1;
4063 + }
4064 + }
4065 +
4066 + if (hc->error_state) {
4067 + hc_intr_mask.b.ack = 1;
4068 + }
4069 + break;
4070 + case DWC_OTG_EP_TYPE_INTR:
4071 + hc_intr_mask.b.xfercompl = 1;
4072 + hc_intr_mask.b.nak = 1;
4073 + hc_intr_mask.b.stall = 1;
4074 + hc_intr_mask.b.xacterr = 1;
4075 + hc_intr_mask.b.datatglerr = 1;
4076 + hc_intr_mask.b.frmovrun = 1;
4077 +
4078 + if (hc->ep_is_in) {
4079 + hc_intr_mask.b.bblerr = 1;
4080 + }
4081 + if (hc->error_state) {
4082 + hc_intr_mask.b.ack = 1;
4083 + }
4084 + if (hc->do_split) {
4085 + if (hc->complete_split) {
4086 + hc_intr_mask.b.nyet = 1;
4087 + }
4088 + else {
4089 + hc_intr_mask.b.ack = 1;
4090 + }
4091 + }
4092 + break;
4093 + case DWC_OTG_EP_TYPE_ISOC:
4094 + hc_intr_mask.b.xfercompl = 1;
4095 + hc_intr_mask.b.frmovrun = 1;
4096 + hc_intr_mask.b.ack = 1;
4097 +
4098 + if (hc->ep_is_in) {
4099 + hc_intr_mask.b.xacterr = 1;
4100 + hc_intr_mask.b.bblerr = 1;
4101 + }
4102 + break;
4103 + }
4104 + }
4105 + dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
4106 +
4107 +// if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in)
4108 +// hc->max_packet = 512;
4109 + /* Enable the top level host channel interrupt. */
4110 + intr_enable = (1 << hc_num);
4111 + dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
4112 +
4113 + /* Make sure host channel interrupts are enabled. */
4114 + gintmsk.b.hcintr = 1;
4115 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
4116 +
4117 + /*
4118 + * Program the HCCHARn register with the endpoint characteristics for
4119 + * the current transfer.
4120 + */
4121 + hcchar.d32 = 0;
4122 + hcchar.b.devaddr = hc->dev_addr;
4123 + hcchar.b.epnum = hc->ep_num;
4124 + hcchar.b.epdir = hc->ep_is_in;
4125 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
4126 + hcchar.b.eptype = hc->ep_type;
4127 + hcchar.b.mps = hc->max_packet;
4128 +
4129 + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
4130 +
4131 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4132 + DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
4133 + DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
4134 + DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
4135 + DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
4136 + DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
4137 + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
4138 + DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
4139 +
4140 + /*
4141 + * Program the HCSPLIT register for SPLITs
4142 + */
4143 + hcsplt.d32 = 0;
4144 + if (hc->do_split) {
4145 + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num,
4146 + hc->complete_split ? "CSPLIT" : "SSPLIT");
4147 + hcsplt.b.compsplt = hc->complete_split;
4148 + hcsplt.b.xactpos = hc->xact_pos;
4149 + hcsplt.b.hubaddr = hc->hub_addr;
4150 + hcsplt.b.prtaddr = hc->port_addr;
4151 + DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split);
4152 + DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos);
4153 + DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr);
4154 + DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr);
4155 + DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in);
4156 + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
4157 + DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len);
4158 + }
4159 + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
4160 +
4161 +}
4162 +
4163 +/**
4164 + * Attempts to halt a host channel. This function should only be called in
4165 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
4166 + * normal circumstances in DMA mode, the controller halts the channel when the
4167 + * transfer is complete or a condition occurs that requires application
4168 + * intervention.
4169 + *
4170 + * In slave mode, checks for a free request queue entry, then sets the Channel
4171 + * Enable and Channel Disable bits of the Host Channel Characteristics
4172 + * register of the specified channel to intiate the halt. If there is no free
4173 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
4174 + * register to flush requests for this channel. In the latter case, sets a
4175 + * flag to indicate that the host channel needs to be halted when a request
4176 + * queue slot is open.
4177 + *
4178 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
4179 + * HCCHARn register. The controller ensures there is space in the request
4180 + * queue before submitting the halt request.
4181 + *
4182 + * Some time may elapse before the core flushes any posted requests for this
4183 + * host channel and halts. The Channel Halted interrupt handler completes the
4184 + * deactivation of the host channel.
4185 + *
4186 + * @param core_if Controller register interface.
4187 + * @param hc Host channel to halt.
4188 + * @param halt_status Reason for halting the channel.
4189 + */
4190 +void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
4191 + dwc_hc_t *hc,
4192 + dwc_otg_halt_status_e halt_status)
4193 +{
4194 + gnptxsts_data_t nptxsts;
4195 + hptxsts_data_t hptxsts;
4196 + hcchar_data_t hcchar;
4197 + dwc_otg_hc_regs_t *hc_regs;
4198 + dwc_otg_core_global_regs_t *global_regs;
4199 + dwc_otg_host_global_regs_t *host_global_regs;
4200 +
4201 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4202 + global_regs = core_if->core_global_regs;
4203 + host_global_regs = core_if->host_if->host_global_regs;
4204 +
4205 + WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
4206 +
4207 + if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
4208 + halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
4209 + /*
4210 + * Disable all channel interrupts except Ch Halted. The QTD
4211 + * and QH state associated with this transfer has been cleared
4212 + * (in the case of URB_DEQUEUE), so the channel needs to be
4213 + * shut down carefully to prevent crashes.
4214 + */
4215 + hcintmsk_data_t hcintmsk;
4216 + hcintmsk.d32 = 0;
4217 + hcintmsk.b.chhltd = 1;
4218 + dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
4219 +
4220 + /*
4221 + * Make sure no other interrupts besides halt are currently
4222 + * pending. Handling another interrupt could cause a crash due
4223 + * to the QTD and QH state.
4224 + */
4225 + dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
4226 +
4227 + /*
4228 + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
4229 + * even if the channel was already halted for some other
4230 + * reason.
4231 + */
4232 + hc->halt_status = halt_status;
4233 +
4234 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4235 + if (hcchar.b.chen == 0) {
4236 + /*
4237 + * The channel is either already halted or it hasn't
4238 + * started yet. In DMA mode, the transfer may halt if
4239 + * it finishes normally or a condition occurs that
4240 + * requires driver intervention. Don't want to halt
4241 + * the channel again. In either Slave or DMA mode,
4242 + * it's possible that the transfer has been assigned
4243 + * to a channel, but not started yet when an URB is
4244 + * dequeued. Don't want to halt a channel that hasn't
4245 + * started yet.
4246 + */
4247 + return;
4248 + }
4249 + }
4250 +
4251 + if (hc->halt_pending) {
4252 + /*
4253 + * A halt has already been issued for this channel. This might
4254 + * happen when a transfer is aborted by a higher level in
4255 + * the stack.
4256 + */
4257 +#ifdef DEBUG
4258 + DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
4259 + __func__, hc->hc_num);
4260 +
4261 +/* dwc_otg_dump_global_registers(core_if); */
4262 +/* dwc_otg_dump_host_registers(core_if); */
4263 +#endif
4264 + return;
4265 + }
4266 +
4267 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4268 + hcchar.b.chen = 1;
4269 + hcchar.b.chdis = 1;
4270 +
4271 + if (!core_if->dma_enable) {
4272 + /* Check for space in the request queue to issue the halt. */
4273 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
4274 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
4275 + nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
4276 + if (nptxsts.b.nptxqspcavail == 0) {
4277 + hcchar.b.chen = 0;
4278 + }
4279 + }
4280 + else {
4281 + hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
4282 + if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) {
4283 + hcchar.b.chen = 0;
4284 + }
4285 + }
4286 + }
4287 +
4288 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4289 +
4290 + hc->halt_status = halt_status;
4291 +
4292 + if (hcchar.b.chen) {
4293 + hc->halt_pending = 1;
4294 + hc->halt_on_queue = 0;
4295 + }
4296 + else {
4297 + hc->halt_on_queue = 1;
4298 + }
4299 +
4300 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4301 + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
4302 + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
4303 + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
4304 + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
4305 +
4306 + return;
4307 +}
4308 +
4309 +/**
4310 + * Clears the transfer state for a host channel. This function is normally
4311 + * called after a transfer is done and the host channel is being released.
4312 + *
4313 + * @param core_if Programming view of DWC_otg controller.
4314 + * @param hc Identifies the host channel to clean up.
4315 + */
4316 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4317 +{
4318 + dwc_otg_hc_regs_t *hc_regs;
4319 +
4320 + hc->xfer_started = 0;
4321 +
4322 + /*
4323 + * Clear channel interrupt enables and any unhandled channel interrupt
4324 + * conditions.
4325 + */
4326 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4327 + dwc_write_reg32(&hc_regs->hcintmsk, 0);
4328 + dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
4329 +
4330 +#ifdef DEBUG
4331 + del_timer(&core_if->hc_xfer_timer[hc->hc_num]);
4332 + {
4333 + hcchar_data_t hcchar;
4334 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4335 + if (hcchar.b.chdis) {
4336 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
4337 + __func__, hc->hc_num, hcchar.d32);
4338 + }
4339 + }
4340 +#endif
4341 +}
4342 +
4343 +/**
4344 + * Sets the channel property that indicates in which frame a periodic transfer
4345 + * should occur. This is always set to the _next_ frame. This function has no
4346 + * effect on non-periodic transfers.
4347 + *
4348 + * @param core_if Programming view of DWC_otg controller.
4349 + * @param hc Identifies the host channel to set up and its properties.
4350 + * @param hcchar Current value of the HCCHAR register for the specified host
4351 + * channel.
4352 + */
4353 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
4354 + dwc_hc_t *hc,
4355 + hcchar_data_t *hcchar)
4356 +{
4357 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4358 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4359 + hfnum_data_t hfnum;
4360 + hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
4361 +
4362 + /* 1 if _next_ frame is odd, 0 if it's even */
4363 + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
4364 +#ifdef DEBUG
4365 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) {
4366 + switch (hfnum.b.frnum & 0x7) {
4367 + case 7:
4368 + core_if->hfnum_7_samples++;
4369 + core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
4370 + break;
4371 + case 0:
4372 + core_if->hfnum_0_samples++;
4373 + core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
4374 + break;
4375 + default:
4376 + core_if->hfnum_other_samples++;
4377 + core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
4378 + break;
4379 + }
4380 + }
4381 +#endif
4382 + }
4383 +}
4384 +
4385 +#ifdef DEBUG
4386 +static void hc_xfer_timeout(unsigned long ptr)
4387 +{
4388 + hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr;
4389 + int hc_num = xfer_info->hc->hc_num;
4390 + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
4391 + DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
4392 +}
4393 +#endif
4394 +
4395 +/*
4396 + * This function does the setup for a data transfer for a host channel and
4397 + * starts the transfer. May be called in either Slave mode or DMA mode. In
4398 + * Slave mode, the caller must ensure that there is sufficient space in the
4399 + * request queue and Tx Data FIFO.
4400 + *
4401 + * For an OUT transfer in Slave mode, it loads a data packet into the
4402 + * appropriate FIFO. If necessary, additional data packets will be loaded in
4403 + * the Host ISR.
4404 + *
4405 + * For an IN transfer in Slave mode, a data packet is requested. The data
4406 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
4407 + * additional data packets are requested in the Host ISR.
4408 + *
4409 + * For a PING transfer in Slave mode, the Do Ping bit is set in the egards,
4410 + *
4411 + * Steven
4412 + *
4413 + * register along with a packet count of 1 and the channel is enabled. This
4414 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
4415 + * simply set to 0 since no data transfer occurs in this case.
4416 + *
4417 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
4418 + * all the information required to perform the subsequent data transfer. In
4419 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
4420 + * controller performs the entire PING protocol, then starts the data
4421 + * transfer.
4422 + *
4423 + * @param core_if Programming view of DWC_otg controller.
4424 + * @param hc Information needed to initialize the host channel. The xfer_len
4425 + * value may be reduced to accommodate the max widths of the XferSize and
4426 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
4427 + * to reflect the final xfer_len value.
4428 + */
4429 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4430 +{
4431 + hcchar_data_t hcchar;
4432 + hctsiz_data_t hctsiz;
4433 + uint16_t num_packets;
4434 + uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
4435 + uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
4436 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4437 +
4438 + hctsiz.d32 = 0;
4439 +
4440 + if (hc->do_ping) {
4441 + if (!core_if->dma_enable) {
4442 + dwc_otg_hc_do_ping(core_if, hc);
4443 + hc->xfer_started = 1;
4444 + return;
4445 + }
4446 + else {
4447 + hctsiz.b.dopng = 1;
4448 + }
4449 + }
4450 +
4451 + if (hc->do_split) {
4452 + num_packets = 1;
4453 +
4454 + if (hc->complete_split && !hc->ep_is_in) {
4455 + /* For CSPLIT OUT Transfer, set the size to 0 so the
4456 + * core doesn't expect any data written to the FIFO */
4457 + hc->xfer_len = 0;
4458 + }
4459 + else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
4460 + hc->xfer_len = hc->max_packet;
4461 + }
4462 + else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
4463 + hc->xfer_len = 188;
4464 + }
4465 +
4466 + hctsiz.b.xfersize = hc->xfer_len;
4467 + }
4468 + else {
4469 + /*
4470 + * Ensure that the transfer length and packet count will fit
4471 + * in the widths allocated for them in the HCTSIZn register.
4472 + */
4473 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4474 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4475 + /*
4476 + * Make sure the transfer size is no larger than one
4477 + * (micro)frame's worth of data. (A check was done
4478 + * when the periodic transfer was accepted to ensure
4479 + * that a (micro)frame's worth of data can be
4480 + * programmed into a channel.)
4481 + */
4482 + uint32_t max_periodic_len = hc->multi_count * hc->max_packet;
4483 + if (hc->xfer_len > max_periodic_len) {
4484 + hc->xfer_len = max_periodic_len;
4485 + }
4486 + else {
4487 + }
4488 +
4489 + }
4490 + else if (hc->xfer_len > max_hc_xfer_size) {
4491 + /* Make sure that xfer_len is a multiple of max packet size. */
4492 + hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
4493 + }
4494 +
4495 + if (hc->xfer_len > 0) {
4496 + num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
4497 + if (num_packets > max_hc_pkt_count) {
4498 + num_packets = max_hc_pkt_count;
4499 + hc->xfer_len = num_packets * hc->max_packet;
4500 + }
4501 + }
4502 + else {
4503 + /* Need 1 packet for transfer length of 0. */
4504 + num_packets = 1;
4505 + }
4506 +
4507 + if (hc->ep_is_in) {
4508 + /* Always program an integral # of max packets for IN transfers. */
4509 + hc->xfer_len = num_packets * hc->max_packet;
4510 + }
4511 +
4512 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4513 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4514 + /*
4515 + * Make sure that the multi_count field matches the
4516 + * actual transfer length.
4517 + */
4518 + hc->multi_count = num_packets;
4519 + }
4520 +
4521 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4522 + /* Set up the initial PID for the transfer. */
4523 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
4524 + if (hc->ep_is_in) {
4525 + if (hc->multi_count == 1) {
4526 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
4527 + }
4528 + else if (hc->multi_count == 2) {
4529 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
4530 + }
4531 + else {
4532 + hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
4533 + }
4534 + }
4535 + else {
4536 + if (hc->multi_count == 1) {
4537 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
4538 + }
4539 + else {
4540 + hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
4541 + }
4542 + }
4543 + }
4544 + else {
4545 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
4546 + }
4547 + }
4548 +
4549 + hctsiz.b.xfersize = hc->xfer_len;
4550 + }
4551 +
4552 + hc->start_pkt_count = num_packets;
4553 + hctsiz.b.pktcnt = num_packets;
4554 + hctsiz.b.pid = hc->data_pid_start;
4555 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
4556 +
4557 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4558 + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
4559 + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
4560 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
4561 +
4562 + if (core_if->dma_enable) {
4563 +#if defined (CONFIG_DWC_OTG_HOST_ONLY)
4564 + if ((uint32_t)hc->xfer_buff & 0x3) {
4565 + /* non DWORD-aligned buffer case*/
4566 + if(!hc->qh->dw_align_buf) {
4567 + hc->qh->dw_align_buf =
4568 + dma_alloc_coherent(NULL,
4569 + core_if->core_params->max_transfer_size,
4570 + &hc->qh->dw_align_buf_dma,
4571 + GFP_ATOMIC | GFP_DMA);
4572 + if (!hc->qh->dw_align_buf) {
4573 +
4574 + DWC_ERROR("%s: Failed to allocate memory to handle "
4575 + "non-dword aligned buffer case\n", __func__);
4576 + return;
4577 + }
4578 +
4579 + }
4580 + if (!hc->ep_is_in) {
4581 + memcpy(hc->qh->dw_align_buf, phys_to_virt((uint32_t)hc->xfer_buff), hc->xfer_len);
4582 + }
4583 +
4584 + dwc_write_reg32(&hc_regs->hcdma, hc->qh->dw_align_buf_dma);
4585 + }
4586 + else
4587 +#endif
4588 + dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff);
4589 + }
4590 +
4591 + /* Start the split */
4592 + if (hc->do_split) {
4593 + hcsplt_data_t hcsplt;
4594 + hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
4595 + hcsplt.b.spltena = 1;
4596 + dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
4597 + }
4598 +
4599 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4600 + hcchar.b.multicnt = hc->multi_count;
4601 + hc_set_even_odd_frame(core_if, hc, &hcchar);
4602 +#ifdef DEBUG
4603 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
4604 + if (hcchar.b.chdis) {
4605 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
4606 + __func__, hc->hc_num, hcchar.d32);
4607 + }
4608 +#endif
4609 +
4610 + /* Set host channel enable after all other setup is complete. */
4611 + hcchar.b.chen = 1;
4612 + hcchar.b.chdis = 0;
4613 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4614 +
4615 + hc->xfer_started = 1;
4616 + hc->requests++;
4617 +
4618 + if (!core_if->dma_enable &&
4619 + !hc->ep_is_in && hc->xfer_len > 0) {
4620 + /* Load OUT packet into the appropriate Tx FIFO. */
4621 + dwc_otg_hc_write_packet(core_if, hc);
4622 + }
4623 +
4624 +#ifdef DEBUG
4625 + /* Start a timer for this transfer. */
4626 + core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout;
4627 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
4628 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
4629 + core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]);
4630 + core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10);
4631 + add_timer(&core_if->hc_xfer_timer[hc->hc_num]);
4632 +#endif
4633 +}
4634 +
4635 +/**
4636 + * This function continues a data transfer that was started by previous call
4637 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
4638 + * sufficient space in the request queue and Tx Data FIFO. This function
4639 + * should only be called in Slave mode. In DMA mode, the controller acts
4640 + * autonomously to complete transfers programmed to a host channel.
4641 + *
4642 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
4643 + * if there is any data remaining to be queued. For an IN transfer, another
4644 + * data packet is always requested. For the SETUP phase of a control transfer,
4645 + * this function does nothing.
4646 + *
4647 + * @return 1 if a new request is queued, 0 if no more requests are required
4648 + * for this transfer.
4649 + */
4650 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4651 +{
4652 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4653 +
4654 + if (hc->do_split) {
4655 + /* SPLITs always queue just once per channel */
4656 + return 0;
4657 + }
4658 + else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
4659 + /* SETUPs are queued only once since they can't be NAKed. */
4660 + return 0;
4661 + }
4662 + else if (hc->ep_is_in) {
4663 + /*
4664 + * Always queue another request for other IN transfers. If
4665 + * back-to-back INs are issued and NAKs are received for both,
4666 + * the driver may still be processing the first NAK when the
4667 + * second NAK is received. When the interrupt handler clears
4668 + * the NAK interrupt for the first NAK, the second NAK will
4669 + * not be seen. So we can't depend on the NAK interrupt
4670 + * handler to requeue a NAKed request. Instead, IN requests
4671 + * are issued each time this function is called. When the
4672 + * transfer completes, the extra requests for the channel will
4673 + * be flushed.
4674 + */
4675 + hcchar_data_t hcchar;
4676 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4677 +
4678 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4679 + hc_set_even_odd_frame(core_if, hc, &hcchar);
4680 + hcchar.b.chen = 1;
4681 + hcchar.b.chdis = 0;
4682 + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32);
4683 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4684 + hc->requests++;
4685 + return 1;
4686 + }
4687 + else {
4688 + /* OUT transfers. */
4689 + if (hc->xfer_count < hc->xfer_len) {
4690 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
4691 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
4692 + hcchar_data_t hcchar;
4693 + dwc_otg_hc_regs_t *hc_regs;
4694 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4695 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4696 + hc_set_even_odd_frame(core_if, hc, &hcchar);
4697 + }
4698 +
4699 + /* Load OUT packet into the appropriate Tx FIFO. */
4700 + dwc_otg_hc_write_packet(core_if, hc);
4701 + hc->requests++;
4702 + return 1;
4703 + }
4704 + else {
4705 + return 0;
4706 + }
4707 + }
4708 +}
4709 +
4710 +/**
4711 + * Starts a PING transfer. This function should only be called in Slave mode.
4712 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
4713 + */
4714 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4715 +{
4716 + hcchar_data_t hcchar;
4717 + hctsiz_data_t hctsiz;
4718 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
4719 +
4720 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
4721 +
4722 + hctsiz.d32 = 0;
4723 + hctsiz.b.dopng = 1;
4724 + hctsiz.b.pktcnt = 1;
4725 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
4726 +
4727 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
4728 + hcchar.b.chen = 1;
4729 + hcchar.b.chdis = 0;
4730 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
4731 +}
4732 +
4733 +/*
4734 + * This function writes a packet into the Tx FIFO associated with the Host
4735 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
4736 + * Tx FIFO is written. For a channel associated with a periodic EP, the
4737 + * periodic Tx FIFO is written. This function should only be called in Slave
4738 + * mode.
4739 + *
4740 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
4741 + * then number of bytes written to the Tx FIFO.
4742 + */
4743 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
4744 +{
4745 + uint32_t i;
4746 + uint32_t remaining_count;
4747 + uint32_t byte_count;
4748 + uint32_t dword_count;
4749 +
4750 + uint32_t *data_buff = (uint32_t *)(hc->xfer_buff);
4751 + uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
4752 +
4753 + remaining_count = hc->xfer_len - hc->xfer_count;
4754 + if (remaining_count > hc->max_packet) {
4755 + byte_count = hc->max_packet;
4756 + }
4757 + else {
4758 + byte_count = remaining_count;
4759 + }
4760 +
4761 + dword_count = (byte_count + 3) / 4;
4762 +
4763 + if ((((unsigned long)data_buff) & 0x3) == 0) {
4764 + /* xfer_buff is DWORD aligned. */
4765 + for (i = 0; i < dword_count; i++, data_buff++)
4766 + {
4767 + dwc_write_reg32(data_fifo, *data_buff);
4768 + }
4769 + }
4770 + else {
4771 + /* xfer_buff is not DWORD aligned. */
4772 + for (i = 0; i < dword_count; i++, data_buff++)
4773 + {
4774 + dwc_write_reg32(data_fifo, get_unaligned(data_buff));
4775 + }
4776 + }
4777 +
4778 + hc->xfer_count += byte_count;
4779 + hc->xfer_buff += byte_count;
4780 +}
4781 +
4782 +/**
4783 + * Gets the current USB frame number. This is the frame number from the last
4784 + * SOF packet.
4785 + */
4786 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
4787 +{
4788 + dsts_data_t dsts;
4789 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
4790 +
4791 + /* read current frame/microframe number from DSTS register */
4792 + return dsts.b.soffn;
4793 +}
4794 +
4795 +/**
4796 + * This function reads a setup packet from the Rx FIFO into the destination
4797 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
4798 + * Interrupt routine when a SETUP packet has been received in Slave mode.
4799 + *
4800 + * @param core_if Programming view of DWC_otg controller.
4801 + * @param dest Destination buffer for packet data.
4802 + */
4803 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
4804 +{
4805 + /* Get the 8 bytes of a setup transaction data */
4806 +
4807 + /* Pop 2 DWORDS off the receive data FIFO into memory */
4808 + dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
4809 + dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
4810 +}
4811 +
4812 +
4813 +/**
4814 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
4815 + * IN for transmitting packets. It is normally called when the
4816 + * "Enumeration Done" interrupt occurs.
4817 + *
4818 + * @param core_if Programming view of DWC_otg controller.
4819 + * @param ep The EP0 data.
4820 + */
4821 +void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4822 +{
4823 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
4824 + dsts_data_t dsts;
4825 + depctl_data_t diepctl;
4826 + depctl_data_t doepctl;
4827 + dctl_data_t dctl = { .d32 = 0 };
4828 +
4829 + /* Read the Device Status and Endpoint 0 Control registers */
4830 + dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
4831 + diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
4832 + doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
4833 +
4834 + /* Set the MPS of the IN EP based on the enumeration speed */
4835 + switch (dsts.b.enumspd) {
4836 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
4837 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
4838 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
4839 + diepctl.b.mps = DWC_DEP0CTL_MPS_64;
4840 + break;
4841 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
4842 + diepctl.b.mps = DWC_DEP0CTL_MPS_8;
4843 + break;
4844 + }
4845 +
4846 + dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
4847 +
4848 + /* Enable OUT EP for receive */
4849 + doepctl.b.epena = 1;
4850 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
4851 +
4852 +#ifdef VERBOSE
4853 + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
4854 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
4855 + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
4856 + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
4857 +#endif
4858 + dctl.b.cgnpinnak = 1;
4859 +
4860 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
4861 + DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
4862 + dwc_read_reg32(&dev_if->dev_global_regs->dctl));
4863 +}
4864 +
4865 +/**
4866 + * This function activates an EP. The Device EP control register for
4867 + * the EP is configured as defined in the ep structure. Note: This
4868 + * function is not used for EP0.
4869 + *
4870 + * @param core_if Programming view of DWC_otg controller.
4871 + * @param ep The EP to activate.
4872 + */
4873 +void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4874 +{
4875 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
4876 + depctl_data_t depctl;
4877 + volatile uint32_t *addr;
4878 + daint_data_t daintmsk = { .d32 = 0 };
4879 +
4880 + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
4881 + (ep->is_in?"IN":"OUT"));
4882 +
4883 + /* Read DEPCTLn register */
4884 + if (ep->is_in == 1) {
4885 + addr = &dev_if->in_ep_regs[ep->num]->diepctl;
4886 + daintmsk.ep.in = 1<<ep->num;
4887 + }
4888 + else {
4889 + addr = &dev_if->out_ep_regs[ep->num]->doepctl;
4890 + daintmsk.ep.out = 1<<ep->num;
4891 + }
4892 +
4893 + /* If the EP is already active don't change the EP Control
4894 + * register. */
4895 + depctl.d32 = dwc_read_reg32(addr);
4896 + if (!depctl.b.usbactep) {
4897 + depctl.b.mps = ep->maxpacket;
4898 + depctl.b.eptype = ep->type;
4899 + depctl.b.txfnum = ep->tx_fifo_num;
4900 +
4901 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
4902 + depctl.b.setd0pid = 1; // ???
4903 + }
4904 + else {
4905 + depctl.b.setd0pid = 1;
4906 + }
4907 + depctl.b.usbactep = 1;
4908 +
4909 + dwc_write_reg32(addr, depctl.d32);
4910 + DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr));
4911 + }
4912 +
4913 + /* Enable the Interrupt for this EP */
4914 + if(core_if->multiproc_int_enable) {
4915 + if (ep->is_in == 1) {
4916 + diepmsk_data_t diepmsk = { .d32 = 0};
4917 + diepmsk.b.xfercompl = 1;
4918 + diepmsk.b.timeout = 1;
4919 + diepmsk.b.epdisabled = 1;
4920 + diepmsk.b.ahberr = 1;
4921 + diepmsk.b.intknepmis = 1;
4922 + diepmsk.b.txfifoundrn = 1; //?????
4923 +
4924 +
4925 + if(core_if->dma_desc_enable) {
4926 + diepmsk.b.bna = 1;
4927 + }
4928 +/*
4929 + if(core_if->dma_enable) {
4930 + doepmsk.b.nak = 1;
4931 + }
4932 +*/
4933 + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32);
4934 +
4935 + } else {
4936 + doepmsk_data_t doepmsk = { .d32 = 0};
4937 + doepmsk.b.xfercompl = 1;
4938 + doepmsk.b.ahberr = 1;
4939 + doepmsk.b.epdisabled = 1;
4940 +
4941 +
4942 + if(core_if->dma_desc_enable) {
4943 + doepmsk.b.bna = 1;
4944 + }
4945 +/*
4946 + doepmsk.b.babble = 1;
4947 + doepmsk.b.nyet = 1;
4948 + doepmsk.b.nak = 1;
4949 +*/
4950 + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32);
4951 + }
4952 + dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
4953 + 0, daintmsk.d32);
4954 + } else {
4955 + dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
4956 + 0, daintmsk.d32);
4957 + }
4958 +
4959 + DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
4960 + dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
4961 +
4962 + ep->stall_clear_flag = 0;
4963 + return;
4964 +}
4965 +
4966 +/**
4967 + * This function deactivates an EP. This is done by clearing the USB Active
4968 + * EP bit in the Device EP control register. Note: This function is not used
4969 + * for EP0. EP0 cannot be deactivated.
4970 + *
4971 + * @param core_if Programming view of DWC_otg controller.
4972 + * @param ep The EP to deactivate.
4973 + */
4974 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4975 +{
4976 + depctl_data_t depctl = { .d32 = 0 };
4977 + volatile uint32_t *addr;
4978 + daint_data_t daintmsk = { .d32 = 0};
4979 +
4980 + /* Read DEPCTLn register */
4981 + if (ep->is_in == 1) {
4982 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
4983 + daintmsk.ep.in = 1<<ep->num;
4984 + }
4985 + else {
4986 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
4987 + daintmsk.ep.out = 1<<ep->num;
4988 + }
4989 +
4990 + depctl.b.usbactep = 0;
4991 +
4992 + if(core_if->dma_desc_enable)
4993 + depctl.b.epdis = 1;
4994 +
4995 + dwc_write_reg32(addr, depctl.d32);
4996 +
4997 + /* Disable the Interrupt for this EP */
4998 + if(core_if->multiproc_int_enable) {
4999 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
5000 + daintmsk.d32, 0);
5001 +
5002 + if (ep->is_in == 1) {
5003 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0);
5004 + } else {
5005 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0);
5006 + }
5007 + } else {
5008 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
5009 + daintmsk.d32, 0);
5010 + }
5011 +}
5012 +
5013 +/**
5014 + * This function does the setup for a data transfer for an EP and
5015 + * starts the transfer. For an IN transfer, the packets will be
5016 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
5017 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
5018 + *
5019 + * @param core_if Programming view of DWC_otg controller.
5020 + * @param ep The EP to start the transfer on.
5021 + */
5022 +static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5023 +{
5024 + dwc_otg_dma_desc_t* dma_desc;
5025 + uint32_t offset;
5026 + uint32_t xfer_est;
5027 + int i;
5028 +
5029 + ep->desc_cnt = ( ep->total_len / ep->maxxfer) +
5030 + ((ep->total_len % ep->maxxfer) ? 1 : 0);
5031 + if(!ep->desc_cnt)
5032 + ep->desc_cnt = 1;
5033 +
5034 + dma_desc = ep->desc_addr;
5035 + xfer_est = ep->total_len;
5036 + offset = 0;
5037 + for( i = 0; i < ep->desc_cnt; ++i) {
5038 + /** DMA Descriptor Setup */
5039 + if(xfer_est > ep->maxxfer) {
5040 + dma_desc->status.b.bs = BS_HOST_BUSY;
5041 + dma_desc->status.b.l = 0;
5042 + dma_desc->status.b.ioc = 0;
5043 + dma_desc->status.b.sp = 0;
5044 + dma_desc->status.b.bytes = ep->maxxfer;
5045 + dma_desc->buf = ep->dma_addr + offset;
5046 + dma_desc->status.b.bs = BS_HOST_READY;
5047 +
5048 + xfer_est -= ep->maxxfer;
5049 + offset += ep->maxxfer;
5050 + } else {
5051 + dma_desc->status.b.bs = BS_HOST_BUSY;
5052 + dma_desc->status.b.l = 1;
5053 + dma_desc->status.b.ioc = 1;
5054 + if(ep->is_in) {
5055 + dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ?
5056 + 1 : ((ep->sent_zlp) ? 1 : 0);
5057 + dma_desc->status.b.bytes = xfer_est;
5058 + } else {
5059 + dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ;
5060 + }
5061 +
5062 + dma_desc->buf = ep->dma_addr + offset;
5063 + dma_desc->status.b.bs = BS_HOST_READY;
5064 + }
5065 + dma_desc ++;
5066 + }
5067 +}
5068 +
5069 +/**
5070 + * This function does the setup for a data transfer for an EP and
5071 + * starts the transfer. For an IN transfer, the packets will be
5072 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
5073 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
5074 + *
5075 + * @param core_if Programming view of DWC_otg controller.
5076 + * @param ep The EP to start the transfer on.
5077 + */
5078 +
5079 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5080 +{
5081 + depctl_data_t depctl;
5082 + deptsiz_data_t deptsiz;
5083 + gintmsk_data_t intr_mask = { .d32 = 0};
5084 +
5085 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
5086 +
5087 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
5088 + "xfer_buff=%p start_xfer_buff=%p\n",
5089 + ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
5090 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
5091 +
5092 + /* IN endpoint */
5093 + if (ep->is_in == 1) {
5094 + dwc_otg_dev_in_ep_regs_t *in_regs =
5095 + core_if->dev_if->in_ep_regs[ep->num];
5096 +
5097 + gnptxsts_data_t gtxstatus;
5098 +
5099 + gtxstatus.d32 =
5100 + dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
5101 +
5102 + if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
5103 +#ifdef DEBUG
5104 + DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
5105 +#endif
5106 + return;
5107 + }
5108 +
5109 + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
5110 + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
5111 +
5112 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
5113 + ep->maxxfer : (ep->total_len - ep->xfer_len);
5114 +
5115 + /* Zero Length Packet? */
5116 + if ((ep->xfer_len - ep->xfer_count) == 0) {
5117 + deptsiz.b.xfersize = 0;
5118 + deptsiz.b.pktcnt = 1;
5119 + }
5120 + else {
5121 + /* Program the transfer size and packet count
5122 + * as follows: xfersize = N * maxpacket +
5123 + * short_packet pktcnt = N + (short_packet
5124 + * exist ? 1 : 0)
5125 + */
5126 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
5127 + deptsiz.b.pktcnt =
5128 + (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) /
5129 + ep->maxpacket;
5130 + }
5131 +
5132 +
5133 + /* Write the DMA register */
5134 + if (core_if->dma_enable) {
5135 + if (core_if->dma_desc_enable == 0) {
5136 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5137 + dwc_write_reg32 (&(in_regs->diepdma),
5138 + (uint32_t)ep->dma_addr);
5139 + }
5140 + else {
5141 + init_dma_desc_chain(core_if, ep);
5142 + /** DIEPDMAn Register write */
5143 + dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr);
5144 + }
5145 + }
5146 + else {
5147 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5148 + if(ep->type != DWC_OTG_EP_TYPE_ISOC) {
5149 + /**
5150 + * Enable the Non-Periodic Tx FIFO empty interrupt,
5151 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
5152 + * the data will be written into the fifo by the ISR.
5153 + */
5154 + if(core_if->en_multiple_tx_fifo == 0) {
5155 + intr_mask.b.nptxfempty = 1;
5156 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5157 + intr_mask.d32, intr_mask.d32);
5158 + }
5159 + else {
5160 + /* Enable the Tx FIFO Empty Interrupt for this EP */
5161 + if(ep->xfer_len > 0) {
5162 + uint32_t fifoemptymsk = 0;
5163 + fifoemptymsk = 1 << ep->num;
5164 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5165 + 0, fifoemptymsk);
5166 +
5167 + }
5168 + }
5169 + }
5170 + }
5171 +
5172 + /* EP enable, IN data in FIFO */
5173 + depctl.b.cnak = 1;
5174 + depctl.b.epena = 1;
5175 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5176 +
5177 + depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
5178 + depctl.b.nextep = ep->num;
5179 + dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
5180 +
5181 + }
5182 + else {
5183 + /* OUT endpoint */
5184 + dwc_otg_dev_out_ep_regs_t *out_regs =
5185 + core_if->dev_if->out_ep_regs[ep->num];
5186 +
5187 + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
5188 + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
5189 +
5190 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
5191 + ep->maxxfer : (ep->total_len - ep->xfer_len);
5192 +
5193 + /* Program the transfer size and packet count as follows:
5194 + *
5195 + * pktcnt = N
5196 + * xfersize = N * maxpacket
5197 + */
5198 + if ((ep->xfer_len - ep->xfer_count) == 0) {
5199 + /* Zero Length Packet */
5200 + deptsiz.b.xfersize = ep->maxpacket;
5201 + deptsiz.b.pktcnt = 1;
5202 + }
5203 + else {
5204 + deptsiz.b.pktcnt =
5205 + (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) /
5206 + ep->maxpacket;
5207 + ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
5208 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
5209 + }
5210 +
5211 + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
5212 + ep->num,
5213 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
5214 +
5215 + if (core_if->dma_enable) {
5216 + if (!core_if->dma_desc_enable) {
5217 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5218 +
5219 + dwc_write_reg32 (&(out_regs->doepdma),
5220 + (uint32_t)ep->dma_addr);
5221 + }
5222 + else {
5223 + init_dma_desc_chain(core_if, ep);
5224 +
5225 + /** DOEPDMAn Register write */
5226 + dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr);
5227 + }
5228 + }
5229 + else {
5230 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5231 + }
5232 +
5233 + /* EP enable */
5234 + depctl.b.cnak = 1;
5235 + depctl.b.epena = 1;
5236 +
5237 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
5238 +
5239 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
5240 + dwc_read_reg32(&out_regs->doepctl),
5241 + dwc_read_reg32(&out_regs->doeptsiz));
5242 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
5243 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
5244 + dwc_read_reg32(&core_if->core_global_regs->gintmsk));
5245 + }
5246 +}
5247 +
5248 +/**
5249 + * This function setup a zero length transfer in Buffer DMA and
5250 + * Slave modes for usb requests with zero field set
5251 + *
5252 + * @param core_if Programming view of DWC_otg controller.
5253 + * @param ep The EP to start the transfer on.
5254 + *
5255 + */
5256 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5257 +{
5258 +
5259 + depctl_data_t depctl;
5260 + deptsiz_data_t deptsiz;
5261 + gintmsk_data_t intr_mask = { .d32 = 0};
5262 +
5263 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
5264 +
5265 + /* IN endpoint */
5266 + if (ep->is_in == 1) {
5267 + dwc_otg_dev_in_ep_regs_t *in_regs =
5268 + core_if->dev_if->in_ep_regs[ep->num];
5269 +
5270 + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
5271 + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
5272 +
5273 + deptsiz.b.xfersize = 0;
5274 + deptsiz.b.pktcnt = 1;
5275 +
5276 +
5277 + /* Write the DMA register */
5278 + if (core_if->dma_enable) {
5279 + if (core_if->dma_desc_enable == 0) {
5280 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5281 + dwc_write_reg32 (&(in_regs->diepdma),
5282 + (uint32_t)ep->dma_addr);
5283 + }
5284 + }
5285 + else {
5286 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5287 + /**
5288 + * Enable the Non-Periodic Tx FIFO empty interrupt,
5289 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
5290 + * the data will be written into the fifo by the ISR.
5291 + */
5292 + if(core_if->en_multiple_tx_fifo == 0) {
5293 + intr_mask.b.nptxfempty = 1;
5294 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5295 + intr_mask.d32, intr_mask.d32);
5296 + }
5297 + else {
5298 + /* Enable the Tx FIFO Empty Interrupt for this EP */
5299 + if(ep->xfer_len > 0) {
5300 + uint32_t fifoemptymsk = 0;
5301 + fifoemptymsk = 1 << ep->num;
5302 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5303 + 0, fifoemptymsk);
5304 + }
5305 + }
5306 + }
5307 +
5308 + /* EP enable, IN data in FIFO */
5309 + depctl.b.cnak = 1;
5310 + depctl.b.epena = 1;
5311 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5312 +
5313 + depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
5314 + depctl.b.nextep = ep->num;
5315 + dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
5316 +
5317 + }
5318 + else {
5319 + /* OUT endpoint */
5320 + dwc_otg_dev_out_ep_regs_t *out_regs =
5321 + core_if->dev_if->out_ep_regs[ep->num];
5322 +
5323 + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
5324 + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
5325 +
5326 + /* Zero Length Packet */
5327 + deptsiz.b.xfersize = ep->maxpacket;
5328 + deptsiz.b.pktcnt = 1;
5329 +
5330 + if (core_if->dma_enable) {
5331 + if (!core_if->dma_desc_enable) {
5332 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5333 +
5334 + dwc_write_reg32 (&(out_regs->doepdma),
5335 + (uint32_t)ep->dma_addr);
5336 + }
5337 + }
5338 + else {
5339 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5340 + }
5341 +
5342 + /* EP enable */
5343 + depctl.b.cnak = 1;
5344 + depctl.b.epena = 1;
5345 +
5346 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
5347 +
5348 + }
5349 +}
5350 +
5351 +/**
5352 + * This function does the setup for a data transfer for EP0 and starts
5353 + * the transfer. For an IN transfer, the packets will be loaded into
5354 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
5355 + * unloaded from the Rx FIFO in the ISR.
5356 + *
5357 + * @param core_if Programming view of DWC_otg controller.
5358 + * @param ep The EP0 data.
5359 + */
5360 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5361 +{
5362 + depctl_data_t depctl;
5363 + deptsiz0_data_t deptsiz;
5364 + gintmsk_data_t intr_mask = { .d32 = 0};
5365 + dwc_otg_dma_desc_t* dma_desc;
5366 +
5367 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
5368 + "xfer_buff=%p start_xfer_buff=%p \n",
5369 + ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
5370 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
5371 +
5372 + ep->total_len = ep->xfer_len;
5373 +
5374 + /* IN endpoint */
5375 + if (ep->is_in == 1) {
5376 + dwc_otg_dev_in_ep_regs_t *in_regs =
5377 + core_if->dev_if->in_ep_regs[0];
5378 +
5379 + gnptxsts_data_t gtxstatus;
5380 +
5381 + gtxstatus.d32 =
5382 + dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
5383 +
5384 + if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
5385 +#ifdef DEBUG
5386 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
5387 + DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
5388 + dwc_read_reg32(&in_regs->diepctl));
5389 + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
5390 + deptsiz.d32,
5391 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
5392 + DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n",
5393 + gtxstatus.d32);
5394 +#endif
5395 + return;
5396 + }
5397 +
5398 +
5399 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
5400 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
5401 +
5402 + /* Zero Length Packet? */
5403 + if (ep->xfer_len == 0) {
5404 + deptsiz.b.xfersize = 0;
5405 + deptsiz.b.pktcnt = 1;
5406 + }
5407 + else {
5408 + /* Program the transfer size and packet count
5409 + * as follows: xfersize = N * maxpacket +
5410 + * short_packet pktcnt = N + (short_packet
5411 + * exist ? 1 : 0)
5412 + */
5413 + if (ep->xfer_len > ep->maxpacket) {
5414 + ep->xfer_len = ep->maxpacket;
5415 + deptsiz.b.xfersize = ep->maxpacket;
5416 + }
5417 + else {
5418 + deptsiz.b.xfersize = ep->xfer_len;
5419 + }
5420 + deptsiz.b.pktcnt = 1;
5421 +
5422 + }
5423 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
5424 + ep->xfer_len,
5425 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
5426 +
5427 + /* Write the DMA register */
5428 + if (core_if->dma_enable) {
5429 + if(core_if->dma_desc_enable == 0) {
5430 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5431 +
5432 + dwc_write_reg32 (&(in_regs->diepdma),
5433 + (uint32_t)ep->dma_addr);
5434 + }
5435 + else {
5436 + dma_desc = core_if->dev_if->in_desc_addr;
5437 +
5438 + /** DMA Descriptor Setup */
5439 + dma_desc->status.b.bs = BS_HOST_BUSY;
5440 + dma_desc->status.b.l = 1;
5441 + dma_desc->status.b.ioc = 1;
5442 + dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
5443 + dma_desc->status.b.bytes = ep->xfer_len;
5444 + dma_desc->buf = ep->dma_addr;
5445 + dma_desc->status.b.bs = BS_HOST_READY;
5446 +
5447 + /** DIEPDMA0 Register write */
5448 + dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
5449 + }
5450 + }
5451 + else {
5452 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5453 + }
5454 +
5455 + /* EP enable, IN data in FIFO */
5456 + depctl.b.cnak = 1;
5457 + depctl.b.epena = 1;
5458 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5459 +
5460 + /**
5461 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
5462 + * data will be written into the fifo by the ISR.
5463 + */
5464 + if (!core_if->dma_enable) {
5465 + if(core_if->en_multiple_tx_fifo == 0) {
5466 + intr_mask.b.nptxfempty = 1;
5467 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5468 + intr_mask.d32, intr_mask.d32);
5469 + }
5470 + else {
5471 + /* Enable the Tx FIFO Empty Interrupt for this EP */
5472 + if(ep->xfer_len > 0) {
5473 + uint32_t fifoemptymsk = 0;
5474 + fifoemptymsk |= 1 << ep->num;
5475 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5476 + 0, fifoemptymsk);
5477 + }
5478 + }
5479 + }
5480 + }
5481 + else {
5482 + /* OUT endpoint */
5483 + dwc_otg_dev_out_ep_regs_t *out_regs =
5484 + core_if->dev_if->out_ep_regs[0];
5485 +
5486 + depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
5487 + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
5488 +
5489 + /* Program the transfer size and packet count as follows:
5490 + * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
5491 + * pktcnt = N */
5492 + /* Zero Length Packet */
5493 + deptsiz.b.xfersize = ep->maxpacket;
5494 + deptsiz.b.pktcnt = 1;
5495 +
5496 + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
5497 + ep->xfer_len,
5498 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
5499 +
5500 + if (core_if->dma_enable) {
5501 + if(!core_if->dma_desc_enable) {
5502 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5503 +
5504 + dwc_write_reg32 (&(out_regs->doepdma),
5505 + (uint32_t)ep->dma_addr);
5506 + }
5507 + else {
5508 + dma_desc = core_if->dev_if->out_desc_addr;
5509 +
5510 + /** DMA Descriptor Setup */
5511 + dma_desc->status.b.bs = BS_HOST_BUSY;
5512 + dma_desc->status.b.l = 1;
5513 + dma_desc->status.b.ioc = 1;
5514 + dma_desc->status.b.bytes = ep->maxpacket;
5515 + dma_desc->buf = ep->dma_addr;
5516 + dma_desc->status.b.bs = BS_HOST_READY;
5517 +
5518 + /** DOEPDMA0 Register write */
5519 + dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
5520 + }
5521 + }
5522 + else {
5523 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5524 + }
5525 +
5526 + /* EP enable */
5527 + depctl.b.cnak = 1;
5528 + depctl.b.epena = 1;
5529 + dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
5530 + }
5531 +}
5532 +
5533 +/**
5534 + * This function continues control IN transfers started by
5535 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
5536 + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
5537 + * bit for the packet count.
5538 + *
5539 + * @param core_if Programming view of DWC_otg controller.
5540 + * @param ep The EP0 data.
5541 + */
5542 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5543 +{
5544 + depctl_data_t depctl;
5545 + deptsiz0_data_t deptsiz;
5546 + gintmsk_data_t intr_mask = { .d32 = 0};
5547 + dwc_otg_dma_desc_t* dma_desc;
5548 +
5549 + if (ep->is_in == 1) {
5550 + dwc_otg_dev_in_ep_regs_t *in_regs =
5551 + core_if->dev_if->in_ep_regs[0];
5552 + gnptxsts_data_t tx_status = { .d32 = 0 };
5553 +
5554 + tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
5555 + /** @todo Should there be check for room in the Tx
5556 + * Status Queue. If not remove the code above this comment. */
5557 +
5558 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
5559 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
5560 +
5561 + /* Program the transfer size and packet count
5562 + * as follows: xfersize = N * maxpacket +
5563 + * short_packet pktcnt = N + (short_packet
5564 + * exist ? 1 : 0)
5565 + */
5566 +
5567 +
5568 + if(core_if->dma_desc_enable == 0) {
5569 + deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
5570 + (ep->total_len - ep->xfer_count);
5571 + deptsiz.b.pktcnt = 1;
5572 + if(core_if->dma_enable == 0) {
5573 + ep->xfer_len += deptsiz.b.xfersize;
5574 + } else {
5575 + ep->xfer_len = deptsiz.b.xfersize;
5576 + }
5577 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
5578 + }
5579 + else {
5580 + ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
5581 + (ep->total_len - ep->xfer_count);
5582 +
5583 + dma_desc = core_if->dev_if->in_desc_addr;
5584 +
5585 + /** DMA Descriptor Setup */
5586 + dma_desc->status.b.bs = BS_HOST_BUSY;
5587 + dma_desc->status.b.l = 1;
5588 + dma_desc->status.b.ioc = 1;
5589 + dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
5590 + dma_desc->status.b.bytes = ep->xfer_len;
5591 + dma_desc->buf = ep->dma_addr;
5592 + dma_desc->status.b.bs = BS_HOST_READY;
5593 +
5594 + /** DIEPDMA0 Register write */
5595 + dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
5596 + }
5597 +
5598 +
5599 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
5600 + ep->xfer_len,
5601 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
5602 +
5603 + /* Write the DMA register */
5604 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
5605 + if(core_if->dma_desc_enable == 0)
5606 + dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr);
5607 + }
5608 +
5609 + /* EP enable, IN data in FIFO */
5610 + depctl.b.cnak = 1;
5611 + depctl.b.epena = 1;
5612 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
5613 +
5614 + /**
5615 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
5616 + * data will be written into the fifo by the ISR.
5617 + */
5618 + if (!core_if->dma_enable) {
5619 + if(core_if->en_multiple_tx_fifo == 0) {
5620 + /* First clear it from GINTSTS */
5621 + intr_mask.b.nptxfempty = 1;
5622 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
5623 + intr_mask.d32, intr_mask.d32);
5624 +
5625 + }
5626 + else {
5627 + /* Enable the Tx FIFO Empty Interrupt for this EP */
5628 + if(ep->xfer_len > 0) {
5629 + uint32_t fifoemptymsk = 0;
5630 + fifoemptymsk |= 1 << ep->num;
5631 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
5632 + 0, fifoemptymsk);
5633 + }
5634 + }
5635 + }
5636 + }
5637 + else {
5638 + dwc_otg_dev_out_ep_regs_t *out_regs =
5639 + core_if->dev_if->out_ep_regs[0];
5640 +
5641 +
5642 + depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
5643 + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
5644 +
5645 + /* Program the transfer size and packet count
5646 + * as follows: xfersize = N * maxpacket +
5647 + * short_packet pktcnt = N + (short_packet
5648 + * exist ? 1 : 0)
5649 + */
5650 + deptsiz.b.xfersize = ep->maxpacket;
5651 + deptsiz.b.pktcnt = 1;
5652 +
5653 +
5654 + if(core_if->dma_desc_enable == 0) {
5655 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
5656 + }
5657 + else {
5658 + dma_desc = core_if->dev_if->out_desc_addr;
5659 +
5660 + /** DMA Descriptor Setup */
5661 + dma_desc->status.b.bs = BS_HOST_BUSY;
5662 + dma_desc->status.b.l = 1;
5663 + dma_desc->status.b.ioc = 1;
5664 + dma_desc->status.b.bytes = ep->maxpacket;
5665 + dma_desc->buf = ep->dma_addr;
5666 + dma_desc->status.b.bs = BS_HOST_READY;
5667 +
5668 + /** DOEPDMA0 Register write */
5669 + dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
5670 + }
5671 +
5672 +
5673 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
5674 + ep->xfer_len,
5675 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
5676 +
5677 + /* Write the DMA register */
5678 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
5679 + if(core_if->dma_desc_enable == 0)
5680 + dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr);
5681 + }
5682 +
5683 + /* EP enable, IN data in FIFO */
5684 + depctl.b.cnak = 1;
5685 + depctl.b.epena = 1;
5686 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
5687 +
5688 + }
5689 +}
5690 +
5691 +#ifdef DEBUG
5692 +void dump_msg(const u8 *buf, unsigned int length)
5693 +{
5694 + unsigned int start, num, i;
5695 + char line[52], *p;
5696 +
5697 + if (length >= 512)
5698 + return;
5699 + start = 0;
5700 + while (length > 0) {
5701 + num = min(length, 16u);
5702 + p = line;
5703 + for (i = 0; i < num; ++i)
5704 + {
5705 + if (i == 8)
5706 + *p++ = ' ';
5707 + sprintf(p, " %02x", buf[i]);
5708 + p += 3;
5709 + }
5710 + *p = 0;
5711 + DWC_PRINT("%6x: %s\n", start, line);
5712 + buf += num;
5713 + start += num;
5714 + length -= num;
5715 + }
5716 +}
5717 +#else
5718 +static inline void dump_msg(const u8 *buf, unsigned int length)
5719 +{
5720 +}
5721 +#endif
5722 +
5723 +/**
5724 + * This function writes a packet into the Tx FIFO associated with the
5725 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
5726 + * periodic EPs the periodic Tx FIFO associated with the EP is written
5727 + * with all packets for the next micro-frame.
5728 + *
5729 + * @param core_if Programming view of DWC_otg controller.
5730 + * @param ep The EP to write packet for.
5731 + * @param dma Indicates if DMA is being used.
5732 + */
5733 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
5734 +{
5735 + /**
5736 + * The buffer is padded to DWORD on a per packet basis in
5737 + * slave/dma mode if the MPS is not DWORD aligned. The last
5738 + * packet, if short, is also padded to a multiple of DWORD.
5739 + *
5740 + * ep->xfer_buff always starts DWORD aligned in memory and is a
5741 + * multiple of DWORD in length
5742 + *
5743 + * ep->xfer_len can be any number of bytes
5744 + *
5745 + * ep->xfer_count is a multiple of ep->maxpacket until the last
5746 + * packet
5747 + *
5748 + * FIFO access is DWORD */
5749 +
5750 + uint32_t i;
5751 + uint32_t byte_count;
5752 + uint32_t dword_count;
5753 + uint32_t *fifo;
5754 + uint32_t *data_buff = (uint32_t *)ep->xfer_buff;
5755 +
5756 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep);
5757 + if (ep->xfer_count >= ep->xfer_len) {
5758 + DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
5759 + return;
5760 + }
5761 +
5762 + /* Find the byte length of the packet either short packet or MPS */
5763 + if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
5764 + byte_count = ep->xfer_len - ep->xfer_count;
5765 + }
5766 + else {
5767 + byte_count = ep->maxpacket;
5768 + }
5769 +
5770 + /* Find the DWORD length, padded by extra bytes as neccessary if MPS
5771 + * is not a multiple of DWORD */
5772 + dword_count = (byte_count + 3) / 4;
5773 +
5774 +#ifdef VERBOSE
5775 + dump_msg(ep->xfer_buff, byte_count);
5776 +#endif
5777 +
5778 + /**@todo NGS Where are the Periodic Tx FIFO addresses
5779 + * intialized? What should this be? */
5780 +
5781 + fifo = core_if->data_fifo[ep->num];
5782 +
5783 +
5784 + DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count);
5785 +
5786 + if (!dma) {
5787 + for (i=0; i<dword_count; i++, data_buff++) {
5788 + dwc_write_reg32(fifo, *data_buff);
5789 + }
5790 + }
5791 +
5792 + ep->xfer_count += byte_count;
5793 + ep->xfer_buff += byte_count;
5794 + ep->dma_addr += byte_count;
5795 +}
5796 +
5797 +/**
5798 + * Set the EP STALL.
5799 + *
5800 + * @param core_if Programming view of DWC_otg controller.
5801 + * @param ep The EP to set the stall on.
5802 + */
5803 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5804 +{
5805 + depctl_data_t depctl;
5806 + volatile uint32_t *depctl_addr;
5807 +
5808 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5809 + (ep->is_in?"IN":"OUT"));
5810 +
5811 + DWC_PRINT("%s ep%d-%s\n", __func__, ep->num,
5812 + (ep->is_in?"in":"out"));
5813 +
5814 + if (ep->is_in == 1) {
5815 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5816 + depctl.d32 = dwc_read_reg32(depctl_addr);
5817 +
5818 + /* set the disable and stall bits */
5819 + if (depctl.b.epena) {
5820 + depctl.b.epdis = 1;
5821 + }
5822 + depctl.b.stall = 1;
5823 + dwc_write_reg32(depctl_addr, depctl.d32);
5824 + }
5825 + else {
5826 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5827 + depctl.d32 = dwc_read_reg32(depctl_addr);
5828 +
5829 + /* set the stall bit */
5830 + depctl.b.stall = 1;
5831 + dwc_write_reg32(depctl_addr, depctl.d32);
5832 + }
5833 +
5834 + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
5835 +
5836 + return;
5837 +}
5838 +
5839 +/**
5840 + * Clear the EP STALL.
5841 + *
5842 + * @param core_if Programming view of DWC_otg controller.
5843 + * @param ep The EP to clear stall from.
5844 + */
5845 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5846 +{
5847 + depctl_data_t depctl;
5848 + volatile uint32_t *depctl_addr;
5849 +
5850 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5851 + (ep->is_in?"IN":"OUT"));
5852 +
5853 + if (ep->is_in == 1) {
5854 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5855 + }
5856 + else {
5857 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5858 + }
5859 +
5860 + depctl.d32 = dwc_read_reg32(depctl_addr);
5861 +
5862 + /* clear the stall bits */
5863 + depctl.b.stall = 0;
5864 +
5865 + /*
5866 + * USB Spec 9.4.5: For endpoints using data toggle, regardless
5867 + * of whether an endpoint has the Halt feature set, a
5868 + * ClearFeature(ENDPOINT_HALT) request always results in the
5869 + * data toggle being reinitialized to DATA0.
5870 + */
5871 + if (ep->type == DWC_OTG_EP_TYPE_INTR ||
5872 + ep->type == DWC_OTG_EP_TYPE_BULK) {
5873 + depctl.b.setd0pid = 1; /* DATA0 */
5874 + }
5875 +
5876 + dwc_write_reg32(depctl_addr, depctl.d32);
5877 + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
5878 + return;
5879 +}
5880 +
5881 +/**
5882 + * This function reads a packet from the Rx FIFO into the destination
5883 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
5884 + *
5885 + * @param core_if Programming view of DWC_otg controller.
5886 + * @param dest Destination buffer for the packet.
5887 + * @param bytes Number of bytes to copy to the destination.
5888 + */
5889 +void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
5890 + uint8_t *dest,
5891 + uint16_t bytes)
5892 +{
5893 + int i;
5894 + int word_count = (bytes + 3) / 4;
5895 +
5896 + volatile uint32_t *fifo = core_if->data_fifo[0];
5897 + uint32_t *data_buff = (uint32_t *)dest;
5898 +
5899 + /**
5900 + * @todo Account for the case where _dest is not dword aligned. This
5901 + * requires reading data from the FIFO into a uint32_t temp buffer,
5902 + * then moving it into the data buffer.
5903 + */
5904 +
5905 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
5906 + core_if, dest, bytes);
5907 +
5908 + for (i=0; i<word_count; i++, data_buff++)
5909 + {
5910 + *data_buff = dwc_read_reg32(fifo);
5911 + }
5912 +
5913 + return;
5914 +}
5915 +
5916 +
5917 +
5918 +/**
5919 + * This functions reads the device registers and prints them
5920 + *
5921 + * @param core_if Programming view of DWC_otg controller.
5922 + */
5923 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
5924 +{
5925 + int i;
5926 + volatile uint32_t *addr;
5927 +
5928 + DWC_PRINT("Device Global Registers\n");
5929 + addr=&core_if->dev_if->dev_global_regs->dcfg;
5930 + DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5931 + addr=&core_if->dev_if->dev_global_regs->dctl;
5932 + DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5933 + addr=&core_if->dev_if->dev_global_regs->dsts;
5934 + DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5935 + addr=&core_if->dev_if->dev_global_regs->diepmsk;
5936 + DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5937 + addr=&core_if->dev_if->dev_global_regs->doepmsk;
5938 + DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5939 + addr=&core_if->dev_if->dev_global_regs->daint;
5940 + DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5941 + addr=&core_if->dev_if->dev_global_regs->daintmsk;
5942 + DWC_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5943 + addr=&core_if->dev_if->dev_global_regs->dtknqr1;
5944 + DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5945 + if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
5946 + addr=&core_if->dev_if->dev_global_regs->dtknqr2;
5947 + DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n",
5948 + (uint32_t)addr,dwc_read_reg32(addr));
5949 + }
5950 +
5951 + addr=&core_if->dev_if->dev_global_regs->dvbusdis;
5952 + DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5953 +
5954 + addr=&core_if->dev_if->dev_global_regs->dvbuspulse;
5955 + DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n",
5956 + (uint32_t)addr,dwc_read_reg32(addr));
5957 +
5958 + if (core_if->hwcfg2.b.dev_token_q_depth > 14) {
5959 + addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
5960 + DWC_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n",
5961 + (uint32_t)addr, dwc_read_reg32(addr));
5962 + }
5963 +/*
5964 + if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
5965 + addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5966 + DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n",
5967 + (uint32_t)addr, dwc_read_reg32(addr));
5968 + }
5969 +*/
5970 + addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5971 + DWC_PRINT("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr));
5972 +
5973 + addr=&core_if->dev_if->dev_global_regs->deachint;
5974 + DWC_PRINT("DEACHINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5975 + addr=&core_if->dev_if->dev_global_regs->deachintmsk;
5976 + DWC_PRINT("DEACHINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5977 +
5978 + for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
5979 + addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i];
5980 + DWC_PRINT("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
5981 + }
5982 +
5983 +
5984 + for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
5985 + addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i];
5986 + DWC_PRINT("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
5987 + }
5988 +
5989 + for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
5990 + DWC_PRINT("Device IN EP %d Registers\n", i);
5991 + addr=&core_if->dev_if->in_ep_regs[i]->diepctl;
5992 + DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5993 + addr=&core_if->dev_if->in_ep_regs[i]->diepint;
5994 + DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5995 + addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz;
5996 + DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5997 + addr=&core_if->dev_if->in_ep_regs[i]->diepdma;
5998 + DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
5999 + addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts;
6000 + DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6001 + addr=&core_if->dev_if->in_ep_regs[i]->diepdmab;
6002 + DWC_PRINT("DIEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6003 + }
6004 +
6005 +
6006 + for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
6007 + DWC_PRINT("Device OUT EP %d Registers\n", i);
6008 + addr=&core_if->dev_if->out_ep_regs[i]->doepctl;
6009 + DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6010 + addr=&core_if->dev_if->out_ep_regs[i]->doepfn;
6011 + DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6012 + addr=&core_if->dev_if->out_ep_regs[i]->doepint;
6013 + DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6014 + addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz;
6015 + DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6016 + addr=&core_if->dev_if->out_ep_regs[i]->doepdma;
6017 + DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6018 + addr=&core_if->dev_if->out_ep_regs[i]->doepdmab;
6019 + DWC_PRINT("DOEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6020 +
6021 + }
6022 +
6023 +
6024 +
6025 + return;
6026 +}
6027 +
6028 +/**
6029 + * This functions reads the SPRAM and prints its content
6030 + *
6031 + * @param core_if Programming view of DWC_otg controller.
6032 + */
6033 +void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
6034 +{
6035 + volatile uint8_t *addr, *start_addr, *end_addr;
6036 +
6037 + DWC_PRINT("SPRAM Data:\n");
6038 + start_addr = (void*)core_if->core_global_regs;
6039 + DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
6040 + start_addr += 0x00028000;
6041 + end_addr=(void*)core_if->core_global_regs;
6042 + end_addr += 0x000280e0;
6043 +
6044 + for(addr = start_addr; addr < end_addr; addr+=16)
6045 + {
6046 + DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr,
6047 + addr[0],
6048 + addr[1],
6049 + addr[2],
6050 + addr[3],
6051 + addr[4],
6052 + addr[5],
6053 + addr[6],
6054 + addr[7],
6055 + addr[8],
6056 + addr[9],
6057 + addr[10],
6058 + addr[11],
6059 + addr[12],
6060 + addr[13],
6061 + addr[14],
6062 + addr[15]
6063 + );
6064 + }
6065 +
6066 + return;
6067 +}
6068 +/**
6069 + * This function reads the host registers and prints them
6070 + *
6071 + * @param core_if Programming view of DWC_otg controller.
6072 + */
6073 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
6074 +{
6075 + int i;
6076 + volatile uint32_t *addr;
6077 +
6078 + DWC_PRINT("Host Global Registers\n");
6079 + addr=&core_if->host_if->host_global_regs->hcfg;
6080 + DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6081 + addr=&core_if->host_if->host_global_regs->hfir;
6082 + DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6083 + addr=&core_if->host_if->host_global_regs->hfnum;
6084 + DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6085 + addr=&core_if->host_if->host_global_regs->hptxsts;
6086 + DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6087 + addr=&core_if->host_if->host_global_regs->haint;
6088 + DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6089 + addr=&core_if->host_if->host_global_regs->haintmsk;
6090 + DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6091 + addr=core_if->host_if->hprt0;
6092 + DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6093 +
6094 + for (i=0; i<core_if->core_params->host_channels; i++)
6095 + {
6096 + DWC_PRINT("Host Channel %d Specific Registers\n", i);
6097 + addr=&core_if->host_if->hc_regs[i]->hcchar;
6098 + DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6099 + addr=&core_if->host_if->hc_regs[i]->hcsplt;
6100 + DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6101 + addr=&core_if->host_if->hc_regs[i]->hcint;
6102 + DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6103 + addr=&core_if->host_if->hc_regs[i]->hcintmsk;
6104 + DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6105 + addr=&core_if->host_if->hc_regs[i]->hctsiz;
6106 + DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6107 + addr=&core_if->host_if->hc_regs[i]->hcdma;
6108 + DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6109 + }
6110 + return;
6111 +}
6112 +
6113 +/**
6114 + * This function reads the core global registers and prints them
6115 + *
6116 + * @param core_if Programming view of DWC_otg controller.
6117 + */
6118 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
6119 +{
6120 + int i;
6121 + volatile uint32_t *addr;
6122 +
6123 + DWC_PRINT("Core Global Registers\n");
6124 + addr=&core_if->core_global_regs->gotgctl;
6125 + DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6126 + addr=&core_if->core_global_regs->gotgint;
6127 + DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6128 + addr=&core_if->core_global_regs->gahbcfg;
6129 + DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6130 + addr=&core_if->core_global_regs->gusbcfg;
6131 + DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6132 + addr=&core_if->core_global_regs->grstctl;
6133 + DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6134 + addr=&core_if->core_global_regs->gintsts;
6135 + DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6136 + addr=&core_if->core_global_regs->gintmsk;
6137 + DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6138 + addr=&core_if->core_global_regs->grxstsr;
6139 + DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6140 + //addr=&core_if->core_global_regs->grxstsp;
6141 + //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6142 + addr=&core_if->core_global_regs->grxfsiz;
6143 + DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6144 + addr=&core_if->core_global_regs->gnptxfsiz;
6145 + DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6146 + addr=&core_if->core_global_regs->gnptxsts;
6147 + DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6148 + addr=&core_if->core_global_regs->gi2cctl;
6149 + DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6150 + addr=&core_if->core_global_regs->gpvndctl;
6151 + DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6152 + addr=&core_if->core_global_regs->ggpio;
6153 + DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6154 + addr=&core_if->core_global_regs->guid;
6155 + DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6156 + addr=&core_if->core_global_regs->gsnpsid;
6157 + DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6158 + addr=&core_if->core_global_regs->ghwcfg1;
6159 + DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6160 + addr=&core_if->core_global_regs->ghwcfg2;
6161 + DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6162 + addr=&core_if->core_global_regs->ghwcfg3;
6163 + DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6164 + addr=&core_if->core_global_regs->ghwcfg4;
6165 + DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6166 + addr=&core_if->core_global_regs->hptxfsiz;
6167 + DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
6168 +
6169 + for (i=0; i<core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
6170 + {
6171 + addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i];
6172 + DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr));
6173 + }
6174 +}
6175 +
6176 +/**
6177 + * Flush a Tx FIFO.
6178 + *
6179 + * @param core_if Programming view of DWC_otg controller.
6180 + * @param num Tx FIFO to flush.
6181 + */
6182 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if,
6183 + const int num)
6184 +{
6185 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
6186 + volatile grstctl_t greset = { .d32 = 0};
6187 + int count = 0;
6188 +
6189 + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num);
6190 +
6191 + greset.b.txfflsh = 1;
6192 + greset.b.txfnum = num;
6193 + dwc_write_reg32(&global_regs->grstctl, greset.d32);
6194 +
6195 + do {
6196 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6197 + if (++count > 10000) {
6198 + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
6199 + __func__, greset.d32,
6200 + dwc_read_reg32(&global_regs->gnptxsts));
6201 + break;
6202 + }
6203 + }
6204 + while (greset.b.txfflsh == 1);
6205 +
6206 + /* Wait for 3 PHY Clocks*/
6207 + UDELAY(1);
6208 +}
6209 +
6210 +/**
6211 + * Flush Rx FIFO.
6212 + *
6213 + * @param core_if Programming view of DWC_otg controller.
6214 + */
6215 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
6216 +{
6217 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
6218 + volatile grstctl_t greset = { .d32 = 0};
6219 + int count = 0;
6220 +
6221 + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
6222 + /*
6223 + *
6224 + */
6225 + greset.b.rxfflsh = 1;
6226 + dwc_write_reg32(&global_regs->grstctl, greset.d32);
6227 +
6228 + do {
6229 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6230 + if (++count > 10000) {
6231 + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
6232 + greset.d32);
6233 + break;
6234 + }
6235 + }
6236 + while (greset.b.rxfflsh == 1);
6237 +
6238 + /* Wait for 3 PHY Clocks*/
6239 + UDELAY(1);
6240 +}
6241 +
6242 +/**
6243 + * Do core a soft reset of the core. Be careful with this because it
6244 + * resets all the internal state machines of the core.
6245 + */
6246 +void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
6247 +{
6248 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
6249 + volatile grstctl_t greset = { .d32 = 0};
6250 + int count = 0;
6251 +
6252 + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
6253 + /* Wait for AHB master IDLE state. */
6254 + do {
6255 + UDELAY(10);
6256 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6257 + if (++count > 100000) {
6258 + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
6259 + greset.d32);
6260 + return;
6261 + }
6262 + }
6263 + while (greset.b.ahbidle == 0);
6264 +
6265 + /* Core Soft Reset */
6266 + count = 0;
6267 + greset.b.csftrst = 1;
6268 + dwc_write_reg32(&global_regs->grstctl, greset.d32);
6269 + do {
6270 + greset.d32 = dwc_read_reg32(&global_regs->grstctl);
6271 + if (++count > 10000) {
6272 + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
6273 + greset.d32);
6274 + break;
6275 + }
6276 + }
6277 + while (greset.b.csftrst == 1);
6278 +
6279 + /* Wait for 3 PHY Clocks*/
6280 + MDELAY(100);
6281 +}
6282 +
6283 +
6284 +
6285 +/**
6286 + * Register HCD callbacks. The callbacks are used to start and stop
6287 + * the HCD for interrupt processing.
6288 + *
6289 + * @param core_if Programming view of DWC_otg controller.
6290 + * @param cb the HCD callback structure.
6291 + * @param p pointer to be passed to callback function (usb_hcd*).
6292 + */
6293 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
6294 + dwc_otg_cil_callbacks_t *cb,
6295 + void *p)
6296 +{
6297 + core_if->hcd_cb = cb;
6298 + cb->p = p;
6299 +}
6300 +
6301 +/**
6302 + * Register PCD callbacks. The callbacks are used to start and stop
6303 + * the PCD for interrupt processing.
6304 + *
6305 + * @param core_if Programming view of DWC_otg controller.
6306 + * @param cb the PCD callback structure.
6307 + * @param p pointer to be passed to callback function (pcd*).
6308 + */
6309 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
6310 + dwc_otg_cil_callbacks_t *cb,
6311 + void *p)
6312 +{
6313 + core_if->pcd_cb = cb;
6314 + cb->p = p;
6315 +}
6316 +
6317 +#ifdef DWC_EN_ISOC
6318 +
6319 +/**
6320 + * This function writes isoc data per 1 (micro)frame into tx fifo
6321 + *
6322 + * @param core_if Programming view of DWC_otg controller.
6323 + * @param ep The EP to start the transfer on.
6324 + *
6325 + */
6326 +void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
6327 +{
6328 + dwc_otg_dev_in_ep_regs_t *ep_regs;
6329 + dtxfsts_data_t txstatus = {.d32 = 0};
6330 + uint32_t len = 0;
6331 + uint32_t dwords;
6332 +
6333 + ep->xfer_len = ep->data_per_frame;
6334 + ep->xfer_count = 0;
6335 +
6336 + ep_regs = core_if->dev_if->in_ep_regs[ep->num];
6337 +
6338 + len = ep->xfer_len - ep->xfer_count;
6339 +
6340 + if (len > ep->maxpacket) {
6341 + len = ep->maxpacket;
6342 + }
6343 +
6344 + dwords = (len + 3)/4;
6345 +
6346 + /* While there is space in the queue and space in the FIFO and
6347 + * More data to tranfer, Write packets to the Tx FIFO */
6348 + txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
6349 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32);
6350 +
6351 + while (txstatus.b.txfspcavail > dwords &&
6352 + ep->xfer_count < ep->xfer_len &&
6353 + ep->xfer_len != 0) {
6354 + /* Write the FIFO */
6355 + dwc_otg_ep_write_packet(core_if, ep, 0);
6356 +
6357 + len = ep->xfer_len - ep->xfer_count;
6358 + if (len > ep->maxpacket) {
6359 + len = ep->maxpacket;
6360 + }
6361 +
6362 + dwords = (len + 3)/4;
6363 + txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
6364 + DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
6365 + }
6366 +}
6367 +
6368 +
6369 +/**
6370 + * This function initializes a descriptor chain for Isochronous transfer
6371 + *
6372 + * @param core_if Programming view of DWC_otg controller.
6373 + * @param ep The EP to start the transfer on.
6374 + *
6375 + */
6376 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
6377 +{
6378 + deptsiz_data_t deptsiz = { .d32 = 0 };
6379 + depctl_data_t depctl = { .d32 = 0 };
6380 + dsts_data_t dsts = { .d32 = 0 };
6381 + volatile uint32_t *addr;
6382 +
6383 + if(ep->is_in) {
6384 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
6385 + } else {
6386 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
6387 + }
6388 +
6389 + ep->xfer_len = ep->data_per_frame;
6390 + ep->xfer_count = 0;
6391 + ep->xfer_buff = ep->cur_pkt_addr;
6392 + ep->dma_addr = ep->cur_pkt_dma_addr;
6393 +
6394 + if(ep->is_in) {
6395 + /* Program the transfer size and packet count
6396 + * as follows: xfersize = N * maxpacket +
6397 + * short_packet pktcnt = N + (short_packet
6398 + * exist ? 1 : 0)
6399 + */
6400 + deptsiz.b.xfersize = ep->xfer_len;
6401 + deptsiz.b.pktcnt =
6402 + (ep->xfer_len - 1 + ep->maxpacket) /
6403 + ep->maxpacket;
6404 + deptsiz.b.mc = deptsiz.b.pktcnt;
6405 + dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
6406 +
6407 + /* Write the DMA register */
6408 + if (core_if->dma_enable) {
6409 + dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
6410 + }
6411 + } else {
6412 + deptsiz.b.pktcnt =
6413 + (ep->xfer_len + (ep->maxpacket - 1)) /
6414 + ep->maxpacket;
6415 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
6416 +
6417 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
6418 +
6419 + if (core_if->dma_enable) {
6420 + dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma),
6421 + (uint32_t)ep->dma_addr);
6422 + }
6423 + }
6424 +
6425 +
6426 + /** Enable endpoint, clear nak */
6427 +
6428 + depctl.d32 = 0;
6429 + if(ep->bInterval == 1) {
6430 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
6431 + ep->next_frame = dsts.b.soffn + ep->bInterval;
6432 +
6433 + if(ep->next_frame & 0x1) {
6434 + depctl.b.setd1pid = 1;
6435 + } else {
6436 + depctl.b.setd0pid = 1;
6437 + }
6438 + } else {
6439 + ep->next_frame += ep->bInterval;
6440 +
6441 + if(ep->next_frame & 0x1) {
6442 + depctl.b.setd1pid = 1;
6443 + } else {
6444 + depctl.b.setd0pid = 1;
6445 + }
6446 + }
6447 + depctl.b.epena = 1;
6448 + depctl.b.cnak = 1;
6449 +
6450 + dwc_modify_reg32(addr, 0, depctl.d32);
6451 + depctl.d32 = dwc_read_reg32(addr);
6452 +
6453 + if(ep->is_in && core_if->dma_enable == 0) {
6454 + write_isoc_frame_data(core_if, ep);
6455 + }
6456 +
6457 +}
6458 +
6459 +#endif //DWC_EN_ISOC
6460 diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.h b/drivers/usb/dwc_otg/dwc_otg_cil.h
6461 new file mode 100644
6462 index 0000000..9507992
6463 --- /dev/null
6464 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
6465 @@ -0,0 +1,1098 @@
6466 +/* ==========================================================================
6467 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
6468 + * $Revision: 1.2 $
6469 + * $Date: 2008-11-21 05:39:15 $
6470 + * $Change: 1099526 $
6471 + *
6472 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6473 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6474 + * otherwise expressly agreed to in writing between Synopsys and you.
6475 + *
6476 + * The Software IS NOT an item of Licensed Software or Licensed Product under
6477 + * any End User Software License Agreement or Agreement for Licensed Product
6478 + * with Synopsys or any supplement thereto. You are permitted to use and
6479 + * redistribute this Software in source and binary forms, with or without
6480 + * modification, provided that redistributions of source code must retain this
6481 + * notice. You may not view, use, disclose, copy or distribute this file or
6482 + * any information contained herein except pursuant to this license grant from
6483 + * Synopsys. If you do not agree with this notice, including the disclaimer
6484 + * below, then you are not authorized to use the Software.
6485 + *
6486 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6487 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6488 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6489 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6490 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6491 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
6492 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6493 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
6494 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
6495 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6496 + * DAMAGE.
6497 + * ========================================================================== */
6498 +
6499 +#if !defined(__DWC_CIL_H__)
6500 +#define __DWC_CIL_H__
6501 +
6502 +#include <linux/workqueue.h>
6503 +#include <linux/version.h>
6504 +#include <asm/param.h>
6505 +
6506 +#include "linux/dwc_otg_plat.h"
6507 +#include "dwc_otg_regs.h"
6508 +#ifdef DEBUG
6509 +#include "linux/timer.h"
6510 +#endif
6511 +
6512 +/**
6513 + * @file
6514 + * This file contains the interface to the Core Interface Layer.
6515 + */
6516 +
6517 +
6518 +/** Macros defined for DWC OTG HW Release verison */
6519 +#define OTG_CORE_REV_2_00 0x4F542000
6520 +#define OTG_CORE_REV_2_60a 0x4F54260A
6521 +#define OTG_CORE_REV_2_71a 0x4F54271A
6522 +#define OTG_CORE_REV_2_72a 0x4F54272A
6523 +
6524 +/**
6525 +*/
6526 +typedef struct iso_pkt_info
6527 +{
6528 + uint32_t offset;
6529 + uint32_t length;
6530 + int32_t status;
6531 +} iso_pkt_info_t;
6532 +/**
6533 + * The <code>dwc_ep</code> structure represents the state of a single
6534 + * endpoint when acting in device mode. It contains the data items
6535 + * needed for an endpoint to be activated and transfer packets.
6536 + */
6537 +typedef struct dwc_ep
6538 +{
6539 + /** EP number used for register address lookup */
6540 + uint8_t num;
6541 + /** EP direction 0 = OUT */
6542 + unsigned is_in : 1;
6543 + /** EP active. */
6544 + unsigned active : 1;
6545 +
6546 + /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
6547 + If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
6548 + unsigned tx_fifo_num : 4;
6549 + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
6550 + unsigned type : 2;
6551 +#define DWC_OTG_EP_TYPE_CONTROL 0
6552 +#define DWC_OTG_EP_TYPE_ISOC 1
6553 +#define DWC_OTG_EP_TYPE_BULK 2
6554 +#define DWC_OTG_EP_TYPE_INTR 3
6555 +
6556 + /** DATA start PID for INTR and BULK EP */
6557 + unsigned data_pid_start : 1;
6558 + /** Frame (even/odd) for ISOC EP */
6559 + unsigned even_odd_frame : 1;
6560 + /** Max Packet bytes */
6561 + unsigned maxpacket : 11;
6562 +
6563 + /** Max Transfer size */
6564 + unsigned maxxfer : 16;
6565 +
6566 + /** @name Transfer state */
6567 + /** @{ */
6568 +
6569 + /**
6570 + * Pointer to the beginning of the transfer buffer -- do not modify
6571 + * during transfer.
6572 + */
6573 +
6574 + uint32_t dma_addr;
6575 +
6576 + uint32_t dma_desc_addr;
6577 + dwc_otg_dma_desc_t* desc_addr;
6578 +
6579 +
6580 + uint8_t *start_xfer_buff;
6581 + /** pointer to the transfer buffer */
6582 + uint8_t *xfer_buff;
6583 + /** Number of bytes to transfer */
6584 + unsigned xfer_len : 19;
6585 + /** Number of bytes transferred. */
6586 + unsigned xfer_count : 19;
6587 + /** Sent ZLP */
6588 + unsigned sent_zlp : 1;
6589 + /** Total len for control transfer */
6590 + unsigned total_len : 19;
6591 +
6592 + /** stall clear flag */
6593 + unsigned stall_clear_flag : 1;
6594 +
6595 + /** Allocated DMA Desc count */
6596 + uint32_t desc_cnt;
6597 +
6598 +#ifdef DWC_EN_ISOC
6599 + /**
6600 + * Variables specific for ISOC EPs
6601 + *
6602 + */
6603 + /** DMA addresses of ISOC buffers */
6604 + uint32_t dma_addr0;
6605 + uint32_t dma_addr1;
6606 +
6607 + uint32_t iso_dma_desc_addr;
6608 + dwc_otg_dma_desc_t* iso_desc_addr;
6609 +
6610 + /** pointer to the transfer buffers */
6611 + uint8_t *xfer_buff0;
6612 + uint8_t *xfer_buff1;
6613 +
6614 + /** number of ISOC Buffer is processing */
6615 + uint32_t proc_buf_num;
6616 + /** Interval of ISOC Buffer processing */
6617 + uint32_t buf_proc_intrvl;
6618 + /** Data size for regular frame */
6619 + uint32_t data_per_frame;
6620 +
6621 + /* todo - pattern data support is to be implemented in the future */
6622 + /** Data size for pattern frame */
6623 + uint32_t data_pattern_frame;
6624 + /** Frame number of pattern data */
6625 + uint32_t sync_frame;
6626 +
6627 + /** bInterval */
6628 + uint32_t bInterval;
6629 + /** ISO Packet number per frame */
6630 + uint32_t pkt_per_frm;
6631 + /** Next frame num for which will be setup DMA Desc */
6632 + uint32_t next_frame;
6633 + /** Number of packets per buffer processing */
6634 + uint32_t pkt_cnt;
6635 + /** Info for all isoc packets */
6636 + iso_pkt_info_t *pkt_info;
6637 + /** current pkt number */
6638 + uint32_t cur_pkt;
6639 + /** current pkt number */
6640 + uint8_t *cur_pkt_addr;
6641 + /** current pkt number */
6642 + uint32_t cur_pkt_dma_addr;
6643 +#endif //DWC_EN_ISOC
6644 +/** @} */
6645 +} dwc_ep_t;
6646 +
6647 +/*
6648 + * Reasons for halting a host channel.
6649 + */
6650 +typedef enum dwc_otg_halt_status
6651 +{
6652 + DWC_OTG_HC_XFER_NO_HALT_STATUS,
6653 + DWC_OTG_HC_XFER_COMPLETE,
6654 + DWC_OTG_HC_XFER_URB_COMPLETE,
6655 + DWC_OTG_HC_XFER_ACK,
6656 + DWC_OTG_HC_XFER_NAK,
6657 + DWC_OTG_HC_XFER_NYET,
6658 + DWC_OTG_HC_XFER_STALL,
6659 + DWC_OTG_HC_XFER_XACT_ERR,
6660 + DWC_OTG_HC_XFER_FRAME_OVERRUN,
6661 + DWC_OTG_HC_XFER_BABBLE_ERR,
6662 + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
6663 + DWC_OTG_HC_XFER_AHB_ERR,
6664 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
6665 + DWC_OTG_HC_XFER_URB_DEQUEUE
6666 +} dwc_otg_halt_status_e;
6667 +
6668 +/**
6669 + * Host channel descriptor. This structure represents the state of a single
6670 + * host channel when acting in host mode. It contains the data items needed to
6671 + * transfer packets to an endpoint via a host channel.
6672 + */
6673 +typedef struct dwc_hc
6674 +{
6675 + /** Host channel number used for register address lookup */
6676 + uint8_t hc_num;
6677 +
6678 + /** Device to access */
6679 + unsigned dev_addr : 7;
6680 +
6681 + /** EP to access */
6682 + unsigned ep_num : 4;
6683 +
6684 + /** EP direction. 0: OUT, 1: IN */
6685 + unsigned ep_is_in : 1;
6686 +
6687 + /**
6688 + * EP speed.
6689 + * One of the following values:
6690 + * - DWC_OTG_EP_SPEED_LOW
6691 + * - DWC_OTG_EP_SPEED_FULL
6692 + * - DWC_OTG_EP_SPEED_HIGH
6693 + */
6694 + unsigned speed : 2;
6695 +#define DWC_OTG_EP_SPEED_LOW 0
6696 +#define DWC_OTG_EP_SPEED_FULL 1
6697 +#define DWC_OTG_EP_SPEED_HIGH 2
6698 +
6699 + /**
6700 + * Endpoint type.
6701 + * One of the following values:
6702 + * - DWC_OTG_EP_TYPE_CONTROL: 0
6703 + * - DWC_OTG_EP_TYPE_ISOC: 1
6704 + * - DWC_OTG_EP_TYPE_BULK: 2
6705 + * - DWC_OTG_EP_TYPE_INTR: 3
6706 + */
6707 + unsigned ep_type : 2;
6708 +
6709 + /** Max packet size in bytes */
6710 + unsigned max_packet : 11;
6711 +
6712 + /**
6713 + * PID for initial transaction.
6714 + * 0: DATA0,<br>
6715 + * 1: DATA2,<br>
6716 + * 2: DATA1,<br>
6717 + * 3: MDATA (non-Control EP),
6718 + * SETUP (Control EP)
6719 + */
6720 + unsigned data_pid_start : 2;
6721 +#define DWC_OTG_HC_PID_DATA0 0
6722 +#define DWC_OTG_HC_PID_DATA2 1
6723 +#define DWC_OTG_HC_PID_DATA1 2
6724 +#define DWC_OTG_HC_PID_MDATA 3
6725 +#define DWC_OTG_HC_PID_SETUP 3
6726 +
6727 + /** Number of periodic transactions per (micro)frame */
6728 + unsigned multi_count: 2;
6729 +
6730 + /** @name Transfer State */
6731 + /** @{ */
6732 +
6733 + /** Pointer to the current transfer buffer position. */
6734 + uint8_t *xfer_buff;
6735 + /** Total number of bytes to transfer. */
6736 + uint32_t xfer_len;
6737 + /** Number of bytes transferred so far. */
6738 + uint32_t xfer_count;
6739 + /** Packet count at start of transfer.*/
6740 + uint16_t start_pkt_count;
6741 +
6742 + /**
6743 + * Flag to indicate whether the transfer has been started. Set to 1 if
6744 + * it has been started, 0 otherwise.
6745 + */
6746 + uint8_t xfer_started;
6747 +
6748 + /**
6749 + * Set to 1 to indicate that a PING request should be issued on this
6750 + * channel. If 0, process normally.
6751 + */
6752 + uint8_t do_ping;
6753 +
6754 + /**
6755 + * Set to 1 to indicate that the error count for this transaction is
6756 + * non-zero. Set to 0 if the error count is 0.
6757 + */
6758 + uint8_t error_state;
6759 +
6760 + /**
6761 + * Set to 1 to indicate that this channel should be halted the next
6762 + * time a request is queued for the channel. This is necessary in
6763 + * slave mode if no request queue space is available when an attempt
6764 + * is made to halt the channel.
6765 + */
6766 + uint8_t halt_on_queue;
6767 +
6768 + /**
6769 + * Set to 1 if the host channel has been halted, but the core is not
6770 + * finished flushing queued requests. Otherwise 0.
6771 + */
6772 + uint8_t halt_pending;
6773 +
6774 + /**
6775 + * Reason for halting the host channel.
6776 + */
6777 + dwc_otg_halt_status_e halt_status;
6778 +
6779 + /*
6780 + * Split settings for the host channel
6781 + */
6782 + uint8_t do_split; /**< Enable split for the channel */
6783 + uint8_t complete_split; /**< Enable complete split */
6784 + uint8_t hub_addr; /**< Address of high speed hub */
6785 +
6786 + uint8_t port_addr; /**< Port of the low/full speed device */
6787 + /** Split transaction position
6788 + * One of the following values:
6789 + * - DWC_HCSPLIT_XACTPOS_MID
6790 + * - DWC_HCSPLIT_XACTPOS_BEGIN
6791 + * - DWC_HCSPLIT_XACTPOS_END
6792 + * - DWC_HCSPLIT_XACTPOS_ALL */
6793 + uint8_t xact_pos;
6794 +
6795 + /** Set when the host channel does a short read. */
6796 + uint8_t short_read;
6797 +
6798 + /**
6799 + * Number of requests issued for this channel since it was assigned to
6800 + * the current transfer (not counting PINGs).
6801 + */
6802 + uint8_t requests;
6803 +
6804 + /**
6805 + * Queue Head for the transfer being processed by this channel.
6806 + */
6807 + struct dwc_otg_qh *qh;
6808 +
6809 + /** @} */
6810 +
6811 + /** Entry in list of host channels. */
6812 + struct list_head hc_list_entry;
6813 +} dwc_hc_t;
6814 +
6815 +/**
6816 + * The following parameters may be specified when starting the module. These
6817 + * parameters define how the DWC_otg controller should be configured.
6818 + * Parameter values are passed to the CIL initialization function
6819 + * dwc_otg_cil_init.
6820 + */
6821 +typedef struct dwc_otg_core_params
6822 +{
6823 + int32_t opt;
6824 +#define dwc_param_opt_default 1
6825 +
6826 + /**
6827 + * Specifies the OTG capabilities. The driver will automatically
6828 + * detect the value for this parameter if none is specified.
6829 + * 0 - HNP and SRP capable (default)
6830 + * 1 - SRP Only capable
6831 + * 2 - No HNP/SRP capable
6832 + */
6833 + int32_t otg_cap;
6834 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
6835 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
6836 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
6837 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
6838 +
6839 + /**
6840 + * Specifies whether to use slave or DMA mode for accessing the data
6841 + * FIFOs. The driver will automatically detect the value for this
6842 + * parameter if none is specified.
6843 + * 0 - Slave
6844 + * 1 - DMA (default, if available)
6845 + */
6846 + int32_t dma_enable;
6847 +#define dwc_param_dma_enable_default 1
6848 +
6849 + /**
6850 + * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
6851 + * FIFOs in device mode. The driver will automatically detect the value for this
6852 + * parameter if none is specified.
6853 + * 0 - address DMA
6854 + * 1 - DMA Descriptor(default, if available)
6855 + */
6856 + int32_t dma_desc_enable;
6857 +#define dwc_param_dma_desc_enable_default 0
6858 + /** The DMA Burst size (applicable only for External DMA
6859 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
6860 + */
6861 + int32_t dma_burst_size; /* Translate this to GAHBCFG values */
6862 +#define dwc_param_dma_burst_size_default 32
6863 +
6864 + /**
6865 + * Specifies the maximum speed of operation in host and device mode.
6866 + * The actual speed depends on the speed of the attached device and
6867 + * the value of phy_type. The actual speed depends on the speed of the
6868 + * attached device.
6869 + * 0 - High Speed (default)
6870 + * 1 - Full Speed
6871 + */
6872 + int32_t speed;
6873 +#define dwc_param_speed_default 0
6874 +#define DWC_SPEED_PARAM_HIGH 0
6875 +#define DWC_SPEED_PARAM_FULL 1
6876 +
6877 + /** Specifies whether low power mode is supported when attached
6878 + * to a Full Speed or Low Speed device in host mode.
6879 + * 0 - Don't support low power mode (default)
6880 + * 1 - Support low power mode
6881 + */
6882 + int32_t host_support_fs_ls_low_power;
6883 +#define dwc_param_host_support_fs_ls_low_power_default 0
6884 +
6885 + /** Specifies the PHY clock rate in low power mode when connected to a
6886 + * Low Speed device in host mode. This parameter is applicable only if
6887 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
6888 + * then defaults to 6 MHZ otherwise 48 MHZ.
6889 + *
6890 + * 0 - 48 MHz
6891 + * 1 - 6 MHz
6892 + */
6893 + int32_t host_ls_low_power_phy_clk;
6894 +#define dwc_param_host_ls_low_power_phy_clk_default 0
6895 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
6896 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
6897 +
6898 + /**
6899 + * 0 - Use cC FIFO size parameters
6900 + * 1 - Allow dynamic FIFO sizing (default)
6901 + */
6902 + int32_t enable_dynamic_fifo;
6903 +#define dwc_param_enable_dynamic_fifo_default 1
6904 +
6905 + /** Total number of 4-byte words in the data FIFO memory. This
6906 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
6907 + * Tx FIFOs.
6908 + * 32 to 32768 (default 8192)
6909 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
6910 + */
6911 + int32_t data_fifo_size;
6912 +#define dwc_param_data_fifo_size_default 8192
6913 +
6914 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
6915 + * FIFO sizing is enabled.
6916 + * 16 to 32768 (default 1064)
6917 + */
6918 + int32_t dev_rx_fifo_size;
6919 +#define dwc_param_dev_rx_fifo_size_default 1064
6920 +
6921 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
6922 + * when dynamic FIFO sizing is enabled.
6923 + * 16 to 32768 (default 1024)
6924 + */
6925 + int32_t dev_nperio_tx_fifo_size;
6926 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
6927 +
6928 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device
6929 + * mode when dynamic FIFO sizing is enabled.
6930 + * 4 to 768 (default 256)
6931 + */
6932 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
6933 +#define dwc_param_dev_perio_tx_fifo_size_default 256
6934 +
6935 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
6936 + * FIFO sizing is enabled.
6937 + * 16 to 32768 (default 1024)
6938 + */
6939 + int32_t host_rx_fifo_size;
6940 +#define dwc_param_host_rx_fifo_size_default 1024
6941 +
6942 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
6943 + * when Dynamic FIFO sizing is enabled in the core.
6944 + * 16 to 32768 (default 1024)
6945 + */
6946 + int32_t host_nperio_tx_fifo_size;
6947 +#define dwc_param_host_nperio_tx_fifo_size_default 1024
6948 +
6949 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
6950 + * FIFO sizing is enabled.
6951 + * 16 to 32768 (default 1024)
6952 + */
6953 + int32_t host_perio_tx_fifo_size;
6954 +#define dwc_param_host_perio_tx_fifo_size_default 1024
6955 +
6956 + /** The maximum transfer size supported in bytes.
6957 + * 2047 to 65,535 (default 65,535)
6958 + */
6959 + int32_t max_transfer_size;
6960 +#define dwc_param_max_transfer_size_default 65535
6961 +
6962 + /** The maximum number of packets in a transfer.
6963 + * 15 to 511 (default 511)
6964 + */
6965 + int32_t max_packet_count;
6966 +#define dwc_param_max_packet_count_default 511
6967 +
6968 + /** The number of host channel registers to use.
6969 + * 1 to 16 (default 12)
6970 + * Note: The FPGA configuration supports a maximum of 12 host channels.
6971 + */
6972 + int32_t host_channels;
6973 +#define dwc_param_host_channels_default 12
6974 +
6975 + /** The number of endpoints in addition to EP0 available for device
6976 + * mode operations.
6977 + * 1 to 15 (default 6 IN and OUT)
6978 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
6979 + * endpoints in addition to EP0.
6980 + */
6981 + int32_t dev_endpoints;
6982 +#define dwc_param_dev_endpoints_default 6
6983 +
6984 + /**
6985 + * Specifies the type of PHY interface to use. By default, the driver
6986 + * will automatically detect the phy_type.
6987 + *
6988 + * 0 - Full Speed PHY
6989 + * 1 - UTMI+ (default)
6990 + * 2 - ULPI
6991 + */
6992 + int32_t phy_type;
6993 +#define DWC_PHY_TYPE_PARAM_FS 0
6994 +#define DWC_PHY_TYPE_PARAM_UTMI 1
6995 +#define DWC_PHY_TYPE_PARAM_ULPI 2
6996 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
6997 +
6998 + /**
6999 + * Specifies the UTMI+ Data Width. This parameter is
7000 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
7001 + * PHY_TYPE, this parameter indicates the data width between
7002 + * the MAC and the ULPI Wrapper.) Also, this parameter is
7003 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
7004 + * to "8 and 16 bits", meaning that the core has been
7005 + * configured to work at either data path width.
7006 + *
7007 + * 8 or 16 bits (default 16)
7008 + */
7009 + int32_t phy_utmi_width;
7010 +#define dwc_param_phy_utmi_width_default 16
7011 +
7012 + /**
7013 + * Specifies whether the ULPI operates at double or single
7014 + * data rate. This parameter is only applicable if PHY_TYPE is
7015 + * ULPI.
7016 + *
7017 + * 0 - single data rate ULPI interface with 8 bit wide data
7018 + * bus (default)
7019 + * 1 - double data rate ULPI interface with 4 bit wide data
7020 + * bus
7021 + */
7022 + int32_t phy_ulpi_ddr;
7023 +#define dwc_param_phy_ulpi_ddr_default 0
7024 +
7025 + /**
7026 + * Specifies whether to use the internal or external supply to
7027 + * drive the vbus with a ULPI phy.
7028 + */
7029 + int32_t phy_ulpi_ext_vbus;
7030 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
7031 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
7032 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
7033 +
7034 + /**
7035 + * Specifies whether to use the I2Cinterface for full speed PHY. This
7036 + * parameter is only applicable if PHY_TYPE is FS.
7037 + * 0 - No (default)
7038 + * 1 - Yes
7039 + */
7040 + int32_t i2c_enable;
7041 +#define dwc_param_i2c_enable_default 0
7042 +
7043 + int32_t ulpi_fs_ls;
7044 +#define dwc_param_ulpi_fs_ls_default 0
7045 +
7046 + int32_t ts_dline;
7047 +#define dwc_param_ts_dline_default 0
7048 +
7049 + /**
7050 + * Specifies whether dedicated transmit FIFOs are
7051 + * enabled for non periodic IN endpoints in device mode
7052 + * 0 - No
7053 + * 1 - Yes
7054 + */
7055 + int32_t en_multiple_tx_fifo;
7056 +#define dwc_param_en_multiple_tx_fifo_default 1
7057 +
7058 + /** Number of 4-byte words in each of the Tx FIFOs in device
7059 + * mode when dynamic FIFO sizing is enabled.
7060 + * 4 to 768 (default 256)
7061 + */
7062 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
7063 +#define dwc_param_dev_tx_fifo_size_default 256
7064 +
7065 + /** Thresholding enable flag-
7066 + * bit 0 - enable non-ISO Tx thresholding
7067 + * bit 1 - enable ISO Tx thresholding
7068 + * bit 2 - enable Rx thresholding
7069 + */
7070 + uint32_t thr_ctl;
7071 +#define dwc_param_thr_ctl_default 0
7072 +
7073 + /** Thresholding length for Tx
7074 + * FIFOs in 32 bit DWORDs
7075 + */
7076 + uint32_t tx_thr_length;
7077 +#define dwc_param_tx_thr_length_default 64
7078 +
7079 + /** Thresholding length for Rx
7080 + * FIFOs in 32 bit DWORDs
7081 + */
7082 + uint32_t rx_thr_length;
7083 +#define dwc_param_rx_thr_length_default 64
7084 +
7085 + /** Per Transfer Interrupt
7086 + * mode enable flag
7087 + * 1 - Enabled
7088 + * 0 - Disabled
7089 + */
7090 + uint32_t pti_enable;
7091 +#define dwc_param_pti_enable_default 0
7092 +
7093 + /** Molti Processor Interrupt
7094 + * mode enable flag
7095 + * 1 - Enabled
7096 + * 0 - Disabled
7097 + */
7098 + uint32_t mpi_enable;
7099 +#define dwc_param_mpi_enable_default 0
7100 +
7101 +} dwc_otg_core_params_t;
7102 +
7103 +#ifdef DEBUG
7104 +struct dwc_otg_core_if;
7105 +typedef struct hc_xfer_info
7106 +{
7107 + struct dwc_otg_core_if *core_if;
7108 + dwc_hc_t *hc;
7109 +} hc_xfer_info_t;
7110 +#endif
7111 +
7112 +/**
7113 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
7114 + * the DWC_otg controller acting in either host or device mode. It
7115 + * represents the programming view of the controller as a whole.
7116 + */
7117 +typedef struct dwc_otg_core_if
7118 +{
7119 + /** Parameters that define how the core should be configured.*/
7120 + dwc_otg_core_params_t *core_params;
7121 +
7122 + /** Core Global registers starting at offset 000h. */
7123 + dwc_otg_core_global_regs_t *core_global_regs;
7124 +
7125 + /** Device-specific information */
7126 + dwc_otg_dev_if_t *dev_if;
7127 + /** Host-specific information */
7128 + dwc_otg_host_if_t *host_if;
7129 +
7130 + /** Value from SNPSID register */
7131 + uint32_t snpsid;
7132 +
7133 + /*
7134 + * Set to 1 if the core PHY interface bits in USBCFG have been
7135 + * initialized.
7136 + */
7137 + uint8_t phy_init_done;
7138 +
7139 + /*
7140 + * SRP Success flag, set by srp success interrupt in FS I2C mode
7141 + */
7142 + uint8_t srp_success;
7143 + uint8_t srp_timer_started;
7144 +
7145 + /* Common configuration information */
7146 + /** Power and Clock Gating Control Register */
7147 + volatile uint32_t *pcgcctl;
7148 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
7149 +
7150 + /** Push/pop addresses for endpoints or host channels.*/
7151 + uint32_t *data_fifo[MAX_EPS_CHANNELS];
7152 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
7153 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
7154 +
7155 + /** Total RAM for FIFOs (Bytes) */
7156 + uint16_t total_fifo_size;
7157 + /** Size of Rx FIFO (Bytes) */
7158 + uint16_t rx_fifo_size;
7159 + /** Size of Non-periodic Tx FIFO (Bytes) */
7160 + uint16_t nperio_tx_fifo_size;
7161 +
7162 +
7163 + /** 1 if DMA is enabled, 0 otherwise. */
7164 + uint8_t dma_enable;
7165 +
7166 + /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
7167 + uint8_t dma_desc_enable;
7168 +
7169 + /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
7170 + uint8_t pti_enh_enable;
7171 +
7172 + /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
7173 + uint8_t multiproc_int_enable;
7174 +
7175 + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
7176 + uint8_t en_multiple_tx_fifo;
7177 +
7178 + /** Set to 1 if multiple packets of a high-bandwidth transfer is in
7179 + * process of being queued */
7180 + uint8_t queuing_high_bandwidth;
7181 +
7182 + /** Hardware Configuration -- stored here for convenience.*/
7183 + hwcfg1_data_t hwcfg1;
7184 + hwcfg2_data_t hwcfg2;
7185 + hwcfg3_data_t hwcfg3;
7186 + hwcfg4_data_t hwcfg4;
7187 +
7188 + /** Host and Device Configuration -- stored here for convenience.*/
7189 + hcfg_data_t hcfg;
7190 + dcfg_data_t dcfg;
7191 +
7192 + /** The operational State, during transations
7193 + * (a_host>>a_peripherial and b_device=>b_host) this may not
7194 + * match the core but allows the software to determine
7195 + * transitions.
7196 + */
7197 + uint8_t op_state;
7198 +
7199 + /**
7200 + * Set to 1 if the HCD needs to be restarted on a session request
7201 + * interrupt. This is required if no connector ID status change has
7202 + * occurred since the HCD was last disconnected.
7203 + */
7204 + uint8_t restart_hcd_on_session_req;
7205 +
7206 + /** HCD callbacks */
7207 + /** A-Device is a_host */
7208 +#define A_HOST (1)
7209 + /** A-Device is a_suspend */
7210 +#define A_SUSPEND (2)
7211 + /** A-Device is a_peripherial */
7212 +#define A_PERIPHERAL (3)
7213 + /** B-Device is operating as a Peripheral. */
7214 +#define B_PERIPHERAL (4)
7215 + /** B-Device is operating as a Host. */
7216 +#define B_HOST (5)
7217 +
7218 + /** HCD callbacks */
7219 + struct dwc_otg_cil_callbacks *hcd_cb;
7220 + /** PCD callbacks */
7221 + struct dwc_otg_cil_callbacks *pcd_cb;
7222 +
7223 + /** Device mode Periodic Tx FIFO Mask */
7224 + uint32_t p_tx_msk;
7225 + /** Device mode Periodic Tx FIFO Mask */
7226 + uint32_t tx_msk;
7227 +
7228 + /** Workqueue object used for handling several interrupts */
7229 + struct workqueue_struct *wq_otg;
7230 +
7231 + /** Work object used for handling "Connector ID Status Change" Interrupt */
7232 + struct work_struct w_conn_id;
7233 +
7234 + /** Work object used for handling "Wakeup Detected" Interrupt */
7235 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7236 + struct work_struct w_wkp;
7237 +#else
7238 + struct delayed_work w_wkp;
7239 +#endif
7240 +
7241 +#ifdef DEBUG
7242 + uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
7243 +
7244 + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
7245 + struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
7246 +
7247 + uint32_t hfnum_7_samples;
7248 + uint64_t hfnum_7_frrem_accum;
7249 + uint32_t hfnum_0_samples;
7250 + uint64_t hfnum_0_frrem_accum;
7251 + uint32_t hfnum_other_samples;
7252 + uint64_t hfnum_other_frrem_accum;
7253 +#endif
7254 +
7255 +
7256 +} dwc_otg_core_if_t;
7257 +
7258 +/*We must clear S3C24XX_EINTPEND external interrupt register
7259 + * because after clearing in this register trigerred IRQ from
7260 + * H/W core in kernel interrupt can be occured again before OTG
7261 + * handlers clear all IRQ sources of Core registers because of
7262 + * timing latencies and Low Level IRQ Type.
7263 + */
7264 +
7265 +#ifdef CONFIG_MACH_IPMATE
7266 +#define S3C2410X_CLEAR_EINTPEND() \
7267 +do { \
7268 + if (!dwc_otg_read_core_intr(core_if)) { \
7269 + __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
7270 + } \
7271 +} while (0)
7272 +#else
7273 +#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
7274 +#endif
7275 +
7276 +/*
7277 + * The following functions are functions for works
7278 + * using during handling some interrupts
7279 + */
7280 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7281 +
7282 +extern void w_conn_id_status_change(void *p);
7283 +extern void w_wakeup_detected(void *p);
7284 +
7285 +#else
7286 +
7287 +extern void w_conn_id_status_change(struct work_struct *p);
7288 +extern void w_wakeup_detected(struct work_struct *p);
7289 +
7290 +#endif
7291 +
7292 +
7293 +/*
7294 + * The following functions support initialization of the CIL driver component
7295 + * and the DWC_otg controller.
7296 + */
7297 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
7298 + dwc_otg_core_params_t *_core_params);
7299 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
7300 +extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
7301 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
7302 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
7303 +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
7304 +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
7305 +
7306 +/** @name Device CIL Functions
7307 + * The following functions support managing the DWC_otg controller in device
7308 + * mode.
7309 + */
7310 +/**@{*/
7311 +extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
7312 +extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
7313 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
7314 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7315 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7316 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7317 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7318 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7319 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7320 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7321 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
7322 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7323 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
7324 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
7325 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
7326 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
7327 +#ifdef DWC_EN_ISOC
7328 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
7329 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
7330 +#endif //DWC_EN_ISOC
7331 +/**@}*/
7332 +
7333 +/** @name Host CIL Functions
7334 + * The following functions support managing the DWC_otg controller in host
7335 + * mode.
7336 + */
7337 +/**@{*/
7338 +extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7339 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
7340 + dwc_hc_t *_hc,
7341 + dwc_otg_halt_status_e _halt_status);
7342 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7343 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7344 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7345 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7346 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
7347 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
7348 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
7349 +
7350 +/**
7351 + * This function Reads HPRT0 in preparation to modify. It keeps the
7352 + * WC bits 0 so that if they are read as 1, they won't clear when you
7353 + * write it back
7354 + */
7355 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
7356 +{
7357 + hprt0_data_t hprt0;
7358 + hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
7359 + hprt0.b.prtena = 0;
7360 + hprt0.b.prtconndet = 0;
7361 + hprt0.b.prtenchng = 0;
7362 + hprt0.b.prtovrcurrchng = 0;
7363 + return hprt0.d32;
7364 +}
7365 +
7366 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
7367 +/**@}*/
7368 +
7369 +/** @name Common CIL Functions
7370 + * The following functions support managing the DWC_otg controller in either
7371 + * device or host mode.
7372 + */
7373 +/**@{*/
7374 +
7375 +extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
7376 + uint8_t *dest,
7377 + uint16_t bytes);
7378 +
7379 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
7380 +
7381 +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
7382 + const int _num );
7383 +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
7384 +extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
7385 +
7386 +extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
7387 +extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
7388 +
7389 +/**
7390 + * This function returns the Core Interrupt register.
7391 + */
7392 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
7393 +{
7394 + return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
7395 + dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
7396 +}
7397 +
7398 +/**
7399 + * This function returns the OTG Interrupt register.
7400 + */
7401 +static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
7402 +{
7403 + return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
7404 +}
7405 +
7406 +/**
7407 + * This function reads the Device All Endpoints Interrupt register and
7408 + * returns the IN endpoint interrupt bits.
7409 + */
7410 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
7411 +{
7412 + uint32_t v;
7413 +
7414 + if(core_if->multiproc_int_enable) {
7415 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
7416 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
7417 + } else {
7418 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
7419 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
7420 + }
7421 + return (v & 0xffff);
7422 +
7423 +}
7424 +
7425 +/**
7426 + * This function reads the Device All Endpoints Interrupt register and
7427 + * returns the OUT endpoint interrupt bits.
7428 + */
7429 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
7430 +{
7431 + uint32_t v;
7432 +
7433 + if(core_if->multiproc_int_enable) {
7434 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
7435 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
7436 + } else {
7437 + v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
7438 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
7439 + }
7440 +
7441 + return ((v & 0xffff0000) >> 16);
7442 +}
7443 +
7444 +/**
7445 + * This function returns the Device IN EP Interrupt register
7446 + */
7447 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
7448 + dwc_ep_t *ep)
7449 +{
7450 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
7451 + uint32_t v, msk, emp;
7452 +
7453 + if(core_if->multiproc_int_enable) {
7454 + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
7455 + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
7456 + msk |= ((emp >> ep->num) & 0x1) << 7;
7457 + v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
7458 + } else {
7459 + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
7460 + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
7461 + msk |= ((emp >> ep->num) & 0x1) << 7;
7462 + v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
7463 + }
7464 +
7465 +
7466 + return v;
7467 +}
7468 +/**
7469 + * This function returns the Device OUT EP Interrupt register
7470 + */
7471 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
7472 + dwc_ep_t *_ep)
7473 +{
7474 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
7475 + uint32_t v;
7476 + doepmsk_data_t msk = { .d32 = 0 };
7477 +
7478 + if(_core_if->multiproc_int_enable) {
7479 + msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
7480 + if(_core_if->pti_enh_enable) {
7481 + msk.b.pktdrpsts = 1;
7482 + }
7483 + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
7484 + } else {
7485 + msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
7486 + if(_core_if->pti_enh_enable) {
7487 + msk.b.pktdrpsts = 1;
7488 + }
7489 + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
7490 + }
7491 + return v;
7492 +}
7493 +
7494 +/**
7495 + * This function returns the Host All Channel Interrupt register
7496 + */
7497 +static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
7498 +{
7499 + return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
7500 +}
7501 +
7502 +static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
7503 +{
7504 + return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
7505 +}
7506 +
7507 +
7508 +/**
7509 + * This function returns the mode of the operation, host or device.
7510 + *
7511 + * @return 0 - Device Mode, 1 - Host Mode
7512 + */
7513 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
7514 +{
7515 + return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
7516 +}
7517 +
7518 +static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
7519 +{
7520 + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
7521 +}
7522 +static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
7523 +{
7524 + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
7525 +}
7526 +
7527 +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
7528 +
7529 +
7530 +/**@}*/
7531 +
7532 +/**
7533 + * DWC_otg CIL callback structure. This structure allows the HCD and
7534 + * PCD to register functions used for starting and stopping the PCD
7535 + * and HCD for role change on for a DRD.
7536 + */
7537 +typedef struct dwc_otg_cil_callbacks
7538 +{
7539 + /** Start function for role change */
7540 + int (*start) (void *_p);
7541 + /** Stop Function for role change */
7542 + int (*stop) (void *_p);
7543 + /** Disconnect Function for role change */
7544 + int (*disconnect) (void *_p);
7545 + /** Resume/Remote wakeup Function */
7546 + int (*resume_wakeup) (void *_p);
7547 + /** Suspend function */
7548 + int (*suspend) (void *_p);
7549 + /** Session Start (SRP) */
7550 + int (*session_start) (void *_p);
7551 + /** Pointer passed to start() and stop() */
7552 + void *p;
7553 +} dwc_otg_cil_callbacks_t;
7554 +
7555 +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
7556 + dwc_otg_cil_callbacks_t *_cb,
7557 + void *_p);
7558 +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
7559 + dwc_otg_cil_callbacks_t *_cb,
7560 + void *_p);
7561 +
7562 +#endif
7563 +
7564 diff --git a/drivers/usb/dwc_otg/dwc_otg_cil_intr.c b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
7565 new file mode 100644
7566 index 0000000..61b17b3
7567 --- /dev/null
7568 +++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
7569 @@ -0,0 +1,750 @@
7570 +/* ==========================================================================
7571 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
7572 + * $Revision: 1.2 $
7573 + * $Date: 2008-11-21 05:39:15 $
7574 + * $Change: 1065567 $
7575 + *
7576 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7577 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7578 + * otherwise expressly agreed to in writing between Synopsys and you.
7579 + *
7580 + * The Software IS NOT an item of Licensed Software or Licensed Product under
7581 + * any End User Software License Agreement or Agreement for Licensed Product
7582 + * with Synopsys or any supplement thereto. You are permitted to use and
7583 + * redistribute this Software in source and binary forms, with or without
7584 + * modification, provided that redistributions of source code must retain this
7585 + * notice. You may not view, use, disclose, copy or distribute this file or
7586 + * any information contained herein except pursuant to this license grant from
7587 + * Synopsys. If you do not agree with this notice, including the disclaimer
7588 + * below, then you are not authorized to use the Software.
7589 + *
7590 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7591 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7592 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7593 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7594 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7595 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7596 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7597 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7598 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7599 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7600 + * DAMAGE.
7601 + * ========================================================================== */
7602 +
7603 +/** @file
7604 + *
7605 + * The Core Interface Layer provides basic services for accessing and
7606 + * managing the DWC_otg hardware. These services are used by both the
7607 + * Host Controller Driver and the Peripheral Controller Driver.
7608 + *
7609 + * This file contains the Common Interrupt handlers.
7610 + */
7611 +#include "linux/dwc_otg_plat.h"
7612 +#include "dwc_otg_regs.h"
7613 +#include "dwc_otg_cil.h"
7614 +
7615 +#ifdef DEBUG
7616 +inline const char *op_state_str(dwc_otg_core_if_t *core_if)
7617 +{
7618 + return (core_if->op_state==A_HOST?"a_host":
7619 + (core_if->op_state==A_SUSPEND?"a_suspend":
7620 + (core_if->op_state==A_PERIPHERAL?"a_peripheral":
7621 + (core_if->op_state==B_PERIPHERAL?"b_peripheral":
7622 + (core_if->op_state==B_HOST?"b_host":
7623 + "unknown")))));
7624 +}
7625 +#endif
7626 +
7627 +/** This function will log a debug message
7628 + *
7629 + * @param core_if Programming view of DWC_otg controller.
7630 + */
7631 +int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
7632 +{
7633 + gintsts_data_t gintsts;
7634 + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
7635 + dwc_otg_mode(core_if) ? "Host" : "Device");
7636 +
7637 + /* Clear interrupt */
7638 + gintsts.d32 = 0;
7639 + gintsts.b.modemismatch = 1;
7640 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
7641 + return 1;
7642 +}
7643 +
7644 +/** Start the HCD. Helper function for using the HCD callbacks.
7645 + *
7646 + * @param core_if Programming view of DWC_otg controller.
7647 + */
7648 +static inline void hcd_start(dwc_otg_core_if_t *core_if)
7649 +{
7650 + if (core_if->hcd_cb && core_if->hcd_cb->start) {
7651 + core_if->hcd_cb->start(core_if->hcd_cb->p);
7652 + }
7653 +}
7654 +/** Stop the HCD. Helper function for using the HCD callbacks.
7655 + *
7656 + * @param core_if Programming view of DWC_otg controller.
7657 + */
7658 +static inline void hcd_stop(dwc_otg_core_if_t *core_if)
7659 +{
7660 + if (core_if->hcd_cb && core_if->hcd_cb->stop) {
7661 + core_if->hcd_cb->stop(core_if->hcd_cb->p);
7662 + }
7663 +}
7664 +/** Disconnect the HCD. Helper function for using the HCD callbacks.
7665 + *
7666 + * @param core_if Programming view of DWC_otg controller.
7667 + */
7668 +static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
7669 +{
7670 + if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
7671 + core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
7672 + }
7673 +}
7674 +/** Inform the HCD the a New Session has begun. Helper function for
7675 + * using the HCD callbacks.
7676 + *
7677 + * @param core_if Programming view of DWC_otg controller.
7678 + */
7679 +static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
7680 +{
7681 + if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
7682 + core_if->hcd_cb->session_start(core_if->hcd_cb->p);
7683 + }
7684 +}
7685 +
7686 +/** Start the PCD. Helper function for using the PCD callbacks.
7687 + *
7688 + * @param core_if Programming view of DWC_otg controller.
7689 + */
7690 +static inline void pcd_start(dwc_otg_core_if_t *core_if)
7691 +{
7692 + if (core_if->pcd_cb && core_if->pcd_cb->start) {
7693 + core_if->pcd_cb->start(core_if->pcd_cb->p);
7694 + }
7695 +}
7696 +/** Stop the PCD. Helper function for using the PCD callbacks.
7697 + *
7698 + * @param core_if Programming view of DWC_otg controller.
7699 + */
7700 +static inline void pcd_stop(dwc_otg_core_if_t *core_if)
7701 +{
7702 + if (core_if->pcd_cb && core_if->pcd_cb->stop) {
7703 + core_if->pcd_cb->stop(core_if->pcd_cb->p);
7704 + }
7705 +}
7706 +/** Suspend the PCD. Helper function for using the PCD callbacks.
7707 + *
7708 + * @param core_if Programming view of DWC_otg controller.
7709 + */
7710 +static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
7711 +{
7712 + if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
7713 + core_if->pcd_cb->suspend(core_if->pcd_cb->p);
7714 + }
7715 +}
7716 +/** Resume the PCD. Helper function for using the PCD callbacks.
7717 + *
7718 + * @param core_if Programming view of DWC_otg controller.
7719 + */
7720 +static inline void pcd_resume(dwc_otg_core_if_t *core_if)
7721 +{
7722 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
7723 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
7724 + }
7725 +}
7726 +
7727 +/**
7728 + * This function handles the OTG Interrupts. It reads the OTG
7729 + * Interrupt Register (GOTGINT) to determine what interrupt has
7730 + * occurred.
7731 + *
7732 + * @param core_if Programming view of DWC_otg controller.
7733 + */
7734 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
7735 +{
7736 + dwc_otg_core_global_regs_t *global_regs =
7737 + core_if->core_global_regs;
7738 + gotgint_data_t gotgint;
7739 + gotgctl_data_t gotgctl;
7740 + gintmsk_data_t gintmsk;
7741 +
7742 + gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
7743 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7744 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
7745 +
7746 + if (gotgint.b.sesenddet) {
7747 + DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: "
7748 + "Session End Detected++ (%s)\n",
7749 + op_state_str(core_if));
7750 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7751 +
7752 + if (core_if->op_state == B_HOST) {
7753 + pcd_start(core_if);
7754 + core_if->op_state = B_PERIPHERAL;
7755 + } else {
7756 + /* If not B_HOST and Device HNP still set. HNP
7757 + * Did not succeed!*/
7758 + if (gotgctl.b.devhnpen) {
7759 + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
7760 + DWC_ERROR("Device Not Connected/Responding!\n");
7761 + }
7762 +
7763 + /* If Session End Detected the B-Cable has
7764 + * been disconnected. */
7765 + /* Reset PCD and Gadget driver to a
7766 + * clean state. */
7767 + pcd_stop(core_if);
7768 + }
7769 + gotgctl.d32 = 0;
7770 + gotgctl.b.devhnpen = 1;
7771 + dwc_modify_reg32(&global_regs->gotgctl,
7772 + gotgctl.d32, 0);
7773 + }
7774 + if (gotgint.b.sesreqsucstschng) {
7775 + DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: "
7776 + "Session Reqeust Success Status Change++\n");
7777 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7778 + if (gotgctl.b.sesreqscs) {
7779 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
7780 + (core_if->core_params->i2c_enable)) {
7781 + core_if->srp_success = 1;
7782 + }
7783 + else {
7784 + pcd_resume(core_if);
7785 + /* Clear Session Request */
7786 + gotgctl.d32 = 0;
7787 + gotgctl.b.sesreq = 1;
7788 + dwc_modify_reg32(&global_regs->gotgctl,
7789 + gotgctl.d32, 0);
7790 + }
7791 + }
7792 + }
7793 + if (gotgint.b.hstnegsucstschng) {
7794 + /* Print statements during the HNP interrupt handling
7795 + * can cause it to fail.*/
7796 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
7797 + if (gotgctl.b.hstnegscs) {
7798 + if (dwc_otg_is_host_mode(core_if)) {
7799 + core_if->op_state = B_HOST;
7800 + /*
7801 + * Need to disable SOF interrupt immediately.
7802 + * When switching from device to host, the PCD
7803 + * interrupt handler won't handle the
7804 + * interrupt if host mode is already set. The
7805 + * HCD interrupt handler won't get called if
7806 + * the HCD state is HALT. This means that the
7807 + * interrupt does not get handled and Linux
7808 + * complains loudly.
7809 + */
7810 + gintmsk.d32 = 0;
7811 + gintmsk.b.sofintr = 1;
7812 + dwc_modify_reg32(&global_regs->gintmsk,
7813 + gintmsk.d32, 0);
7814 + pcd_stop(core_if);
7815 + /*
7816 + * Initialize the Core for Host mode.
7817 + */
7818 + hcd_start(core_if);
7819 + core_if->op_state = B_HOST;
7820 + }
7821 + } else {
7822 + gotgctl.d32 = 0;
7823 + gotgctl.b.hnpreq = 1;
7824 + gotgctl.b.devhnpen = 1;
7825 + dwc_modify_reg32(&global_regs->gotgctl,
7826 + gotgctl.d32, 0);
7827 + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
7828 + DWC_ERROR("Device Not Connected/Responding\n");
7829 + }
7830 + }
7831 + if (gotgint.b.hstnegdet) {
7832 + /* The disconnect interrupt is set at the same time as
7833 + * Host Negotiation Detected. During the mode
7834 + * switch all interrupts are cleared so the disconnect
7835 + * interrupt handler will not get executed.
7836 + */
7837 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
7838 + "Host Negotiation Detected++ (%s)\n",
7839 + (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
7840 + if (dwc_otg_is_device_mode(core_if)){
7841 + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
7842 + hcd_disconnect(core_if);
7843 + pcd_start(core_if);
7844 + core_if->op_state = A_PERIPHERAL;
7845 + } else {
7846 + /*
7847 + * Need to disable SOF interrupt immediately. When
7848 + * switching from device to host, the PCD interrupt
7849 + * handler won't handle the interrupt if host mode is
7850 + * already set. The HCD interrupt handler won't get
7851 + * called if the HCD state is HALT. This means that
7852 + * the interrupt does not get handled and Linux
7853 + * complains loudly.
7854 + */
7855 + gintmsk.d32 = 0;
7856 + gintmsk.b.sofintr = 1;
7857 + dwc_modify_reg32(&global_regs->gintmsk,
7858 + gintmsk.d32, 0);
7859 + pcd_stop(core_if);
7860 + hcd_start(core_if);
7861 + core_if->op_state = A_HOST;
7862 + }
7863 + }
7864 + if (gotgint.b.adevtoutchng) {
7865 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
7866 + "A-Device Timeout Change++\n");
7867 + }
7868 + if (gotgint.b.debdone) {
7869 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
7870 + "Debounce Done++\n");
7871 + }
7872 +
7873 + /* Clear GOTGINT */
7874 + dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
7875 +
7876 + return 1;
7877 +}
7878 +
7879 +
7880 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
7881 +
7882 +void w_conn_id_status_change(void *p)
7883 +{
7884 + dwc_otg_core_if_t *core_if = p;
7885 +
7886 +#else
7887 +
7888 +void w_conn_id_status_change(struct work_struct *p)
7889 +{
7890 + dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
7891 +
7892 +#endif
7893 +
7894 +
7895 + uint32_t count = 0;
7896 + gotgctl_data_t gotgctl = { .d32 = 0 };
7897 +
7898 + gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
7899 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
7900 + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
7901 +
7902 + /* B-Device connector (Device Mode) */
7903 + if (gotgctl.b.conidsts) {
7904 + /* Wait for switch to device mode. */
7905 + while (!dwc_otg_is_device_mode(core_if)){
7906 + DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
7907 + (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
7908 + MDELAY(100);
7909 + if (++count > 10000) *(uint32_t*)NULL=0;
7910 + }
7911 + core_if->op_state = B_PERIPHERAL;
7912 + dwc_otg_core_init(core_if);
7913 + dwc_otg_enable_global_interrupts(core_if);
7914 + pcd_start(core_if);
7915 + } else {
7916 + /* A-Device connector (Host Mode) */
7917 + while (!dwc_otg_is_host_mode(core_if)) {
7918 + DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
7919 + (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
7920 + MDELAY(100);
7921 + if (++count > 10000) *(uint32_t*)NULL=0;
7922 + }
7923 + core_if->op_state = A_HOST;
7924 + /*
7925 + * Initialize the Core for Host mode.
7926 + */
7927 + dwc_otg_core_init(core_if);
7928 + dwc_otg_enable_global_interrupts(core_if);
7929 + hcd_start(core_if);
7930 + }
7931 +}
7932 +
7933 +
7934 +/**
7935 + * This function handles the Connector ID Status Change Interrupt. It
7936 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
7937 + * is a Device to Host Mode transition or a Host Mode to Device
7938 + * Transition.
7939 + *
7940 + * This only occurs when the cable is connected/removed from the PHY
7941 + * connector.
7942 + *
7943 + * @param core_if Programming view of DWC_otg controller.
7944 + */
7945 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
7946 +{
7947 +
7948 + /*
7949 + * Need to disable SOF interrupt immediately. If switching from device
7950 + * to host, the PCD interrupt handler won't handle the interrupt if
7951 + * host mode is already set. The HCD interrupt handler won't get
7952 + * called if the HCD state is HALT. This means that the interrupt does
7953 + * not get handled and Linux complains loudly.
7954 + */
7955 + gintmsk_data_t gintmsk = { .d32 = 0 };
7956 + gintsts_data_t gintsts = { .d32 = 0 };
7957 +
7958 + gintmsk.b.sofintr = 1;
7959 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
7960 +
7961 + DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
7962 + (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
7963 +
7964 + /*
7965 + * Need to schedule a work, as there are possible DELAY function calls
7966 + */
7967 + queue_work(core_if->wq_otg, &core_if->w_conn_id);
7968 +
7969 + /* Set flag and clear interrupt */
7970 + gintsts.b.conidstschng = 1;
7971 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
7972 +
7973 + return 1;
7974 +}
7975 +
7976 +/**
7977 + * This interrupt indicates that a device is initiating the Session
7978 + * Request Protocol to request the host to turn on bus power so a new
7979 + * session can begin. The handler responds by turning on bus power. If
7980 + * the DWC_otg controller is in low power mode, the handler brings the
7981 + * controller out of low power mode before turning on bus power.
7982 + *
7983 + * @param core_if Programming view of DWC_otg controller.
7984 + */
7985 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
7986 +{
7987 + gintsts_data_t gintsts;
7988 +
7989 +#ifndef DWC_HOST_ONLY
7990 + hprt0_data_t hprt0;
7991 + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
7992 +
7993 + if (dwc_otg_is_device_mode(core_if)) {
7994 + DWC_PRINT("SRP: Device mode\n");
7995 + } else {
7996 + DWC_PRINT("SRP: Host mode\n");
7997 +
7998 + /* Turn on the port power bit. */
7999 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
8000 + hprt0.b.prtpwr = 1;
8001 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8002 +
8003 + /* Start the Connection timer. So a message can be displayed
8004 + * if connect does not occur within 10 seconds. */
8005 + hcd_session_start(core_if);
8006 + }
8007 +#endif
8008 +
8009 + /* Clear interrupt */
8010 + gintsts.d32 = 0;
8011 + gintsts.b.sessreqintr = 1;
8012 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
8013 +
8014 + return 1;
8015 +}
8016 +
8017 +
8018 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
8019 +void w_wakeup_detected(void *p)
8020 +{
8021 + dwc_otg_core_if_t* core_if = p;
8022 +
8023 +#else
8024 +
8025 +void w_wakeup_detected(struct work_struct *p)
8026 +{
8027 + struct delayed_work *dw = container_of(p, struct delayed_work, work);
8028 + dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
8029 +
8030 +#endif
8031 + /*
8032 + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
8033 + * so that OPT tests pass with all PHYs).
8034 + */
8035 + hprt0_data_t hprt0 = {.d32=0};
8036 +#if 0
8037 + pcgcctl_data_t pcgcctl = {.d32=0};
8038 + /* Restart the Phy Clock */
8039 + pcgcctl.b.stoppclk = 1;
8040 + dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
8041 + UDELAY(10);
8042 +#endif //0
8043 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
8044 + DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
8045 +// MDELAY(70);
8046 + hprt0.b.prtres = 0; /* Resume */
8047 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8048 + DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
8049 +}
8050 +/**
8051 + * This interrupt indicates that the DWC_otg controller has detected a
8052 + * resume or remote wakeup sequence. If the DWC_otg controller is in
8053 + * low power mode, the handler must brings the controller out of low
8054 + * power mode. The controller automatically begins resume
8055 + * signaling. The handler schedules a time to stop resume signaling.
8056 + */
8057 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
8058 +{
8059 + gintsts_data_t gintsts;
8060 +
8061 + DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
8062 +
8063 + if (dwc_otg_is_device_mode(core_if)) {
8064 + dctl_data_t dctl = {.d32=0};
8065 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
8066 + dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
8067 +#ifdef PARTIAL_POWER_DOWN
8068 + if (core_if->hwcfg4.b.power_optimiz) {
8069 + pcgcctl_data_t power = {.d32=0};
8070 +
8071 + power.d32 = dwc_read_reg32(core_if->pcgcctl);
8072 + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
8073 +
8074 + power.b.stoppclk = 0;
8075 + dwc_write_reg32(core_if->pcgcctl, power.d32);
8076 +
8077 + power.b.pwrclmp = 0;
8078 + dwc_write_reg32(core_if->pcgcctl, power.d32);
8079 +
8080 + power.b.rstpdwnmodule = 0;
8081 + dwc_write_reg32(core_if->pcgcctl, power.d32);
8082 + }
8083 +#endif
8084 + /* Clear the Remote Wakeup Signalling */
8085 + dctl.b.rmtwkupsig = 1;
8086 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
8087 + dctl.d32, 0);
8088 +
8089 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
8090 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
8091 + }
8092 +
8093 + } else {
8094 + pcgcctl_data_t pcgcctl = {.d32=0};
8095 +
8096 + /* Restart the Phy Clock */
8097 + pcgcctl.b.stoppclk = 1;
8098 + dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
8099 +
8100 + queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
8101 + }
8102 +
8103 + /* Clear interrupt */
8104 + gintsts.d32 = 0;
8105 + gintsts.b.wkupintr = 1;
8106 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
8107 +
8108 + return 1;
8109 +}
8110 +
8111 +/**
8112 + * This interrupt indicates that a device has been disconnected from
8113 + * the root port.
8114 + */
8115 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
8116 +{
8117 + gintsts_data_t gintsts;
8118 +
8119 + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
8120 + (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
8121 + op_state_str(core_if));
8122 +
8123 +/** @todo Consolidate this if statement. */
8124 +#ifndef DWC_HOST_ONLY
8125 + if (core_if->op_state == B_HOST) {
8126 + /* If in device mode Disconnect and stop the HCD, then
8127 + * start the PCD. */
8128 + hcd_disconnect(core_if);
8129 + pcd_start(core_if);
8130 + core_if->op_state = B_PERIPHERAL;
8131 + } else if (dwc_otg_is_device_mode(core_if)) {
8132 + gotgctl_data_t gotgctl = { .d32 = 0 };
8133 + gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
8134 + if (gotgctl.b.hstsethnpen==1) {
8135 + /* Do nothing, if HNP in process the OTG
8136 + * interrupt "Host Negotiation Detected"
8137 + * interrupt will do the mode switch.
8138 + */
8139 + } else if (gotgctl.b.devhnpen == 0) {
8140 + /* If in device mode Disconnect and stop the HCD, then
8141 + * start the PCD. */
8142 + hcd_disconnect(core_if);
8143 + pcd_start(core_if);
8144 + core_if->op_state = B_PERIPHERAL;
8145 + } else {
8146 + DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
8147 + }
8148 + } else {
8149 + if (core_if->op_state == A_HOST) {
8150 + /* A-Cable still connected but device disconnected. */
8151 + hcd_disconnect(core_if);
8152 + }
8153 + }
8154 +#endif
8155 +
8156 + gintsts.d32 = 0;
8157 + gintsts.b.disconnect = 1;
8158 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
8159 + return 1;
8160 +}
8161 +/**
8162 + * This interrupt indicates that SUSPEND state has been detected on
8163 + * the USB.
8164 + *
8165 + * For HNP the USB Suspend interrupt signals the change from
8166 + * "a_peripheral" to "a_host".
8167 + *
8168 + * When power management is enabled the core will be put in low power
8169 + * mode.
8170 + */
8171 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
8172 +{
8173 + dsts_data_t dsts;
8174 + gintsts_data_t gintsts;
8175 +
8176 + DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
8177 +
8178 + if (dwc_otg_is_device_mode(core_if)) {
8179 + /* Check the Device status register to determine if the Suspend
8180 + * state is active. */
8181 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
8182 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
8183 + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
8184 + "HWCFG4.power Optimize=%d\n",
8185 + dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
8186 +
8187 +
8188 +#ifdef PARTIAL_POWER_DOWN
8189 +/** @todo Add a module parameter for power management. */
8190 +
8191 + if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
8192 + pcgcctl_data_t power = {.d32=0};
8193 + DWC_DEBUGPL(DBG_CIL, "suspend\n");
8194 +
8195 + power.b.pwrclmp = 1;
8196 + dwc_write_reg32(core_if->pcgcctl, power.d32);
8197 +
8198 + power.b.rstpdwnmodule = 1;
8199 + dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
8200 +
8201 + power.b.stoppclk = 1;
8202 + dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
8203 +
8204 + } else {
8205 + DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
8206 + }
8207 +#endif
8208 + /* PCD callback for suspend. */
8209 + pcd_suspend(core_if);
8210 + } else {
8211 + if (core_if->op_state == A_PERIPHERAL) {
8212 + DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
8213 + /* Clear the a_peripheral flag, back to a_host. */
8214 + pcd_stop(core_if);
8215 + hcd_start(core_if);
8216 + core_if->op_state = A_HOST;
8217 + }
8218 + }
8219 +
8220 + /* Clear interrupt */
8221 + gintsts.d32 = 0;
8222 + gintsts.b.usbsuspend = 1;
8223 + dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
8224 +
8225 + return 1;
8226 +}
8227 +
8228 +
8229 +/**
8230 + * This function returns the Core Interrupt register.
8231 + */
8232 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
8233 +{
8234 + gintsts_data_t gintsts;
8235 + gintmsk_data_t gintmsk;
8236 + gintmsk_data_t gintmsk_common = {.d32=0};
8237 + gintmsk_common.b.wkupintr = 1;
8238 + gintmsk_common.b.sessreqintr = 1;
8239 + gintmsk_common.b.conidstschng = 1;
8240 + gintmsk_common.b.otgintr = 1;
8241 + gintmsk_common.b.modemismatch = 1;
8242 + gintmsk_common.b.disconnect = 1;
8243 + gintmsk_common.b.usbsuspend = 1;
8244 + /** @todo: The port interrupt occurs while in device
8245 + * mode. Added code to CIL to clear the interrupt for now!
8246 + */
8247 + gintmsk_common.b.portintr = 1;
8248 +
8249 + gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
8250 + gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
8251 +#ifdef DEBUG
8252 + /* if any common interrupts set */
8253 + if (gintsts.d32 & gintmsk_common.d32) {
8254 + DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
8255 + gintsts.d32, gintmsk.d32);
8256 + }
8257 +#endif
8258 +
8259 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
8260 +
8261 +}
8262 +
8263 +/**
8264 + * Common interrupt handler.
8265 + *
8266 + * The common interrupts are those that occur in both Host and Device mode.
8267 + * This handler handles the following interrupts:
8268 + * - Mode Mismatch Interrupt
8269 + * - Disconnect Interrupt
8270 + * - OTG Interrupt
8271 + * - Connector ID Status Change Interrupt
8272 + * - Session Request Interrupt.
8273 + * - Resume / Remote Wakeup Detected Interrupt.
8274 + *
8275 + */
8276 +int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
8277 +{
8278 + int retval = 0;
8279 + gintsts_data_t gintsts;
8280 +
8281 + gintsts.d32 = dwc_otg_read_common_intr(core_if);
8282 +
8283 + if (gintsts.b.modemismatch) {
8284 + retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
8285 + }
8286 + if (gintsts.b.otgintr) {
8287 + retval |= dwc_otg_handle_otg_intr(core_if);
8288 + }
8289 + if (gintsts.b.conidstschng) {
8290 + retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
8291 + }
8292 + if (gintsts.b.disconnect) {
8293 + retval |= dwc_otg_handle_disconnect_intr(core_if);
8294 + }
8295 + if (gintsts.b.sessreqintr) {
8296 + retval |= dwc_otg_handle_session_req_intr(core_if);
8297 + }
8298 + if (gintsts.b.wkupintr) {
8299 + retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
8300 + }
8301 + if (gintsts.b.usbsuspend) {
8302 + retval |= dwc_otg_handle_usb_suspend_intr(core_if);
8303 + }
8304 + if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
8305 + /* The port interrupt occurs while in device mode with HPRT0
8306 + * Port Enable/Disable.
8307 + */
8308 + gintsts.d32 = 0;
8309 + gintsts.b.portintr = 1;
8310 + dwc_write_reg32(&core_if->core_global_regs->gintsts,
8311 + gintsts.d32);
8312 + retval |= 1;
8313 +
8314 + }
8315 +
8316 + S3C2410X_CLEAR_EINTPEND();
8317 +
8318 + return retval;
8319 +}
8320 diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c
8321 new file mode 100644
8322 index 0000000..63272d0
8323 --- /dev/null
8324 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
8325 @@ -0,0 +1,1273 @@
8326 +/* ==========================================================================
8327 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
8328 + * $Revision: 1.7 $
8329 + * $Date: 2008-11-21 05:39:15 $
8330 + * $Change: 791271 $
8331 + *
8332 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8333 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
8334 + * otherwise expressly agreed to in writing between Synopsys and you.
8335 + *
8336 + * The Software IS NOT an item of Licensed Software or Licensed Product under
8337 + * any End User Software License Agreement or Agreement for Licensed Product
8338 + * with Synopsys or any supplement thereto. You are permitted to use and
8339 + * redistribute this Software in source and binary forms, with or without
8340 + * modification, provided that redistributions of source code must retain this
8341 + * notice. You may not view, use, disclose, copy or distribute this file or
8342 + * any information contained herein except pursuant to this license grant from
8343 + * Synopsys. If you do not agree with this notice, including the disclaimer
8344 + * below, then you are not authorized to use the Software.
8345 + *
8346 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
8347 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8348 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
8349 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
8350 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8351 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
8352 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
8353 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
8354 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
8355 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
8356 + * DAMAGE.
8357 + * ========================================================================== */
8358 +
8359 +/** @file
8360 + * The dwc_otg_driver module provides the initialization and cleanup entry
8361 + * points for the DWC_otg driver. This module will be dynamically installed
8362 + * after Linux is booted using the insmod command. When the module is
8363 + * installed, the dwc_otg_driver_init function is called. When the module is
8364 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
8365 + *
8366 + * This module also defines a data structure for the dwc_otg_driver, which is
8367 + * used in conjunction with the standard ARM platform_device structure. These
8368 + * structures allow the OTG driver to comply with the standard Linux driver
8369 + * model in which devices and drivers are registered with a bus driver. This
8370 + * has the benefit that Linux can expose attributes of the driver and device
8371 + * in its special sysfs file system. Users can then read or write files in
8372 + * this file system to perform diagnostics on the driver components or the
8373 + * device.
8374 + */
8375 +
8376 +#include <linux/kernel.h>
8377 +#include <linux/module.h>
8378 +#include <linux/moduleparam.h>
8379 +#include <linux/init.h>
8380 +#include <linux/device.h>
8381 +#include <linux/errno.h>
8382 +#include <linux/types.h>
8383 +#include <linux/stat.h> /* permission constants */
8384 +#include <linux/version.h>
8385 +#include <linux/platform_device.h>
8386 +
8387 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
8388 +# include <linux/irq.h>
8389 +#endif
8390 +
8391 +#include <asm/io.h>
8392 +
8393 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
8394 +# include <asm/irq.h>
8395 +#endif
8396 +
8397 +#include "linux/dwc_otg_plat.h"
8398 +#include "dwc_otg_attr.h"
8399 +#include "dwc_otg_driver.h"
8400 +#include "dwc_otg_cil.h"
8401 +#include "dwc_otg_pcd.h"
8402 +#include "dwc_otg_hcd.h"
8403 +
8404 +#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008"
8405 +#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
8406 +
8407 +static const char dwc_driver_name[] = "dwc_otg";
8408 +
8409 +/*-------------------------------------------------------------------------*/
8410 +/* Encapsulate the module parameter settings */
8411 +
8412 +static dwc_otg_core_params_t dwc_otg_module_params = {
8413 + .opt = -1,
8414 + .otg_cap = -1,
8415 + .dma_enable = -1,
8416 + .dma_desc_enable = -1,
8417 + .dma_burst_size = -1,
8418 + .speed = -1,
8419 + .host_support_fs_ls_low_power = -1,
8420 + .host_ls_low_power_phy_clk = -1,
8421 + .enable_dynamic_fifo = -1,
8422 + .data_fifo_size = -1,
8423 + .dev_rx_fifo_size = -1,
8424 + .dev_nperio_tx_fifo_size = -1,
8425 + .dev_perio_tx_fifo_size = {
8426 + /* dev_perio_tx_fifo_size_1 */
8427 + -1,
8428 + -1,
8429 + -1,
8430 + -1,
8431 + -1,
8432 + -1,
8433 + -1,
8434 + -1,
8435 + -1,
8436 + -1,
8437 + -1,
8438 + -1,
8439 + -1,
8440 + -1,
8441 + -1
8442 + /* 15 */
8443 + },
8444 + .host_rx_fifo_size = -1,
8445 + .host_nperio_tx_fifo_size = -1,
8446 + .host_perio_tx_fifo_size = -1,
8447 + .max_transfer_size = -1,
8448 + .max_packet_count = -1,
8449 + .host_channels = -1,
8450 + .dev_endpoints = -1,
8451 + .phy_type = -1,
8452 + .phy_utmi_width = -1,
8453 + .phy_ulpi_ddr = -1,
8454 + .phy_ulpi_ext_vbus = -1,
8455 + .i2c_enable = -1,
8456 + .ulpi_fs_ls = -1,
8457 + .ts_dline = -1,
8458 + .en_multiple_tx_fifo = -1,
8459 + .dev_tx_fifo_size = {
8460 + /* dev_tx_fifo_size */
8461 + -1,
8462 + -1,
8463 + -1,
8464 + -1,
8465 + -1,
8466 + -1,
8467 + -1,
8468 + -1,
8469 + -1,
8470 + -1,
8471 + -1,
8472 + -1,
8473 + -1,
8474 + -1,
8475 + -1
8476 + /* 15 */
8477 + },
8478 + .thr_ctl = -1,
8479 + .tx_thr_length = -1,
8480 + .rx_thr_length = -1,
8481 + .pti_enable = -1,
8482 + .mpi_enable = -1,
8483 +};
8484 +
8485 +/**
8486 + * This function shows the Driver Version.
8487 + */
8488 +static ssize_t version_show(struct device_driver *dev, char *buf)
8489 +{
8490 + return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n",
8491 + DWC_DRIVER_VERSION);
8492 +}
8493 +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
8494 +
8495 +/**
8496 + * Global Debug Level Mask.
8497 + */
8498 +uint32_t g_dbg_lvl = 0; /* OFF */
8499 +
8500 +/**
8501 + * This function shows the driver Debug Level.
8502 + */
8503 +static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
8504 +{
8505 + return sprintf(buf, "0x%0x\n", g_dbg_lvl);
8506 +}
8507 +
8508 +/**
8509 + * This function stores the driver Debug Level.
8510 + */
8511 +static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
8512 + size_t count)
8513 +{
8514 + g_dbg_lvl = simple_strtoul(buf, NULL, 16);
8515 + return count;
8516 +}
8517 +static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
8518 +
8519 +/**
8520 + * This function is called during module intialization to verify that
8521 + * the module parameters are in a valid state.
8522 + */
8523 +static int check_parameters(dwc_otg_core_if_t *core_if)
8524 +{
8525 + int i;
8526 + int retval = 0;
8527 +
8528 +/* Checks if the parameter is outside of its valid range of values */
8529 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
8530 + ((dwc_otg_module_params._param_ < (_low_)) || \
8531 + (dwc_otg_module_params._param_ > (_high_)))
8532 +
8533 +/* If the parameter has been set by the user, check that the parameter value is
8534 + * within the value range of values. If not, report a module error. */
8535 +#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
8536 + do { \
8537 + if (dwc_otg_module_params._param_ != -1) { \
8538 + if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
8539 + DWC_ERROR("`%d' invalid for parameter `%s'\n", \
8540 + dwc_otg_module_params._param_, _string_); \
8541 + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
8542 + retval++; \
8543 + } \
8544 + } \
8545 + } while (0)
8546 +
8547 + DWC_OTG_PARAM_ERR(opt,0,1,"opt");
8548 + DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
8549 + DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
8550 + DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
8551 + DWC_OTG_PARAM_ERR(speed,0,1,"speed");
8552 + DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
8553 + DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
8554 + DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
8555 + DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
8556 + DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
8557 + DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
8558 + DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
8559 + DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
8560 + DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
8561 + DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
8562 + DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
8563 + DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
8564 + DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
8565 + DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
8566 + DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
8567 + DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
8568 + DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
8569 + DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
8570 + DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
8571 +
8572 + if (dwc_otg_module_params.dma_burst_size != -1) {
8573 + if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
8574 + DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
8575 + DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
8576 + DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
8577 + DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
8578 + DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
8579 + DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
8580 + DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
8581 + DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
8582 + dwc_otg_module_params.dma_burst_size);
8583 + dwc_otg_module_params.dma_burst_size = 32;
8584 + retval++;
8585 + }
8586 +
8587 + {
8588 + uint8_t brst_sz = 0;
8589 + while(dwc_otg_module_params.dma_burst_size > 1) {
8590 + brst_sz ++;
8591 + dwc_otg_module_params.dma_burst_size >>= 1;
8592 + }
8593 + dwc_otg_module_params.dma_burst_size = brst_sz;
8594 + }
8595 + }
8596 +
8597 + if (dwc_otg_module_params.phy_utmi_width != -1) {
8598 + if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
8599 + DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
8600 + DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
8601 + dwc_otg_module_params.phy_utmi_width);
8602 + dwc_otg_module_params.phy_utmi_width = 16;
8603 + retval++;
8604 + }
8605 + }
8606 +
8607 + for (i = 0; i < 15; i++) {
8608 + /** @todo should be like above */
8609 + //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
8610 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
8611 + if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
8612 + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
8613 + dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
8614 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
8615 + retval++;
8616 + }
8617 + }
8618 + }
8619 +
8620 + DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
8621 +
8622 + for (i = 0; i < 15; i++) {
8623 + /** @todo should be like above */
8624 + //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
8625 + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
8626 + if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
8627 + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
8628 + dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
8629 + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
8630 + retval++;
8631 + }
8632 + }
8633 + }
8634 +
8635 + DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
8636 + DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
8637 + DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
8638 +
8639 + DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
8640 + DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
8641 +
8642 + /* At this point, all module parameters that have been set by the user
8643 + * are valid, and those that have not are left unset. Now set their
8644 + * default values and/or check the parameters against the hardware
8645 + * configurations of the OTG core. */
8646 +
8647 +/* This sets the parameter to the default value if it has not been set by the
8648 + * user */
8649 +#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
8650 + ({ \
8651 + int changed = 1; \
8652 + if (dwc_otg_module_params._param_ == -1) { \
8653 + changed = 0; \
8654 + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
8655 + } \
8656 + changed; \
8657 + })
8658 +
8659 +/* This checks the macro agains the hardware configuration to see if it is
8660 + * valid. It is possible that the default value could be invalid. In this
8661 + * case, it will report a module error if the user touched the parameter.
8662 + * Otherwise it will adjust the value without any error. */
8663 +#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
8664 + ({ \
8665 + int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
8666 + int error = 0; \
8667 + if (!(_is_valid_)) { \
8668 + if (changed) { \
8669 + DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
8670 + error = 1; \
8671 + } \
8672 + dwc_otg_module_params._param_ = (_set_valid_); \
8673 + } \
8674 + error; \
8675 + })
8676 +
8677 + /* OTG Cap */
8678 + retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
8679 + ({
8680 + int valid;
8681 + valid = 1;
8682 + switch (dwc_otg_module_params.otg_cap) {
8683 + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
8684 + if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
8685 + valid = 0;
8686 + break;
8687 + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
8688 + if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
8689 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
8690 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
8691 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
8692 + valid = 0;
8693 + }
8694 + break;
8695 + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
8696 + /* always valid */
8697 + break;
8698 + }
8699 + valid;
8700 + }),
8701 + (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
8702 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
8703 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
8704 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
8705 + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
8706 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
8707 +
8708 + retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
8709 + ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
8710 + 0);
8711 +
8712 + retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
8713 + ((dwc_otg_module_params.dma_desc_enable == 1) &&
8714 + ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
8715 + 0);
8716 +
8717 + retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
8718 +
8719 + DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
8720 +
8721 + retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
8722 + "host_support_fs_ls_low_power",
8723 + 1, 0);
8724 +
8725 + retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
8726 + "enable_dynamic_fifo",
8727 + ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
8728 + (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
8729 +
8730 + retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
8731 + "data_fifo_size",
8732 + (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
8733 + core_if->hwcfg3.b.dfifo_depth);
8734 +
8735 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
8736 + "dev_rx_fifo_size",
8737 + (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
8738 + dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
8739 +
8740 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
8741 + "dev_nperio_tx_fifo_size",
8742 + (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
8743 + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
8744 +
8745 + retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
8746 + "host_rx_fifo_size",
8747 + (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
8748 + dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
8749 +
8750 + retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
8751 + "host_nperio_tx_fifo_size",
8752 + (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
8753 + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
8754 +
8755 + retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
8756 + "host_perio_tx_fifo_size",
8757 + (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
8758 + ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
8759 +
8760 + retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
8761 + "max_transfer_size",
8762 + (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
8763 + ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
8764 +
8765 + retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
8766 + "max_packet_count",
8767 + (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
8768 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
8769 +
8770 + retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
8771 + "host_channels",
8772 + (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
8773 + (core_if->hwcfg2.b.num_host_chan + 1));
8774 +
8775 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
8776 + "dev_endpoints",
8777 + (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
8778 + core_if->hwcfg2.b.num_dev_ep);
8779 +
8780 +/*
8781 + * Define the following to disable the FS PHY Hardware checking. This is for
8782 + * internal testing only.
8783 + *
8784 + * #define NO_FS_PHY_HW_CHECKS
8785 + */
8786 +
8787 +#ifdef NO_FS_PHY_HW_CHECKS
8788 + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
8789 + "phy_type", 1, 0);
8790 +#else
8791 + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
8792 + "phy_type",
8793 + ({
8794 + int valid = 0;
8795 + if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
8796 + ((core_if->hwcfg2.b.hs_phy_type == 1) ||
8797 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
8798 + valid = 1;
8799 + }
8800 + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
8801 + ((core_if->hwcfg2.b.hs_phy_type == 2) ||
8802 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
8803 + valid = 1;
8804 + }
8805 + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
8806 + (core_if->hwcfg2.b.fs_phy_type == 1)) {
8807 + valid = 1;
8808 + }
8809 + valid;
8810 + }),
8811 + ({
8812 + int set = DWC_PHY_TYPE_PARAM_FS;
8813 + if (core_if->hwcfg2.b.hs_phy_type) {
8814 + if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
8815 + (core_if->hwcfg2.b.hs_phy_type == 1)) {
8816 + set = DWC_PHY_TYPE_PARAM_UTMI;
8817 + }
8818 + else {
8819 + set = DWC_PHY_TYPE_PARAM_ULPI;
8820 + }
8821 + }
8822 + set;
8823 + }));
8824 +#endif
8825 +
8826 + retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
8827 + (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
8828 + dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
8829 +
8830 + retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
8831 + "host_ls_low_power_phy_clk",
8832 + ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
8833 + ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
8834 +
8835 + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
8836 + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
8837 + DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
8838 + DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
8839 + DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
8840 +
8841 +#ifdef NO_FS_PHY_HW_CHECKS
8842 + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
8843 +#else
8844 + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
8845 + "i2c_enable",
8846 + (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
8847 + 0);
8848 +#endif
8849 +
8850 + for (i = 0; i < 15; i++) {
8851 + int changed = 1;
8852 + int error = 0;
8853 +
8854 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
8855 + changed = 0;
8856 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
8857 + }
8858 + if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
8859 + if (changed) {
8860 + DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
8861 + error = 1;
8862 + }
8863 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
8864 + }
8865 + retval += error;
8866 + }
8867 +
8868 + retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
8869 + ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
8870 + 0);
8871 +
8872 + for (i = 0; i < 15; i++) {
8873 + int changed = 1;
8874 + int error = 0;
8875 +
8876 + if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
8877 + changed = 0;
8878 + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
8879 + }
8880 + if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
8881 + if (changed) {
8882 + DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
8883 + error = 1;
8884 + }
8885 + dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
8886 + }
8887 + retval += error;
8888 + }
8889 +
8890 + retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
8891 + ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
8892 + 0);
8893 +
8894 + DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
8895 + DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
8896 +
8897 + retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
8898 + ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
8899 + 0);
8900 +
8901 + retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
8902 + ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
8903 + 0);
8904 + return retval;
8905 +}
8906 +
8907 +/**
8908 + * This function is the top level interrupt handler for the Common
8909 + * (Device and host modes) interrupts.
8910 + */
8911 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev
8912 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
8913 + , struct pt_regs *r
8914 +#endif
8915 + )
8916 +{
8917 + dwc_otg_device_t *otg_dev = dev;
8918 + int32_t retval = IRQ_NONE;
8919 +
8920 + retval = dwc_otg_handle_common_intr(otg_dev->core_if);
8921 + return IRQ_RETVAL(retval);
8922 +}
8923 +
8924 +/**
8925 + * This function is called when a platform_device is unregistered with the
8926 + * dwc_otg_driver. This happens, for example, when the rmmod command is
8927 + * executed. The device may or may not be electrically present. If it is
8928 + * present, the driver stops device processing. Any resources used on behalf
8929 + * of this device are freed.
8930 + *
8931 + * @param[in] pdev
8932 + */
8933 +static int dwc_otg_driver_remove(struct platform_device *pdev)
8934 +{
8935 + dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
8936 + DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
8937 +
8938 + if (!otg_dev) {
8939 + /* Memory allocation for the dwc_otg_device failed. */
8940 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
8941 + return 0;
8942 + }
8943 +
8944 + /*
8945 + * Free the IRQ
8946 + */
8947 + if (otg_dev->common_irq_installed) {
8948 + free_irq(otg_dev->irq, otg_dev);
8949 + }
8950 +
8951 +#ifndef DWC_DEVICE_ONLY
8952 + if (otg_dev->hcd) {
8953 + dwc_otg_hcd_remove(&pdev->dev);
8954 + } else {
8955 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
8956 + return 0;
8957 + }
8958 +#endif
8959 +
8960 +#ifndef DWC_HOST_ONLY
8961 + if (otg_dev->pcd) {
8962 + dwc_otg_pcd_remove(&pdev->dev);
8963 + }
8964 +#endif
8965 + if (otg_dev->core_if) {
8966 + dwc_otg_cil_remove(otg_dev->core_if);
8967 + }
8968 +
8969 + /*
8970 + * Remove the device attributes
8971 + */
8972 + dwc_otg_attr_remove(otg_dev->parent);
8973 +
8974 + /* Disable USB port */
8975 + dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0xf);
8976 +
8977 + /*
8978 + * Return the memory.
8979 + */
8980 + if (otg_dev->base) {
8981 + iounmap(otg_dev->base);
8982 + }
8983 +
8984 + if (otg_dev->phys_addr != 0) {
8985 + release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
8986 + }
8987 +
8988 + kfree(otg_dev);
8989 +
8990 + /*
8991 + * Clear the drvdata pointer.
8992 + */
8993 + platform_set_drvdata(pdev, NULL);
8994 +
8995 + return 0;
8996 +}
8997 +
8998 +/**
8999 + * This function is called when an platform_device is bound to a
9000 + * dwc_otg_driver. It creates the driver components required to
9001 + * control the device (CIL, HCD, and PCD) and it initializes the
9002 + * device. The driver components are stored in a dwc_otg_device
9003 + * structure. A reference to the dwc_otg_device is saved in the
9004 + * platform_device. This allows the driver to access the dwc_otg_device
9005 + * structure on subsequent calls to driver methods for this device.
9006 + *
9007 + * @param[in] pdev platform_device definition
9008 + */
9009 +static int dwc_otg_driver_probe(struct platform_device *pdev)
9010 +{
9011 + int retval = 0;
9012 + uint32_t snpsid;
9013 + dwc_otg_device_t *otg_dev;
9014 + struct resource *res;
9015 +
9016 + dev_dbg(&pdev->dev, "dwc_otg_driver_probe(%p)\n", pdev);
9017 +
9018 + otg_dev= kzalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
9019 + if (!otg_dev) {
9020 + dev_err(&pdev->dev, "kmalloc of dwc_otg_device failed\n");
9021 + retval = -ENOMEM;
9022 + goto fail;
9023 + }
9024 +
9025 + otg_dev->reg_offset = 0xFFFFFFFF;
9026 +
9027 + /*
9028 + * Retrieve the memory and IRQ resources.
9029 + */
9030 + otg_dev->irq = platform_get_irq(pdev, 0);
9031 + if (otg_dev->irq <= 0) {
9032 + dev_err(&pdev->dev, "no device irq\n");
9033 + retval = -EINVAL;
9034 + goto fail;
9035 + }
9036 +
9037 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9038 + if (res == NULL) {
9039 + dev_err(&pdev->dev, "no CSR address\n");
9040 + retval = -EINVAL;
9041 + goto fail;
9042 + }
9043 +
9044 + otg_dev->parent = &pdev->dev;
9045 + otg_dev->phys_addr = res->start;
9046 + otg_dev->base_len = res->end - res->start + 1;
9047 + if (request_mem_region(otg_dev->phys_addr,
9048 + otg_dev->base_len,
9049 + dwc_driver_name) == NULL) {
9050 + dev_err(&pdev->dev, "request_mem_region failed\n");
9051 + retval = -EBUSY;
9052 + goto fail;
9053 + }
9054 +
9055 + /*
9056 + * Map the DWC_otg Core memory into virtual address space.
9057 + */
9058 + otg_dev->base = ioremap(otg_dev->phys_addr, otg_dev->base_len);
9059 + if (!otg_dev->base) {
9060 + dev_err(&pdev->dev, "ioremap() failed\n");
9061 + retval = -ENOMEM;
9062 + goto fail;
9063 + }
9064 + dev_dbg(&pdev->dev, "mapped base=0x%08x\n", (unsigned) otg_dev->base);
9065 +
9066 + /* Enable USB Port */
9067 + dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0);
9068 +
9069 + /*
9070 + * Attempt to ensure this device is really a DWC_otg Controller.
9071 + * Read and verify the SNPSID register contents. The value should be
9072 + * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
9073 + */
9074 + snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0x40));
9075 +
9076 + if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
9077 + dev_err(&pdev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
9078 + retval = -EINVAL;
9079 + goto fail;
9080 + }
9081 +
9082 + DWC_PRINT("Core Release: %x.%x%x%x\n",
9083 + (snpsid >> 12 & 0xF),
9084 + (snpsid >> 8 & 0xF),
9085 + (snpsid >> 4 & 0xF),
9086 + (snpsid & 0xF));
9087 +
9088 + /*
9089 + * Initialize driver data to point to the global DWC_otg
9090 + * Device structure.
9091 + */
9092 + platform_set_drvdata(pdev, otg_dev);
9093 + dev_dbg(&pdev->dev, "dwc_otg_device=0x%p\n", otg_dev);
9094 +
9095 +
9096 + otg_dev->core_if = dwc_otg_cil_init(otg_dev->base,
9097 + &dwc_otg_module_params);
9098 +
9099 + otg_dev->core_if->snpsid = snpsid;
9100 +
9101 + if (!otg_dev->core_if) {
9102 + dev_err(&pdev->dev, "CIL initialization failed!\n");
9103 + retval = -ENOMEM;
9104 + goto fail;
9105 + }
9106 +
9107 + /*
9108 + * Validate parameter values.
9109 + */
9110 + if (check_parameters(otg_dev->core_if)) {
9111 + retval = -EINVAL;
9112 + goto fail;
9113 + }
9114 +
9115 + /*
9116 + * Create Device Attributes in sysfs
9117 + */
9118 + dwc_otg_attr_create(&pdev->dev);
9119 +
9120 + /*
9121 + * Disable the global interrupt until all the interrupt
9122 + * handlers are installed.
9123 + */
9124 + dwc_otg_disable_global_interrupts(otg_dev->core_if);
9125 +
9126 + /*
9127 + * Install the interrupt handler for the common interrupts before
9128 + * enabling common interrupts in core_init below.
9129 + */
9130 + DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
9131 + otg_dev->irq);
9132 + retval = request_irq(otg_dev->irq, dwc_otg_common_irq,
9133 + IRQF_SHARED, "dwc_otg", otg_dev);
9134 + if (retval) {
9135 + DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
9136 + retval = -EBUSY;
9137 + goto fail;
9138 + } else {
9139 + otg_dev->common_irq_installed = 1;
9140 + }
9141 +
9142 + /*
9143 + * Initialize the DWC_otg core.
9144 + */
9145 + dwc_otg_core_init(otg_dev->core_if);
9146 +
9147 +#ifndef DWC_HOST_ONLY
9148 + /*
9149 + * Initialize the PCD
9150 + */
9151 + retval = dwc_otg_pcd_init(&pdev->dev);
9152 + if (retval != 0) {
9153 + DWC_ERROR("dwc_otg_pcd_init failed\n");
9154 + otg_dev->pcd = NULL;
9155 + goto fail;
9156 + }
9157 +#endif
9158 +#ifndef DWC_DEVICE_ONLY
9159 + /*
9160 + * Initialize the HCD
9161 + */
9162 + retval = dwc_otg_hcd_init(&pdev->dev);
9163 + if (retval != 0) {
9164 + DWC_ERROR("dwc_otg_hcd_init failed\n");
9165 + otg_dev->hcd = NULL;
9166 + goto fail;
9167 + }
9168 +#endif
9169 +
9170 + /*
9171 + * Enable the global interrupt after all the interrupt
9172 + * handlers are installed.
9173 + */
9174 + dwc_otg_enable_global_interrupts(otg_dev->core_if);
9175 +
9176 + return 0;
9177 +
9178 + fail:
9179 + dwc_otg_driver_remove(pdev);
9180 + return retval;
9181 +}
9182 +
9183 +/**
9184 + * This structure defines the methods to be called by a bus driver
9185 + * during the lifecycle of a device on that bus. Both drivers and
9186 + * devices are registered with a bus driver. The bus driver matches
9187 + * devices to drivers based on information in the device and driver
9188 + * structures.
9189 + *
9190 + * The probe function is called when the bus driver matches a device
9191 + * to this driver. The remove function is called when a device is
9192 + * unregistered with the bus driver.
9193 + */
9194 +
9195 +static const struct of_device_id ralink_otg_match[] = {
9196 + { .compatible = "ralink,rt3050-otg" },
9197 + {},
9198 +};
9199 +MODULE_DEVICE_TABLE(of, ralink_otg_match);
9200 +
9201 +static struct platform_driver dwc_otg_driver = {
9202 + .driver = {
9203 + .name = (char *)dwc_driver_name,
9204 + .of_match_table = ralink_otg_match,
9205 + },
9206 + .probe = dwc_otg_driver_probe,
9207 + .remove = dwc_otg_driver_remove,
9208 +};
9209 +
9210 +/**
9211 + * This function is called when the dwc_otg_driver is installed with the
9212 + * insmod command. It registers the dwc_otg_driver structure with the
9213 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
9214 + * to be called. In addition, the bus driver will automatically expose
9215 + * attributes defined for the device and driver in the special sysfs file
9216 + * system.
9217 + *
9218 + * @return
9219 + */
9220 +static int __init dwc_otg_driver_init(void)
9221 +{
9222 + int retval = 0;
9223 + int error;
9224 +
9225 + printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
9226 +
9227 + retval = platform_driver_register(&dwc_otg_driver);
9228 + if (retval) {
9229 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
9230 + return retval;
9231 + }
9232 +
9233 + error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
9234 + error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
9235 +
9236 + return retval;
9237 +}
9238 +module_init(dwc_otg_driver_init);
9239 +
9240 +/**
9241 + * This function is called when the driver is removed from the kernel
9242 + * with the rmmod command. The driver unregisters itself with its bus
9243 + * driver.
9244 + *
9245 + */
9246 +static void __exit dwc_otg_driver_cleanup(void)
9247 +{
9248 + printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
9249 +
9250 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
9251 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
9252 +
9253 + platform_driver_unregister(&dwc_otg_driver);
9254 +
9255 + printk(KERN_INFO "%s module removed\n", dwc_driver_name);
9256 +}
9257 +module_exit(dwc_otg_driver_cleanup);
9258 +
9259 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
9260 +MODULE_AUTHOR("Synopsys Inc.");
9261 +MODULE_LICENSE("GPL");
9262 +
9263 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
9264 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
9265 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
9266 +MODULE_PARM_DESC(opt, "OPT Mode");
9267 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
9268 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
9269 +
9270 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
9271 +MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
9272 +
9273 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
9274 +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
9275 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
9276 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
9277 +module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
9278 +MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
9279 +module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
9280 +MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
9281 +module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
9282 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
9283 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
9284 +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
9285 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
9286 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
9287 +module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
9288 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
9289 +module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
9290 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
9291 +module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
9292 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
9293 +module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
9294 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
9295 +module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
9296 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
9297 +module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
9298 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
9299 +module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
9300 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
9301 +module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
9302 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
9303 +module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
9304 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
9305 +module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
9306 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
9307 +module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
9308 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
9309 +module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
9310 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
9311 +module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
9312 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
9313 +module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
9314 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
9315 +module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
9316 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
9317 +module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
9318 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
9319 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
9320 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
9321 +module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
9322 +MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
9323 +module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
9324 +MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
9325 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
9326 +/** @todo Set the max to 512K, modify checks */
9327 +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
9328 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
9329 +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
9330 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
9331 +MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
9332 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
9333 +MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
9334 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
9335 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
9336 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
9337 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
9338 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
9339 +MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
9340 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
9341 +MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
9342 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
9343 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
9344 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
9345 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
9346 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
9347 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
9348 +module_param_named(debug, g_dbg_lvl, int, 0444);
9349 +MODULE_PARM_DESC(debug, "");
9350 +
9351 +module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
9352 +MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
9353 +module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
9354 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
9355 +module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
9356 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
9357 +module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
9358 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
9359 +module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
9360 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
9361 +module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
9362 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
9363 +module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
9364 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
9365 +module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
9366 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
9367 +module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
9368 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
9369 +module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
9370 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
9371 +module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
9372 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
9373 +module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
9374 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
9375 +module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
9376 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
9377 +module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
9378 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
9379 +module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
9380 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
9381 +module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
9382 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
9383 +
9384 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
9385 +MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
9386 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
9387 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
9388 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
9389 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
9390 +
9391 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
9392 +MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
9393 +
9394 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
9395 +MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
9396 +
9397 +/** @page "Module Parameters"
9398 + *
9399 + * The following parameters may be specified when starting the module.
9400 + * These parameters define how the DWC_otg controller should be
9401 + * configured. Parameter values are passed to the CIL initialization
9402 + * function dwc_otg_cil_init
9403 + *
9404 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
9405 + *
9406 +
9407 + <table>
9408 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
9409 +
9410 + <tr>
9411 + <td>otg_cap</td>
9412 + <td>Specifies the OTG capabilities. The driver will automatically detect the
9413 + value for this parameter if none is specified.
9414 + - 0: HNP and SRP capable (default, if available)
9415 + - 1: SRP Only capable
9416 + - 2: No HNP/SRP capable
9417 + </td></tr>
9418 +
9419 + <tr>
9420 + <td>dma_enable</td>
9421 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
9422 + The driver will automatically detect the value for this parameter if none is
9423 + specified.
9424 + - 0: Slave
9425 + - 1: DMA (default, if available)
9426 + </td></tr>
9427 +
9428 + <tr>
9429 + <td>dma_burst_size</td>
9430 + <td>The DMA Burst size (applicable only for External DMA Mode).
9431 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
9432 + </td></tr>
9433 +
9434 + <tr>
9435 + <td>speed</td>
9436 + <td>Specifies the maximum speed of operation in host and device mode. The
9437 + actual speed depends on the speed of the attached device and the value of
9438 + phy_type.
9439 + - 0: High Speed (default)
9440 + - 1: Full Speed
9441 + </td></tr>
9442 +
9443 + <tr>
9444 + <td>host_support_fs_ls_low_power</td>
9445 + <td>Specifies whether low power mode is supported when attached to a Full
9446 + Speed or Low Speed device in host mode.
9447 + - 0: Don't support low power mode (default)
9448 + - 1: Support low power mode
9449 + </td></tr>
9450 +
9451 + <tr>
9452 + <td>host_ls_low_power_phy_clk</td>
9453 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
9454 + Speed device in host mode. This parameter is applicable only if
9455 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
9456 + - 0: 48 MHz (default)
9457 + - 1: 6 MHz
9458 + </td></tr>
9459 +
9460 + <tr>
9461 + <td>enable_dynamic_fifo</td>
9462 + <td> Specifies whether FIFOs may be resized by the driver software.
9463 + - 0: Use cC FIFO size parameters
9464 + - 1: Allow dynamic FIFO sizing (default)
9465 + </td></tr>
9466 +
9467 + <tr>
9468 + <td>data_fifo_size</td>
9469 + <td>Total number of 4-byte words in the data FIFO memory. This memory
9470 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
9471 + - Values: 32 to 32768 (default 8192)
9472 +
9473 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
9474 + </td></tr>
9475 +
9476 + <tr>
9477 + <td>dev_rx_fifo_size</td>
9478 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
9479 + FIFO sizing is enabled.
9480 + - Values: 16 to 32768 (default 1064)
9481 + </td></tr>
9482 +
9483 + <tr>
9484 + <td>dev_nperio_tx_fifo_size</td>
9485 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
9486 + dynamic FIFO sizing is enabled.
9487 + - Values: 16 to 32768 (default 1024)
9488 + </td></tr>
9489 +
9490 + <tr>
9491 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
9492 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
9493 + when dynamic FIFO sizing is enabled.
9494 + - Values: 4 to 768 (default 256)
9495 + </td></tr>
9496 +
9497 + <tr>
9498 + <td>host_rx_fifo_size</td>
9499 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
9500 + sizing is enabled.
9501 + - Values: 16 to 32768 (default 1024)
9502 + </td></tr>
9503 +
9504 + <tr>
9505 + <td>host_nperio_tx_fifo_size</td>
9506 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
9507 + dynamic FIFO sizing is enabled in the core.
9508 + - Values: 16 to 32768 (default 1024)
9509 + </td></tr>
9510 +
9511 + <tr>
9512 + <td>host_perio_tx_fifo_size</td>
9513 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
9514 + sizing is enabled.
9515 + - Values: 16 to 32768 (default 1024)
9516 + </td></tr>
9517 +
9518 + <tr>
9519 + <td>max_transfer_size</td>
9520 + <td>The maximum transfer size supported in bytes.
9521 + - Values: 2047 to 65,535 (default 65,535)
9522 + </td></tr>
9523 +
9524 + <tr>
9525 + <td>max_packet_count</td>
9526 + <td>The maximum number of packets in a transfer.
9527 + - Values: 15 to 511 (default 511)
9528 + </td></tr>
9529 +
9530 + <tr>
9531 + <td>host_channels</td>
9532 + <td>The number of host channel registers to use.
9533 + - Values: 1 to 16 (default 12)
9534 +
9535 + Note: The FPGA configuration supports a maximum of 12 host channels.
9536 + </td></tr>
9537 +
9538 + <tr>
9539 + <td>dev_endpoints</td>
9540 + <td>The number of endpoints in addition to EP0 available for device mode
9541 + operations.
9542 + - Values: 1 to 15 (default 6 IN and OUT)
9543 +
9544 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
9545 + addition to EP0.
9546 + </td></tr>
9547 +
9548 + <tr>
9549 + <td>phy_type</td>
9550 + <td>Specifies the type of PHY interface to use. By default, the driver will
9551 + automatically detect the phy_type.
9552 + - 0: Full Speed
9553 + - 1: UTMI+ (default, if available)
9554 + - 2: ULPI
9555 + </td></tr>
9556 +
9557 + <tr>
9558 + <td>phy_utmi_width</td>
9559 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
9560 + phy_type of UTMI+. Also, this parameter is applicable only if the
9561 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
9562 + core has been configured to work at either data path width.
9563 + - Values: 8 or 16 bits (default 16)
9564 + </td></tr>
9565 +
9566 + <tr>
9567 + <td>phy_ulpi_ddr</td>
9568 + <td>Specifies whether the ULPI operates at double or single data rate. This
9569 + parameter is only applicable if phy_type is ULPI.
9570 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
9571 + - 1: double data rate ULPI interface with 4 bit wide data bus
9572 + </td></tr>
9573 +
9574 + <tr>
9575 + <td>i2c_enable</td>
9576 + <td>Specifies whether to use the I2C interface for full speed PHY. This
9577 + parameter is only applicable if PHY_TYPE is FS.
9578 + - 0: Disabled (default)
9579 + - 1: Enabled
9580 + </td></tr>
9581 +
9582 + <tr>
9583 + <td>otg_en_multiple_tx_fifo</td>
9584 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
9585 + The driver will automatically detect the value for this parameter if none is
9586 + specified.
9587 + - 0: Disabled
9588 + - 1: Enabled (default, if available)
9589 + </td></tr>
9590 +
9591 + <tr>
9592 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
9593 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
9594 + when dynamic FIFO sizing is enabled.
9595 + - Values: 4 to 768 (default 256)
9596 + </td></tr>
9597 +
9598 +*/
9599 diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.h b/drivers/usb/dwc_otg/dwc_otg_driver.h
9600 new file mode 100644
9601 index 0000000..fd7f0a4
9602 --- /dev/null
9603 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
9604 @@ -0,0 +1,83 @@
9605 +/* ==========================================================================
9606 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
9607 + * $Revision: 1.2 $
9608 + * $Date: 2008-11-21 05:39:15 $
9609 + * $Change: 1064918 $
9610 + *
9611 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
9612 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9613 + * otherwise expressly agreed to in writing between Synopsys and you.
9614 + *
9615 + * The Software IS NOT an item of Licensed Software or Licensed Product under
9616 + * any End User Software License Agreement or Agreement for Licensed Product
9617 + * with Synopsys or any supplement thereto. You are permitted to use and
9618 + * redistribute this Software in source and binary forms, with or without
9619 + * modification, provided that redistributions of source code must retain this
9620 + * notice. You may not view, use, disclose, copy or distribute this file or
9621 + * any information contained herein except pursuant to this license grant from
9622 + * Synopsys. If you do not agree with this notice, including the disclaimer
9623 + * below, then you are not authorized to use the Software.
9624 + *
9625 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
9626 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9627 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9628 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
9629 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9630 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
9631 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
9632 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
9633 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
9634 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9635 + * DAMAGE.
9636 + * ========================================================================== */
9637 +
9638 +#ifndef __DWC_OTG_DRIVER_H__
9639 +#define __DWC_OTG_DRIVER_H__
9640 +
9641 +/** @file
9642 + * This file contains the interface to the Linux driver.
9643 + */
9644 +#include "dwc_otg_cil.h"
9645 +
9646 +/* Type declarations */
9647 +struct dwc_otg_pcd;
9648 +struct dwc_otg_hcd;
9649 +
9650 +/**
9651 + * This structure is a wrapper that encapsulates the driver components used to
9652 + * manage a single DWC_otg controller.
9653 + */
9654 +typedef struct dwc_otg_device {
9655 + /** Base address returned from ioremap() */
9656 + void *base;
9657 +
9658 + struct device *parent;
9659 +
9660 + /** Pointer to the core interface structure. */
9661 + dwc_otg_core_if_t *core_if;
9662 +
9663 + /** Register offset for Diagnostic API. */
9664 + uint32_t reg_offset;
9665 +
9666 + /** Pointer to the PCD structure. */
9667 + struct dwc_otg_pcd *pcd;
9668 +
9669 + /** Pointer to the HCD structure. */
9670 + struct dwc_otg_hcd *hcd;
9671 +
9672 + /** Flag to indicate whether the common IRQ handler is installed. */
9673 + uint8_t common_irq_installed;
9674 +
9675 + /* Interrupt request number. */
9676 + unsigned int irq;
9677 +
9678 + /* Physical address of Control and Status registers, used by
9679 + * release_mem_region().
9680 + */
9681 + resource_size_t phys_addr;
9682 +
9683 + /* Length of memory region, used by release_mem_region(). */
9684 + unsigned long base_len;
9685 +} dwc_otg_device_t;
9686 +
9687 +#endif
9688 diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd.c b/drivers/usb/dwc_otg/dwc_otg_hcd.c
9689 new file mode 100644
9690 index 0000000..fe643b6
9691 --- /dev/null
9692 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c
9693 @@ -0,0 +1,2852 @@
9694 +/* ==========================================================================
9695 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
9696 + * $Revision: 1.4 $
9697 + * $Date: 2008-11-21 05:39:15 $
9698 + * $Change: 1064940 $
9699 + *
9700 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
9701 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9702 + * otherwise expressly agreed to in writing between Synopsys and you.
9703 + *
9704 + * The Software IS NOT an item of Licensed Software or Licensed Product under
9705 + * any End User Software License Agreement or Agreement for Licensed Product
9706 + * with Synopsys or any supplement thereto. You are permitted to use and
9707 + * redistribute this Software in source and binary forms, with or without
9708 + * modification, provided that redistributions of source code must retain this
9709 + * notice. You may not view, use, disclose, copy or distribute this file or
9710 + * any information contained herein except pursuant to this license grant from
9711 + * Synopsys. If you do not agree with this notice, including the disclaimer
9712 + * below, then you are not authorized to use the Software.
9713 + *
9714 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
9715 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9716 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9717 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
9718 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9719 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
9720 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
9721 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
9722 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
9723 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9724 + * DAMAGE.
9725 + * ========================================================================== */
9726 +#ifndef DWC_DEVICE_ONLY
9727 +
9728 +/**
9729 + * @file
9730 + *
9731 + * This file contains the implementation of the HCD. In Linux, the HCD
9732 + * implements the hc_driver API.
9733 + */
9734 +#include <linux/kernel.h>
9735 +#include <linux/module.h>
9736 +#include <linux/moduleparam.h>
9737 +#include <linux/init.h>
9738 +#include <linux/device.h>
9739 +#include <linux/errno.h>
9740 +#include <linux/list.h>
9741 +#include <linux/interrupt.h>
9742 +#include <linux/string.h>
9743 +#include <linux/dma-mapping.h>
9744 +#include <linux/version.h>
9745 +
9746 +#include "dwc_otg_driver.h"
9747 +#include "dwc_otg_hcd.h"
9748 +#include "dwc_otg_regs.h"
9749 +
9750 +static const char dwc_otg_hcd_name[] = "dwc_otg";
9751 +
9752 +static const struct hc_driver dwc_otg_hc_driver = {
9753 +
9754 + .description = dwc_otg_hcd_name,
9755 + .product_desc = "DWC OTG Controller",
9756 + .hcd_priv_size = sizeof(dwc_otg_hcd_t),
9757 +
9758 + .irq = dwc_otg_hcd_irq,
9759 +
9760 + .flags = HCD_MEMORY | HCD_USB2,
9761 +
9762 + //.reset =
9763 + .start = dwc_otg_hcd_start,
9764 + //.suspend =
9765 + //.resume =
9766 + .stop = dwc_otg_hcd_stop,
9767 +
9768 + .urb_enqueue = dwc_otg_hcd_urb_enqueue,
9769 + .urb_dequeue = dwc_otg_hcd_urb_dequeue,
9770 + .endpoint_disable = dwc_otg_hcd_endpoint_disable,
9771 +
9772 + .get_frame_number = dwc_otg_hcd_get_frame_number,
9773 +
9774 + .hub_status_data = dwc_otg_hcd_hub_status_data,
9775 + .hub_control = dwc_otg_hcd_hub_control,
9776 + //.hub_suspend =
9777 + //.hub_resume =
9778 +};
9779 +
9780 +/**
9781 + * Work queue function for starting the HCD when A-Cable is connected.
9782 + * The dwc_otg_hcd_start() must be called in a process context.
9783 + */
9784 +static void hcd_start_func(
9785 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
9786 + void *_vp
9787 +#else
9788 + struct work_struct *_work
9789 +#endif
9790 + )
9791 +{
9792 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
9793 + struct usb_hcd *usb_hcd = (struct usb_hcd *)_vp;
9794 +#else
9795 + struct delayed_work *dw = container_of(_work, struct delayed_work, work);
9796 + struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work);
9797 + struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv);
9798 +#endif
9799 + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
9800 + if (usb_hcd) {
9801 + dwc_otg_hcd_start(usb_hcd);
9802 + }
9803 +}
9804 +
9805 +/**
9806 + * HCD Callback function for starting the HCD when A-Cable is
9807 + * connected.
9808 + *
9809 + * @param p void pointer to the <code>struct usb_hcd</code>
9810 + */
9811 +static int32_t dwc_otg_hcd_start_cb(void *p)
9812 +{
9813 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
9814 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
9815 + hprt0_data_t hprt0;
9816 +
9817 + if (core_if->op_state == B_HOST) {
9818 + /*
9819 + * Reset the port. During a HNP mode switch the reset
9820 + * needs to occur within 1ms and have a duration of at
9821 + * least 50ms.
9822 + */
9823 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
9824 + hprt0.b.prtrst = 1;
9825 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9826 + ((struct usb_hcd *)p)->self.is_b_host = 1;
9827 + } else {
9828 + ((struct usb_hcd *)p)->self.is_b_host = 0;
9829 + }
9830 +
9831 + /* Need to start the HCD in a non-interrupt context. */
9832 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
9833 + INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p);
9834 +// INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p);
9835 +#else
9836 +// INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
9837 + INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
9838 +#endif
9839 +// schedule_work(&dwc_otg_hcd->start_work);
9840 + queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000);
9841 +
9842 + return 1;
9843 +}
9844 +
9845 +/**
9846 + * HCD Callback function for stopping the HCD.
9847 + *
9848 + * @param p void pointer to the <code>struct usb_hcd</code>
9849 + */
9850 +static int32_t dwc_otg_hcd_stop_cb(void *p)
9851 +{
9852 + struct usb_hcd *usb_hcd = (struct usb_hcd *)p;
9853 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
9854 + dwc_otg_hcd_stop(usb_hcd);
9855 + return 1;
9856 +}
9857 +
9858 +static void del_xfer_timers(dwc_otg_hcd_t *hcd)
9859 +{
9860 +#ifdef DEBUG
9861 + int i;
9862 + int num_channels = hcd->core_if->core_params->host_channels;
9863 + for (i = 0; i < num_channels; i++) {
9864 + del_timer(&hcd->core_if->hc_xfer_timer[i]);
9865 + }
9866 +#endif
9867 +}
9868 +
9869 +static void del_timers(dwc_otg_hcd_t *hcd)
9870 +{
9871 + del_xfer_timers(hcd);
9872 + del_timer(&hcd->conn_timer);
9873 +}
9874 +
9875 +/**
9876 + * Processes all the URBs in a single list of QHs. Completes them with
9877 + * -ETIMEDOUT and frees the QTD.
9878 + */
9879 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
9880 +{
9881 + struct list_head *qh_item;
9882 + dwc_otg_qh_t *qh;
9883 + struct list_head *qtd_item;
9884 + dwc_otg_qtd_t *qtd;
9885 +
9886 + list_for_each(qh_item, qh_list) {
9887 + qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
9888 + for (qtd_item = qh->qtd_list.next;
9889 + qtd_item != &qh->qtd_list;
9890 + qtd_item = qh->qtd_list.next) {
9891 + qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
9892 + if (qtd->urb != NULL) {
9893 + dwc_otg_hcd_complete_urb(hcd, qtd->urb,
9894 + -ETIMEDOUT);
9895 + }
9896 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
9897 + }
9898 + }
9899 +}
9900 +
9901 +/**
9902 + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
9903 + * and periodic schedules. The QTD associated with each URB is removed from
9904 + * the schedule and freed. This function may be called when a disconnect is
9905 + * detected or when the HCD is being stopped.
9906 + */
9907 +static void kill_all_urbs(dwc_otg_hcd_t *hcd)
9908 +{
9909 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
9910 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
9911 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
9912 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
9913 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
9914 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
9915 +}
9916 +
9917 +/**
9918 + * HCD Callback function for disconnect of the HCD.
9919 + *
9920 + * @param p void pointer to the <code>struct usb_hcd</code>
9921 + */
9922 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
9923 +{
9924 + gintsts_data_t intr;
9925 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
9926 +
9927 + //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
9928 +
9929 + /*
9930 + * Set status flags for the hub driver.
9931 + */
9932 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
9933 + dwc_otg_hcd->flags.b.port_connect_status = 0;
9934 +
9935 + /*
9936 + * Shutdown any transfers in process by clearing the Tx FIFO Empty
9937 + * interrupt mask and status bits and disabling subsequent host
9938 + * channel interrupts.
9939 + */
9940 + intr.d32 = 0;
9941 + intr.b.nptxfempty = 1;
9942 + intr.b.ptxfempty = 1;
9943 + intr.b.hcintr = 1;
9944 + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
9945 + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
9946 +
9947 + del_timers(dwc_otg_hcd);
9948 +
9949 + /*
9950 + * Turn off the vbus power only if the core has transitioned to device
9951 + * mode. If still in host mode, need to keep power on to detect a
9952 + * reconnection.
9953 + */
9954 + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
9955 + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
9956 + hprt0_data_t hprt0 = { .d32=0 };
9957 + DWC_PRINT("Disconnect: PortPower off\n");
9958 + hprt0.b.prtpwr = 0;
9959 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
9960 + }
9961 +
9962 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
9963 + }
9964 +
9965 + /* Respond with an error status to all URBs in the schedule. */
9966 + kill_all_urbs(dwc_otg_hcd);
9967 +
9968 + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
9969 + /* Clean up any host channels that were in use. */
9970 + int num_channels;
9971 + int i;
9972 + dwc_hc_t *channel;
9973 + dwc_otg_hc_regs_t *hc_regs;
9974 + hcchar_data_t hcchar;
9975 +
9976 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
9977 +
9978 + if (!dwc_otg_hcd->core_if->dma_enable) {
9979 + /* Flush out any channel requests in slave mode. */
9980 + for (i = 0; i < num_channels; i++) {
9981 + channel = dwc_otg_hcd->hc_ptr_array[i];
9982 + if (list_empty(&channel->hc_list_entry)) {
9983 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
9984 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9985 + if (hcchar.b.chen) {
9986 + hcchar.b.chen = 0;
9987 + hcchar.b.chdis = 1;
9988 + hcchar.b.epdir = 0;
9989 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9990 + }
9991 + }
9992 + }
9993 + }
9994 +
9995 + for (i = 0; i < num_channels; i++) {
9996 + channel = dwc_otg_hcd->hc_ptr_array[i];
9997 + if (list_empty(&channel->hc_list_entry)) {
9998 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
9999 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10000 + if (hcchar.b.chen) {
10001 + /* Halt the channel. */
10002 + hcchar.b.chdis = 1;
10003 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
10004 + }
10005 +
10006 + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
10007 + list_add_tail(&channel->hc_list_entry,
10008 + &dwc_otg_hcd->free_hc_list);
10009 + }
10010 + }
10011 + }
10012 +
10013 + /* A disconnect will end the session so the B-Device is no
10014 + * longer a B-host. */
10015 + ((struct usb_hcd *)p)->self.is_b_host = 0;
10016 + return 1;
10017 +}
10018 +
10019 +/**
10020 + * Connection timeout function. An OTG host is required to display a
10021 + * message if the device does not connect within 10 seconds.
10022 + */
10023 +void dwc_otg_hcd_connect_timeout(unsigned long ptr)
10024 +{
10025 + DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr);
10026 + DWC_PRINT("Connect Timeout\n");
10027 + DWC_ERROR("Device Not Connected/Responding\n");
10028 +}
10029 +
10030 +/**
10031 + * Start the connection timer. An OTG host is required to display a
10032 + * message if the device does not connect within 10 seconds. The
10033 + * timer is deleted if a port connect interrupt occurs before the
10034 + * timer expires.
10035 + */
10036 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
10037 +{
10038 + init_timer(&hcd->conn_timer);
10039 + hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
10040 + hcd->conn_timer.data = 0;
10041 + hcd->conn_timer.expires = jiffies + (HZ * 10);
10042 + add_timer(&hcd->conn_timer);
10043 +}
10044 +
10045 +/**
10046 + * HCD Callback function for disconnect of the HCD.
10047 + *
10048 + * @param p void pointer to the <code>struct usb_hcd</code>
10049 + */
10050 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
10051 +{
10052 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
10053 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
10054 + dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
10055 + return 1;
10056 +}
10057 +
10058 +/**
10059 + * HCD Callback structure for handling mode switching.
10060 + */
10061 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
10062 + .start = dwc_otg_hcd_start_cb,
10063 + .stop = dwc_otg_hcd_stop_cb,
10064 + .disconnect = dwc_otg_hcd_disconnect_cb,
10065 + .session_start = dwc_otg_hcd_session_start_cb,
10066 + .p = 0,
10067 +};
10068 +
10069 +/**
10070 + * Reset tasklet function
10071 + */
10072 +static void reset_tasklet_func(unsigned long data)
10073 +{
10074 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data;
10075 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
10076 + hprt0_data_t hprt0;
10077 +
10078 + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
10079 +
10080 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
10081 + hprt0.b.prtrst = 1;
10082 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
10083 + mdelay(60);
10084 +
10085 + hprt0.b.prtrst = 0;
10086 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
10087 + dwc_otg_hcd->flags.b.port_reset_change = 1;
10088 +}
10089 +
10090 +static struct tasklet_struct reset_tasklet = {
10091 + .next = NULL,
10092 + .state = 0,
10093 + .count = ATOMIC_INIT(0),
10094 + .func = reset_tasklet_func,
10095 + .data = 0,
10096 +};
10097 +
10098 +/**
10099 + * Initializes the HCD. This function allocates memory for and initializes the
10100 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
10101 + * USB bus with the core and calls the hc_driver->start() function. It returns
10102 + * a negative error on failure.
10103 + */
10104 +int dwc_otg_hcd_init(struct device *dev)
10105 +{
10106 + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
10107 + struct usb_hcd *hcd = NULL;
10108 + dwc_otg_hcd_t *dwc_otg_hcd = NULL;
10109 +
10110 + int num_channels;
10111 + int i;
10112 + dwc_hc_t *channel;
10113 +
10114 + int retval = 0;
10115 +
10116 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
10117 +
10118 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10119 + /* 2.6.20+ requires dev.dma_mask to be set prior to calling usb_create_hcd() */
10120 +
10121 + /* Set device flags indicating whether the HCD supports DMA. */
10122 + if (otg_dev->core_if->dma_enable) {
10123 + DWC_PRINT("Using DMA mode\n");
10124 + dev->dma_mask = (void *)~0;
10125 + dev->coherent_dma_mask = ~0;
10126 +
10127 + if (otg_dev->core_if->dma_desc_enable) {
10128 + DWC_PRINT("Device using Descriptor DMA mode\n");
10129 + } else {
10130 + DWC_PRINT("Device using Buffer DMA mode\n");
10131 + }
10132 + } else {
10133 + DWC_PRINT("Using Slave mode\n");
10134 + dev->dma_mask = (void *)0;
10135 + dev->coherent_dma_mask = 0;
10136 + }
10137 +#endif
10138 + /*
10139 + * Allocate memory for the base HCD plus the DWC OTG HCD.
10140 + * Initialize the base HCD.
10141 + */
10142 + hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
10143 + if (!hcd) {
10144 + retval = -ENOMEM;
10145 + goto error1;
10146 + }
10147 +
10148 + dev_set_drvdata(dev, otg_dev);
10149 + hcd->regs = otg_dev->base;
10150 + hcd->rsrc_start = otg_dev->phys_addr;
10151 + hcd->rsrc_len = otg_dev->base_len;
10152 + hcd->self.otg_port = 1;
10153 + hcd->has_tt = 1;
10154 +
10155 + /* Initialize the DWC OTG HCD. */
10156 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10157 + dwc_otg_hcd->core_if = otg_dev->core_if;
10158 + otg_dev->hcd = dwc_otg_hcd;
10159 +
10160 + /* */
10161 + spin_lock_init(&dwc_otg_hcd->lock);
10162 +
10163 + /* Register the HCD CIL Callbacks */
10164 + dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
10165 + &hcd_cil_callbacks, hcd);
10166 +
10167 + /* Initialize the non-periodic schedule. */
10168 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
10169 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
10170 +
10171 + /* Initialize the periodic schedule. */
10172 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
10173 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
10174 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
10175 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
10176 +
10177 + /*
10178 + * Create a host channel descriptor for each host channel implemented
10179 + * in the controller. Initialize the channel descriptor array.
10180 + */
10181 + INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
10182 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
10183 + memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array));
10184 + for (i = 0; i < num_channels; i++) {
10185 + channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
10186 + if (channel == NULL) {
10187 + retval = -ENOMEM;
10188 + DWC_ERROR("%s: host channel allocation failed\n", __func__);
10189 + goto error2;
10190 + }
10191 + memset(channel, 0, sizeof(dwc_hc_t));
10192 + channel->hc_num = i;
10193 + dwc_otg_hcd->hc_ptr_array[i] = channel;
10194 +#ifdef DEBUG
10195 + init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
10196 +#endif
10197 + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
10198 + }
10199 +
10200 + /* Initialize the Connection timeout timer. */
10201 + init_timer(&dwc_otg_hcd->conn_timer);
10202 +
10203 + /* Initialize reset tasklet. */
10204 + reset_tasklet.data = (unsigned long) dwc_otg_hcd;
10205 + dwc_otg_hcd->reset_tasklet = &reset_tasklet;
10206 +
10207 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10208 + /* Set device flags indicating whether the HCD supports DMA. */
10209 + if (otg_dev->core_if->dma_enable) {
10210 + DWC_PRINT("Using DMA mode\n");
10211 + dev->dma_mask = (void *)~0;
10212 + dev->coherent_dma_mask = ~0;
10213 +
10214 + if (otg_dev->core_if->dma_desc_enable){
10215 + DWC_PRINT("Device using Descriptor DMA mode\n");
10216 + } else {
10217 + DWC_PRINT("Device using Buffer DMA mode\n");
10218 + }
10219 + } else {
10220 + DWC_PRINT("Using Slave mode\n");
10221 + dev->dma_mask = (void *)0;
10222 + dev->dev.coherent_dma_mask = 0;
10223 + }
10224 +#endif
10225 + /*
10226 + * Finish generic HCD initialization and start the HCD. This function
10227 + * allocates the DMA buffer pool, registers the USB bus, requests the
10228 + * IRQ line, and calls dwc_otg_hcd_start method.
10229 + */
10230 + retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED);
10231 + if (retval < 0) {
10232 + goto error2;
10233 + }
10234 +
10235 + /*
10236 + * Allocate space for storing data on status transactions. Normally no
10237 + * data is sent, but this space acts as a bit bucket. This must be
10238 + * done after usb_add_hcd since that function allocates the DMA buffer
10239 + * pool.
10240 + */
10241 + if (otg_dev->core_if->dma_enable) {
10242 + dwc_otg_hcd->status_buf =
10243 + dma_alloc_coherent(dev,
10244 + DWC_OTG_HCD_STATUS_BUF_SIZE,
10245 + &dwc_otg_hcd->status_buf_dma,
10246 + GFP_KERNEL | GFP_DMA);
10247 + } else {
10248 + dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
10249 + GFP_KERNEL);
10250 + }
10251 + if (!dwc_otg_hcd->status_buf) {
10252 + retval = -ENOMEM;
10253 + DWC_ERROR("%s: status_buf allocation failed\n", __func__);
10254 + goto error3;
10255 + }
10256 +
10257 + dwc_otg_hcd->otg_dev = otg_dev;
10258 +
10259 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
10260 + dev_name(dev), hcd->self.busnum);
10261 +
10262 + return 0;
10263 +
10264 + /* Error conditions */
10265 + error3:
10266 + usb_remove_hcd(hcd);
10267 + error2:
10268 + dwc_otg_hcd_free(hcd);
10269 + usb_put_hcd(hcd);
10270 +
10271 + /* FIXME: 2008/05/03 by Steven
10272 + * write back to device:
10273 + * dwc_otg_hcd has already been released by dwc_otg_hcd_free()
10274 + */
10275 + dev_set_drvdata(dev, otg_dev);
10276 +
10277 + error1:
10278 + return retval;
10279 +}
10280 +
10281 +/**
10282 + * Removes the HCD.
10283 + * Frees memory and resources associated with the HCD and deregisters the bus.
10284 + */
10285 +void dwc_otg_hcd_remove(struct device *dev)
10286 +{
10287 + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
10288 + dwc_otg_hcd_t *dwc_otg_hcd;
10289 + struct usb_hcd *hcd;
10290 +
10291 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
10292 +
10293 + if (!otg_dev) {
10294 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
10295 + return;
10296 + }
10297 +
10298 + dwc_otg_hcd = otg_dev->hcd;
10299 +
10300 + if (!dwc_otg_hcd) {
10301 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
10302 + return;
10303 + }
10304 +
10305 + hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
10306 +
10307 + if (!hcd) {
10308 + DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__);
10309 + return;
10310 + }
10311 +
10312 + /* Turn off all interrupts */
10313 + dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
10314 + dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
10315 +
10316 + usb_remove_hcd(hcd);
10317 + dwc_otg_hcd_free(hcd);
10318 + usb_put_hcd(hcd);
10319 +}
10320 +
10321 +/* =========================================================================
10322 + * Linux HC Driver Functions
10323 + * ========================================================================= */
10324 +
10325 +/**
10326 + * Initializes dynamic portions of the DWC_otg HCD state.
10327 + */
10328 +static void hcd_reinit(dwc_otg_hcd_t *hcd)
10329 +{
10330 + struct list_head *item;
10331 + int num_channels;
10332 + int i;
10333 + dwc_hc_t *channel;
10334 +
10335 + hcd->flags.d32 = 0;
10336 +
10337 + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
10338 + hcd->non_periodic_channels = 0;
10339 + hcd->periodic_channels = 0;
10340 +
10341 + /*
10342 + * Put all channels in the free channel list and clean up channel
10343 + * states.
10344 + */
10345 + item = hcd->free_hc_list.next;
10346 + while (item != &hcd->free_hc_list) {
10347 + list_del(item);
10348 + item = hcd->free_hc_list.next;
10349 + }
10350 + num_channels = hcd->core_if->core_params->host_channels;
10351 + for (i = 0; i < num_channels; i++) {
10352 + channel = hcd->hc_ptr_array[i];
10353 + list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list);
10354 + dwc_otg_hc_cleanup(hcd->core_if, channel);
10355 + }
10356 +
10357 + /* Initialize the DWC core for host mode operation. */
10358 + dwc_otg_core_host_init(hcd->core_if);
10359 +}
10360 +
10361 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
10362 + * mode operation. Activates the root port. Returns 0 on success and a negative
10363 + * error code on failure. */
10364 +int dwc_otg_hcd_start(struct usb_hcd *hcd)
10365 +{
10366 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10367 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
10368 + struct usb_bus *bus;
10369 +
10370 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10371 + struct usb_device *udev;
10372 + int retval;
10373 +#endif
10374 +
10375 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
10376 +
10377 + bus = hcd_to_bus(hcd);
10378 +
10379 + /* Initialize the bus state. If the core is in Device Mode
10380 + * HALT the USB bus and return. */
10381 + if (dwc_otg_is_device_mode(core_if)) {
10382 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10383 + hcd->state = HC_STATE_HALT;
10384 +#else
10385 + hcd->state = HC_STATE_RUNNING;
10386 +#endif
10387 + return 0;
10388 + }
10389 + hcd->state = HC_STATE_RUNNING;
10390 +
10391 + /* Initialize and connect root hub if one is not already attached */
10392 + if (bus->root_hub) {
10393 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
10394 + /* Inform the HUB driver to resume. */
10395 + usb_hcd_resume_root_hub(hcd);
10396 + }
10397 + else {
10398 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n");
10399 +
10400 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10401 + udev = usb_alloc_dev(NULL, bus, 0);
10402 + udev->speed = USB_SPEED_HIGH;
10403 + if (!udev) {
10404 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
10405 + return -ENODEV;
10406 + }
10407 + if ((retval = usb_hcd_register_root_hub(udev, hcd)) != 0) {
10408 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
10409 + return -ENODEV;
10410 + }
10411 +#endif
10412 + }
10413 +
10414 + hcd_reinit(dwc_otg_hcd);
10415 +
10416 + return 0;
10417 +}
10418 +
10419 +static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
10420 +{
10421 + struct list_head *item;
10422 + dwc_otg_qh_t *qh;
10423 +
10424 + if (!qh_list->next) {
10425 + /* The list hasn't been initialized yet. */
10426 + return;
10427 + }
10428 +
10429 + /* Ensure there are no QTDs or URBs left. */
10430 + kill_urbs_in_qh_list(hcd, qh_list);
10431 +
10432 + for (item = qh_list->next; item != qh_list; item = qh_list->next) {
10433 + qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
10434 + dwc_otg_hcd_qh_remove_and_free(hcd, qh);
10435 + }
10436 +}
10437 +
10438 +/**
10439 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
10440 + * stopped.
10441 + */
10442 +void dwc_otg_hcd_stop(struct usb_hcd *hcd)
10443 +{
10444 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10445 + hprt0_data_t hprt0 = { .d32=0 };
10446 +
10447 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
10448 +
10449 + /* Turn off all host-specific interrupts. */
10450 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
10451 +
10452 + /*
10453 + * The root hub should be disconnected before this function is called.
10454 + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
10455 + * and the QH lists (via ..._hcd_endpoint_disable).
10456 + */
10457 +
10458 + /* Turn off the vbus power */
10459 + DWC_PRINT("PortPower off\n");
10460 + hprt0.b.prtpwr = 0;
10461 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
10462 +}
10463 +
10464 +/** Returns the current frame number. */
10465 +int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd)
10466 +{
10467 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10468 + hfnum_data_t hfnum;
10469 +
10470 + hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
10471 + host_if->host_global_regs->hfnum);
10472 +
10473 +#ifdef DEBUG_SOF
10474 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
10475 +#endif
10476 + return hfnum.b.frnum;
10477 +}
10478 +
10479 +/**
10480 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
10481 + * in the struct usb_hcd field.
10482 + */
10483 +void dwc_otg_hcd_free(struct usb_hcd *hcd)
10484 +{
10485 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10486 + int i;
10487 +
10488 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
10489 +
10490 + del_timers(dwc_otg_hcd);
10491 +
10492 + /* Free memory for QH/QTD lists */
10493 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
10494 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
10495 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
10496 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
10497 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
10498 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
10499 +
10500 + /* Free memory for the host channels. */
10501 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
10502 + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
10503 + if (hc != NULL) {
10504 + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
10505 + kfree(hc);
10506 + }
10507 + }
10508 +
10509 + if (dwc_otg_hcd->core_if->dma_enable) {
10510 + if (dwc_otg_hcd->status_buf_dma) {
10511 + dma_free_coherent(hcd->self.controller,
10512 + DWC_OTG_HCD_STATUS_BUF_SIZE,
10513 + dwc_otg_hcd->status_buf,
10514 + dwc_otg_hcd->status_buf_dma);
10515 + }
10516 + } else if (dwc_otg_hcd->status_buf != NULL) {
10517 + kfree(dwc_otg_hcd->status_buf);
10518 + }
10519 +}
10520 +
10521 +#ifdef DEBUG
10522 +static void dump_urb_info(struct urb *urb, char* fn_name)
10523 +{
10524 + DWC_PRINT("%s, urb %p\n", fn_name, urb);
10525 + DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe));
10526 + DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
10527 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
10528 + DWC_PRINT(" Endpoint type: %s\n",
10529 + ({char *pipetype;
10530 + switch (usb_pipetype(urb->pipe)) {
10531 + case PIPE_CONTROL: pipetype = "CONTROL"; break;
10532 + case PIPE_BULK: pipetype = "BULK"; break;
10533 + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
10534 + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
10535 + default: pipetype = "UNKNOWN"; break;
10536 + }; pipetype;}));
10537 + DWC_PRINT(" Speed: %s\n",
10538 + ({char *speed;
10539 + switch (urb->dev->speed) {
10540 + case USB_SPEED_HIGH: speed = "HIGH"; break;
10541 + case USB_SPEED_FULL: speed = "FULL"; break;
10542 + case USB_SPEED_LOW: speed = "LOW"; break;
10543 + default: speed = "UNKNOWN"; break;
10544 + }; speed;}));
10545 + DWC_PRINT(" Max packet size: %d\n",
10546 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
10547 + DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length);
10548 + DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
10549 + urb->transfer_buffer, (void *)urb->transfer_dma);
10550 + DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
10551 + urb->setup_packet, (void *)urb->setup_dma);
10552 + DWC_PRINT(" Interval: %d\n", urb->interval);
10553 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
10554 + int i;
10555 + for (i = 0; i < urb->number_of_packets; i++) {
10556 + DWC_PRINT(" ISO Desc %d:\n", i);
10557 + DWC_PRINT(" offset: %d, length %d\n",
10558 + urb->iso_frame_desc[i].offset,
10559 + urb->iso_frame_desc[i].length);
10560 + }
10561 + }
10562 +}
10563 +
10564 +static void dump_channel_info(dwc_otg_hcd_t *hcd,
10565 + dwc_otg_qh_t *qh)
10566 +{
10567 + if (qh->channel != NULL) {
10568 + dwc_hc_t *hc = qh->channel;
10569 + struct list_head *item;
10570 + dwc_otg_qh_t *qh_item;
10571 + int num_channels = hcd->core_if->core_params->host_channels;
10572 + int i;
10573 +
10574 + dwc_otg_hc_regs_t *hc_regs;
10575 + hcchar_data_t hcchar;
10576 + hcsplt_data_t hcsplt;
10577 + hctsiz_data_t hctsiz;
10578 + uint32_t hcdma;
10579 +
10580 + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
10581 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10582 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
10583 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
10584 + hcdma = dwc_read_reg32(&hc_regs->hcdma);
10585 +
10586 + DWC_PRINT(" Assigned to channel %p:\n", hc);
10587 + DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
10588 + DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
10589 + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
10590 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
10591 + DWC_PRINT(" ep_type: %d\n", hc->ep_type);
10592 + DWC_PRINT(" max_packet: %d\n", hc->max_packet);
10593 + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
10594 + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
10595 + DWC_PRINT(" halt_status: %d\n", hc->halt_status);
10596 + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
10597 + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
10598 + DWC_PRINT(" qh: %p\n", hc->qh);
10599 + DWC_PRINT(" NP inactive sched:\n");
10600 + list_for_each(item, &hcd->non_periodic_sched_inactive) {
10601 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
10602 + DWC_PRINT(" %p\n", qh_item);
10603 + }
10604 + DWC_PRINT(" NP active sched:\n");
10605 + list_for_each(item, &hcd->non_periodic_sched_active) {
10606 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
10607 + DWC_PRINT(" %p\n", qh_item);
10608 + }
10609 + DWC_PRINT(" Channels: \n");
10610 + for (i = 0; i < num_channels; i++) {
10611 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
10612 + DWC_PRINT(" %2d: %p\n", i, hc);
10613 + }
10614 + }
10615 +}
10616 +#endif
10617 +
10618 +/** Starts processing a USB transfer request specified by a USB Request Block
10619 + * (URB). mem_flags indicates the type of memory allocation to use while
10620 + * processing this URB. */
10621 +int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
10622 + struct urb *urb,
10623 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
10624 + int mem_flags
10625 +#else
10626 + gfp_t mem_flags
10627 +#endif
10628 + )
10629 +{
10630 + int retval = 0;
10631 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10632 + dwc_otg_qtd_t *qtd;
10633 +
10634 +#ifdef DEBUG
10635 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10636 + dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue");
10637 + }
10638 +#endif
10639 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
10640 + /* No longer connected. */
10641 + return -ENODEV;
10642 + }
10643 +
10644 + qtd = dwc_otg_hcd_qtd_create(urb);
10645 + if (qtd == NULL) {
10646 + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
10647 + return -ENOMEM;
10648 + }
10649 +
10650 + retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
10651 + if (retval < 0) {
10652 + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
10653 + "Error status %d\n", retval);
10654 + dwc_otg_hcd_qtd_free(qtd);
10655 + }
10656 +
10657 + return retval;
10658 +}
10659 +
10660 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
10661 + * success. */
10662 +int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
10663 + struct urb *urb,
10664 + int status)
10665 +{
10666 + unsigned long flags;
10667 + dwc_otg_hcd_t *dwc_otg_hcd;
10668 + dwc_otg_qtd_t *urb_qtd;
10669 + dwc_otg_qh_t *qh;
10670 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10671 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
10672 +#endif
10673 +
10674 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
10675 +
10676 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10677 +
10678 + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
10679 +
10680 + urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
10681 + qh = (dwc_otg_qh_t *)ep->hcpriv;
10682 +
10683 +#ifdef DEBUG
10684 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10685 + dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
10686 + if (urb_qtd == qh->qtd_in_process) {
10687 + dump_channel_info(dwc_otg_hcd, qh);
10688 + }
10689 + }
10690 +#endif
10691 +
10692 + if (urb_qtd == qh->qtd_in_process) {
10693 + /* The QTD is in process (it has been assigned to a channel). */
10694 +
10695 + if (dwc_otg_hcd->flags.b.port_connect_status) {
10696 + /*
10697 + * If still connected (i.e. in host mode), halt the
10698 + * channel so it can be used for other transfers. If
10699 + * no longer connected, the host registers can't be
10700 + * written to halt the channel since the core is in
10701 + * device mode.
10702 + */
10703 + dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
10704 + DWC_OTG_HC_XFER_URB_DEQUEUE);
10705 + }
10706 + }
10707 +
10708 + /*
10709 + * Free the QTD and clean up the associated QH. Leave the QH in the
10710 + * schedule if it has any remaining QTDs.
10711 + */
10712 + dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
10713 + if (urb_qtd == qh->qtd_in_process) {
10714 + dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
10715 + qh->channel = NULL;
10716 + qh->qtd_in_process = NULL;
10717 + } else if (list_empty(&qh->qtd_list)) {
10718 + dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
10719 + }
10720 +
10721 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
10722 +
10723 + urb->hcpriv = NULL;
10724 +
10725 + /* Higher layer software sets URB status. */
10726 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10727 + usb_hcd_giveback_urb(hcd, urb, status);
10728 +#else
10729 + usb_hcd_giveback_urb(hcd, urb, NULL);
10730 +#endif
10731 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10732 + DWC_PRINT("Called usb_hcd_giveback_urb()\n");
10733 + DWC_PRINT(" urb->status = %d\n", urb->status);
10734 + }
10735 +
10736 + return 0;
10737 +}
10738 +
10739 +/** Frees resources in the DWC_otg controller related to a given endpoint. Also
10740 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
10741 + * must already be dequeued. */
10742 +void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
10743 + struct usb_host_endpoint *ep)
10744 +{
10745 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10746 + dwc_otg_qh_t *qh;
10747 +
10748 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10749 + unsigned long flags;
10750 + int retry = 0;
10751 +#endif
10752 +
10753 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
10754 + "endpoint=%d\n", ep->desc.bEndpointAddress,
10755 + dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
10756 +
10757 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
10758 +rescan:
10759 + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
10760 + qh = (dwc_otg_qh_t *)(ep->hcpriv);
10761 + if (!qh)
10762 + goto done;
10763 +
10764 + /** Check that the QTD list is really empty */
10765 + if (!list_empty(&qh->qtd_list)) {
10766 + if (retry++ < 250) {
10767 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
10768 + schedule_timeout_uninterruptible(1);
10769 + goto rescan;
10770 + }
10771 +
10772 + DWC_WARN("DWC OTG HCD EP DISABLE:"
10773 + " QTD List for this endpoint is not empty\n");
10774 + }
10775 +
10776 + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
10777 + ep->hcpriv = NULL;
10778 +done:
10779 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
10780 +
10781 +#else // LINUX_VERSION_CODE
10782 +
10783 + qh = (dwc_otg_qh_t *)(ep->hcpriv);
10784 + if (qh != NULL) {
10785 +#ifdef DEBUG
10786 + /** Check that the QTD list is really empty */
10787 + if (!list_empty(&qh->qtd_list)) {
10788 + DWC_WARN("DWC OTG HCD EP DISABLE:"
10789 + " QTD List for this endpoint is not empty\n");
10790 + }
10791 +#endif
10792 + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
10793 + ep->hcpriv = NULL;
10794 + }
10795 +#endif // LINUX_VERSION_CODE
10796 +}
10797 +
10798 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
10799 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
10800 + * interrupt.
10801 + *
10802 + * This function is called by the USB core when an interrupt occurs */
10803 +irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
10804 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
10805 + , struct pt_regs *regs
10806 +#endif
10807 + )
10808 +{
10809 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10810 + return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
10811 +}
10812 +
10813 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
10814 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
10815 + * is the status change indicator for the single root port. Returns 1 if either
10816 + * change indicator is 1, otherwise returns 0. */
10817 +int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
10818 +{
10819 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
10820 +
10821 + buf[0] = 0;
10822 + buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
10823 + dwc_otg_hcd->flags.b.port_reset_change ||
10824 + dwc_otg_hcd->flags.b.port_enable_change ||
10825 + dwc_otg_hcd->flags.b.port_suspend_change ||
10826 + dwc_otg_hcd->flags.b.port_over_current_change) << 1;
10827 +
10828 +#ifdef DEBUG
10829 + if (buf[0]) {
10830 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
10831 + " Root port status changed\n");
10832 + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
10833 + dwc_otg_hcd->flags.b.port_connect_status_change);
10834 + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
10835 + dwc_otg_hcd->flags.b.port_reset_change);
10836 + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
10837 + dwc_otg_hcd->flags.b.port_enable_change);
10838 + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
10839 + dwc_otg_hcd->flags.b.port_suspend_change);
10840 + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
10841 + dwc_otg_hcd->flags.b.port_over_current_change);
10842 + }
10843 +#endif
10844 + return (buf[0] != 0);
10845 +}
10846 +
10847 +#ifdef DWC_HS_ELECT_TST
10848 +/*
10849 + * Quick and dirty hack to implement the HS Electrical Test
10850 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
10851 + *
10852 + * This code was copied from our userspace app "hset". It sends a
10853 + * Get Device Descriptor control sequence in two parts, first the
10854 + * Setup packet by itself, followed some time later by the In and
10855 + * Ack packets. Rather than trying to figure out how to add this
10856 + * functionality to the normal driver code, we just hijack the
10857 + * hardware, using these two function to drive the hardware
10858 + * directly.
10859 + */
10860 +
10861 +dwc_otg_core_global_regs_t *global_regs;
10862 +dwc_otg_host_global_regs_t *hc_global_regs;
10863 +dwc_otg_hc_regs_t *hc_regs;
10864 +uint32_t *data_fifo;
10865 +
10866 +static void do_setup(void)
10867 +{
10868 + gintsts_data_t gintsts;
10869 + hctsiz_data_t hctsiz;
10870 + hcchar_data_t hcchar;
10871 + haint_data_t haint;
10872 + hcint_data_t hcint;
10873 +
10874 + /* Enable HAINTs */
10875 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
10876 +
10877 + /* Enable HCINTs */
10878 + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
10879 +
10880 + /* Read GINTSTS */
10881 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10882 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10883 +
10884 + /* Read HAINT */
10885 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
10886 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
10887 +
10888 + /* Read HCINT */
10889 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
10890 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
10891 +
10892 + /* Read HCCHAR */
10893 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10894 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
10895 +
10896 + /* Clear HCINT */
10897 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
10898 +
10899 + /* Clear HAINT */
10900 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
10901 +
10902 + /* Clear GINTSTS */
10903 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
10904 +
10905 + /* Read GINTSTS */
10906 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10907 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10908 +
10909 + /*
10910 + * Send Setup packet (Get Device Descriptor)
10911 + */
10912 +
10913 + /* Make sure channel is disabled */
10914 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10915 + if (hcchar.b.chen) {
10916 + //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
10917 + hcchar.b.chdis = 1;
10918 +// hcchar.b.chen = 1;
10919 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
10920 + //sleep(1);
10921 + mdelay(1000);
10922 +
10923 + /* Read GINTSTS */
10924 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10925 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
10926 +
10927 + /* Read HAINT */
10928 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
10929 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
10930 +
10931 + /* Read HCINT */
10932 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
10933 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
10934 +
10935 + /* Read HCCHAR */
10936 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10937 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
10938 +
10939 + /* Clear HCINT */
10940 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
10941 +
10942 + /* Clear HAINT */
10943 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
10944 +
10945 + /* Clear GINTSTS */
10946 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
10947 +
10948 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10949 + //if (hcchar.b.chen) {
10950 + // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
10951 + //}
10952 + }
10953 +
10954 + /* Set HCTSIZ */
10955 + hctsiz.d32 = 0;
10956 + hctsiz.b.xfersize = 8;
10957 + hctsiz.b.pktcnt = 1;
10958 + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
10959 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
10960 +
10961 + /* Set HCCHAR */
10962 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
10963 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
10964 + hcchar.b.epdir = 0;
10965 + hcchar.b.epnum = 0;
10966 + hcchar.b.mps = 8;
10967 + hcchar.b.chen = 1;
10968 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
10969 +
10970 + /* Fill FIFO with Setup data for Get Device Descriptor */
10971 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
10972 + dwc_write_reg32(data_fifo++, 0x01000680);
10973 + dwc_write_reg32(data_fifo++, 0x00080000);
10974 +
10975 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10976 + //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
10977 +
10978 + /* Wait for host channel interrupt */
10979 + do {
10980 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
10981 + } while (gintsts.b.hcintr == 0);
10982 +
10983 + //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
10984 +
10985 + /* Disable HCINTs */
10986 + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
10987 +
10988 + /* Disable HAINTs */
10989 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
10990 +
10991 + /* Read HAINT */
10992 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
10993 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
10994 +
10995 + /* Read HCINT */
10996 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
10997 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
10998 +
10999 + /* Read HCCHAR */
11000 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11001 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11002 +
11003 + /* Clear HCINT */
11004 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11005 +
11006 + /* Clear HAINT */
11007 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11008 +
11009 + /* Clear GINTSTS */
11010 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11011 +
11012 + /* Read GINTSTS */
11013 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11014 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11015 +}
11016 +
11017 +static void do_in_ack(void)
11018 +{
11019 + gintsts_data_t gintsts;
11020 + hctsiz_data_t hctsiz;
11021 + hcchar_data_t hcchar;
11022 + haint_data_t haint;
11023 + hcint_data_t hcint;
11024 + host_grxsts_data_t grxsts;
11025 +
11026 + /* Enable HAINTs */
11027 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
11028 +
11029 + /* Enable HCINTs */
11030 + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
11031 +
11032 + /* Read GINTSTS */
11033 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11034 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11035 +
11036 + /* Read HAINT */
11037 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11038 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11039 +
11040 + /* Read HCINT */
11041 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11042 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11043 +
11044 + /* Read HCCHAR */
11045 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11046 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11047 +
11048 + /* Clear HCINT */
11049 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11050 +
11051 + /* Clear HAINT */
11052 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11053 +
11054 + /* Clear GINTSTS */
11055 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11056 +
11057 + /* Read GINTSTS */
11058 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11059 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11060 +
11061 + /*
11062 + * Receive Control In packet
11063 + */
11064 +
11065 + /* Make sure channel is disabled */
11066 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11067 + if (hcchar.b.chen) {
11068 + //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
11069 + hcchar.b.chdis = 1;
11070 + hcchar.b.chen = 1;
11071 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11072 + //sleep(1);
11073 + mdelay(1000);
11074 +
11075 + /* Read GINTSTS */
11076 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11077 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11078 +
11079 + /* Read HAINT */
11080 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11081 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11082 +
11083 + /* Read HCINT */
11084 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11085 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11086 +
11087 + /* Read HCCHAR */
11088 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11089 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11090 +
11091 + /* Clear HCINT */
11092 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11093 +
11094 + /* Clear HAINT */
11095 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11096 +
11097 + /* Clear GINTSTS */
11098 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11099 +
11100 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11101 + //if (hcchar.b.chen) {
11102 + // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
11103 + //}
11104 + }
11105 +
11106 + /* Set HCTSIZ */
11107 + hctsiz.d32 = 0;
11108 + hctsiz.b.xfersize = 8;
11109 + hctsiz.b.pktcnt = 1;
11110 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
11111 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
11112 +
11113 + /* Set HCCHAR */
11114 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11115 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
11116 + hcchar.b.epdir = 1;
11117 + hcchar.b.epnum = 0;
11118 + hcchar.b.mps = 8;
11119 + hcchar.b.chen = 1;
11120 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11121 +
11122 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11123 + //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
11124 +
11125 + /* Wait for receive status queue interrupt */
11126 + do {
11127 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11128 + } while (gintsts.b.rxstsqlvl == 0);
11129 +
11130 + //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
11131 +
11132 + /* Read RXSTS */
11133 + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
11134 + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
11135 +
11136 + /* Clear RXSTSQLVL in GINTSTS */
11137 + gintsts.d32 = 0;
11138 + gintsts.b.rxstsqlvl = 1;
11139 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11140 +
11141 + switch (grxsts.b.pktsts) {
11142 + case DWC_GRXSTS_PKTSTS_IN:
11143 + /* Read the data into the host buffer */
11144 + if (grxsts.b.bcnt > 0) {
11145 + int i;
11146 + int word_count = (grxsts.b.bcnt + 3) / 4;
11147 +
11148 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
11149 +
11150 + for (i = 0; i < word_count; i++) {
11151 + (void)dwc_read_reg32(data_fifo++);
11152 + }
11153 + }
11154 +
11155 + //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
11156 + break;
11157 +
11158 + default:
11159 + //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
11160 + break;
11161 + }
11162 +
11163 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11164 + //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
11165 +
11166 + /* Wait for receive status queue interrupt */
11167 + do {
11168 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11169 + } while (gintsts.b.rxstsqlvl == 0);
11170 +
11171 + //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
11172 +
11173 + /* Read RXSTS */
11174 + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
11175 + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
11176 +
11177 + /* Clear RXSTSQLVL in GINTSTS */
11178 + gintsts.d32 = 0;
11179 + gintsts.b.rxstsqlvl = 1;
11180 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11181 +
11182 + switch (grxsts.b.pktsts) {
11183 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
11184 + break;
11185 +
11186 + default:
11187 + //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
11188 + break;
11189 + }
11190 +
11191 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11192 + //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
11193 +
11194 + /* Wait for host channel interrupt */
11195 + do {
11196 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11197 + } while (gintsts.b.hcintr == 0);
11198 +
11199 + //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
11200 +
11201 + /* Read HAINT */
11202 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11203 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11204 +
11205 + /* Read HCINT */
11206 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11207 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11208 +
11209 + /* Read HCCHAR */
11210 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11211 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11212 +
11213 + /* Clear HCINT */
11214 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11215 +
11216 + /* Clear HAINT */
11217 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11218 +
11219 + /* Clear GINTSTS */
11220 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11221 +
11222 + /* Read GINTSTS */
11223 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11224 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11225 +
11226 +// usleep(100000);
11227 +// mdelay(100);
11228 + mdelay(1);
11229 +
11230 + /*
11231 + * Send handshake packet
11232 + */
11233 +
11234 + /* Read HAINT */
11235 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11236 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11237 +
11238 + /* Read HCINT */
11239 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11240 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11241 +
11242 + /* Read HCCHAR */
11243 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11244 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11245 +
11246 + /* Clear HCINT */
11247 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11248 +
11249 + /* Clear HAINT */
11250 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11251 +
11252 + /* Clear GINTSTS */
11253 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11254 +
11255 + /* Read GINTSTS */
11256 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11257 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11258 +
11259 + /* Make sure channel is disabled */
11260 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11261 + if (hcchar.b.chen) {
11262 + //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
11263 + hcchar.b.chdis = 1;
11264 + hcchar.b.chen = 1;
11265 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11266 + //sleep(1);
11267 + mdelay(1000);
11268 +
11269 + /* Read GINTSTS */
11270 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11271 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11272 +
11273 + /* Read HAINT */
11274 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11275 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11276 +
11277 + /* Read HCINT */
11278 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11279 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11280 +
11281 + /* Read HCCHAR */
11282 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11283 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11284 +
11285 + /* Clear HCINT */
11286 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11287 +
11288 + /* Clear HAINT */
11289 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11290 +
11291 + /* Clear GINTSTS */
11292 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11293 +
11294 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11295 + //if (hcchar.b.chen) {
11296 + // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
11297 + //}
11298 + }
11299 +
11300 + /* Set HCTSIZ */
11301 + hctsiz.d32 = 0;
11302 + hctsiz.b.xfersize = 0;
11303 + hctsiz.b.pktcnt = 1;
11304 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
11305 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
11306 +
11307 + /* Set HCCHAR */
11308 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11309 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
11310 + hcchar.b.epdir = 0;
11311 + hcchar.b.epnum = 0;
11312 + hcchar.b.mps = 8;
11313 + hcchar.b.chen = 1;
11314 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
11315 +
11316 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11317 + //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
11318 +
11319 + /* Wait for host channel interrupt */
11320 + do {
11321 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11322 + } while (gintsts.b.hcintr == 0);
11323 +
11324 + //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
11325 +
11326 + /* Disable HCINTs */
11327 + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
11328 +
11329 + /* Disable HAINTs */
11330 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
11331 +
11332 + /* Read HAINT */
11333 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
11334 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
11335 +
11336 + /* Read HCINT */
11337 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
11338 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
11339 +
11340 + /* Read HCCHAR */
11341 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
11342 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
11343 +
11344 + /* Clear HCINT */
11345 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
11346 +
11347 + /* Clear HAINT */
11348 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
11349 +
11350 + /* Clear GINTSTS */
11351 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
11352 +
11353 + /* Read GINTSTS */
11354 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
11355 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
11356 +}
11357 +#endif /* DWC_HS_ELECT_TST */
11358 +
11359 +/** Handles hub class-specific requests. */
11360 +int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
11361 + u16 typeReq,
11362 + u16 wValue,
11363 + u16 wIndex,
11364 + char *buf,
11365 + u16 wLength)
11366 +{
11367 + int retval = 0;
11368 +
11369 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
11370 + dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if;
11371 + struct usb_hub_descriptor *desc;
11372 + hprt0_data_t hprt0 = {.d32 = 0};
11373 +
11374 + uint32_t port_status;
11375 +
11376 + switch (typeReq) {
11377 + case ClearHubFeature:
11378 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11379 + "ClearHubFeature 0x%x\n", wValue);
11380 + switch (wValue) {
11381 + case C_HUB_LOCAL_POWER:
11382 + case C_HUB_OVER_CURRENT:
11383 + /* Nothing required here */
11384 + break;
11385 + default:
11386 + retval = -EINVAL;
11387 + DWC_ERROR("DWC OTG HCD - "
11388 + "ClearHubFeature request %xh unknown\n", wValue);
11389 + }
11390 + break;
11391 + case ClearPortFeature:
11392 + if (!wIndex || wIndex > 1)
11393 + goto error;
11394 +
11395 + switch (wValue) {
11396 + case USB_PORT_FEAT_ENABLE:
11397 + DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
11398 + "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
11399 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11400 + hprt0.b.prtena = 1;
11401 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11402 + break;
11403 + case USB_PORT_FEAT_SUSPEND:
11404 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11405 + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
11406 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11407 + hprt0.b.prtres = 1;
11408 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11409 + /* Clear Resume bit */
11410 + mdelay(100);
11411 + hprt0.b.prtres = 0;
11412 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11413 + break;
11414 + case USB_PORT_FEAT_POWER:
11415 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11416 + "ClearPortFeature USB_PORT_FEAT_POWER\n");
11417 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11418 + hprt0.b.prtpwr = 0;
11419 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11420 + break;
11421 + case USB_PORT_FEAT_INDICATOR:
11422 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11423 + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
11424 + /* Port inidicator not supported */
11425 + break;
11426 + case USB_PORT_FEAT_C_CONNECTION:
11427 + /* Clears drivers internal connect status change
11428 + * flag */
11429 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11430 + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
11431 + dwc_otg_hcd->flags.b.port_connect_status_change = 0;
11432 + break;
11433 + case USB_PORT_FEAT_C_RESET:
11434 + /* Clears the driver's internal Port Reset Change
11435 + * flag */
11436 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11437 + "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
11438 + dwc_otg_hcd->flags.b.port_reset_change = 0;
11439 + break;
11440 + case USB_PORT_FEAT_C_ENABLE:
11441 + /* Clears the driver's internal Port
11442 + * Enable/Disable Change flag */
11443 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11444 + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
11445 + dwc_otg_hcd->flags.b.port_enable_change = 0;
11446 + break;
11447 + case USB_PORT_FEAT_C_SUSPEND:
11448 + /* Clears the driver's internal Port Suspend
11449 + * Change flag, which is set when resume signaling on
11450 + * the host port is complete */
11451 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11452 + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
11453 + dwc_otg_hcd->flags.b.port_suspend_change = 0;
11454 + break;
11455 + case USB_PORT_FEAT_C_OVER_CURRENT:
11456 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11457 + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
11458 + dwc_otg_hcd->flags.b.port_over_current_change = 0;
11459 + break;
11460 + default:
11461 + retval = -EINVAL;
11462 + DWC_ERROR("DWC OTG HCD - "
11463 + "ClearPortFeature request %xh "
11464 + "unknown or unsupported\n", wValue);
11465 + }
11466 + break;
11467 + case GetHubDescriptor:
11468 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11469 + "GetHubDescriptor\n");
11470 + desc = (struct usb_hub_descriptor *)buf;
11471 + desc->bDescLength = 9;
11472 + desc->bDescriptorType = 0x29;
11473 + desc->bNbrPorts = 1;
11474 + desc->wHubCharacteristics = 0x08;
11475 + desc->bPwrOn2PwrGood = 1;
11476 + desc->bHubContrCurrent = 0;
11477 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39)
11478 + desc->u.hs.DeviceRemovable[0] = 0;
11479 + desc->u.hs.DeviceRemovable[1] = 0xff;
11480 +#endif
11481 + break;
11482 + case GetHubStatus:
11483 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11484 + "GetHubStatus\n");
11485 + memset(buf, 0, 4);
11486 + break;
11487 + case GetPortStatus:
11488 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11489 + "GetPortStatus\n");
11490 +
11491 + if (!wIndex || wIndex > 1)
11492 + goto error;
11493 +
11494 + port_status = 0;
11495 +
11496 + if (dwc_otg_hcd->flags.b.port_connect_status_change)
11497 + port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
11498 +
11499 + if (dwc_otg_hcd->flags.b.port_enable_change)
11500 + port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
11501 +
11502 + if (dwc_otg_hcd->flags.b.port_suspend_change)
11503 + port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
11504 +
11505 + if (dwc_otg_hcd->flags.b.port_reset_change)
11506 + port_status |= (1 << USB_PORT_FEAT_C_RESET);
11507 +
11508 + if (dwc_otg_hcd->flags.b.port_over_current_change) {
11509 + DWC_ERROR("Device Not Supported\n");
11510 + port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
11511 + }
11512 +
11513 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
11514 + /*
11515 + * The port is disconnected, which means the core is
11516 + * either in device mode or it soon will be. Just
11517 + * return 0's for the remainder of the port status
11518 + * since the port register can't be read if the core
11519 + * is in device mode.
11520 + */
11521 + *((__le32 *) buf) = cpu_to_le32(port_status);
11522 + break;
11523 + }
11524 +
11525 + hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
11526 + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
11527 +
11528 + if (hprt0.b.prtconnsts)
11529 + port_status |= (1 << USB_PORT_FEAT_CONNECTION);
11530 +
11531 + if (hprt0.b.prtena)
11532 + port_status |= (1 << USB_PORT_FEAT_ENABLE);
11533 +
11534 + if (hprt0.b.prtsusp)
11535 + port_status |= (1 << USB_PORT_FEAT_SUSPEND);
11536 +
11537 + if (hprt0.b.prtovrcurract)
11538 + port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
11539 +
11540 + if (hprt0.b.prtrst)
11541 + port_status |= (1 << USB_PORT_FEAT_RESET);
11542 +
11543 + if (hprt0.b.prtpwr)
11544 + port_status |= (1 << USB_PORT_FEAT_POWER);
11545 +
11546 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
11547 + port_status |= USB_PORT_STAT_HIGH_SPEED;
11548 + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
11549 + port_status |= USB_PORT_STAT_LOW_SPEED;
11550 +
11551 + if (hprt0.b.prttstctl)
11552 + port_status |= (1 << USB_PORT_FEAT_TEST);
11553 +
11554 + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
11555 +
11556 + *((__le32 *) buf) = cpu_to_le32(port_status);
11557 +
11558 + break;
11559 + case SetHubFeature:
11560 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11561 + "SetHubFeature\n");
11562 + /* No HUB features supported */
11563 + break;
11564 + case SetPortFeature:
11565 + if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1))
11566 + goto error;
11567 +
11568 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
11569 + /*
11570 + * The port is disconnected, which means the core is
11571 + * either in device mode or it soon will be. Just
11572 + * return without doing anything since the port
11573 + * register can't be written if the core is in device
11574 + * mode.
11575 + */
11576 + break;
11577 + }
11578 +
11579 + switch (wValue) {
11580 + case USB_PORT_FEAT_SUSPEND:
11581 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11582 + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
11583 + if (hcd->self.otg_port == wIndex &&
11584 + hcd->self.b_hnp_enable) {
11585 + gotgctl_data_t gotgctl = {.d32=0};
11586 + gotgctl.b.hstsethnpen = 1;
11587 + dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
11588 + 0, gotgctl.d32);
11589 + core_if->op_state = A_SUSPEND;
11590 + }
11591 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11592 + hprt0.b.prtsusp = 1;
11593 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11594 + //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32);
11595 + /* Suspend the Phy Clock */
11596 + {
11597 + pcgcctl_data_t pcgcctl = {.d32=0};
11598 + pcgcctl.b.stoppclk = 1;
11599 + dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
11600 + }
11601 +
11602 + /* For HNP the bus must be suspended for at least 200ms. */
11603 + if (hcd->self.b_hnp_enable) {
11604 + mdelay(200);
11605 + //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state);
11606 + }
11607 + break;
11608 + case USB_PORT_FEAT_POWER:
11609 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11610 + "SetPortFeature - USB_PORT_FEAT_POWER\n");
11611 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11612 + hprt0.b.prtpwr = 1;
11613 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11614 + break;
11615 + case USB_PORT_FEAT_RESET:
11616 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11617 + "SetPortFeature - USB_PORT_FEAT_RESET\n");
11618 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11619 + /* When B-Host the Port reset bit is set in
11620 + * the Start HCD Callback function, so that
11621 + * the reset is started within 1ms of the HNP
11622 + * success interrupt. */
11623 + if (!hcd->self.is_b_host) {
11624 + hprt0.b.prtrst = 1;
11625 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11626 + }
11627 + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
11628 + MDELAY(60);
11629 + hprt0.b.prtrst = 0;
11630 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11631 + break;
11632 +
11633 +#ifdef DWC_HS_ELECT_TST
11634 + case USB_PORT_FEAT_TEST:
11635 + {
11636 + uint32_t t;
11637 + gintmsk_data_t gintmsk;
11638 +
11639 + t = (wIndex >> 8); /* MSB wIndex USB */
11640 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11641 + "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
11642 + warn("USB_PORT_FEAT_TEST %d\n", t);
11643 + if (t < 6) {
11644 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11645 + hprt0.b.prttstctl = t;
11646 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11647 + } else {
11648 + /* Setup global vars with reg addresses (quick and
11649 + * dirty hack, should be cleaned up)
11650 + */
11651 + global_regs = core_if->core_global_regs;
11652 + hc_global_regs = core_if->host_if->host_global_regs;
11653 + hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
11654 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
11655 +
11656 + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
11657 + /* Save current interrupt mask */
11658 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
11659 +
11660 + /* Disable all interrupts while we muck with
11661 + * the hardware directly
11662 + */
11663 + dwc_write_reg32(&global_regs->gintmsk, 0);
11664 +
11665 + /* 15 second delay per the test spec */
11666 + mdelay(15000);
11667 +
11668 + /* Drive suspend on the root port */
11669 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11670 + hprt0.b.prtsusp = 1;
11671 + hprt0.b.prtres = 0;
11672 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11673 +
11674 + /* 15 second delay per the test spec */
11675 + mdelay(15000);
11676 +
11677 + /* Drive resume on the root port */
11678 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
11679 + hprt0.b.prtsusp = 0;
11680 + hprt0.b.prtres = 1;
11681 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11682 + mdelay(100);
11683 +
11684 + /* Clear the resume bit */
11685 + hprt0.b.prtres = 0;
11686 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
11687 +
11688 + /* Restore interrupts */
11689 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
11690 + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
11691 + /* Save current interrupt mask */
11692 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
11693 +
11694 + /* Disable all interrupts while we muck with
11695 + * the hardware directly
11696 + */
11697 + dwc_write_reg32(&global_regs->gintmsk, 0);
11698 +
11699 + /* 15 second delay per the test spec */
11700 + mdelay(15000);
11701 +
11702 + /* Send the Setup packet */
11703 + do_setup();
11704 +
11705 + /* 15 second delay so nothing else happens for awhile */
11706 + mdelay(15000);
11707 +
11708 + /* Restore interrupts */
11709 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
11710 + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
11711 + /* Save current interrupt mask */
11712 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
11713 +
11714 + /* Disable all interrupts while we muck with
11715 + * the hardware directly
11716 + */
11717 + dwc_write_reg32(&global_regs->gintmsk, 0);
11718 +
11719 + /* Send the Setup packet */
11720 + do_setup();
11721 +
11722 + /* 15 second delay so nothing else happens for awhile */
11723 + mdelay(15000);
11724 +
11725 + /* Send the In and Ack packets */
11726 + do_in_ack();
11727 +
11728 + /* 15 second delay so nothing else happens for awhile */
11729 + mdelay(15000);
11730 +
11731 + /* Restore interrupts */
11732 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
11733 + }
11734 + }
11735 + break;
11736 + }
11737 +#endif /* DWC_HS_ELECT_TST */
11738 +
11739 + case USB_PORT_FEAT_INDICATOR:
11740 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
11741 + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
11742 + /* Not supported */
11743 + break;
11744 + default:
11745 + retval = -EINVAL;
11746 + DWC_ERROR("DWC OTG HCD - "
11747 + "SetPortFeature request %xh "
11748 + "unknown or unsupported\n", wValue);
11749 + break;
11750 + }
11751 + break;
11752 + default:
11753 + error:
11754 + retval = -EINVAL;
11755 + DWC_WARN("DWC OTG HCD - "
11756 + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
11757 + typeReq, wIndex, wValue);
11758 + break;
11759 + }
11760 +
11761 + return retval;
11762 +}
11763 +
11764 +/**
11765 + * Assigns transactions from a QTD to a free host channel and initializes the
11766 + * host channel to perform the transactions. The host channel is removed from
11767 + * the free list.
11768 + *
11769 + * @param hcd The HCD state structure.
11770 + * @param qh Transactions from the first QTD for this QH are selected and
11771 + * assigned to a free host channel.
11772 + */
11773 +static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
11774 +{
11775 + dwc_hc_t *hc;
11776 + dwc_otg_qtd_t *qtd;
11777 + struct urb *urb;
11778 +
11779 + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
11780 +
11781 + hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
11782 +
11783 + /* Remove the host channel from the free list. */
11784 + list_del_init(&hc->hc_list_entry);
11785 +
11786 + qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
11787 + urb = qtd->urb;
11788 + qh->channel = hc;
11789 + qh->qtd_in_process = qtd;
11790 +
11791 + /*
11792 + * Use usb_pipedevice to determine device address. This address is
11793 + * 0 before the SET_ADDRESS command and the correct address afterward.
11794 + */
11795 + hc->dev_addr = usb_pipedevice(urb->pipe);
11796 + hc->ep_num = usb_pipeendpoint(urb->pipe);
11797 +
11798 + if (urb->dev->speed == USB_SPEED_LOW) {
11799 + hc->speed = DWC_OTG_EP_SPEED_LOW;
11800 + } else if (urb->dev->speed == USB_SPEED_FULL) {
11801 + hc->speed = DWC_OTG_EP_SPEED_FULL;
11802 + } else {
11803 + hc->speed = DWC_OTG_EP_SPEED_HIGH;
11804 + }
11805 +
11806 + hc->max_packet = dwc_max_packet(qh->maxp);
11807 +
11808 + hc->xfer_started = 0;
11809 + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
11810 + hc->error_state = (qtd->error_count > 0);
11811 + hc->halt_on_queue = 0;
11812 + hc->halt_pending = 0;
11813 + hc->requests = 0;
11814 +
11815 + /*
11816 + * The following values may be modified in the transfer type section
11817 + * below. The xfer_len value may be reduced when the transfer is
11818 + * started to accommodate the max widths of the XferSize and PktCnt
11819 + * fields in the HCTSIZn register.
11820 + */
11821 + hc->do_ping = qh->ping_state;
11822 + hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
11823 + hc->data_pid_start = qh->data_toggle;
11824 + hc->multi_count = 1;
11825 +
11826 + if (hcd->core_if->dma_enable) {
11827 + hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
11828 + } else {
11829 + hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
11830 + }
11831 + hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
11832 + hc->xfer_count = 0;
11833 +
11834 + /*
11835 + * Set the split attributes
11836 + */
11837 + hc->do_split = 0;
11838 + if (qh->do_split) {
11839 + hc->do_split = 1;
11840 + hc->xact_pos = qtd->isoc_split_pos;
11841 + hc->complete_split = qtd->complete_split;
11842 + hc->hub_addr = urb->dev->tt->hub->devnum;
11843 + hc->port_addr = urb->dev->ttport;
11844 + }
11845 +
11846 + switch (usb_pipetype(urb->pipe)) {
11847 + case PIPE_CONTROL:
11848 + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
11849 + switch (qtd->control_phase) {
11850 + case DWC_OTG_CONTROL_SETUP:
11851 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
11852 + hc->do_ping = 0;
11853 + hc->ep_is_in = 0;
11854 + hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
11855 + if (hcd->core_if->dma_enable) {
11856 + hc->xfer_buff = (uint8_t *)urb->setup_dma;
11857 + } else {
11858 + hc->xfer_buff = (uint8_t *)urb->setup_packet;
11859 + }
11860 + hc->xfer_len = 8;
11861 + break;
11862 + case DWC_OTG_CONTROL_DATA:
11863 + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
11864 + hc->data_pid_start = qtd->data_toggle;
11865 + break;
11866 + case DWC_OTG_CONTROL_STATUS:
11867 + /*
11868 + * Direction is opposite of data direction or IN if no
11869 + * data.
11870 + */
11871 + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
11872 + if (urb->transfer_buffer_length == 0) {
11873 + hc->ep_is_in = 1;
11874 + } else {
11875 + hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
11876 + }
11877 + if (hc->ep_is_in) {
11878 + hc->do_ping = 0;
11879 + }
11880 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
11881 + hc->xfer_len = 0;
11882 + if (hcd->core_if->dma_enable) {
11883 + hc->xfer_buff = (uint8_t *)hcd->status_buf_dma;
11884 + } else {
11885 + hc->xfer_buff = (uint8_t *)hcd->status_buf;
11886 + }
11887 + break;
11888 + }
11889 + break;
11890 + case PIPE_BULK:
11891 + hc->ep_type = DWC_OTG_EP_TYPE_BULK;
11892 + break;
11893 + case PIPE_INTERRUPT:
11894 + hc->ep_type = DWC_OTG_EP_TYPE_INTR;
11895 + break;
11896 + case PIPE_ISOCHRONOUS:
11897 + {
11898 + struct usb_iso_packet_descriptor *frame_desc;
11899 + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
11900 + hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
11901 + if (hcd->core_if->dma_enable) {
11902 + hc->xfer_buff = (uint8_t *)urb->transfer_dma;
11903 + } else {
11904 + hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
11905 + }
11906 + hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
11907 + hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
11908 +
11909 + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
11910 + if (hc->xfer_len <= 188) {
11911 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
11912 + }
11913 + else {
11914 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
11915 + }
11916 + }
11917 + }
11918 + break;
11919 + }
11920 +
11921 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
11922 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
11923 + /*
11924 + * This value may be modified when the transfer is started to
11925 + * reflect the actual transfer length.
11926 + */
11927 + hc->multi_count = dwc_hb_mult(qh->maxp);
11928 + }
11929 +
11930 + dwc_otg_hc_init(hcd->core_if, hc);
11931 + hc->qh = qh;
11932 +}
11933 +
11934 +/**
11935 + * This function selects transactions from the HCD transfer schedule and
11936 + * assigns them to available host channels. It is called from HCD interrupt
11937 + * handler functions.
11938 + *
11939 + * @param hcd The HCD state structure.
11940 + *
11941 + * @return The types of new transactions that were assigned to host channels.
11942 + */
11943 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
11944 +{
11945 + struct list_head *qh_ptr;
11946 + dwc_otg_qh_t *qh;
11947 + int num_channels;
11948 + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
11949 +
11950 +#ifdef DEBUG_SOF
11951 + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
11952 +#endif
11953 +
11954 + /* Process entries in the periodic ready list. */
11955 + qh_ptr = hcd->periodic_sched_ready.next;
11956 + while (qh_ptr != &hcd->periodic_sched_ready &&
11957 + !list_empty(&hcd->free_hc_list)) {
11958 +
11959 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
11960 + assign_and_init_hc(hcd, qh);
11961 +
11962 + /*
11963 + * Move the QH from the periodic ready schedule to the
11964 + * periodic assigned schedule.
11965 + */
11966 + qh_ptr = qh_ptr->next;
11967 + list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned);
11968 +
11969 + ret_val = DWC_OTG_TRANSACTION_PERIODIC;
11970 + }
11971 +
11972 + /*
11973 + * Process entries in the inactive portion of the non-periodic
11974 + * schedule. Some free host channels may not be used if they are
11975 + * reserved for periodic transfers.
11976 + */
11977 + qh_ptr = hcd->non_periodic_sched_inactive.next;
11978 + num_channels = hcd->core_if->core_params->host_channels;
11979 + while (qh_ptr != &hcd->non_periodic_sched_inactive &&
11980 + (hcd->non_periodic_channels <
11981 + num_channels - hcd->periodic_channels) &&
11982 + !list_empty(&hcd->free_hc_list)) {
11983 +
11984 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
11985 + assign_and_init_hc(hcd, qh);
11986 +
11987 + /*
11988 + * Move the QH from the non-periodic inactive schedule to the
11989 + * non-periodic active schedule.
11990 + */
11991 + qh_ptr = qh_ptr->next;
11992 + list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
11993 +
11994 + if (ret_val == DWC_OTG_TRANSACTION_NONE) {
11995 + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
11996 + } else {
11997 + ret_val = DWC_OTG_TRANSACTION_ALL;
11998 + }
11999 +
12000 + hcd->non_periodic_channels++;
12001 + }
12002 +
12003 + return ret_val;
12004 +}
12005 +
12006 +/**
12007 + * Attempts to queue a single transaction request for a host channel
12008 + * associated with either a periodic or non-periodic transfer. This function
12009 + * assumes that there is space available in the appropriate request queue. For
12010 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
12011 + * is available in the appropriate Tx FIFO.
12012 + *
12013 + * @param hcd The HCD state structure.
12014 + * @param hc Host channel descriptor associated with either a periodic or
12015 + * non-periodic transfer.
12016 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
12017 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
12018 + * transfers.
12019 + *
12020 + * @return 1 if a request is queued and more requests may be needed to
12021 + * complete the transfer, 0 if no more requests are required for this
12022 + * transfer, -1 if there is insufficient space in the Tx FIFO.
12023 + */
12024 +static int queue_transaction(dwc_otg_hcd_t *hcd,
12025 + dwc_hc_t *hc,
12026 + uint16_t fifo_dwords_avail)
12027 +{
12028 + int retval;
12029 +
12030 + if (hcd->core_if->dma_enable) {
12031 + if (!hc->xfer_started) {
12032 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
12033 + hc->qh->ping_state = 0;
12034 + }
12035 + retval = 0;
12036 + } else if (hc->halt_pending) {
12037 + /* Don't queue a request if the channel has been halted. */
12038 + retval = 0;
12039 + } else if (hc->halt_on_queue) {
12040 + dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
12041 + retval = 0;
12042 + } else if (hc->do_ping) {
12043 + if (!hc->xfer_started) {
12044 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
12045 + }
12046 + retval = 0;
12047 + } else if (!hc->ep_is_in ||
12048 + hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
12049 + if ((fifo_dwords_avail * 4) >= hc->max_packet) {
12050 + if (!hc->xfer_started) {
12051 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
12052 + retval = 1;
12053 + } else {
12054 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
12055 + }
12056 + } else {
12057 + retval = -1;
12058 + }
12059 + } else {
12060 + if (!hc->xfer_started) {
12061 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
12062 + retval = 1;
12063 + } else {
12064 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
12065 + }
12066 + }
12067 +
12068 + return retval;
12069 +}
12070 +
12071 +/**
12072 + * Processes active non-periodic channels and queues transactions for these
12073 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
12074 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
12075 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
12076 + * FIFO Empty interrupt is disabled.
12077 + */
12078 +static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
12079 +{
12080 + gnptxsts_data_t tx_status;
12081 + struct list_head *orig_qh_ptr;
12082 + dwc_otg_qh_t *qh;
12083 + int status;
12084 + int no_queue_space = 0;
12085 + int no_fifo_space = 0;
12086 + int more_to_do = 0;
12087 +
12088 + dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs;
12089 +
12090 + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
12091 +#ifdef DEBUG
12092 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
12093 + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
12094 + tx_status.b.nptxqspcavail);
12095 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
12096 + tx_status.b.nptxfspcavail);
12097 +#endif
12098 + /*
12099 + * Keep track of the starting point. Skip over the start-of-list
12100 + * entry.
12101 + */
12102 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
12103 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
12104 + }
12105 + orig_qh_ptr = hcd->non_periodic_qh_ptr;
12106 +
12107 + /*
12108 + * Process once through the active list or until no more space is
12109 + * available in the request queue or the Tx FIFO.
12110 + */
12111 + do {
12112 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
12113 + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
12114 + no_queue_space = 1;
12115 + break;
12116 + }
12117 +
12118 + qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
12119 + status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail);
12120 +
12121 + if (status > 0) {
12122 + more_to_do = 1;
12123 + } else if (status < 0) {
12124 + no_fifo_space = 1;
12125 + break;
12126 + }
12127 +
12128 + /* Advance to next QH, skipping start-of-list entry. */
12129 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
12130 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
12131 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
12132 + }
12133 +
12134 + } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
12135 +
12136 + if (!hcd->core_if->dma_enable) {
12137 + gintmsk_data_t intr_mask = {.d32 = 0};
12138 + intr_mask.b.nptxfempty = 1;
12139 +
12140 +#ifdef DEBUG
12141 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
12142 + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
12143 + tx_status.b.nptxqspcavail);
12144 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
12145 + tx_status.b.nptxfspcavail);
12146 +#endif
12147 + if (more_to_do || no_queue_space || no_fifo_space) {
12148 + /*
12149 + * May need to queue more transactions as the request
12150 + * queue or Tx FIFO empties. Enable the non-periodic
12151 + * Tx FIFO empty interrupt. (Always use the half-empty
12152 + * level to ensure that new requests are loaded as
12153 + * soon as possible.)
12154 + */
12155 + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
12156 + } else {
12157 + /*
12158 + * Disable the Tx FIFO empty interrupt since there are
12159 + * no more transactions that need to be queued right
12160 + * now. This function is called from interrupt
12161 + * handlers to queue more transactions as transfer
12162 + * states change.
12163 + */
12164 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
12165 + }
12166 + }
12167 +}
12168 +
12169 +/**
12170 + * Processes periodic channels for the next frame and queues transactions for
12171 + * these channels to the DWC_otg controller. After queueing transactions, the
12172 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
12173 + * to queue as Periodic Tx FIFO or request queue space becomes available.
12174 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
12175 + */
12176 +static void process_periodic_channels(dwc_otg_hcd_t *hcd)
12177 +{
12178 + hptxsts_data_t tx_status;
12179 + struct list_head *qh_ptr;
12180 + dwc_otg_qh_t *qh;
12181 + int status;
12182 + int no_queue_space = 0;
12183 + int no_fifo_space = 0;
12184 +
12185 + dwc_otg_host_global_regs_t *host_regs;
12186 + host_regs = hcd->core_if->host_if->host_global_regs;
12187 +
12188 + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
12189 +#ifdef DEBUG
12190 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
12191 + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
12192 + tx_status.b.ptxqspcavail);
12193 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
12194 + tx_status.b.ptxfspcavail);
12195 +#endif
12196 +
12197 + qh_ptr = hcd->periodic_sched_assigned.next;
12198 + while (qh_ptr != &hcd->periodic_sched_assigned) {
12199 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
12200 + if (tx_status.b.ptxqspcavail == 0) {
12201 + no_queue_space = 1;
12202 + break;
12203 + }
12204 +
12205 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
12206 +
12207 + /*
12208 + * Set a flag if we're queuing high-bandwidth in slave mode.
12209 + * The flag prevents any halts to get into the request queue in
12210 + * the middle of multiple high-bandwidth packets getting queued.
12211 + */
12212 + if (!hcd->core_if->dma_enable &&
12213 + qh->channel->multi_count > 1)
12214 + {
12215 + hcd->core_if->queuing_high_bandwidth = 1;
12216 + }
12217 +
12218 + status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail);
12219 + if (status < 0) {
12220 + no_fifo_space = 1;
12221 + break;
12222 + }
12223 +
12224 + /*
12225 + * In Slave mode, stay on the current transfer until there is
12226 + * nothing more to do or the high-bandwidth request count is
12227 + * reached. In DMA mode, only need to queue one request. The
12228 + * controller automatically handles multiple packets for
12229 + * high-bandwidth transfers.
12230 + */
12231 + if (hcd->core_if->dma_enable || status == 0 ||
12232 + qh->channel->requests == qh->channel->multi_count) {
12233 + qh_ptr = qh_ptr->next;
12234 + /*
12235 + * Move the QH from the periodic assigned schedule to
12236 + * the periodic queued schedule.
12237 + */
12238 + list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued);
12239 +
12240 + /* done queuing high bandwidth */
12241 + hcd->core_if->queuing_high_bandwidth = 0;
12242 + }
12243 + }
12244 +
12245 + if (!hcd->core_if->dma_enable) {
12246 + dwc_otg_core_global_regs_t *global_regs;
12247 + gintmsk_data_t intr_mask = {.d32 = 0};
12248 +
12249 + global_regs = hcd->core_if->core_global_regs;
12250 + intr_mask.b.ptxfempty = 1;
12251 +#ifdef DEBUG
12252 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
12253 + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
12254 + tx_status.b.ptxqspcavail);
12255 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
12256 + tx_status.b.ptxfspcavail);
12257 +#endif
12258 + if (!list_empty(&hcd->periodic_sched_assigned) ||
12259 + no_queue_space || no_fifo_space) {
12260 + /*
12261 + * May need to queue more transactions as the request
12262 + * queue or Tx FIFO empties. Enable the periodic Tx
12263 + * FIFO empty interrupt. (Always use the half-empty
12264 + * level to ensure that new requests are loaded as
12265 + * soon as possible.)
12266 + */
12267 + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
12268 + } else {
12269 + /*
12270 + * Disable the Tx FIFO empty interrupt since there are
12271 + * no more transactions that need to be queued right
12272 + * now. This function is called from interrupt
12273 + * handlers to queue more transactions as transfer
12274 + * states change.
12275 + */
12276 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
12277 + }
12278 + }
12279 +}
12280 +
12281 +/**
12282 + * This function processes the currently active host channels and queues
12283 + * transactions for these channels to the DWC_otg controller. It is called
12284 + * from HCD interrupt handler functions.
12285 + *
12286 + * @param hcd The HCD state structure.
12287 + * @param tr_type The type(s) of transactions to queue (non-periodic,
12288 + * periodic, or both).
12289 + */
12290 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
12291 + dwc_otg_transaction_type_e tr_type)
12292 +{
12293 +#ifdef DEBUG_SOF
12294 + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
12295 +#endif
12296 + /* Process host channels associated with periodic transfers. */
12297 + if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
12298 + tr_type == DWC_OTG_TRANSACTION_ALL) &&
12299 + !list_empty(&hcd->periodic_sched_assigned)) {
12300 +
12301 + process_periodic_channels(hcd);
12302 + }
12303 +
12304 + /* Process host channels associated with non-periodic transfers. */
12305 + if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
12306 + tr_type == DWC_OTG_TRANSACTION_ALL) {
12307 + if (!list_empty(&hcd->non_periodic_sched_active)) {
12308 + process_non_periodic_channels(hcd);
12309 + } else {
12310 + /*
12311 + * Ensure NP Tx FIFO empty interrupt is disabled when
12312 + * there are no non-periodic transfers to process.
12313 + */
12314 + gintmsk_data_t gintmsk = {.d32 = 0};
12315 + gintmsk.b.nptxfempty = 1;
12316 + dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk,
12317 + gintmsk.d32, 0);
12318 + }
12319 + }
12320 +}
12321 +
12322 +/**
12323 + * Sets the final status of an URB and returns it to the device driver. Any
12324 + * required cleanup of the URB is performed.
12325 + */
12326 +void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status)
12327 +{
12328 +#ifdef DEBUG
12329 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
12330 + DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
12331 + __func__, urb, usb_pipedevice(urb->pipe),
12332 + usb_pipeendpoint(urb->pipe),
12333 + usb_pipein(urb->pipe) ? "IN" : "OUT", status);
12334 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
12335 + int i;
12336 + for (i = 0; i < urb->number_of_packets; i++) {
12337 + DWC_PRINT(" ISO Desc %d status: %d\n",
12338 + i, urb->iso_frame_desc[i].status);
12339 + }
12340 + }
12341 + }
12342 +#endif
12343 +
12344 + urb->status = status;
12345 + urb->hcpriv = NULL;
12346 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
12347 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
12348 +#else
12349 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, NULL);
12350 +#endif
12351 +}
12352 +
12353 +/*
12354 + * Returns the Queue Head for an URB.
12355 + */
12356 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb)
12357 +{
12358 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
12359 + return (dwc_otg_qh_t *)ep->hcpriv;
12360 +}
12361 +
12362 +#ifdef DEBUG
12363 +void dwc_print_setup_data(uint8_t *setup)
12364 +{
12365 + int i;
12366 + if (CHK_DEBUG_LEVEL(DBG_HCD)){
12367 + DWC_PRINT("Setup Data = MSB ");
12368 + for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]);
12369 + DWC_PRINT("\n");
12370 + DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device");
12371 + DWC_PRINT(" bmRequestType Type = ");
12372 + switch ((setup[0] & 0x60) >> 5) {
12373 + case 0: DWC_PRINT("Standard\n"); break;
12374 + case 1: DWC_PRINT("Class\n"); break;
12375 + case 2: DWC_PRINT("Vendor\n"); break;
12376 + case 3: DWC_PRINT("Reserved\n"); break;
12377 + }
12378 + DWC_PRINT(" bmRequestType Recipient = ");
12379 + switch (setup[0] & 0x1f) {
12380 + case 0: DWC_PRINT("Device\n"); break;
12381 + case 1: DWC_PRINT("Interface\n"); break;
12382 + case 2: DWC_PRINT("Endpoint\n"); break;
12383 + case 3: DWC_PRINT("Other\n"); break;
12384 + default: DWC_PRINT("Reserved\n"); break;
12385 + }
12386 + DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
12387 + DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
12388 + DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
12389 + DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
12390 + }
12391 +}
12392 +#endif
12393 +
12394 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) {
12395 +#if defined(DEBUG) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12396 + DWC_PRINT("Frame remaining at SOF:\n");
12397 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12398 + hcd->frrem_samples, hcd->frrem_accum,
12399 + (hcd->frrem_samples > 0) ?
12400 + hcd->frrem_accum/hcd->frrem_samples : 0);
12401 +
12402 + DWC_PRINT("\n");
12403 + DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
12404 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12405 + hcd->core_if->hfnum_7_samples, hcd->core_if->hfnum_7_frrem_accum,
12406 + (hcd->core_if->hfnum_7_samples > 0) ?
12407 + hcd->core_if->hfnum_7_frrem_accum/hcd->core_if->hfnum_7_samples : 0);
12408 + DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
12409 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12410 + hcd->core_if->hfnum_0_samples, hcd->core_if->hfnum_0_frrem_accum,
12411 + (hcd->core_if->hfnum_0_samples > 0) ?
12412 + hcd->core_if->hfnum_0_frrem_accum/hcd->core_if->hfnum_0_samples : 0);
12413 + DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
12414 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12415 + hcd->core_if->hfnum_other_samples, hcd->core_if->hfnum_other_frrem_accum,
12416 + (hcd->core_if->hfnum_other_samples > 0) ?
12417 + hcd->core_if->hfnum_other_frrem_accum/hcd->core_if->hfnum_other_samples : 0);
12418 +
12419 + DWC_PRINT("\n");
12420 + DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
12421 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12422 + hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
12423 + (hcd->hfnum_7_samples_a > 0) ?
12424 + hcd->hfnum_7_frrem_accum_a/hcd->hfnum_7_samples_a : 0);
12425 + DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
12426 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12427 + hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
12428 + (hcd->hfnum_0_samples_a > 0) ?
12429 + hcd->hfnum_0_frrem_accum_a/hcd->hfnum_0_samples_a : 0);
12430 + DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
12431 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12432 + hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
12433 + (hcd->hfnum_other_samples_a > 0) ?
12434 + hcd->hfnum_other_frrem_accum_a/hcd->hfnum_other_samples_a : 0);
12435 +
12436 + DWC_PRINT("\n");
12437 + DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
12438 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12439 + hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
12440 + (hcd->hfnum_7_samples_b > 0) ?
12441 + hcd->hfnum_7_frrem_accum_b/hcd->hfnum_7_samples_b : 0);
12442 + DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
12443 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12444 + hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
12445 + (hcd->hfnum_0_samples_b > 0) ?
12446 + hcd->hfnum_0_frrem_accum_b/hcd->hfnum_0_samples_b : 0);
12447 + DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
12448 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
12449 + hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
12450 + (hcd->hfnum_other_samples_b > 0) ?
12451 + hcd->hfnum_other_frrem_accum_b/hcd->hfnum_other_samples_b : 0);
12452 +#endif
12453 +}
12454 +
12455 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
12456 +{
12457 +#ifdef DEBUG
12458 + int num_channels;
12459 + int i;
12460 + gnptxsts_data_t np_tx_status;
12461 + hptxsts_data_t p_tx_status;
12462 +
12463 + num_channels = hcd->core_if->core_params->host_channels;
12464 + DWC_PRINT("\n");
12465 + DWC_PRINT("************************************************************\n");
12466 + DWC_PRINT("HCD State:\n");
12467 + DWC_PRINT(" Num channels: %d\n", num_channels);
12468 + for (i = 0; i < num_channels; i++) {
12469 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
12470 + DWC_PRINT(" Channel %d:\n", i);
12471 + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
12472 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
12473 + DWC_PRINT(" speed: %d\n", hc->speed);
12474 + DWC_PRINT(" ep_type: %d\n", hc->ep_type);
12475 + DWC_PRINT(" max_packet: %d\n", hc->max_packet);
12476 + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
12477 + DWC_PRINT(" multi_count: %d\n", hc->multi_count);
12478 + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
12479 + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
12480 + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
12481 + DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
12482 + DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
12483 + DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
12484 + DWC_PRINT(" halt_status: %d\n", hc->halt_status);
12485 + DWC_PRINT(" do_split: %d\n", hc->do_split);
12486 + DWC_PRINT(" complete_split: %d\n", hc->complete_split);
12487 + DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
12488 + DWC_PRINT(" port_addr: %d\n", hc->port_addr);
12489 + DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
12490 + DWC_PRINT(" requests: %d\n", hc->requests);
12491 + DWC_PRINT(" qh: %p\n", hc->qh);
12492 + if (hc->xfer_started) {
12493 + hfnum_data_t hfnum;
12494 + hcchar_data_t hcchar;
12495 + hctsiz_data_t hctsiz;
12496 + hcint_data_t hcint;
12497 + hcintmsk_data_t hcintmsk;
12498 + hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
12499 + hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar);
12500 + hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz);
12501 + hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint);
12502 + hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk);
12503 + DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
12504 + DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
12505 + DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
12506 + DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
12507 + DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
12508 + }
12509 + if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) {
12510 + dwc_otg_qtd_t *qtd;
12511 + struct urb *urb;
12512 + qtd = hc->qh->qtd_in_process;
12513 + urb = qtd->urb;
12514 + DWC_PRINT(" URB Info:\n");
12515 + DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
12516 + if (urb) {
12517 + DWC_PRINT(" Dev: %d, EP: %d %s\n",
12518 + usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
12519 + usb_pipein(urb->pipe) ? "IN" : "OUT");
12520 + DWC_PRINT(" Max packet size: %d\n",
12521 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
12522 + DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
12523 + DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
12524 + DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
12525 + DWC_PRINT(" actual_length: %d\n", urb->actual_length);
12526 + }
12527 + }
12528 + }
12529 + DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
12530 + DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels);
12531 + DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs);
12532 + np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
12533 + DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
12534 + DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
12535 + p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
12536 + DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
12537 + DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
12538 + dwc_otg_hcd_dump_frrem(hcd);
12539 + dwc_otg_dump_global_registers(hcd->core_if);
12540 + dwc_otg_dump_host_registers(hcd->core_if);
12541 + DWC_PRINT("************************************************************\n");
12542 + DWC_PRINT("\n");
12543 +#endif
12544 +}
12545 +#endif /* DWC_DEVICE_ONLY */
12546 diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd.h b/drivers/usb/dwc_otg/dwc_otg_hcd.h
12547 new file mode 100644
12548 index 0000000..ee41dc9
12549 --- /dev/null
12550 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h
12551 @@ -0,0 +1,668 @@
12552 +/* ==========================================================================
12553 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
12554 + * $Revision: 1.3 $
12555 + * $Date: 2008-12-15 06:51:32 $
12556 + * $Change: 1064918 $
12557 + *
12558 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
12559 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
12560 + * otherwise expressly agreed to in writing between Synopsys and you.
12561 + *
12562 + * The Software IS NOT an item of Licensed Software or Licensed Product under
12563 + * any End User Software License Agreement or Agreement for Licensed Product
12564 + * with Synopsys or any supplement thereto. You are permitted to use and
12565 + * redistribute this Software in source and binary forms, with or without
12566 + * modification, provided that redistributions of source code must retain this
12567 + * notice. You may not view, use, disclose, copy or distribute this file or
12568 + * any information contained herein except pursuant to this license grant from
12569 + * Synopsys. If you do not agree with this notice, including the disclaimer
12570 + * below, then you are not authorized to use the Software.
12571 + *
12572 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
12573 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12574 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12575 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
12576 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
12577 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12578 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
12579 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
12580 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
12581 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12582 + * DAMAGE.
12583 + * ========================================================================== */
12584 +#ifndef DWC_DEVICE_ONLY
12585 +#ifndef __DWC_HCD_H__
12586 +#define __DWC_HCD_H__
12587 +
12588 +#include <linux/list.h>
12589 +#include <linux/usb.h>
12590 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
12591 +#include <linux/usb/hcd.h>
12592 +#else
12593 +#include <../drivers/usb/core/hcd.h>
12594 +#endif
12595 +
12596 +struct dwc_otg_device;
12597 +
12598 +#include "dwc_otg_cil.h"
12599 +
12600 +/**
12601 + * @file
12602 + *
12603 + * This file contains the structures, constants, and interfaces for
12604 + * the Host Contoller Driver (HCD).
12605 + *
12606 + * The Host Controller Driver (HCD) is responsible for translating requests
12607 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
12608 + * It isolates the USBD from the specifics of the controller by providing an
12609 + * API to the USBD.
12610 + */
12611 +
12612 +/**
12613 + * Phases for control transfers.
12614 + */
12615 +typedef enum dwc_otg_control_phase {
12616 + DWC_OTG_CONTROL_SETUP,
12617 + DWC_OTG_CONTROL_DATA,
12618 + DWC_OTG_CONTROL_STATUS
12619 +} dwc_otg_control_phase_e;
12620 +
12621 +/** Transaction types. */
12622 +typedef enum dwc_otg_transaction_type {
12623 + DWC_OTG_TRANSACTION_NONE,
12624 + DWC_OTG_TRANSACTION_PERIODIC,
12625 + DWC_OTG_TRANSACTION_NON_PERIODIC,
12626 + DWC_OTG_TRANSACTION_ALL
12627 +} dwc_otg_transaction_type_e;
12628 +
12629 +/**
12630 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
12631 + * interrupt, or isochronous transfer. A single QTD is created for each URB
12632 + * (of one of these types) submitted to the HCD. The transfer associated with
12633 + * a QTD may require one or multiple transactions.
12634 + *
12635 + * A QTD is linked to a Queue Head, which is entered in either the
12636 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
12637 + * execution, some or all of its transactions may be executed. After
12638 + * execution, the state of the QTD is updated. The QTD may be retired if all
12639 + * its transactions are complete or if an error occurred. Otherwise, it
12640 + * remains in the schedule so more transactions can be executed later.
12641 + */
12642 +typedef struct dwc_otg_qtd {
12643 + /**
12644 + * Determines the PID of the next data packet for the data phase of
12645 + * control transfers. Ignored for other transfer types.<br>
12646 + * One of the following values:
12647 + * - DWC_OTG_HC_PID_DATA0
12648 + * - DWC_OTG_HC_PID_DATA1
12649 + */
12650 + uint8_t data_toggle;
12651 +
12652 + /** Current phase for control transfers (Setup, Data, or Status). */
12653 + dwc_otg_control_phase_e control_phase;
12654 +
12655 + /** Keep track of the current split type
12656 + * for FS/LS endpoints on a HS Hub */
12657 + uint8_t complete_split;
12658 +
12659 + /** How many bytes transferred during SSPLIT OUT */
12660 + uint32_t ssplit_out_xfer_count;
12661 +
12662 + /**
12663 + * Holds the number of bus errors that have occurred for a transaction
12664 + * within this transfer.
12665 + */
12666 + uint8_t error_count;
12667 +
12668 + /**
12669 + * Index of the next frame descriptor for an isochronous transfer. A
12670 + * frame descriptor describes the buffer position and length of the
12671 + * data to be transferred in the next scheduled (micro)frame of an
12672 + * isochronous transfer. It also holds status for that transaction.
12673 + * The frame index starts at 0.
12674 + */
12675 + int isoc_frame_index;
12676 +
12677 + /** Position of the ISOC split on full/low speed */
12678 + uint8_t isoc_split_pos;
12679 +
12680 + /** Position of the ISOC split in the buffer for the current frame */
12681 + uint16_t isoc_split_offset;
12682 +
12683 + /** URB for this transfer */
12684 + struct urb *urb;
12685 +
12686 + /** This list of QTDs */
12687 + struct list_head qtd_list_entry;
12688 +
12689 +} dwc_otg_qtd_t;
12690 +
12691 +/**
12692 + * A Queue Head (QH) holds the static characteristics of an endpoint and
12693 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
12694 + * be entered in either the non-periodic or periodic schedule.
12695 + */
12696 +typedef struct dwc_otg_qh {
12697 + /**
12698 + * Endpoint type.
12699 + * One of the following values:
12700 + * - USB_ENDPOINT_XFER_CONTROL
12701 + * - USB_ENDPOINT_XFER_ISOC
12702 + * - USB_ENDPOINT_XFER_BULK
12703 + * - USB_ENDPOINT_XFER_INT
12704 + */
12705 + uint8_t ep_type;
12706 + uint8_t ep_is_in;
12707 +
12708 + /** wMaxPacketSize Field of Endpoint Descriptor. */
12709 + uint16_t maxp;
12710 +
12711 + /**
12712 + * Determines the PID of the next data packet for non-control
12713 + * transfers. Ignored for control transfers.<br>
12714 + * One of the following values:
12715 + * - DWC_OTG_HC_PID_DATA0
12716 + * - DWC_OTG_HC_PID_DATA1
12717 + */
12718 + uint8_t data_toggle;
12719 +
12720 + /** Ping state if 1. */
12721 + uint8_t ping_state;
12722 +
12723 + /**
12724 + * List of QTDs for this QH.
12725 + */
12726 + struct list_head qtd_list;
12727 +
12728 + /** Host channel currently processing transfers for this QH. */
12729 + dwc_hc_t *channel;
12730 +
12731 + /** QTD currently assigned to a host channel for this QH. */
12732 + dwc_otg_qtd_t *qtd_in_process;
12733 +
12734 + /** Full/low speed endpoint on high-speed hub requires split. */
12735 + uint8_t do_split;
12736 +
12737 + /** @name Periodic schedule information */
12738 + /** @{ */
12739 +
12740 + /** Bandwidth in microseconds per (micro)frame. */
12741 + uint8_t usecs;
12742 +
12743 + /** Interval between transfers in (micro)frames. */
12744 + uint16_t interval;
12745 +
12746 + /**
12747 + * (micro)frame to initialize a periodic transfer. The transfer
12748 + * executes in the following (micro)frame.
12749 + */
12750 + uint16_t sched_frame;
12751 +
12752 + /** (micro)frame at which last start split was initialized. */
12753 + uint16_t start_split_frame;
12754 +
12755 + /** @} */
12756 +
12757 + /** Entry for QH in either the periodic or non-periodic schedule. */
12758 + struct list_head qh_list_entry;
12759 +
12760 + /* For non-dword aligned buffer support */
12761 + uint8_t *dw_align_buf;
12762 + dma_addr_t dw_align_buf_dma;
12763 +} dwc_otg_qh_t;
12764 +
12765 +/**
12766 + * This structure holds the state of the HCD, including the non-periodic and
12767 + * periodic schedules.
12768 + */
12769 +typedef struct dwc_otg_hcd {
12770 + /** The DWC otg device pointer */
12771 + struct dwc_otg_device *otg_dev;
12772 +
12773 + /** DWC OTG Core Interface Layer */
12774 + dwc_otg_core_if_t *core_if;
12775 +
12776 + /** Internal DWC HCD Flags */
12777 + volatile union dwc_otg_hcd_internal_flags {
12778 + uint32_t d32;
12779 + struct {
12780 + unsigned port_connect_status_change : 1;
12781 + unsigned port_connect_status : 1;
12782 + unsigned port_reset_change : 1;
12783 + unsigned port_enable_change : 1;
12784 + unsigned port_suspend_change : 1;
12785 + unsigned port_over_current_change : 1;
12786 + unsigned reserved : 27;
12787 + } b;
12788 + } flags;
12789 +
12790 + /**
12791 + * Inactive items in the non-periodic schedule. This is a list of
12792 + * Queue Heads. Transfers associated with these Queue Heads are not
12793 + * currently assigned to a host channel.
12794 + */
12795 + struct list_head non_periodic_sched_inactive;
12796 +
12797 + /**
12798 + * Active items in the non-periodic schedule. This is a list of
12799 + * Queue Heads. Transfers associated with these Queue Heads are
12800 + * currently assigned to a host channel.
12801 + */
12802 + struct list_head non_periodic_sched_active;
12803 +
12804 + /**
12805 + * Pointer to the next Queue Head to process in the active
12806 + * non-periodic schedule.
12807 + */
12808 + struct list_head *non_periodic_qh_ptr;
12809 +
12810 + /**
12811 + * Inactive items in the periodic schedule. This is a list of QHs for
12812 + * periodic transfers that are _not_ scheduled for the next frame.
12813 + * Each QH in the list has an interval counter that determines when it
12814 + * needs to be scheduled for execution. This scheduling mechanism
12815 + * allows only a simple calculation for periodic bandwidth used (i.e.
12816 + * must assume that all periodic transfers may need to execute in the
12817 + * same frame). However, it greatly simplifies scheduling and should
12818 + * be sufficient for the vast majority of OTG hosts, which need to
12819 + * connect to a small number of peripherals at one time.
12820 + *
12821 + * Items move from this list to periodic_sched_ready when the QH
12822 + * interval counter is 0 at SOF.
12823 + */
12824 + struct list_head periodic_sched_inactive;
12825 +
12826 + /**
12827 + * List of periodic QHs that are ready for execution in the next
12828 + * frame, but have not yet been assigned to host channels.
12829 + *
12830 + * Items move from this list to periodic_sched_assigned as host
12831 + * channels become available during the current frame.
12832 + */
12833 + struct list_head periodic_sched_ready;
12834 +
12835 + /**
12836 + * List of periodic QHs to be executed in the next frame that are
12837 + * assigned to host channels.
12838 + *
12839 + * Items move from this list to periodic_sched_queued as the
12840 + * transactions for the QH are queued to the DWC_otg controller.
12841 + */
12842 + struct list_head periodic_sched_assigned;
12843 +
12844 + /**
12845 + * List of periodic QHs that have been queued for execution.
12846 + *
12847 + * Items move from this list to either periodic_sched_inactive or
12848 + * periodic_sched_ready when the channel associated with the transfer
12849 + * is released. If the interval for the QH is 1, the item moves to
12850 + * periodic_sched_ready because it must be rescheduled for the next
12851 + * frame. Otherwise, the item moves to periodic_sched_inactive.
12852 + */
12853 + struct list_head periodic_sched_queued;
12854 +
12855 + /**
12856 + * Total bandwidth claimed so far for periodic transfers. This value
12857 + * is in microseconds per (micro)frame. The assumption is that all
12858 + * periodic transfers may occur in the same (micro)frame.
12859 + */
12860 + uint16_t periodic_usecs;
12861 +
12862 + /**
12863 + * Frame number read from the core at SOF. The value ranges from 0 to
12864 + * DWC_HFNUM_MAX_FRNUM.
12865 + */
12866 + uint16_t frame_number;
12867 +
12868 + /**
12869 + * Free host channels in the controller. This is a list of
12870 + * dwc_hc_t items.
12871 + */
12872 + struct list_head free_hc_list;
12873 +
12874 + /**
12875 + * Number of host channels assigned to periodic transfers. Currently
12876 + * assuming that there is a dedicated host channel for each periodic
12877 + * transaction and at least one host channel available for
12878 + * non-periodic transactions.
12879 + */
12880 + int periodic_channels;
12881 +
12882 + /**
12883 + * Number of host channels assigned to non-periodic transfers.
12884 + */
12885 + int non_periodic_channels;
12886 +
12887 + /**
12888 + * Array of pointers to the host channel descriptors. Allows accessing
12889 + * a host channel descriptor given the host channel number. This is
12890 + * useful in interrupt handlers.
12891 + */
12892 + dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
12893 +
12894 + /**
12895 + * Buffer to use for any data received during the status phase of a
12896 + * control transfer. Normally no data is transferred during the status
12897 + * phase. This buffer is used as a bit bucket.
12898 + */
12899 + uint8_t *status_buf;
12900 +
12901 + /**
12902 + * DMA address for status_buf.
12903 + */
12904 + dma_addr_t status_buf_dma;
12905 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
12906 +
12907 + /**
12908 + * Structure to allow starting the HCD in a non-interrupt context
12909 + * during an OTG role change.
12910 + */
12911 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12912 + struct work_struct start_work;
12913 +#else
12914 + struct delayed_work start_work;
12915 +#endif
12916 +
12917 + /**
12918 + * Connection timer. An OTG host must display a message if the device
12919 + * does not connect. Started when the VBus power is turned on via
12920 + * sysfs attribute "buspower".
12921 + */
12922 + struct timer_list conn_timer;
12923 +
12924 + /* Tasket to do a reset */
12925 + struct tasklet_struct *reset_tasklet;
12926 +
12927 + /* */
12928 + spinlock_t lock;
12929 +
12930 +#ifdef DEBUG
12931 + uint32_t frrem_samples;
12932 + uint64_t frrem_accum;
12933 +
12934 + uint32_t hfnum_7_samples_a;
12935 + uint64_t hfnum_7_frrem_accum_a;
12936 + uint32_t hfnum_0_samples_a;
12937 + uint64_t hfnum_0_frrem_accum_a;
12938 + uint32_t hfnum_other_samples_a;
12939 + uint64_t hfnum_other_frrem_accum_a;
12940 +
12941 + uint32_t hfnum_7_samples_b;
12942 + uint64_t hfnum_7_frrem_accum_b;
12943 + uint32_t hfnum_0_samples_b;
12944 + uint64_t hfnum_0_frrem_accum_b;
12945 + uint32_t hfnum_other_samples_b;
12946 + uint64_t hfnum_other_frrem_accum_b;
12947 +#endif
12948 +} dwc_otg_hcd_t;
12949 +
12950 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
12951 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
12952 +{
12953 + return (dwc_otg_hcd_t *)(hcd->hcd_priv);
12954 +}
12955 +
12956 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
12957 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
12958 +{
12959 + return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
12960 +}
12961 +
12962 +/** @name HCD Create/Destroy Functions */
12963 +/** @{ */
12964 +extern int dwc_otg_hcd_init(struct device *dev);
12965 +extern void dwc_otg_hcd_remove(struct device *dev);
12966 +/** @} */
12967 +
12968 +/** @name Linux HC Driver API Functions */
12969 +/** @{ */
12970 +
12971 +extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
12972 +extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
12973 +extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
12974 +extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
12975 +extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
12976 + struct urb *urb,
12977 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12978 + int mem_flags
12979 +#else
12980 + gfp_t mem_flags
12981 +#endif
12982 + );
12983 +extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
12984 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12985 +#endif
12986 + struct urb *urb, int status);
12987 +extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
12988 + struct usb_host_endpoint *ep);
12989 +extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
12990 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
12991 + , struct pt_regs *regs
12992 +#endif
12993 + );
12994 +extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
12995 + char *buf);
12996 +extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
12997 + u16 typeReq,
12998 + u16 wValue,
12999 + u16 wIndex,
13000 + char *buf,
13001 + u16 wLength);
13002 +
13003 +/** @} */
13004 +
13005 +/** @name Transaction Execution Functions */
13006 +/** @{ */
13007 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
13008 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
13009 + dwc_otg_transaction_type_e tr_type);
13010 +extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
13011 + int status);
13012 +/** @} */
13013 +
13014 +/** @name Interrupt Handler Functions */
13015 +/** @{ */
13016 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13017 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13018 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13019 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13020 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13021 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13022 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13023 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13024 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13025 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13026 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
13027 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13028 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
13029 +/** @} */
13030 +
13031 +
13032 +/** @name Schedule Queue Functions */
13033 +/** @{ */
13034 +
13035 +/* Implemented in dwc_otg_hcd_queue.c */
13036 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
13037 +extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
13038 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
13039 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
13040 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
13041 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
13042 +
13043 +/** Remove and free a QH */
13044 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
13045 + dwc_otg_qh_t *qh)
13046 +{
13047 + dwc_otg_hcd_qh_remove(hcd, qh);
13048 + dwc_otg_hcd_qh_free(hcd, qh);
13049 +}
13050 +
13051 +/** Allocates memory for a QH structure.
13052 + * @return Returns the memory allocate or NULL on error. */
13053 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
13054 +{
13055 + return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
13056 +}
13057 +
13058 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
13059 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
13060 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
13061 +
13062 +/** Allocates memory for a QTD structure.
13063 + * @return Returns the memory allocate or NULL on error. */
13064 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
13065 +{
13066 + return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
13067 +}
13068 +
13069 +/** Frees the memory for a QTD structure. QTD should already be removed from
13070 + * list.
13071 + * @param[in] qtd QTD to free.*/
13072 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
13073 +{
13074 + kfree(qtd);
13075 +}
13076 +
13077 +/** Removes a QTD from list.
13078 + * @param[in] hcd HCD instance.
13079 + * @param[in] qtd QTD to remove from list. */
13080 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
13081 +{
13082 + unsigned long flags;
13083 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
13084 + list_del(&qtd->qtd_list_entry);
13085 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
13086 +}
13087 +
13088 +/** Remove and free a QTD */
13089 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
13090 +{
13091 + dwc_otg_hcd_qtd_remove(hcd, qtd);
13092 + dwc_otg_hcd_qtd_free(qtd);
13093 +}
13094 +
13095 +/** @} */
13096 +
13097 +
13098 +/** @name Internal Functions */
13099 +/** @{ */
13100 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
13101 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
13102 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
13103 +/** @} */
13104 +
13105 +/** Gets the usb_host_endpoint associated with an URB. */
13106 +static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
13107 +{
13108 + struct usb_device *dev = urb->dev;
13109 + int ep_num = usb_pipeendpoint(urb->pipe);
13110 +
13111 + if (usb_pipein(urb->pipe))
13112 + return dev->ep_in[ep_num];
13113 + else
13114 + return dev->ep_out[ep_num];
13115 +}
13116 +
13117 +/**
13118 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
13119 + * qualified with its direction (possible 32 endpoints per device).
13120 + */
13121 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
13122 + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
13123 +
13124 +/** Gets the QH that contains the list_head */
13125 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
13126 +
13127 +/** Gets the QTD that contains the list_head */
13128 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
13129 +
13130 +/** Check if QH is non-periodic */
13131 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
13132 + (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
13133 +
13134 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
13135 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
13136 +
13137 +/** Packet size for any kind of endpoint descriptor */
13138 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
13139 +
13140 +/**
13141 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
13142 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
13143 + * frame number when the max frame number is reached.
13144 + */
13145 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
13146 +{
13147 + return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
13148 + (DWC_HFNUM_MAX_FRNUM >> 1);
13149 +}
13150 +
13151 +/**
13152 + * Returns true if _frame1 is greater than _frame2. The comparison is done
13153 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
13154 + * number when the max frame number is reached.
13155 + */
13156 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
13157 +{
13158 + return (frame1 != frame2) &&
13159 + (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
13160 + (DWC_HFNUM_MAX_FRNUM >> 1));
13161 +}
13162 +
13163 +/**
13164 + * Increments _frame by the amount specified by _inc. The addition is done
13165 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
13166 + */
13167 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
13168 +{
13169 + return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
13170 +}
13171 +
13172 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
13173 +{
13174 + return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
13175 +}
13176 +
13177 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
13178 +{
13179 + return frame & 0x7;
13180 +}
13181 +
13182 +#ifdef DEBUG
13183 +/**
13184 + * Macro to sample the remaining PHY clocks left in the current frame. This
13185 + * may be used during debugging to determine the average time it takes to
13186 + * execute sections of code. There are two possible sample points, "a" and
13187 + * "b", so the _letter argument must be one of these values.
13188 + *
13189 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
13190 + * example, "cat /sys/devices/lm0/hcd_frrem".
13191 + */
13192 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
13193 +{ \
13194 + hfnum_data_t hfnum; \
13195 + dwc_otg_qtd_t *qtd; \
13196 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
13197 + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
13198 + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
13199 + switch (hfnum.b.frnum & 0x7) { \
13200 + case 7: \
13201 + _hcd->hfnum_7_samples_##_letter++; \
13202 + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
13203 + break; \
13204 + case 0: \
13205 + _hcd->hfnum_0_samples_##_letter++; \
13206 + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
13207 + break; \
13208 + default: \
13209 + _hcd->hfnum_other_samples_##_letter++; \
13210 + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
13211 + break; \
13212 + } \
13213 + } \
13214 +}
13215 +#else
13216 +#define dwc_sample_frrem(_hcd, _qh, _letter)
13217 +#endif
13218 +#endif
13219 +#endif /* DWC_DEVICE_ONLY */
13220 diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
13221 new file mode 100644
13222 index 0000000..bdf2db9
13223 --- /dev/null
13224 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
13225 @@ -0,0 +1,1873 @@
13226 +/* ==========================================================================
13227 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
13228 + * $Revision: 1.6.2.1 $
13229 + * $Date: 2009-04-22 03:48:22 $
13230 + * $Change: 1117667 $
13231 + *
13232 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13233 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13234 + * otherwise expressly agreed to in writing between Synopsys and you.
13235 + *
13236 + * The Software IS NOT an item of Licensed Software or Licensed Product under
13237 + * any End User Software License Agreement or Agreement for Licensed Product
13238 + * with Synopsys or any supplement thereto. You are permitted to use and
13239 + * redistribute this Software in source and binary forms, with or without
13240 + * modification, provided that redistributions of source code must retain this
13241 + * notice. You may not view, use, disclose, copy or distribute this file or
13242 + * any information contained herein except pursuant to this license grant from
13243 + * Synopsys. If you do not agree with this notice, including the disclaimer
13244 + * below, then you are not authorized to use the Software.
13245 + *
13246 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13247 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13248 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13249 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13250 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13251 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13252 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13253 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13254 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13255 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13256 + * DAMAGE.
13257 + * ========================================================================== */
13258 +#ifndef DWC_DEVICE_ONLY
13259 +
13260 +#include <linux/version.h>
13261 +
13262 +#include "dwc_otg_driver.h"
13263 +#include "dwc_otg_hcd.h"
13264 +#include "dwc_otg_regs.h"
13265 +
13266 +/** @file
13267 + * This file contains the implementation of the HCD Interrupt handlers.
13268 + */
13269 +
13270 +/** This function handles interrupts for the HCD. */
13271 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13272 +{
13273 + int retval = 0;
13274 +
13275 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
13276 + gintsts_data_t gintsts;
13277 +#ifdef DEBUG
13278 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
13279 +#endif
13280 +
13281 + /* Check if HOST Mode */
13282 + if (dwc_otg_is_host_mode(core_if)) {
13283 + gintsts.d32 = dwc_otg_read_core_intr(core_if);
13284 + if (!gintsts.d32) {
13285 + return 0;
13286 + }
13287 +
13288 +#ifdef DEBUG
13289 + /* Don't print debug message in the interrupt handler on SOF */
13290 +# ifndef DEBUG_SOF
13291 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
13292 +# endif
13293 + DWC_DEBUGPL(DBG_HCD, "\n");
13294 +#endif
13295 +
13296 +#ifdef DEBUG
13297 +# ifndef DEBUG_SOF
13298 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
13299 +# endif
13300 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
13301 +#endif
13302 + if (gintsts.b.usbreset) {
13303 + DWC_PRINT("Usb Reset In Host Mode\n");
13304 + }
13305 +
13306 +
13307 + if (gintsts.b.sofintr) {
13308 + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
13309 + }
13310 + if (gintsts.b.rxstsqlvl) {
13311 + retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd);
13312 + }
13313 + if (gintsts.b.nptxfempty) {
13314 + retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd);
13315 + }
13316 + if (gintsts.b.i2cintr) {
13317 + /** @todo Implement i2cintr handler. */
13318 + }
13319 + if (gintsts.b.portintr) {
13320 + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
13321 + }
13322 + if (gintsts.b.hcintr) {
13323 + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
13324 + }
13325 + if (gintsts.b.ptxfempty) {
13326 + retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd);
13327 + }
13328 +#ifdef DEBUG
13329 +# ifndef DEBUG_SOF
13330 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
13331 +# endif
13332 + {
13333 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
13334 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
13335 + dwc_read_reg32(&global_regs->gintsts));
13336 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
13337 + dwc_read_reg32(&global_regs->gintmsk));
13338 + }
13339 +#endif
13340 +
13341 +#ifdef DEBUG
13342 +# ifndef DEBUG_SOF
13343 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
13344 +# endif
13345 + DWC_DEBUGPL(DBG_HCD, "\n");
13346 +#endif
13347 +
13348 + }
13349 +
13350 + S3C2410X_CLEAR_EINTPEND();
13351 +
13352 + return retval;
13353 +}
13354 +
13355 +#ifdef DWC_TRACK_MISSED_SOFS
13356 +#warning Compiling code to track missed SOFs
13357 +#define FRAME_NUM_ARRAY_SIZE 1000
13358 +/**
13359 + * This function is for debug only.
13360 + */
13361 +static inline void track_missed_sofs(uint16_t curr_frame_number)
13362 +{
13363 + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
13364 + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
13365 + static int frame_num_idx = 0;
13366 + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
13367 + static int dumped_frame_num_array = 0;
13368 +
13369 + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
13370 + if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) {
13371 + frame_num_array[frame_num_idx] = curr_frame_number;
13372 + last_frame_num_array[frame_num_idx++] = last_frame_num;
13373 + }
13374 + } else if (!dumped_frame_num_array) {
13375 + int i;
13376 + printk(KERN_EMERG USB_DWC "Frame Last Frame\n");
13377 + printk(KERN_EMERG USB_DWC "----- ----------\n");
13378 + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
13379 + printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n",
13380 + frame_num_array[i], last_frame_num_array[i]);
13381 + }
13382 + dumped_frame_num_array = 1;
13383 + }
13384 + last_frame_num = curr_frame_number;
13385 +}
13386 +#endif
13387 +
13388 +/**
13389 + * Handles the start-of-frame interrupt in host mode. Non-periodic
13390 + * transactions may be queued to the DWC_otg controller for the current
13391 + * (micro)frame. Periodic transactions may be queued to the controller for the
13392 + * next (micro)frame.
13393 + */
13394 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
13395 +{
13396 + hfnum_data_t hfnum;
13397 + struct list_head *qh_entry;
13398 + dwc_otg_qh_t *qh;
13399 + dwc_otg_transaction_type_e tr_type;
13400 + gintsts_data_t gintsts = {.d32 = 0};
13401 +
13402 + hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
13403 +
13404 +#ifdef DEBUG_SOF
13405 + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
13406 +#endif
13407 + hcd->frame_number = hfnum.b.frnum;
13408 +
13409 +#ifdef DEBUG
13410 + hcd->frrem_accum += hfnum.b.frrem;
13411 + hcd->frrem_samples++;
13412 +#endif
13413 +
13414 +#ifdef DWC_TRACK_MISSED_SOFS
13415 + track_missed_sofs(hcd->frame_number);
13416 +#endif
13417 +
13418 + /* Determine whether any periodic QHs should be executed. */
13419 + qh_entry = hcd->periodic_sched_inactive.next;
13420 + while (qh_entry != &hcd->periodic_sched_inactive) {
13421 + qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
13422 + qh_entry = qh_entry->next;
13423 + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
13424 + /*
13425 + * Move QH to the ready list to be executed next
13426 + * (micro)frame.
13427 + */
13428 + list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready);
13429 + }
13430 + }
13431 +
13432 + tr_type = dwc_otg_hcd_select_transactions(hcd);
13433 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
13434 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
13435 + }
13436 +
13437 + /* Clear interrupt */
13438 + gintsts.b.sofintr = 1;
13439 + dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
13440 +
13441 + return 1;
13442 +}
13443 +
13444 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
13445 + * least one packet in the Rx FIFO. The packets are moved from the FIFO to
13446 + * memory if the DWC_otg controller is operating in Slave mode. */
13447 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13448 +{
13449 + host_grxsts_data_t grxsts;
13450 + dwc_hc_t *hc = NULL;
13451 +
13452 + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
13453 +
13454 + grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
13455 +
13456 + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
13457 +
13458 + /* Packet Status */
13459 + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
13460 + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
13461 + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
13462 + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
13463 +
13464 + switch (grxsts.b.pktsts) {
13465 + case DWC_GRXSTS_PKTSTS_IN:
13466 + /* Read the data into the host buffer. */
13467 + if (grxsts.b.bcnt > 0) {
13468 + dwc_otg_read_packet(dwc_otg_hcd->core_if,
13469 + hc->xfer_buff,
13470 + grxsts.b.bcnt);
13471 +
13472 + /* Update the HC fields for the next packet received. */
13473 + hc->xfer_count += grxsts.b.bcnt;
13474 + hc->xfer_buff += grxsts.b.bcnt;
13475 + }
13476 +
13477 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
13478 + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
13479 + case DWC_GRXSTS_PKTSTS_CH_HALTED:
13480 + /* Handled in interrupt, just ignore data */
13481 + break;
13482 + default:
13483 + DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
13484 + break;
13485 + }
13486 +
13487 + return 1;
13488 +}
13489 +
13490 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
13491 + * data packets may be written to the FIFO for OUT transfers. More requests
13492 + * may be written to the non-periodic request queue for IN transfers. This
13493 + * interrupt is enabled only in Slave mode. */
13494 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13495 +{
13496 + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
13497 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
13498 + DWC_OTG_TRANSACTION_NON_PERIODIC);
13499 + return 1;
13500 +}
13501 +
13502 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
13503 + * packets may be written to the FIFO for OUT transfers. More requests may be
13504 + * written to the periodic request queue for IN transfers. This interrupt is
13505 + * enabled only in Slave mode. */
13506 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13507 +{
13508 + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
13509 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
13510 + DWC_OTG_TRANSACTION_PERIODIC);
13511 + return 1;
13512 +}
13513 +
13514 +/** There are multiple conditions that can cause a port interrupt. This function
13515 + * determines which interrupt conditions have occurred and handles them
13516 + * appropriately. */
13517 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13518 +{
13519 + int retval = 0;
13520 + hprt0_data_t hprt0;
13521 + hprt0_data_t hprt0_modify;
13522 +
13523 + hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
13524 + hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
13525 +
13526 + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
13527 + * GINTSTS */
13528 +
13529 + hprt0_modify.b.prtena = 0;
13530 + hprt0_modify.b.prtconndet = 0;
13531 + hprt0_modify.b.prtenchng = 0;
13532 + hprt0_modify.b.prtovrcurrchng = 0;
13533 +
13534 + /* Port Connect Detected
13535 + * Set flag and clear if detected */
13536 + if (hprt0.b.prtconndet) {
13537 + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
13538 + "Port Connect Detected--\n", hprt0.d32);
13539 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
13540 + dwc_otg_hcd->flags.b.port_connect_status = 1;
13541 + hprt0_modify.b.prtconndet = 1;
13542 +
13543 + /* B-Device has connected, Delete the connection timer. */
13544 + del_timer( &dwc_otg_hcd->conn_timer );
13545 +
13546 + /* The Hub driver asserts a reset when it sees port connect
13547 + * status change flag */
13548 + retval |= 1;
13549 + }
13550 +
13551 + /* Port Enable Changed
13552 + * Clear if detected - Set internal flag if disabled */
13553 + if (hprt0.b.prtenchng) {
13554 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
13555 + "Port Enable Changed--\n", hprt0.d32);
13556 + hprt0_modify.b.prtenchng = 1;
13557 + if (hprt0.b.prtena == 1) {
13558 + int do_reset = 0;
13559 + dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params;
13560 + dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs;
13561 + dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if;
13562 +
13563 + /* Check if we need to adjust the PHY clock speed for
13564 + * low power and adjust it */
13565 + if (params->host_support_fs_ls_low_power) {
13566 + gusbcfg_data_t usbcfg;
13567 +
13568 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
13569 +
13570 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ||
13571 + hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
13572 + /*
13573 + * Low power
13574 + */
13575 + hcfg_data_t hcfg;
13576 + if (usbcfg.b.phylpwrclksel == 0) {
13577 + /* Set PHY low power clock select for FS/LS devices */
13578 + usbcfg.b.phylpwrclksel = 1;
13579 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
13580 + do_reset = 1;
13581 + }
13582 +
13583 + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
13584 +
13585 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED &&
13586 + params->host_ls_low_power_phy_clk ==
13587 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
13588 + /* 6 MHZ */
13589 + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
13590 + if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
13591 + hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
13592 + dwc_write_reg32(&host_if->host_global_regs->hcfg,
13593 + hcfg.d32);
13594 + do_reset = 1;
13595 + }
13596 + } else {
13597 + /* 48 MHZ */
13598 + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
13599 + if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
13600 + hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
13601 + dwc_write_reg32(&host_if->host_global_regs->hcfg,
13602 + hcfg.d32);
13603 + do_reset = 1;
13604 + }
13605 + }
13606 + } else {
13607 + /*
13608 + * Not low power
13609 + */
13610 + if (usbcfg.b.phylpwrclksel == 1) {
13611 + usbcfg.b.phylpwrclksel = 0;
13612 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
13613 + do_reset = 1;
13614 + }
13615 + }
13616 +
13617 + if (do_reset) {
13618 + tasklet_schedule(dwc_otg_hcd->reset_tasklet);
13619 + }
13620 + }
13621 +
13622 + if (!do_reset) {
13623 + /* Port has been enabled set the reset change flag */
13624 + dwc_otg_hcd->flags.b.port_reset_change = 1;
13625 + }
13626 + } else {
13627 + dwc_otg_hcd->flags.b.port_enable_change = 1;
13628 + }
13629 + retval |= 1;
13630 + }
13631 +
13632 + /** Overcurrent Change Interrupt */
13633 + if (hprt0.b.prtovrcurrchng) {
13634 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
13635 + "Port Overcurrent Changed--\n", hprt0.d32);
13636 + dwc_otg_hcd->flags.b.port_over_current_change = 1;
13637 + hprt0_modify.b.prtovrcurrchng = 1;
13638 + retval |= 1;
13639 + }
13640 +
13641 + /* Clear Port Interrupts */
13642 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
13643 +
13644 + return retval;
13645 +}
13646 +
13647 +/** This interrupt indicates that one or more host channels has a pending
13648 + * interrupt. There are multiple conditions that can cause each host channel
13649 + * interrupt. This function determines which conditions have occurred for each
13650 + * host channel interrupt and handles them appropriately. */
13651 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
13652 +{
13653 + int i;
13654 + int retval = 0;
13655 + haint_data_t haint;
13656 +
13657 + /* Clear appropriate bits in HCINTn to clear the interrupt bit in
13658 + * GINTSTS */
13659 +
13660 + haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
13661 +
13662 + for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
13663 + if (haint.b2.chint & (1 << i)) {
13664 + retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
13665 + }
13666 + }
13667 +
13668 + return retval;
13669 +}
13670 +
13671 +/* Macro used to clear one channel interrupt */
13672 +#define clear_hc_int(_hc_regs_, _intr_) \
13673 +do { \
13674 + hcint_data_t hcint_clear = {.d32 = 0}; \
13675 + hcint_clear.b._intr_ = 1; \
13676 + dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
13677 +} while (0)
13678 +
13679 +/*
13680 + * Macro used to disable one channel interrupt. Channel interrupts are
13681 + * disabled when the channel is halted or released by the interrupt handler.
13682 + * There is no need to handle further interrupts of that type until the
13683 + * channel is re-assigned. In fact, subsequent handling may cause crashes
13684 + * because the channel structures are cleaned up when the channel is released.
13685 + */
13686 +#define disable_hc_int(_hc_regs_, _intr_) \
13687 +do { \
13688 + hcintmsk_data_t hcintmsk = {.d32 = 0}; \
13689 + hcintmsk.b._intr_ = 1; \
13690 + dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
13691 +} while (0)
13692 +
13693 +/**
13694 + * Gets the actual length of a transfer after the transfer halts. _halt_status
13695 + * holds the reason for the halt.
13696 + *
13697 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
13698 + * *short_read is set to 1 upon return if less than the requested
13699 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
13700 + * return. short_read may also be NULL on entry, in which case it remains
13701 + * unchanged.
13702 + */
13703 +static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
13704 + dwc_otg_hc_regs_t *hc_regs,
13705 + dwc_otg_qtd_t *qtd,
13706 + dwc_otg_halt_status_e halt_status,
13707 + int *short_read)
13708 +{
13709 + hctsiz_data_t hctsiz;
13710 + uint32_t length;
13711 +
13712 + if (short_read != NULL) {
13713 + *short_read = 0;
13714 + }
13715 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
13716 +
13717 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
13718 + if (hc->ep_is_in) {
13719 + length = hc->xfer_len - hctsiz.b.xfersize;
13720 + if (short_read != NULL) {
13721 + *short_read = (hctsiz.b.xfersize != 0);
13722 + }
13723 + } else if (hc->qh->do_split) {
13724 + length = qtd->ssplit_out_xfer_count;
13725 + } else {
13726 + length = hc->xfer_len;
13727 + }
13728 + } else {
13729 + /*
13730 + * Must use the hctsiz.pktcnt field to determine how much data
13731 + * has been transferred. This field reflects the number of
13732 + * packets that have been transferred via the USB. This is
13733 + * always an integral number of packets if the transfer was
13734 + * halted before its normal completion. (Can't use the
13735 + * hctsiz.xfersize field because that reflects the number of
13736 + * bytes transferred via the AHB, not the USB).
13737 + */
13738 + length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
13739 + }
13740 +
13741 + return length;
13742 +}
13743 +
13744 +/**
13745 + * Updates the state of the URB after a Transfer Complete interrupt on the
13746 + * host channel. Updates the actual_length field of the URB based on the
13747 + * number of bytes transferred via the host channel. Sets the URB status
13748 + * if the data transfer is finished.
13749 + *
13750 + * @return 1 if the data transfer specified by the URB is completely finished,
13751 + * 0 otherwise.
13752 + */
13753 +static int update_urb_state_xfer_comp(dwc_hc_t *hc,
13754 + dwc_otg_hc_regs_t *hc_regs,
13755 + struct urb *urb,
13756 + dwc_otg_qtd_t *qtd)
13757 +{
13758 + int xfer_done = 0;
13759 + int short_read = 0;
13760 + int overflow_read=0;
13761 + uint32_t len = 0;
13762 + int max_packet;
13763 +
13764 + len = get_actual_xfer_length(hc, hc_regs, qtd,
13765 + DWC_OTG_HC_XFER_COMPLETE,
13766 + &short_read);
13767 +
13768 + /* Data overflow case: by Steven */
13769 + if (len > urb->transfer_buffer_length) {
13770 + len = urb->transfer_buffer_length;
13771 + overflow_read = 1;
13772 + }
13773 +
13774 + /* non DWORD-aligned buffer case handling. */
13775 + if (((uint32_t)hc->xfer_buff & 0x3) && len && hc->qh->dw_align_buf && hc->ep_is_in) {
13776 + memcpy(urb->transfer_buffer + urb->actual_length, hc->qh->dw_align_buf, len);
13777 + }
13778 + urb->actual_length +=len;
13779 +
13780 + max_packet = usb_maxpacket(urb->dev, urb->pipe, !usb_pipein(urb->pipe));
13781 + if((len) && usb_pipebulk(urb->pipe) &&
13782 + (urb->transfer_flags & URB_ZERO_PACKET) &&
13783 + (urb->actual_length == urb->transfer_buffer_length) &&
13784 + (!(urb->transfer_buffer_length % max_packet))) {
13785 + } else if (short_read || urb->actual_length == urb->transfer_buffer_length) {
13786 + xfer_done = 1;
13787 + if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) {
13788 + urb->status = -EREMOTEIO;
13789 + } else if (overflow_read) {
13790 + urb->status = -EOVERFLOW;
13791 + } else {
13792 + urb->status = 0;
13793 + }
13794 + }
13795 +
13796 +#ifdef DEBUG
13797 + {
13798 + hctsiz_data_t hctsiz;
13799 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
13800 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
13801 + __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
13802 + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
13803 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize);
13804 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
13805 + urb->transfer_buffer_length);
13806 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
13807 + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
13808 + short_read, xfer_done);
13809 + }
13810 +#endif
13811 +
13812 + return xfer_done;
13813 +}
13814 +
13815 +/*
13816 + * Save the starting data toggle for the next transfer. The data toggle is
13817 + * saved in the QH for non-control transfers and it's saved in the QTD for
13818 + * control transfers.
13819 + */
13820 +static void save_data_toggle(dwc_hc_t *hc,
13821 + dwc_otg_hc_regs_t *hc_regs,
13822 + dwc_otg_qtd_t *qtd)
13823 +{
13824 + hctsiz_data_t hctsiz;
13825 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
13826 +
13827 + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
13828 + dwc_otg_qh_t *qh = hc->qh;
13829 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
13830 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
13831 + } else {
13832 + qh->data_toggle = DWC_OTG_HC_PID_DATA1;
13833 + }
13834 + } else {
13835 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
13836 + qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
13837 + } else {
13838 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
13839 + }
13840 + }
13841 +}
13842 +
13843 +/**
13844 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
13845 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
13846 + * still linked to the QH, the QH is added to the end of the inactive
13847 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
13848 + * schedule if no more QTDs are linked to the QH.
13849 + */
13850 +static void deactivate_qh(dwc_otg_hcd_t *hcd,
13851 + dwc_otg_qh_t *qh,
13852 + int free_qtd)
13853 +{
13854 + int continue_split = 0;
13855 + dwc_otg_qtd_t *qtd;
13856 +
13857 + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
13858 +
13859 + qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
13860 +
13861 + if (qtd->complete_split) {
13862 + continue_split = 1;
13863 + } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
13864 + qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
13865 + continue_split = 1;
13866 + }
13867 +
13868 + if (free_qtd) {
13869 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
13870 + continue_split = 0;
13871 + }
13872 +
13873 + qh->channel = NULL;
13874 + qh->qtd_in_process = NULL;
13875 + dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
13876 +}
13877 +
13878 +/**
13879 + * Updates the state of an Isochronous URB when the transfer is stopped for
13880 + * any reason. The fields of the current entry in the frame descriptor array
13881 + * are set based on the transfer state and the input _halt_status. Completes
13882 + * the Isochronous URB if all the URB frames have been completed.
13883 + *
13884 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
13885 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
13886 + */
13887 +static dwc_otg_halt_status_e
13888 +update_isoc_urb_state(dwc_otg_hcd_t *hcd,
13889 + dwc_hc_t *hc,
13890 + dwc_otg_hc_regs_t *hc_regs,
13891 + dwc_otg_qtd_t *qtd,
13892 + dwc_otg_halt_status_e halt_status)
13893 +{
13894 + struct urb *urb = qtd->urb;
13895 + dwc_otg_halt_status_e ret_val = halt_status;
13896 + struct usb_iso_packet_descriptor *frame_desc;
13897 +
13898 + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
13899 + switch (halt_status) {
13900 + case DWC_OTG_HC_XFER_COMPLETE:
13901 + frame_desc->status = 0;
13902 + frame_desc->actual_length =
13903 + get_actual_xfer_length(hc, hc_regs, qtd,
13904 + halt_status, NULL);
13905 +
13906 + /* non DWORD-aligned buffer case handling. */
13907 + if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) &&
13908 + hc->qh->dw_align_buf && hc->ep_is_in) {
13909 + memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset,
13910 + hc->qh->dw_align_buf, frame_desc->actual_length);
13911 +
13912 + }
13913 +
13914 + break;
13915 + case DWC_OTG_HC_XFER_FRAME_OVERRUN:
13916 + printk("DWC_OTG_HC_XFER_FRAME_OVERRUN: %d\n", halt_status);
13917 + urb->error_count++;
13918 + if (hc->ep_is_in) {
13919 + frame_desc->status = -ENOSR;
13920 + } else {
13921 + frame_desc->status = -ECOMM;
13922 + }
13923 + frame_desc->actual_length = 0;
13924 + break;
13925 + case DWC_OTG_HC_XFER_BABBLE_ERR:
13926 + printk("DWC_OTG_HC_XFER_BABBLE_ERR: %d\n", halt_status);
13927 + urb->error_count++;
13928 + frame_desc->status = -EOVERFLOW;
13929 + /* Don't need to update actual_length in this case. */
13930 + break;
13931 + case DWC_OTG_HC_XFER_XACT_ERR:
13932 + printk("DWC_OTG_HC_XFER_XACT_ERR: %d\n", halt_status);
13933 + urb->error_count++;
13934 + frame_desc->status = -EPROTO;
13935 + frame_desc->actual_length =
13936 + get_actual_xfer_length(hc, hc_regs, qtd,
13937 + halt_status, NULL);
13938 +
13939 + /* non DWORD-aligned buffer case handling. */
13940 + if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) &&
13941 + hc->qh->dw_align_buf && hc->ep_is_in) {
13942 + memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset,
13943 + hc->qh->dw_align_buf, frame_desc->actual_length);
13944 +
13945 + }
13946 + break;
13947 + default:
13948 +
13949 + DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
13950 + halt_status);
13951 + BUG();
13952 + break;
13953 + }
13954 +
13955 + if (++qtd->isoc_frame_index == urb->number_of_packets) {
13956 + /*
13957 + * urb->status is not used for isoc transfers.
13958 + * The individual frame_desc statuses are used instead.
13959 + */
13960 + dwc_otg_hcd_complete_urb(hcd, urb, 0);
13961 + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
13962 + } else {
13963 + ret_val = DWC_OTG_HC_XFER_COMPLETE;
13964 + }
13965 +
13966 + return ret_val;
13967 +}
13968 +
13969 +/**
13970 + * Releases a host channel for use by other transfers. Attempts to select and
13971 + * queue more transactions since at least one host channel is available.
13972 + *
13973 + * @param hcd The HCD state structure.
13974 + * @param hc The host channel to release.
13975 + * @param qtd The QTD associated with the host channel. This QTD may be freed
13976 + * if the transfer is complete or an error has occurred.
13977 + * @param halt_status Reason the channel is being released. This status
13978 + * determines the actions taken by this function.
13979 + */
13980 +static void release_channel(dwc_otg_hcd_t *hcd,
13981 + dwc_hc_t *hc,
13982 + dwc_otg_qtd_t *qtd,
13983 + dwc_otg_halt_status_e halt_status)
13984 +{
13985 + dwc_otg_transaction_type_e tr_type;
13986 + int free_qtd;
13987 +
13988 + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n",
13989 + __func__, hc->hc_num, halt_status);
13990 +
13991 + switch (halt_status) {
13992 + case DWC_OTG_HC_XFER_URB_COMPLETE:
13993 + free_qtd = 1;
13994 + break;
13995 + case DWC_OTG_HC_XFER_AHB_ERR:
13996 + case DWC_OTG_HC_XFER_STALL:
13997 + case DWC_OTG_HC_XFER_BABBLE_ERR:
13998 + free_qtd = 1;
13999 + break;
14000 + case DWC_OTG_HC_XFER_XACT_ERR:
14001 + if (qtd->error_count >= 3) {
14002 + DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n");
14003 + free_qtd = 1;
14004 + qtd->urb->status = -EPROTO;
14005 + dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO);
14006 + } else {
14007 + free_qtd = 0;
14008 + }
14009 + break;
14010 + case DWC_OTG_HC_XFER_URB_DEQUEUE:
14011 + /*
14012 + * The QTD has already been removed and the QH has been
14013 + * deactivated. Don't want to do anything except release the
14014 + * host channel and try to queue more transfers.
14015 + */
14016 + goto cleanup;
14017 + case DWC_OTG_HC_XFER_NO_HALT_STATUS:
14018 + DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num);
14019 + free_qtd = 0;
14020 + break;
14021 + default:
14022 + free_qtd = 0;
14023 + break;
14024 + }
14025 +
14026 + deactivate_qh(hcd, hc->qh, free_qtd);
14027 +
14028 + cleanup:
14029 + /*
14030 + * Release the host channel for use by other transfers. The cleanup
14031 + * function clears the channel interrupt enables and conditions, so
14032 + * there's no need to clear the Channel Halted interrupt separately.
14033 + */
14034 + dwc_otg_hc_cleanup(hcd->core_if, hc);
14035 + list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list);
14036 +
14037 + switch (hc->ep_type) {
14038 + case DWC_OTG_EP_TYPE_CONTROL:
14039 + case DWC_OTG_EP_TYPE_BULK:
14040 + hcd->non_periodic_channels--;
14041 + break;
14042 +
14043 + default:
14044 + /*
14045 + * Don't release reservations for periodic channels here.
14046 + * That's done when a periodic transfer is descheduled (i.e.
14047 + * when the QH is removed from the periodic schedule).
14048 + */
14049 + break;
14050 + }
14051 +
14052 + /* Try to queue more transfers now that there's a free channel. */
14053 + tr_type = dwc_otg_hcd_select_transactions(hcd);
14054 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
14055 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
14056 + }
14057 +}
14058 +
14059 +/**
14060 + * Halts a host channel. If the channel cannot be halted immediately because
14061 + * the request queue is full, this function ensures that the FIFO empty
14062 + * interrupt for the appropriate queue is enabled so that the halt request can
14063 + * be queued when there is space in the request queue.
14064 + *
14065 + * This function may also be called in DMA mode. In that case, the channel is
14066 + * simply released since the core always halts the channel automatically in
14067 + * DMA mode.
14068 + */
14069 +static void halt_channel(dwc_otg_hcd_t *hcd,
14070 + dwc_hc_t *hc,
14071 + dwc_otg_qtd_t *qtd,
14072 + dwc_otg_halt_status_e halt_status)
14073 +{
14074 + if (hcd->core_if->dma_enable) {
14075 + release_channel(hcd, hc, qtd, halt_status);
14076 + return;
14077 + }
14078 +
14079 + /* Slave mode processing... */
14080 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
14081 +
14082 + if (hc->halt_on_queue) {
14083 + gintmsk_data_t gintmsk = {.d32 = 0};
14084 + dwc_otg_core_global_regs_t *global_regs;
14085 + global_regs = hcd->core_if->core_global_regs;
14086 +
14087 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
14088 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
14089 + /*
14090 + * Make sure the Non-periodic Tx FIFO empty interrupt
14091 + * is enabled so that the non-periodic schedule will
14092 + * be processed.
14093 + */
14094 + gintmsk.b.nptxfempty = 1;
14095 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
14096 + } else {
14097 + /*
14098 + * Move the QH from the periodic queued schedule to
14099 + * the periodic assigned schedule. This allows the
14100 + * halt to be queued when the periodic schedule is
14101 + * processed.
14102 + */
14103 + list_move(&hc->qh->qh_list_entry,
14104 + &hcd->periodic_sched_assigned);
14105 +
14106 + /*
14107 + * Make sure the Periodic Tx FIFO Empty interrupt is
14108 + * enabled so that the periodic schedule will be
14109 + * processed.
14110 + */
14111 + gintmsk.b.ptxfempty = 1;
14112 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
14113 + }
14114 + }
14115 +}
14116 +
14117 +/**
14118 + * Performs common cleanup for non-periodic transfers after a Transfer
14119 + * Complete interrupt. This function should be called after any endpoint type
14120 + * specific handling is finished to release the host channel.
14121 + */
14122 +static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
14123 + dwc_hc_t *hc,
14124 + dwc_otg_hc_regs_t *hc_regs,
14125 + dwc_otg_qtd_t *qtd,
14126 + dwc_otg_halt_status_e halt_status)
14127 +{
14128 + hcint_data_t hcint;
14129 +
14130 + qtd->error_count = 0;
14131 +
14132 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
14133 + if (hcint.b.nyet) {
14134 + /*
14135 + * Got a NYET on the last transaction of the transfer. This
14136 + * means that the endpoint should be in the PING state at the
14137 + * beginning of the next transfer.
14138 + */
14139 + hc->qh->ping_state = 1;
14140 + clear_hc_int(hc_regs, nyet);
14141 + }
14142 +
14143 + /*
14144 + * Always halt and release the host channel to make it available for
14145 + * more transfers. There may still be more phases for a control
14146 + * transfer or more data packets for a bulk transfer at this point,
14147 + * but the host channel is still halted. A channel will be reassigned
14148 + * to the transfer when the non-periodic schedule is processed after
14149 + * the channel is released. This allows transactions to be queued
14150 + * properly via dwc_otg_hcd_queue_transactions, which also enables the
14151 + * Tx FIFO Empty interrupt if necessary.
14152 + */
14153 + if (hc->ep_is_in) {
14154 + /*
14155 + * IN transfers in Slave mode require an explicit disable to
14156 + * halt the channel. (In DMA mode, this call simply releases
14157 + * the channel.)
14158 + */
14159 + halt_channel(hcd, hc, qtd, halt_status);
14160 + } else {
14161 + /*
14162 + * The channel is automatically disabled by the core for OUT
14163 + * transfers in Slave mode.
14164 + */
14165 + release_channel(hcd, hc, qtd, halt_status);
14166 + }
14167 +}
14168 +
14169 +/**
14170 + * Performs common cleanup for periodic transfers after a Transfer Complete
14171 + * interrupt. This function should be called after any endpoint type specific
14172 + * handling is finished to release the host channel.
14173 + */
14174 +static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
14175 + dwc_hc_t *hc,
14176 + dwc_otg_hc_regs_t *hc_regs,
14177 + dwc_otg_qtd_t *qtd,
14178 + dwc_otg_halt_status_e halt_status)
14179 +{
14180 + hctsiz_data_t hctsiz;
14181 + qtd->error_count = 0;
14182 +
14183 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14184 + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
14185 + /* Core halts channel in these cases. */
14186 + release_channel(hcd, hc, qtd, halt_status);
14187 + } else {
14188 + /* Flush any outstanding requests from the Tx queue. */
14189 + halt_channel(hcd, hc, qtd, halt_status);
14190 + }
14191 +}
14192 +
14193 +/**
14194 + * Handles a host channel Transfer Complete interrupt. This handler may be
14195 + * called in either DMA mode or Slave mode.
14196 + */
14197 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
14198 + dwc_hc_t *hc,
14199 + dwc_otg_hc_regs_t *hc_regs,
14200 + dwc_otg_qtd_t *qtd)
14201 +{
14202 + int urb_xfer_done;
14203 + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
14204 + struct urb *urb = qtd->urb;
14205 + int pipe_type = usb_pipetype(urb->pipe);
14206 +
14207 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14208 + "Transfer Complete--\n", hc->hc_num);
14209 +
14210 + /*
14211 + * Handle xfer complete on CSPLIT.
14212 + */
14213 + if (hc->qh->do_split) {
14214 + qtd->complete_split = 0;
14215 + }
14216 +
14217 + /* Update the QTD and URB states. */
14218 + switch (pipe_type) {
14219 + case PIPE_CONTROL:
14220 + switch (qtd->control_phase) {
14221 + case DWC_OTG_CONTROL_SETUP:
14222 + if (urb->transfer_buffer_length > 0) {
14223 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
14224 + } else {
14225 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
14226 + }
14227 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
14228 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
14229 + break;
14230 + case DWC_OTG_CONTROL_DATA: {
14231 + urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
14232 + if (urb_xfer_done) {
14233 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
14234 + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
14235 + } else {
14236 + save_data_toggle(hc, hc_regs, qtd);
14237 + }
14238 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
14239 + break;
14240 + }
14241 + case DWC_OTG_CONTROL_STATUS:
14242 + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
14243 + if (urb->status == -EINPROGRESS) {
14244 + urb->status = 0;
14245 + }
14246 + dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
14247 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
14248 + break;
14249 + }
14250 +
14251 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
14252 + break;
14253 + case PIPE_BULK:
14254 + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
14255 + urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
14256 + if (urb_xfer_done) {
14257 + dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
14258 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
14259 + } else {
14260 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
14261 + }
14262 +
14263 + save_data_toggle(hc, hc_regs, qtd);
14264 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
14265 + break;
14266 + case PIPE_INTERRUPT:
14267 + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
14268 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
14269 +
14270 + /*
14271 + * Interrupt URB is done on the first transfer complete
14272 + * interrupt.
14273 + */
14274 + dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
14275 + save_data_toggle(hc, hc_regs, qtd);
14276 + complete_periodic_xfer(hcd, hc, hc_regs, qtd,
14277 + DWC_OTG_HC_XFER_URB_COMPLETE);
14278 + break;
14279 + case PIPE_ISOCHRONOUS:
14280 + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
14281 + if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
14282 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14283 + DWC_OTG_HC_XFER_COMPLETE);
14284 + }
14285 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
14286 + break;
14287 + }
14288 +
14289 + disable_hc_int(hc_regs, xfercompl);
14290 +
14291 + return 1;
14292 +}
14293 +
14294 +/**
14295 + * Handles a host channel STALL interrupt. This handler may be called in
14296 + * either DMA mode or Slave mode.
14297 + */
14298 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
14299 + dwc_hc_t *hc,
14300 + dwc_otg_hc_regs_t *hc_regs,
14301 + dwc_otg_qtd_t *qtd)
14302 +{
14303 + struct urb *urb = qtd->urb;
14304 + int pipe_type = usb_pipetype(urb->pipe);
14305 +
14306 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14307 + "STALL Received--\n", hc->hc_num);
14308 +
14309 + if (pipe_type == PIPE_CONTROL) {
14310 + dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
14311 + }
14312 +
14313 + if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
14314 + dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
14315 + /*
14316 + * USB protocol requires resetting the data toggle for bulk
14317 + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
14318 + * setup command is issued to the endpoint. Anticipate the
14319 + * CLEAR_FEATURE command since a STALL has occurred and reset
14320 + * the data toggle now.
14321 + */
14322 + hc->qh->data_toggle = 0;
14323 + }
14324 +
14325 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
14326 +
14327 + disable_hc_int(hc_regs, stall);
14328 +
14329 + return 1;
14330 +}
14331 +
14332 +/*
14333 + * Updates the state of the URB when a transfer has been stopped due to an
14334 + * abnormal condition before the transfer completes. Modifies the
14335 + * actual_length field of the URB to reflect the number of bytes that have
14336 + * actually been transferred via the host channel.
14337 + */
14338 +static void update_urb_state_xfer_intr(dwc_hc_t *hc,
14339 + dwc_otg_hc_regs_t *hc_regs,
14340 + struct urb *urb,
14341 + dwc_otg_qtd_t *qtd,
14342 + dwc_otg_halt_status_e halt_status)
14343 +{
14344 + uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
14345 + halt_status, NULL);
14346 + urb->actual_length += bytes_transferred;
14347 +
14348 +#ifdef DEBUG
14349 + {
14350 + hctsiz_data_t hctsiz;
14351 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14352 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
14353 + __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
14354 + DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", hc->start_pkt_count);
14355 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
14356 + DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
14357 + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred);
14358 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
14359 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
14360 + urb->transfer_buffer_length);
14361 + }
14362 +#endif
14363 +}
14364 +
14365 +/**
14366 + * Handles a host channel NAK interrupt. This handler may be called in either
14367 + * DMA mode or Slave mode.
14368 + */
14369 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
14370 + dwc_hc_t *hc,
14371 + dwc_otg_hc_regs_t *hc_regs,
14372 + dwc_otg_qtd_t *qtd)
14373 +{
14374 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14375 + "NAK Received--\n", hc->hc_num);
14376 +
14377 + /*
14378 + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
14379 + * interrupt. Re-start the SSPLIT transfer.
14380 + */
14381 + if (hc->do_split) {
14382 + if (hc->complete_split) {
14383 + qtd->error_count = 0;
14384 + }
14385 + qtd->complete_split = 0;
14386 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
14387 + goto handle_nak_done;
14388 + }
14389 +
14390 + switch (usb_pipetype(qtd->urb->pipe)) {
14391 + case PIPE_CONTROL:
14392 + case PIPE_BULK:
14393 + if (hcd->core_if->dma_enable && hc->ep_is_in) {
14394 + /*
14395 + * NAK interrupts are enabled on bulk/control IN
14396 + * transfers in DMA mode for the sole purpose of
14397 + * resetting the error count after a transaction error
14398 + * occurs. The core will continue transferring data.
14399 + */
14400 + qtd->error_count = 0;
14401 + goto handle_nak_done;
14402 + }
14403 +
14404 + /*
14405 + * NAK interrupts normally occur during OUT transfers in DMA
14406 + * or Slave mode. For IN transfers, more requests will be
14407 + * queued as request queue space is available.
14408 + */
14409 + qtd->error_count = 0;
14410 +
14411 + if (!hc->qh->ping_state) {
14412 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
14413 + qtd, DWC_OTG_HC_XFER_NAK);
14414 + save_data_toggle(hc, hc_regs, qtd);
14415 + if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
14416 + hc->qh->ping_state = 1;
14417 + }
14418 + }
14419 +
14420 + /*
14421 + * Halt the channel so the transfer can be re-started from
14422 + * the appropriate point or the PING protocol will
14423 + * start/continue.
14424 + */
14425 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
14426 + break;
14427 + case PIPE_INTERRUPT:
14428 + qtd->error_count = 0;
14429 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
14430 + break;
14431 + case PIPE_ISOCHRONOUS:
14432 + /* Should never get called for isochronous transfers. */
14433 + BUG();
14434 + break;
14435 + }
14436 +
14437 + handle_nak_done:
14438 + disable_hc_int(hc_regs, nak);
14439 +
14440 + return 1;
14441 +}
14442 +
14443 +/**
14444 + * Handles a host channel ACK interrupt. This interrupt is enabled when
14445 + * performing the PING protocol in Slave mode, when errors occur during
14446 + * either Slave mode or DMA mode, and during Start Split transactions.
14447 + */
14448 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
14449 + dwc_hc_t *hc,
14450 + dwc_otg_hc_regs_t *hc_regs,
14451 + dwc_otg_qtd_t *qtd)
14452 +{
14453 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14454 + "ACK Received--\n", hc->hc_num);
14455 +
14456 + if (hc->do_split) {
14457 + /*
14458 + * Handle ACK on SSPLIT.
14459 + * ACK should not occur in CSPLIT.
14460 + */
14461 + if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
14462 + qtd->ssplit_out_xfer_count = hc->xfer_len;
14463 + }
14464 + if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
14465 + /* Don't need complete for isochronous out transfers. */
14466 + qtd->complete_split = 1;
14467 + }
14468 +
14469 + /* ISOC OUT */
14470 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
14471 + switch (hc->xact_pos) {
14472 + case DWC_HCSPLIT_XACTPOS_ALL:
14473 + break;
14474 + case DWC_HCSPLIT_XACTPOS_END:
14475 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
14476 + qtd->isoc_split_offset = 0;
14477 + break;
14478 + case DWC_HCSPLIT_XACTPOS_BEGIN:
14479 + case DWC_HCSPLIT_XACTPOS_MID:
14480 + /*
14481 + * For BEGIN or MID, calculate the length for
14482 + * the next microframe to determine the correct
14483 + * SSPLIT token, either MID or END.
14484 + */
14485 + {
14486 + struct usb_iso_packet_descriptor *frame_desc;
14487 +
14488 + frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index];
14489 + qtd->isoc_split_offset += 188;
14490 +
14491 + if ((frame_desc->length - qtd->isoc_split_offset) <= 188) {
14492 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
14493 + } else {
14494 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
14495 + }
14496 +
14497 + }
14498 + break;
14499 + }
14500 + } else {
14501 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
14502 + }
14503 + } else {
14504 + qtd->error_count = 0;
14505 +
14506 + if (hc->qh->ping_state) {
14507 + hc->qh->ping_state = 0;
14508 + /*
14509 + * Halt the channel so the transfer can be re-started
14510 + * from the appropriate point. This only happens in
14511 + * Slave mode. In DMA mode, the ping_state is cleared
14512 + * when the transfer is started because the core
14513 + * automatically executes the PING, then the transfer.
14514 + */
14515 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
14516 + }
14517 + }
14518 +
14519 + /*
14520 + * If the ACK occurred when _not_ in the PING state, let the channel
14521 + * continue transferring data after clearing the error count.
14522 + */
14523 +
14524 + disable_hc_int(hc_regs, ack);
14525 +
14526 + return 1;
14527 +}
14528 +
14529 +/**
14530 + * Handles a host channel NYET interrupt. This interrupt should only occur on
14531 + * Bulk and Control OUT endpoints and for complete split transactions. If a
14532 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
14533 + * handled in the xfercomp interrupt handler, not here. This handler may be
14534 + * called in either DMA mode or Slave mode.
14535 + */
14536 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
14537 + dwc_hc_t *hc,
14538 + dwc_otg_hc_regs_t *hc_regs,
14539 + dwc_otg_qtd_t *qtd)
14540 +{
14541 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14542 + "NYET Received--\n", hc->hc_num);
14543 +
14544 + /*
14545 + * NYET on CSPLIT
14546 + * re-do the CSPLIT immediately on non-periodic
14547 + */
14548 + if (hc->do_split && hc->complete_split) {
14549 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
14550 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
14551 + int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
14552 +
14553 + if (dwc_full_frame_num(frnum) !=
14554 + dwc_full_frame_num(hc->qh->sched_frame)) {
14555 + /*
14556 + * No longer in the same full speed frame.
14557 + * Treat this as a transaction error.
14558 + */
14559 +#if 0
14560 + /** @todo Fix system performance so this can
14561 + * be treated as an error. Right now complete
14562 + * splits cannot be scheduled precisely enough
14563 + * due to other system activity, so this error
14564 + * occurs regularly in Slave mode.
14565 + */
14566 + qtd->error_count++;
14567 +#endif
14568 + qtd->complete_split = 0;
14569 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
14570 + /** @todo add support for isoc release */
14571 + goto handle_nyet_done;
14572 + }
14573 + }
14574 +
14575 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
14576 + goto handle_nyet_done;
14577 + }
14578 +
14579 + hc->qh->ping_state = 1;
14580 + qtd->error_count = 0;
14581 +
14582 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
14583 + DWC_OTG_HC_XFER_NYET);
14584 + save_data_toggle(hc, hc_regs, qtd);
14585 +
14586 + /*
14587 + * Halt the channel and re-start the transfer so the PING
14588 + * protocol will start.
14589 + */
14590 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
14591 +
14592 +handle_nyet_done:
14593 + disable_hc_int(hc_regs, nyet);
14594 + return 1;
14595 +}
14596 +
14597 +/**
14598 + * Handles a host channel babble interrupt. This handler may be called in
14599 + * either DMA mode or Slave mode.
14600 + */
14601 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
14602 + dwc_hc_t *hc,
14603 + dwc_otg_hc_regs_t *hc_regs,
14604 + dwc_otg_qtd_t *qtd)
14605 +{
14606 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14607 + "Babble Error--\n", hc->hc_num);
14608 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
14609 + dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW);
14610 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
14611 + } else {
14612 + dwc_otg_halt_status_e halt_status;
14613 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14614 + DWC_OTG_HC_XFER_BABBLE_ERR);
14615 + halt_channel(hcd, hc, qtd, halt_status);
14616 + }
14617 + disable_hc_int(hc_regs, bblerr);
14618 + return 1;
14619 +}
14620 +
14621 +/**
14622 + * Handles a host channel AHB error interrupt. This handler is only called in
14623 + * DMA mode.
14624 + */
14625 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
14626 + dwc_hc_t *hc,
14627 + dwc_otg_hc_regs_t *hc_regs,
14628 + dwc_otg_qtd_t *qtd)
14629 +{
14630 + hcchar_data_t hcchar;
14631 + hcsplt_data_t hcsplt;
14632 + hctsiz_data_t hctsiz;
14633 + uint32_t hcdma;
14634 + struct urb *urb = qtd->urb;
14635 +
14636 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14637 + "AHB Error--\n", hc->hc_num);
14638 +
14639 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
14640 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
14641 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14642 + hcdma = dwc_read_reg32(&hc_regs->hcdma);
14643 +
14644 + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
14645 + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
14646 + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
14647 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
14648 + DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe));
14649 + DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
14650 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
14651 + DWC_ERROR(" Endpoint type: %s\n",
14652 + ({char *pipetype;
14653 + switch (usb_pipetype(urb->pipe)) {
14654 + case PIPE_CONTROL: pipetype = "CONTROL"; break;
14655 + case PIPE_BULK: pipetype = "BULK"; break;
14656 + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
14657 + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
14658 + default: pipetype = "UNKNOWN"; break;
14659 + }; pipetype;}));
14660 + DWC_ERROR(" Speed: %s\n",
14661 + ({char *speed;
14662 + switch (urb->dev->speed) {
14663 + case USB_SPEED_HIGH: speed = "HIGH"; break;
14664 + case USB_SPEED_FULL: speed = "FULL"; break;
14665 + case USB_SPEED_LOW: speed = "LOW"; break;
14666 + default: speed = "UNKNOWN"; break;
14667 + }; speed;}));
14668 + DWC_ERROR(" Max packet size: %d\n",
14669 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
14670 + DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length);
14671 + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
14672 + urb->transfer_buffer, (void *)urb->transfer_dma);
14673 + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
14674 + urb->setup_packet, (void *)urb->setup_dma);
14675 + DWC_ERROR(" Interval: %d\n", urb->interval);
14676 +
14677 + dwc_otg_hcd_complete_urb(hcd, urb, -EIO);
14678 +
14679 + /*
14680 + * Force a channel halt. Don't call halt_channel because that won't
14681 + * write to the HCCHARn register in DMA mode to force the halt.
14682 + */
14683 + dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
14684 +
14685 + disable_hc_int(hc_regs, ahberr);
14686 + return 1;
14687 +}
14688 +
14689 +/**
14690 + * Handles a host channel transaction error interrupt. This handler may be
14691 + * called in either DMA mode or Slave mode.
14692 + */
14693 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
14694 + dwc_hc_t *hc,
14695 + dwc_otg_hc_regs_t *hc_regs,
14696 + dwc_otg_qtd_t *qtd)
14697 +{
14698 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14699 + "Transaction Error--\n", hc->hc_num);
14700 +
14701 + switch (usb_pipetype(qtd->urb->pipe)) {
14702 + case PIPE_CONTROL:
14703 + case PIPE_BULK:
14704 + qtd->error_count++;
14705 + if (!hc->qh->ping_state) {
14706 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
14707 + qtd, DWC_OTG_HC_XFER_XACT_ERR);
14708 + save_data_toggle(hc, hc_regs, qtd);
14709 + if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) {
14710 + hc->qh->ping_state = 1;
14711 + }
14712 + }
14713 +
14714 + /*
14715 + * Halt the channel so the transfer can be re-started from
14716 + * the appropriate point or the PING protocol will start.
14717 + */
14718 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
14719 + break;
14720 + case PIPE_INTERRUPT:
14721 + qtd->error_count++;
14722 + if (hc->do_split && hc->complete_split) {
14723 + qtd->complete_split = 0;
14724 + }
14725 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
14726 + break;
14727 + case PIPE_ISOCHRONOUS:
14728 + {
14729 + dwc_otg_halt_status_e halt_status;
14730 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14731 + DWC_OTG_HC_XFER_XACT_ERR);
14732 +
14733 + halt_channel(hcd, hc, qtd, halt_status);
14734 + }
14735 + break;
14736 + }
14737 +
14738 + disable_hc_int(hc_regs, xacterr);
14739 +
14740 + return 1;
14741 +}
14742 +
14743 +/**
14744 + * Handles a host channel frame overrun interrupt. This handler may be called
14745 + * in either DMA mode or Slave mode.
14746 + */
14747 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
14748 + dwc_hc_t *hc,
14749 + dwc_otg_hc_regs_t *hc_regs,
14750 + dwc_otg_qtd_t *qtd)
14751 +{
14752 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14753 + "Frame Overrun--\n", hc->hc_num);
14754 +
14755 + switch (usb_pipetype(qtd->urb->pipe)) {
14756 + case PIPE_CONTROL:
14757 + case PIPE_BULK:
14758 + break;
14759 + case PIPE_INTERRUPT:
14760 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
14761 + break;
14762 + case PIPE_ISOCHRONOUS:
14763 + {
14764 + dwc_otg_halt_status_e halt_status;
14765 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
14766 + DWC_OTG_HC_XFER_FRAME_OVERRUN);
14767 +
14768 + halt_channel(hcd, hc, qtd, halt_status);
14769 + }
14770 + break;
14771 + }
14772 +
14773 + disable_hc_int(hc_regs, frmovrun);
14774 +
14775 + return 1;
14776 +}
14777 +
14778 +/**
14779 + * Handles a host channel data toggle error interrupt. This handler may be
14780 + * called in either DMA mode or Slave mode.
14781 + */
14782 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
14783 + dwc_hc_t *hc,
14784 + dwc_otg_hc_regs_t *hc_regs,
14785 + dwc_otg_qtd_t *qtd)
14786 +{
14787 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
14788 + "Data Toggle Error--\n", hc->hc_num);
14789 +
14790 + if (hc->ep_is_in) {
14791 + qtd->error_count = 0;
14792 + } else {
14793 + DWC_ERROR("Data Toggle Error on OUT transfer,"
14794 + "channel %d\n", hc->hc_num);
14795 + }
14796 +
14797 + disable_hc_int(hc_regs, datatglerr);
14798 +
14799 + return 1;
14800 +}
14801 +
14802 +#ifdef DEBUG
14803 +/**
14804 + * This function is for debug only. It checks that a valid halt status is set
14805 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
14806 + * taken and a warning is issued.
14807 + * @return 1 if halt status is ok, 0 otherwise.
14808 + */
14809 +static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
14810 + dwc_hc_t *hc,
14811 + dwc_otg_hc_regs_t *hc_regs,
14812 + dwc_otg_qtd_t *qtd)
14813 +{
14814 + hcchar_data_t hcchar;
14815 + hctsiz_data_t hctsiz;
14816 + hcint_data_t hcint;
14817 + hcintmsk_data_t hcintmsk;
14818 + hcsplt_data_t hcsplt;
14819 +
14820 + if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
14821 + /*
14822 + * This code is here only as a check. This condition should
14823 + * never happen. Ignore the halt if it does occur.
14824 + */
14825 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
14826 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
14827 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
14828 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
14829 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
14830 + DWC_WARN("%s: hc->halt_status == DWC_OTG"
14831 + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
14832 + "hcint 0x%08x, hcintmsk 0x%08x, "
14833 + "hcsplt 0x%08x, qtd->complete_split %d\n",
14834 + __func__, hc->hc_num, hcchar.d32, hctsiz.d32,
14835 + hcint.d32, hcintmsk.d32,
14836 + hcsplt.d32, qtd->complete_split);
14837 +
14838 + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
14839 + __func__, hc->hc_num);
14840 + DWC_WARN("\n");
14841 + clear_hc_int(hc_regs, chhltd);
14842 + return 0;
14843 + }
14844 +
14845 + /*
14846 + * This code is here only as a check. hcchar.chdis should
14847 + * never be set when the halt interrupt occurs. Halt the
14848 + * channel again if it does occur.
14849 + */
14850 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
14851 + if (hcchar.b.chdis) {
14852 + DWC_WARN("%s: hcchar.chdis set unexpectedly, "
14853 + "hcchar 0x%08x, trying to halt again\n",
14854 + __func__, hcchar.d32);
14855 + clear_hc_int(hc_regs, chhltd);
14856 + hc->halt_pending = 0;
14857 + halt_channel(hcd, hc, qtd, hc->halt_status);
14858 + return 0;
14859 + }
14860 +
14861 + return 1;
14862 +}
14863 +#endif
14864 +
14865 +/**
14866 + * Handles a host Channel Halted interrupt in DMA mode. This handler
14867 + * determines the reason the channel halted and proceeds accordingly.
14868 + */
14869 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
14870 + dwc_hc_t *hc,
14871 + dwc_otg_hc_regs_t *hc_regs,
14872 + dwc_otg_qtd_t *qtd)
14873 +{
14874 + hcint_data_t hcint;
14875 + hcintmsk_data_t hcintmsk;
14876 + int out_nak_enh = 0;
14877 +
14878 + /* For core with OUT NAK enhancement, the flow for high-
14879 + * speed CONTROL/BULK OUT is handled a little differently.
14880 + */
14881 + if (hcd->core_if->snpsid >= 0x4F54271A) {
14882 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
14883 + (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
14884 + hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
14885 + printk(KERN_DEBUG "OUT NAK enhancement enabled\n");
14886 + out_nak_enh = 1;
14887 + } else {
14888 + printk(KERN_DEBUG "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
14889 + }
14890 + } else {
14891 +// printk(KERN_DEBUG "OUT NAK enhancement disabled, no core support\n");
14892 + }
14893 +
14894 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
14895 + hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
14896 + /*
14897 + * Just release the channel. A dequeue can happen on a
14898 + * transfer timeout. In the case of an AHB Error, the channel
14899 + * was forced to halt because there's no way to gracefully
14900 + * recover.
14901 + */
14902 + release_channel(hcd, hc, qtd, hc->halt_status);
14903 + return;
14904 + }
14905 +
14906 + /* Read the HCINTn register to determine the cause for the halt. */
14907 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
14908 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
14909 +
14910 + if (hcint.b.xfercomp) {
14911 + /** @todo This is here because of a possible hardware bug. Spec
14912 + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
14913 + * interrupt w/ACK bit set should occur, but I only see the
14914 + * XFERCOMP bit, even with it masked out. This is a workaround
14915 + * for that behavior. Should fix this when hardware is fixed.
14916 + */
14917 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
14918 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
14919 + }
14920 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
14921 + } else if (hcint.b.stall) {
14922 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
14923 + } else if (hcint.b.xacterr) {
14924 + if (out_nak_enh) {
14925 + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
14926 + printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
14927 + qtd->error_count = 0;
14928 + } else {
14929 + printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
14930 + }
14931 + }
14932 +
14933 + /*
14934 + * Must handle xacterr before nak or ack. Could get a xacterr
14935 + * at the same time as either of these on a BULK/CONTROL OUT
14936 + * that started with a PING. The xacterr takes precedence.
14937 + */
14938 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
14939 + } else if (!out_nak_enh) {
14940 + if (hcint.b.nyet) {
14941 + /*
14942 + * Must handle nyet before nak or ack. Could get a nyet at the
14943 + * same time as either of those on a BULK/CONTROL OUT that
14944 + * started with a PING. The nyet takes precedence.
14945 + */
14946 + handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
14947 + } else if (hcint.b.bblerr) {
14948 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
14949 + } else if (hcint.b.frmovrun) {
14950 + handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
14951 + } else if (hcint.b.nak && !hcintmsk.b.nak) {
14952 + /*
14953 + * If nak is not masked, it's because a non-split IN transfer
14954 + * is in an error state. In that case, the nak is handled by
14955 + * the nak interrupt handler, not here. Handle nak here for
14956 + * BULK/CONTROL OUT transfers, which halt on a NAK to allow
14957 + * rewinding the buffer pointer.
14958 + */
14959 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
14960 + } else if (hcint.b.ack && !hcintmsk.b.ack) {
14961 + /*
14962 + * If ack is not masked, it's because a non-split IN transfer
14963 + * is in an error state. In that case, the ack is handled by
14964 + * the ack interrupt handler, not here. Handle ack here for
14965 + * split transfers. Start splits halt on ACK.
14966 + */
14967 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
14968 + } else {
14969 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
14970 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
14971 + /*
14972 + * A periodic transfer halted with no other channel
14973 + * interrupts set. Assume it was halted by the core
14974 + * because it could not be completed in its scheduled
14975 + * (micro)frame.
14976 + */
14977 +#ifdef DEBUG
14978 + DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
14979 + __func__, hc->hc_num);
14980 +#endif
14981 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
14982 + } else {
14983 + DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
14984 + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
14985 + __func__, hc->hc_num, hcint.d32,
14986 + dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
14987 + }
14988 + }
14989 + } else {
14990 + printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
14991 + }
14992 +}
14993 +
14994 +/**
14995 + * Handles a host channel Channel Halted interrupt.
14996 + *
14997 + * In slave mode, this handler is called only when the driver specifically
14998 + * requests a halt. This occurs during handling other host channel interrupts
14999 + * (e.g. nak, xacterr, stall, nyet, etc.).
15000 + *
15001 + * In DMA mode, this is the interrupt that occurs when the core has finished
15002 + * processing a transfer on a channel. Other host channel interrupts (except
15003 + * ahberr) are disabled in DMA mode.
15004 + */
15005 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
15006 + dwc_hc_t *hc,
15007 + dwc_otg_hc_regs_t *hc_regs,
15008 + dwc_otg_qtd_t *qtd)
15009 +{
15010 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
15011 + "Channel Halted--\n", hc->hc_num);
15012 +
15013 + if (hcd->core_if->dma_enable) {
15014 + handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
15015 + } else {
15016 +#ifdef DEBUG
15017 + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
15018 + return 1;
15019 + }
15020 +#endif
15021 + release_channel(hcd, hc, qtd, hc->halt_status);
15022 + }
15023 +
15024 + return 1;
15025 +}
15026 +
15027 +/** Handles interrupt for a specific Host Channel */
15028 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
15029 +{
15030 + int retval = 0;
15031 + hcint_data_t hcint;
15032 + hcintmsk_data_t hcintmsk;
15033 + dwc_hc_t *hc;
15034 + dwc_otg_hc_regs_t *hc_regs;
15035 + dwc_otg_qtd_t *qtd;
15036 +
15037 + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
15038 +
15039 + hc = dwc_otg_hcd->hc_ptr_array[num];
15040 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
15041 + qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
15042 +
15043 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
15044 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
15045 + DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
15046 + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
15047 + hcint.d32 = hcint.d32 & hcintmsk.d32;
15048 +
15049 + if (!dwc_otg_hcd->core_if->dma_enable) {
15050 + if (hcint.b.chhltd && hcint.d32 != 0x2) {
15051 + hcint.b.chhltd = 0;
15052 + }
15053 + }
15054 +
15055 + if (hcint.b.xfercomp) {
15056 + retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15057 + /*
15058 + * If NYET occurred at same time as Xfer Complete, the NYET is
15059 + * handled by the Xfer Complete interrupt handler. Don't want
15060 + * to call the NYET interrupt handler in this case.
15061 + */
15062 + hcint.b.nyet = 0;
15063 + }
15064 + if (hcint.b.chhltd) {
15065 + retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15066 + }
15067 + if (hcint.b.ahberr) {
15068 + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15069 + }
15070 + if (hcint.b.stall) {
15071 + retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15072 + }
15073 + if (hcint.b.nak) {
15074 + retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15075 + }
15076 + if (hcint.b.ack) {
15077 + retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15078 + }
15079 + if (hcint.b.nyet) {
15080 + retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15081 + }
15082 + if (hcint.b.xacterr) {
15083 + retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15084 + }
15085 + if (hcint.b.bblerr) {
15086 + retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15087 + }
15088 + if (hcint.b.frmovrun) {
15089 + retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15090 + }
15091 + if (hcint.b.datatglerr) {
15092 + retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
15093 + }
15094 +
15095 + return retval;
15096 +}
15097 +
15098 +#endif /* DWC_DEVICE_ONLY */
15099 diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
15100 new file mode 100644
15101 index 0000000..cfb1f16
15102 --- /dev/null
15103 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
15104 @@ -0,0 +1,684 @@
15105 +/* ==========================================================================
15106 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
15107 + * $Revision: 1.5 $
15108 + * $Date: 2008-12-15 06:51:32 $
15109 + * $Change: 537387 $
15110 + *
15111 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
15112 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
15113 + * otherwise expressly agreed to in writing between Synopsys and you.
15114 + *
15115 + * The Software IS NOT an item of Licensed Software or Licensed Product under
15116 + * any End User Software License Agreement or Agreement for Licensed Product
15117 + * with Synopsys or any supplement thereto. You are permitted to use and
15118 + * redistribute this Software in source and binary forms, with or without
15119 + * modification, provided that redistributions of source code must retain this
15120 + * notice. You may not view, use, disclose, copy or distribute this file or
15121 + * any information contained herein except pursuant to this license grant from
15122 + * Synopsys. If you do not agree with this notice, including the disclaimer
15123 + * below, then you are not authorized to use the Software.
15124 + *
15125 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
15126 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15127 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15128 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
15129 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15130 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
15131 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
15132 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
15133 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15134 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
15135 + * DAMAGE.
15136 + * ========================================================================== */
15137 +#ifndef DWC_DEVICE_ONLY
15138 +
15139 +/**
15140 + * @file
15141 + *
15142 + * This file contains the functions to manage Queue Heads and Queue
15143 + * Transfer Descriptors.
15144 + */
15145 +#include <linux/kernel.h>
15146 +#include <linux/module.h>
15147 +#include <linux/moduleparam.h>
15148 +#include <linux/init.h>
15149 +#include <linux/device.h>
15150 +#include <linux/errno.h>
15151 +#include <linux/list.h>
15152 +#include <linux/interrupt.h>
15153 +#include <linux/string.h>
15154 +#include <linux/dma-mapping.h>
15155 +
15156 +#include "dwc_otg_driver.h"
15157 +#include "dwc_otg_hcd.h"
15158 +#include "dwc_otg_regs.h"
15159 +
15160 +/**
15161 + * This function allocates and initializes a QH.
15162 + *
15163 + * @param hcd The HCD state structure for the DWC OTG controller.
15164 + * @param[in] urb Holds the information about the device/endpoint that we need
15165 + * to initialize the QH.
15166 + *
15167 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
15168 +dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
15169 +{
15170 + dwc_otg_qh_t *qh;
15171 +
15172 + /* Allocate memory */
15173 + /** @todo add memflags argument */
15174 + qh = dwc_otg_hcd_qh_alloc ();
15175 + if (qh == NULL) {
15176 + return NULL;
15177 + }
15178 +
15179 + dwc_otg_hcd_qh_init (hcd, qh, urb);
15180 + return qh;
15181 +}
15182 +
15183 +/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
15184 + * removed from a list. QTD list should already be empty if called from URB
15185 + * Dequeue.
15186 + *
15187 + * @param[in] hcd HCD instance.
15188 + * @param[in] qh The QH to free.
15189 + */
15190 +void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15191 +{
15192 + dwc_otg_qtd_t *qtd;
15193 + struct list_head *pos;
15194 + unsigned long flags;
15195 +
15196 + /* Free each QTD in the QTD list */
15197 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
15198 + for (pos = qh->qtd_list.next;
15199 + pos != &qh->qtd_list;
15200 + pos = qh->qtd_list.next)
15201 + {
15202 + list_del (pos);
15203 + qtd = dwc_list_to_qtd (pos);
15204 + dwc_otg_hcd_qtd_free (qtd);
15205 + }
15206 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
15207 +
15208 + if (qh->dw_align_buf) {
15209 + dma_free_coherent((dwc_otg_hcd_to_hcd(hcd))->self.controller,
15210 + hcd->core_if->core_params->max_transfer_size,
15211 + qh->dw_align_buf,
15212 + qh->dw_align_buf_dma);
15213 + }
15214 +
15215 + kfree (qh);
15216 + return;
15217 +}
15218 +
15219 +/** Initializes a QH structure.
15220 + *
15221 + * @param[in] hcd The HCD state structure for the DWC OTG controller.
15222 + * @param[in] qh The QH to init.
15223 + * @param[in] urb Holds the information about the device/endpoint that we need
15224 + * to initialize the QH. */
15225 +#define SCHEDULE_SLOP 10
15226 +void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
15227 +{
15228 + char *speed, *type;
15229 + memset (qh, 0, sizeof (dwc_otg_qh_t));
15230 +
15231 + /* Initialize QH */
15232 + switch (usb_pipetype(urb->pipe)) {
15233 + case PIPE_CONTROL:
15234 + qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
15235 + break;
15236 + case PIPE_BULK:
15237 + qh->ep_type = USB_ENDPOINT_XFER_BULK;
15238 + break;
15239 + case PIPE_ISOCHRONOUS:
15240 + qh->ep_type = USB_ENDPOINT_XFER_ISOC;
15241 + break;
15242 + case PIPE_INTERRUPT:
15243 + qh->ep_type = USB_ENDPOINT_XFER_INT;
15244 + break;
15245 + }
15246 +
15247 + qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
15248 +
15249 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
15250 + qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
15251 + INIT_LIST_HEAD(&qh->qtd_list);
15252 + INIT_LIST_HEAD(&qh->qh_list_entry);
15253 + qh->channel = NULL;
15254 +
15255 + /* FS/LS Enpoint on HS Hub
15256 + * NOT virtual root hub */
15257 + qh->do_split = 0;
15258 + if (((urb->dev->speed == USB_SPEED_LOW) ||
15259 + (urb->dev->speed == USB_SPEED_FULL)) &&
15260 + (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
15261 + {
15262 + DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
15263 + usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
15264 + urb->dev->ttport);
15265 + qh->do_split = 1;
15266 + }
15267 +
15268 + if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
15269 + qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
15270 + /* Compute scheduling parameters once and save them. */
15271 + hprt0_data_t hprt;
15272 +
15273 + /** @todo Account for split transfers in the bus time. */
15274 + int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
15275 +
15276 + /* FIXME: work-around patch by Steven */
15277 + qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
15278 + usb_pipein(urb->pipe),
15279 + (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
15280 + bytecount));
15281 +
15282 + /* Start in a slightly future (micro)frame. */
15283 + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
15284 + SCHEDULE_SLOP);
15285 + qh->interval = urb->interval;
15286 +#if 0
15287 + /* Increase interrupt polling rate for debugging. */
15288 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15289 + qh->interval = 8;
15290 + }
15291 +#endif
15292 + hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
15293 + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
15294 + ((urb->dev->speed == USB_SPEED_LOW) ||
15295 + (urb->dev->speed == USB_SPEED_FULL))) {
15296 + qh->interval *= 8;
15297 + qh->sched_frame |= 0x7;
15298 + qh->start_split_frame = qh->sched_frame;
15299 + }
15300 +
15301 + }
15302 +
15303 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
15304 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
15305 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
15306 + urb->dev->devnum);
15307 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
15308 + usb_pipeendpoint(urb->pipe),
15309 + usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
15310 +
15311 + switch(urb->dev->speed) {
15312 + case USB_SPEED_LOW:
15313 + speed = "low";
15314 + break;
15315 + case USB_SPEED_FULL:
15316 + speed = "full";
15317 + break;
15318 + case USB_SPEED_HIGH:
15319 + speed = "high";
15320 + break;
15321 + default:
15322 + speed = "?";
15323 + break;
15324 + }
15325 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
15326 +
15327 + switch (qh->ep_type) {
15328 + case USB_ENDPOINT_XFER_ISOC:
15329 + type = "isochronous";
15330 + break;
15331 + case USB_ENDPOINT_XFER_INT:
15332 + type = "interrupt";
15333 + break;
15334 + case USB_ENDPOINT_XFER_CONTROL:
15335 + type = "control";
15336 + break;
15337 + case USB_ENDPOINT_XFER_BULK:
15338 + type = "bulk";
15339 + break;
15340 + default:
15341 + type = "?";
15342 + break;
15343 + }
15344 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type);
15345 +
15346 +#ifdef DEBUG
15347 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15348 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
15349 + qh->usecs);
15350 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
15351 + qh->interval);
15352 + }
15353 +#endif
15354 + qh->dw_align_buf = NULL;
15355 + return;
15356 +}
15357 +
15358 +/**
15359 + * Checks that a channel is available for a periodic transfer.
15360 + *
15361 + * @return 0 if successful, negative error code otherise.
15362 + */
15363 +static int periodic_channel_available(dwc_otg_hcd_t *hcd)
15364 +{
15365 + /*
15366 + * Currently assuming that there is a dedicated host channnel for each
15367 + * periodic transaction plus at least one host channel for
15368 + * non-periodic transactions.
15369 + */
15370 + int status;
15371 + int num_channels;
15372 +
15373 + num_channels = hcd->core_if->core_params->host_channels;
15374 + if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
15375 + (hcd->periodic_channels < num_channels - 1)) {
15376 + status = 0;
15377 + }
15378 + else {
15379 + DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
15380 + __func__, num_channels, hcd->periodic_channels,
15381 + hcd->non_periodic_channels);
15382 + status = -ENOSPC;
15383 + }
15384 +
15385 + return status;
15386 +}
15387 +
15388 +/**
15389 + * Checks that there is sufficient bandwidth for the specified QH in the
15390 + * periodic schedule. For simplicity, this calculation assumes that all the
15391 + * transfers in the periodic schedule may occur in the same (micro)frame.
15392 + *
15393 + * @param hcd The HCD state structure for the DWC OTG controller.
15394 + * @param qh QH containing periodic bandwidth required.
15395 + *
15396 + * @return 0 if successful, negative error code otherwise.
15397 + */
15398 +static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15399 +{
15400 + int status;
15401 + uint16_t max_claimed_usecs;
15402 +
15403 + status = 0;
15404 +
15405 + if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
15406 + /*
15407 + * High speed mode.
15408 + * Max periodic usecs is 80% x 125 usec = 100 usec.
15409 + */
15410 + max_claimed_usecs = 100 - qh->usecs;
15411 + } else {
15412 + /*
15413 + * Full speed mode.
15414 + * Max periodic usecs is 90% x 1000 usec = 900 usec.
15415 + */
15416 + max_claimed_usecs = 900 - qh->usecs;
15417 + }
15418 +
15419 + if (hcd->periodic_usecs > max_claimed_usecs) {
15420 + DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
15421 + __func__, hcd->periodic_usecs, qh->usecs);
15422 + status = -ENOSPC;
15423 + }
15424 +
15425 + return status;
15426 +}
15427 +
15428 +/**
15429 + * Checks that the max transfer size allowed in a host channel is large enough
15430 + * to handle the maximum data transfer in a single (micro)frame for a periodic
15431 + * transfer.
15432 + *
15433 + * @param hcd The HCD state structure for the DWC OTG controller.
15434 + * @param qh QH for a periodic endpoint.
15435 + *
15436 + * @return 0 if successful, negative error code otherwise.
15437 + */
15438 +static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15439 +{
15440 + int status;
15441 + uint32_t max_xfer_size;
15442 + uint32_t max_channel_xfer_size;
15443 +
15444 + status = 0;
15445 +
15446 + max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
15447 + max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
15448 +
15449 + if (max_xfer_size > max_channel_xfer_size) {
15450 + DWC_NOTICE("%s: Periodic xfer length %d > "
15451 + "max xfer length for channel %d\n",
15452 + __func__, max_xfer_size, max_channel_xfer_size);
15453 + status = -ENOSPC;
15454 + }
15455 +
15456 + return status;
15457 +}
15458 +
15459 +/**
15460 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
15461 + *
15462 + * @param hcd The HCD state structure for the DWC OTG controller.
15463 + * @param qh QH for the periodic transfer. The QH should already contain the
15464 + * scheduling information.
15465 + *
15466 + * @return 0 if successful, negative error code otherwise.
15467 + */
15468 +static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15469 +{
15470 + int status = 0;
15471 +
15472 + status = periodic_channel_available(hcd);
15473 + if (status) {
15474 + DWC_NOTICE("%s: No host channel available for periodic "
15475 + "transfer.\n", __func__);
15476 + return status;
15477 + }
15478 +
15479 + status = check_periodic_bandwidth(hcd, qh);
15480 + if (status) {
15481 + DWC_NOTICE("%s: Insufficient periodic bandwidth for "
15482 + "periodic transfer.\n", __func__);
15483 + return status;
15484 + }
15485 +
15486 + status = check_max_xfer_size(hcd, qh);
15487 + if (status) {
15488 + DWC_NOTICE("%s: Channel max transfer size too small "
15489 + "for periodic transfer.\n", __func__);
15490 + return status;
15491 + }
15492 +
15493 + /* Always start in the inactive schedule. */
15494 + list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
15495 +
15496 + /* Reserve the periodic channel. */
15497 + hcd->periodic_channels++;
15498 +
15499 + /* Update claimed usecs per (micro)frame. */
15500 + hcd->periodic_usecs += qh->usecs;
15501 +
15502 + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
15503 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval;
15504 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15505 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++;
15506 + DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
15507 + qh, qh->usecs, qh->interval);
15508 + } else {
15509 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++;
15510 + DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
15511 + qh, qh->usecs, qh->interval);
15512 + }
15513 +
15514 + return status;
15515 +}
15516 +
15517 +/**
15518 + * This function adds a QH to either the non periodic or periodic schedule if
15519 + * it is not already in the schedule. If the QH is already in the schedule, no
15520 + * action is taken.
15521 + *
15522 + * @return 0 if successful, negative error code otherwise.
15523 + */
15524 +int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15525 +{
15526 + unsigned long flags;
15527 + int status = 0;
15528 +
15529 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
15530 +
15531 + if (!list_empty(&qh->qh_list_entry)) {
15532 + /* QH already in a schedule. */
15533 + goto done;
15534 + }
15535 +
15536 + /* Add the new QH to the appropriate schedule */
15537 + if (dwc_qh_is_non_per(qh)) {
15538 + /* Always start in the inactive schedule. */
15539 + list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
15540 + } else {
15541 + status = schedule_periodic(hcd, qh);
15542 + }
15543 +
15544 + done:
15545 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
15546 +
15547 + return status;
15548 +}
15549 +
15550 +/**
15551 + * Removes an interrupt or isochronous transfer from the periodic schedule.
15552 + *
15553 + * @param hcd The HCD state structure for the DWC OTG controller.
15554 + * @param qh QH for the periodic transfer.
15555 + */
15556 +static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15557 +{
15558 + list_del_init(&qh->qh_list_entry);
15559 +
15560 + /* Release the periodic channel reservation. */
15561 + hcd->periodic_channels--;
15562 +
15563 + /* Update claimed usecs per (micro)frame. */
15564 + hcd->periodic_usecs -= qh->usecs;
15565 +
15566 + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
15567 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval;
15568 +
15569 + if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
15570 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--;
15571 + DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
15572 + qh, qh->usecs, qh->interval);
15573 + } else {
15574 + hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--;
15575 + DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
15576 + qh, qh->usecs, qh->interval);
15577 + }
15578 +}
15579 +
15580 +/**
15581 + * Removes a QH from either the non-periodic or periodic schedule. Memory is
15582 + * not freed.
15583 + *
15584 + * @param[in] hcd The HCD state structure.
15585 + * @param[in] qh QH to remove from schedule. */
15586 +void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
15587 +{
15588 + unsigned long flags;
15589 +
15590 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
15591 +
15592 + if (list_empty(&qh->qh_list_entry)) {
15593 + /* QH is not in a schedule. */
15594 + goto done;
15595 + }
15596 +
15597 + if (dwc_qh_is_non_per(qh)) {
15598 + if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
15599 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
15600 + }
15601 + list_del_init(&qh->qh_list_entry);
15602 + } else {
15603 + deschedule_periodic(hcd, qh);
15604 + }
15605 +
15606 + done:
15607 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
15608 +}
15609 +
15610 +/**
15611 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
15612 + * non-periodic schedule. The QH is added to the inactive non-periodic
15613 + * schedule if any QTDs are still attached to the QH.
15614 + *
15615 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
15616 + * there are any QTDs still attached to the QH, the QH is added to either the
15617 + * periodic inactive schedule or the periodic ready schedule and its next
15618 + * scheduled frame is calculated. The QH is placed in the ready schedule if
15619 + * the scheduled frame has been reached already. Otherwise it's placed in the
15620 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
15621 + * completely removed from the periodic schedule.
15622 + */
15623 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
15624 +{
15625 + unsigned long flags;
15626 + SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
15627 +
15628 + if (dwc_qh_is_non_per(qh)) {
15629 + dwc_otg_hcd_qh_remove(hcd, qh);
15630 + if (!list_empty(&qh->qtd_list)) {
15631 + /* Add back to inactive non-periodic schedule. */
15632 + dwc_otg_hcd_qh_add(hcd, qh);
15633 + }
15634 + } else {
15635 + uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
15636 +
15637 + if (qh->do_split) {
15638 + /* Schedule the next continuing periodic split transfer */
15639 + if (sched_next_periodic_split) {
15640 +
15641 + qh->sched_frame = frame_number;
15642 + if (dwc_frame_num_le(frame_number,
15643 + dwc_frame_num_inc(qh->start_split_frame, 1))) {
15644 + /*
15645 + * Allow one frame to elapse after start
15646 + * split microframe before scheduling
15647 + * complete split, but DONT if we are
15648 + * doing the next start split in the
15649 + * same frame for an ISOC out.
15650 + */
15651 + if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
15652 + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
15653 + }
15654 + }
15655 + } else {
15656 + qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
15657 + qh->interval);
15658 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
15659 + qh->sched_frame = frame_number;
15660 + }
15661 + qh->sched_frame |= 0x7;
15662 + qh->start_split_frame = qh->sched_frame;
15663 + }
15664 + } else {
15665 + qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
15666 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
15667 + qh->sched_frame = frame_number;
15668 + }
15669 + }
15670 +
15671 + if (list_empty(&qh->qtd_list)) {
15672 + dwc_otg_hcd_qh_remove(hcd, qh);
15673 + } else {
15674 + /*
15675 + * Remove from periodic_sched_queued and move to
15676 + * appropriate queue.
15677 + */
15678 + if (qh->sched_frame == frame_number) {
15679 + list_move(&qh->qh_list_entry,
15680 + &hcd->periodic_sched_ready);
15681 + } else {
15682 + list_move(&qh->qh_list_entry,
15683 + &hcd->periodic_sched_inactive);
15684 + }
15685 + }
15686 + }
15687 +
15688 + SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
15689 +}
15690 +
15691 +/**
15692 + * This function allocates and initializes a QTD.
15693 + *
15694 + * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up
15695 + * pointing to each other so each pair should have a unique correlation.
15696 + *
15697 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
15698 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
15699 +{
15700 + dwc_otg_qtd_t *qtd;
15701 +
15702 + qtd = dwc_otg_hcd_qtd_alloc ();
15703 + if (qtd == NULL) {
15704 + return NULL;
15705 + }
15706 +
15707 + dwc_otg_hcd_qtd_init (qtd, urb);
15708 + return qtd;
15709 +}
15710 +
15711 +/**
15712 + * Initializes a QTD structure.
15713 + *
15714 + * @param[in] qtd The QTD to initialize.
15715 + * @param[in] urb The URB to use for initialization. */
15716 +void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
15717 +{
15718 + memset (qtd, 0, sizeof (dwc_otg_qtd_t));
15719 + qtd->urb = urb;
15720 + if (usb_pipecontrol(urb->pipe)) {
15721 + /*
15722 + * The only time the QTD data toggle is used is on the data
15723 + * phase of control transfers. This phase always starts with
15724 + * DATA1.
15725 + */
15726 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
15727 + qtd->control_phase = DWC_OTG_CONTROL_SETUP;
15728 + }
15729 +
15730 + /* start split */
15731 + qtd->complete_split = 0;
15732 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
15733 + qtd->isoc_split_offset = 0;
15734 +
15735 + /* Store the qtd ptr in the urb to reference what QTD. */
15736 + urb->hcpriv = qtd;
15737 + return;
15738 +}
15739 +
15740 +/**
15741 + * This function adds a QTD to the QTD-list of a QH. It will find the correct
15742 + * QH to place the QTD into. If it does not find a QH, then it will create a
15743 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
15744 + * is placed into the proper schedule based on its EP type.
15745 + *
15746 + * @param[in] qtd The QTD to add
15747 + * @param[in] dwc_otg_hcd The DWC HCD structure
15748 + *
15749 + * @return 0 if successful, negative error code otherwise.
15750 + */
15751 +int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
15752 + dwc_otg_hcd_t *dwc_otg_hcd)
15753 +{
15754 + struct usb_host_endpoint *ep;
15755 + dwc_otg_qh_t *qh;
15756 + unsigned long flags;
15757 + int retval = 0;
15758 +
15759 + struct urb *urb = qtd->urb;
15760 +
15761 + SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
15762 +
15763 + /*
15764 + * Get the QH which holds the QTD-list to insert to. Create QH if it
15765 + * doesn't exist.
15766 + */
15767 + ep = dwc_urb_to_endpoint(urb);
15768 + qh = (dwc_otg_qh_t *)ep->hcpriv;
15769 + if (qh == NULL) {
15770 + qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
15771 + if (qh == NULL) {
15772 + goto done;
15773 + }
15774 + ep->hcpriv = qh;
15775 + }
15776 +
15777 + retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
15778 + if (retval == 0) {
15779 + list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
15780 + }
15781 +
15782 + done:
15783 + SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
15784 +
15785 + return retval;
15786 +}
15787 +
15788 +#endif /* DWC_DEVICE_ONLY */
15789 diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c b/drivers/usb/dwc_otg/dwc_otg_pcd.c
15790 new file mode 100644
15791 index 0000000..030a3f2
15792 --- /dev/null
15793 +++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
15794 @@ -0,0 +1,2523 @@
15795 +/* ==========================================================================
15796 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
15797 + * $Revision: 1.5 $
15798 + * $Date: 2008-11-27 09:21:25 $
15799 + * $Change: 1115682 $
15800 + *
15801 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
15802 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
15803 + * otherwise expressly agreed to in writing between Synopsys and you.
15804 + *
15805 + * The Software IS NOT an item of Licensed Software or Licensed Product under
15806 + * any End User Software License Agreement or Agreement for Licensed Product
15807 + * with Synopsys or any supplement thereto. You are permitted to use and
15808 + * redistribute this Software in source and binary forms, with or without
15809 + * modification, provided that redistributions of source code must retain this
15810 + * notice. You may not view, use, disclose, copy or distribute this file or
15811 + * any information contained herein except pursuant to this license grant from
15812 + * Synopsys. If you do not agree with this notice, including the disclaimer
15813 + * below, then you are not authorized to use the Software.
15814 + *
15815 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
15816 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15817 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15818 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
15819 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15820 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
15821 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
15822 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
15823 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15824 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
15825 + * DAMAGE.
15826 + * ========================================================================== */
15827 +#ifndef DWC_HOST_ONLY
15828 +
15829 +/** @file
15830 + * This file implements the Peripheral Controller Driver.
15831 + *
15832 + * The Peripheral Controller Driver (PCD) is responsible for
15833 + * translating requests from the Function Driver into the appropriate
15834 + * actions on the DWC_otg controller. It isolates the Function Driver
15835 + * from the specifics of the controller by providing an API to the
15836 + * Function Driver.
15837 + *
15838 + * The Peripheral Controller Driver for Linux will implement the
15839 + * Gadget API, so that the existing Gadget drivers can be used.
15840 + * (Gadget Driver is the Linux terminology for a Function Driver.)
15841 + *
15842 + * The Linux Gadget API is defined in the header file
15843 + * <code><linux/usb_gadget.h></code>. The USB EP operations API is
15844 + * defined in the structure <code>usb_ep_ops</code> and the USB
15845 + * Controller API is defined in the structure
15846 + * <code>usb_gadget_ops</code>.
15847 + *
15848 + * An important function of the PCD is managing interrupts generated
15849 + * by the DWC_otg controller. The implementation of the DWC_otg device
15850 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
15851 + *
15852 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
15853 + * @todo Does it work when the request size is greater than DEPTSIZ
15854 + * transfer size
15855 + *
15856 + */
15857 +
15858 +
15859 +#include <linux/kernel.h>
15860 +#include <linux/module.h>
15861 +#include <linux/moduleparam.h>
15862 +#include <linux/init.h>
15863 +#include <linux/device.h>
15864 +#include <linux/errno.h>
15865 +#include <linux/list.h>
15866 +#include <linux/interrupt.h>
15867 +#include <linux/string.h>
15868 +#include <linux/dma-mapping.h>
15869 +#include <linux/version.h>
15870 +
15871 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
15872 +# include <linux/usb/ch9.h>
15873 +#else
15874 +# include <linux/usb_ch9.h>
15875 +#endif
15876 +
15877 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
15878 +#include <linux/usb/gadget.h>
15879 +#else
15880 +#include <linux/usb_gadget.h>
15881 +#endif
15882 +
15883 +#include "dwc_otg_driver.h"
15884 +#include "dwc_otg_pcd.h"
15885 +
15886 +
15887 +/**
15888 + * Static PCD pointer for use in usb_gadget_register_driver and
15889 + * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
15890 + */
15891 +static dwc_otg_pcd_t *s_pcd = 0;
15892 +
15893 +
15894 +/* Display the contents of the buffer */
15895 +extern void dump_msg(const u8 *buf, unsigned int length);
15896 +
15897 +
15898 +/**
15899 + * This function completes a request. It call's the request call back.
15900 + */
15901 +void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req,
15902 + int status)
15903 +{
15904 + unsigned stopped = ep->stopped;
15905 +
15906 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
15907 + list_del_init(&req->queue);
15908 +
15909 + if (req->req.status == -EINPROGRESS) {
15910 + req->req.status = status;
15911 + } else {
15912 + status = req->req.status;
15913 + }
15914 +
15915 + /* don't modify queue heads during completion callback */
15916 + ep->stopped = 1;
15917 + SPIN_UNLOCK(&ep->pcd->lock);
15918 + req->req.complete(&ep->ep, &req->req);
15919 + SPIN_LOCK(&ep->pcd->lock);
15920 +
15921 + if (ep->pcd->request_pending > 0) {
15922 + --ep->pcd->request_pending;
15923 + }
15924 +
15925 + ep->stopped = stopped;
15926 +}
15927 +
15928 +/**
15929 + * This function terminates all the requsts in the EP request queue.
15930 + */
15931 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep)
15932 +{
15933 + dwc_otg_pcd_request_t *req;
15934 +
15935 + ep->stopped = 1;
15936 +
15937 + /* called with irqs blocked?? */
15938 + while (!list_empty(&ep->queue)) {
15939 + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
15940 + queue);
15941 + dwc_otg_request_done(ep, req, -ESHUTDOWN);
15942 + }
15943 +}
15944 +
15945 +/* USB Endpoint Operations */
15946 +/*
15947 + * The following sections briefly describe the behavior of the Gadget
15948 + * API endpoint operations implemented in the DWC_otg driver
15949 + * software. Detailed descriptions of the generic behavior of each of
15950 + * these functions can be found in the Linux header file
15951 + * include/linux/usb_gadget.h.
15952 + *
15953 + * The Gadget API provides wrapper functions for each of the function
15954 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
15955 + * function, which then calls the underlying PCD function. The
15956 + * following sections are named according to the wrapper
15957 + * functions. Within each section, the corresponding DWC_otg PCD
15958 + * function name is specified.
15959 + *
15960 + */
15961 +
15962 +/**
15963 + * This function assigns periodic Tx FIFO to an periodic EP
15964 + * in shared Tx FIFO mode
15965 + */
15966 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t *core_if)
15967 +{
15968 + uint32_t PerTxMsk = 1;
15969 + int i;
15970 + for(i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i)
15971 + {
15972 + if((PerTxMsk & core_if->p_tx_msk) == 0) {
15973 + core_if->p_tx_msk |= PerTxMsk;
15974 + return i + 1;
15975 + }
15976 + PerTxMsk <<= 1;
15977 + }
15978 + return 0;
15979 +}
15980 +/**
15981 + * This function releases periodic Tx FIFO
15982 + * in shared Tx FIFO mode
15983 + */
15984 +static void release_perio_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
15985 +{
15986 + core_if->p_tx_msk = (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
15987 +}
15988 +/**
15989 + * This function assigns periodic Tx FIFO to an periodic EP
15990 + * in shared Tx FIFO mode
15991 + */
15992 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if)
15993 +{
15994 + uint32_t TxMsk = 1;
15995 + int i;
15996 +
15997 + for(i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i)
15998 + {
15999 + if((TxMsk & core_if->tx_msk) == 0) {
16000 + core_if->tx_msk |= TxMsk;
16001 + return i + 1;
16002 + }
16003 + TxMsk <<= 1;
16004 + }
16005 + return 0;
16006 +}
16007 +/**
16008 + * This function releases periodic Tx FIFO
16009 + * in shared Tx FIFO mode
16010 + */
16011 +static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
16012 +{
16013 + core_if->tx_msk = (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
16014 +}
16015 +
16016 +/**
16017 + * This function is called by the Gadget Driver for each EP to be
16018 + * configured for the current configuration (SET_CONFIGURATION).
16019 + *
16020 + * This function initializes the dwc_otg_ep_t data structure, and then
16021 + * calls dwc_otg_ep_activate.
16022 + */
16023 +static int dwc_otg_pcd_ep_enable(struct usb_ep *usb_ep,
16024 + const struct usb_endpoint_descriptor *ep_desc)
16025 +{
16026 + dwc_otg_pcd_ep_t *ep = 0;
16027 + dwc_otg_pcd_t *pcd = 0;
16028 + unsigned long flags;
16029 +
16030 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, ep_desc);
16031 +
16032 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16033 + if (!usb_ep || !ep_desc || ep->desc ||
16034 + ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
16035 + DWC_WARN("%s, bad ep or descriptor\n", __func__);
16036 + return -EINVAL;
16037 + }
16038 + if (ep == &ep->pcd->ep0) {
16039 + DWC_WARN("%s, bad ep(0)\n", __func__);
16040 + return -EINVAL;
16041 + }
16042 +
16043 + /* Check FIFO size? */
16044 + if (!ep_desc->wMaxPacketSize) {
16045 + DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
16046 + return -ERANGE;
16047 + }
16048 +
16049 + pcd = ep->pcd;
16050 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
16051 + DWC_WARN("%s, bogus device state\n", __func__);
16052 + return -ESHUTDOWN;
16053 + }
16054 +
16055 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
16056 +
16057 + ep->desc = ep_desc;
16058 + ep->ep.maxpacket = le16_to_cpu (ep_desc->wMaxPacketSize);
16059 +
16060 + /*
16061 + * Activate the EP
16062 + */
16063 + ep->stopped = 0;
16064 +
16065 + ep->dwc_ep.is_in = (USB_DIR_IN & ep_desc->bEndpointAddress) != 0;
16066 + ep->dwc_ep.maxpacket = ep->ep.maxpacket;
16067 +
16068 + ep->dwc_ep.type = ep_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
16069 +
16070 + if(ep->dwc_ep.is_in) {
16071 + if(!pcd->otg_dev->core_if->en_multiple_tx_fifo) {
16072 + ep->dwc_ep.tx_fifo_num = 0;
16073 +
16074 + if (ep->dwc_ep.type == USB_ENDPOINT_XFER_ISOC) {
16075 + /*
16076 + * if ISOC EP then assign a Periodic Tx FIFO.
16077 + */
16078 + ep->dwc_ep.tx_fifo_num = assign_perio_tx_fifo(pcd->otg_dev->core_if);
16079 + }
16080 + } else {
16081 + /*
16082 + * if Dedicated FIFOs mode is on then assign a Tx FIFO.
16083 + */
16084 + ep->dwc_ep.tx_fifo_num = assign_tx_fifo(pcd->otg_dev->core_if);
16085 +
16086 + }
16087 + }
16088 + /* Set initial data PID. */
16089 + if (ep->dwc_ep.type == USB_ENDPOINT_XFER_BULK) {
16090 + ep->dwc_ep.data_pid_start = 0;
16091 + }
16092 +
16093 + DWC_DEBUGPL(DBG_PCD, "Activate %s-%s: type=%d, mps=%d desc=%p\n",
16094 + ep->ep.name, (ep->dwc_ep.is_in ?"IN":"OUT"),
16095 + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
16096 +
16097 + if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC) {
16098 + ep->dwc_ep.desc_addr = dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
16099 + }
16100 +
16101 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
16102 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16103 +
16104 + return 0;
16105 +}
16106 +
16107 +/**
16108 + * This function is called when an EP is disabled due to disconnect or
16109 + * change in configuration. Any pending requests will terminate with a
16110 + * status of -ESHUTDOWN.
16111 + *
16112 + * This function modifies the dwc_otg_ep_t data structure for this EP,
16113 + * and then calls dwc_otg_ep_deactivate.
16114 + */
16115 +static int dwc_otg_pcd_ep_disable(struct usb_ep *usb_ep)
16116 +{
16117 + dwc_otg_pcd_ep_t *ep;
16118 + dwc_otg_pcd_t *pcd = 0;
16119 + unsigned long flags;
16120 +
16121 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, usb_ep);
16122 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16123 + if (!usb_ep || !ep->desc) {
16124 + DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
16125 + usb_ep ? ep->ep.name : NULL);
16126 + return -EINVAL;
16127 + }
16128 +
16129 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
16130 +
16131 + dwc_otg_request_nuke(ep);
16132 +
16133 + dwc_otg_ep_deactivate(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
16134 + ep->desc = 0;
16135 + ep->stopped = 1;
16136 +
16137 + if(ep->dwc_ep.is_in) {
16138 + dwc_otg_flush_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
16139 + release_perio_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
16140 + release_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
16141 + }
16142 +
16143 + /* Free DMA Descriptors */
16144 + pcd = ep->pcd;
16145 +
16146 + SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
16147 +
16148 + if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC && ep->dwc_ep.desc_addr) {
16149 + dwc_otg_ep_free_desc_chain(ep->dwc_ep.desc_addr, ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
16150 + }
16151 +
16152 + DWC_DEBUGPL(DBG_PCD, "%s disabled\n", usb_ep->name);
16153 + return 0;
16154 +}
16155 +
16156 +
16157 +/**
16158 + * This function allocates a request object to use with the specified
16159 + * endpoint.
16160 + *
16161 + * @param ep The endpoint to be used with with the request
16162 + * @param gfp_flags the GFP_* flags to use.
16163 + */
16164 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
16165 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
16166 + int gfp_flags
16167 +#else
16168 + gfp_t gfp_flags
16169 +#endif
16170 + )
16171 +{
16172 + dwc_otg_pcd_request_t *req;
16173 +
16174 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d)\n", __func__, ep, gfp_flags);
16175 + if (0 == ep) {
16176 + DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
16177 + return 0;
16178 + }
16179 + req = kmalloc(sizeof(dwc_otg_pcd_request_t), gfp_flags);
16180 + if (0 == req) {
16181 + DWC_WARN("%s() %s\n", __func__,
16182 + "request allocation failed!\n");
16183 + return 0;
16184 + }
16185 + memset(req, 0, sizeof(dwc_otg_pcd_request_t));
16186 + req->req.dma = DMA_ADDR_INVALID;
16187 + INIT_LIST_HEAD(&req->queue);
16188 + return &req->req;
16189 +}
16190 +
16191 +/**
16192 + * This function frees a request object.
16193 + *
16194 + * @param ep The endpoint associated with the request
16195 + * @param req The request being freed
16196 + */
16197 +static void dwc_otg_pcd_free_request(struct usb_ep *ep,
16198 + struct usb_request *req)
16199 +{
16200 + dwc_otg_pcd_request_t *request;
16201 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, ep, req);
16202 +
16203 + if (0 == ep || 0 == req) {
16204 + DWC_WARN("%s() %s\n", __func__,
16205 + "Invalid ep or req argument!\n");
16206 + return;
16207 + }
16208 +
16209 + request = container_of(req, dwc_otg_pcd_request_t, req);
16210 + kfree(request);
16211 +}
16212 +
16213 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
16214 +/**
16215 + * This function allocates an I/O buffer to be used for a transfer
16216 + * to/from the specified endpoint.
16217 + *
16218 + * @param usb_ep The endpoint to be used with with the request
16219 + * @param bytes The desired number of bytes for the buffer
16220 + * @param dma Pointer to the buffer's DMA address; must be valid
16221 + * @param gfp_flags the GFP_* flags to use.
16222 + * @return address of a new buffer or null is buffer could not be allocated.
16223 + */
16224 +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
16225 + dma_addr_t *dma,
16226 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
16227 + int gfp_flags
16228 +#else
16229 + gfp_t gfp_flags
16230 +#endif
16231 + )
16232 +{
16233 + void *buf;
16234 + dwc_otg_pcd_ep_t *ep;
16235 + dwc_otg_pcd_t *pcd = 0;
16236 +
16237 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16238 + pcd = ep->pcd;
16239 +
16240 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
16241 + dma, gfp_flags);
16242 +
16243 + /* Check dword alignment */
16244 + if ((bytes & 0x3UL) != 0) {
16245 + DWC_WARN("%s() Buffer size is not a multiple of"
16246 + "DWORD size (%d)",__func__, bytes);
16247 + }
16248 +
16249 + if (GET_CORE_IF(pcd)->dma_enable) {
16250 + buf = dma_alloc_coherent (NULL, bytes, dma, gfp_flags);
16251 + }
16252 + else {
16253 + buf = kmalloc(bytes, gfp_flags);
16254 + }
16255 +
16256 + /* Check dword alignment */
16257 + if (((int)buf & 0x3UL) != 0) {
16258 + DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
16259 + __func__, buf);
16260 + }
16261 +
16262 + return buf;
16263 +}
16264 +
16265 +/**
16266 + * This function frees an I/O buffer that was allocated by alloc_buffer.
16267 + *
16268 + * @param usb_ep the endpoint associated with the buffer
16269 + * @param buf address of the buffer
16270 + * @param dma The buffer's DMA address
16271 + * @param bytes The number of bytes of the buffer
16272 + */
16273 +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
16274 + dma_addr_t dma, unsigned bytes)
16275 +{
16276 + dwc_otg_pcd_ep_t *ep;
16277 + dwc_otg_pcd_t *pcd = 0;
16278 +
16279 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16280 + pcd = ep->pcd;
16281 +
16282 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%0x,%d)\n", __func__, ep, buf, dma, bytes);
16283 +
16284 + if (GET_CORE_IF(pcd)->dma_enable) {
16285 + dma_free_coherent (NULL, bytes, buf, dma);
16286 + }
16287 + else {
16288 + kfree(buf);
16289 + }
16290 +}
16291 +#endif
16292 +
16293 +
16294 +/**
16295 + * This function is used to submit an I/O Request to an EP.
16296 + *
16297 + * - When the request completes the request's completion callback
16298 + * is called to return the request to the driver.
16299 + * - An EP, except control EPs, may have multiple requests
16300 + * pending.
16301 + * - Once submitted the request cannot be examined or modified.
16302 + * - Each request is turned into one or more packets.
16303 + * - A BULK EP can queue any amount of data; the transfer is
16304 + * packetized.
16305 + * - Zero length Packets are specified with the request 'zero'
16306 + * flag.
16307 + */
16308 +static int dwc_otg_pcd_ep_queue(struct usb_ep *usb_ep,
16309 + struct usb_request *usb_req,
16310 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
16311 + int gfp_flags
16312 +#else
16313 + gfp_t gfp_flags
16314 +#endif
16315 + )
16316 +{
16317 + int prevented = 0;
16318 + dwc_otg_pcd_request_t *req;
16319 + dwc_otg_pcd_ep_t *ep;
16320 + dwc_otg_pcd_t *pcd;
16321 + unsigned long flags = 0;
16322 + dwc_otg_core_if_t *_core_if;
16323 +
16324 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%d)\n",
16325 + __func__, usb_ep, usb_req, gfp_flags);
16326 +
16327 + req = container_of(usb_req, dwc_otg_pcd_request_t, req);
16328 + if (!usb_req || !usb_req->complete || !usb_req->buf ||
16329 + !list_empty(&req->queue)) {
16330 + DWC_WARN("%s, bad params\n", __func__);
16331 + return -EINVAL;
16332 + }
16333 +
16334 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16335 + if (!usb_ep || (!ep->desc && ep->dwc_ep.num != 0)/* || ep->stopped != 0*/) {
16336 + DWC_WARN("%s, bad ep\n", __func__);
16337 + return -EINVAL;
16338 + }
16339 +
16340 + pcd = ep->pcd;
16341 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
16342 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
16343 + DWC_WARN("%s, bogus device state\n", __func__);
16344 + return -ESHUTDOWN;
16345 + }
16346 +
16347 +
16348 + DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
16349 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
16350 +
16351 + if (!GET_CORE_IF(pcd)->core_params->opt) {
16352 + if (ep->dwc_ep.num != 0) {
16353 + DWC_ERROR("%s queue req %p, len %d buf %p\n",
16354 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
16355 + }
16356 + }
16357 +
16358 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
16359 +
16360 +
16361 + /**************************************************
16362 + New add by kaiker ,for DMA mode bug
16363 + ************************************************/
16364 + //by kaiker ,for RT3052 USB OTG device mode
16365 +
16366 + _core_if = GET_CORE_IF(pcd);
16367 +
16368 + if (_core_if->dma_enable)
16369 + {
16370 + usb_req->dma = virt_to_phys((void *)usb_req->buf);
16371 +
16372 + if(ep->dwc_ep.is_in)
16373 + {
16374 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) || defined(CONFIG_MIPS)
16375 + if(usb_req->length)
16376 + dma_cache_wback_inv((unsigned long)usb_req->buf, usb_req->length + 2);
16377 +#endif
16378 + }
16379 + }
16380 +
16381 +
16382 +
16383 +#if defined(DEBUG) & defined(VERBOSE)
16384 + dump_msg(usb_req->buf, usb_req->length);
16385 +#endif
16386 +
16387 + usb_req->status = -EINPROGRESS;
16388 + usb_req->actual = 0;
16389 +
16390 + /*
16391 + * For EP0 IN without premature status, zlp is required?
16392 + */
16393 + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
16394 + DWC_DEBUGPL(DBG_PCDV, "%s-OUT ZLP\n", usb_ep->name);
16395 + //_req->zero = 1;
16396 + }
16397 +
16398 + /* Start the transfer */
16399 + if (list_empty(&ep->queue) && !ep->stopped) {
16400 + /* EP0 Transfer? */
16401 + if (ep->dwc_ep.num == 0) {
16402 + switch (pcd->ep0state) {
16403 + case EP0_IN_DATA_PHASE:
16404 + DWC_DEBUGPL(DBG_PCD,
16405 + "%s ep0: EP0_IN_DATA_PHASE\n",
16406 + __func__);
16407 + break;
16408 +
16409 + case EP0_OUT_DATA_PHASE:
16410 + DWC_DEBUGPL(DBG_PCD,
16411 + "%s ep0: EP0_OUT_DATA_PHASE\n",
16412 + __func__);
16413 + if (pcd->request_config) {
16414 + /* Complete STATUS PHASE */
16415 + ep->dwc_ep.is_in = 1;
16416 + pcd->ep0state = EP0_IN_STATUS_PHASE;
16417 + }
16418 + break;
16419 +
16420 + case EP0_IN_STATUS_PHASE:
16421 + DWC_DEBUGPL(DBG_PCD,
16422 + "%s ep0: EP0_IN_STATUS_PHASE\n",
16423 + __func__);
16424 + break;
16425 +
16426 + default:
16427 + DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
16428 + pcd->ep0state);
16429 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16430 + return -EL2HLT;
16431 + }
16432 + ep->dwc_ep.dma_addr = usb_req->dma;
16433 + ep->dwc_ep.start_xfer_buff = usb_req->buf;
16434 + ep->dwc_ep.xfer_buff = usb_req->buf;
16435 + ep->dwc_ep.xfer_len = usb_req->length;
16436 + ep->dwc_ep.xfer_count = 0;
16437 + ep->dwc_ep.sent_zlp = 0;
16438 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
16439 +
16440 + if(usb_req->zero) {
16441 + if((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket == 0)
16442 + && (ep->dwc_ep.xfer_len != 0)) {
16443 + ep->dwc_ep.sent_zlp = 1;
16444 + }
16445 +
16446 + }
16447 +
16448 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
16449 + }
16450 + else {
16451 +
16452 + uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
16453 +
16454 + /* Setup and start the Transfer */
16455 + ep->dwc_ep.dma_addr = usb_req->dma;
16456 + ep->dwc_ep.start_xfer_buff = usb_req->buf;
16457 + ep->dwc_ep.xfer_buff = usb_req->buf;
16458 + ep->dwc_ep.sent_zlp = 0;
16459 + ep->dwc_ep.total_len = usb_req->length;
16460 + ep->dwc_ep.xfer_len = 0;
16461 + ep->dwc_ep.xfer_count = 0;
16462 +
16463 + if(max_transfer > MAX_TRANSFER_SIZE) {
16464 + ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
16465 + } else {
16466 + ep->dwc_ep.maxxfer = max_transfer;
16467 + }
16468 +
16469 + if(usb_req->zero) {
16470 + if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
16471 + && (ep->dwc_ep.total_len != 0)) {
16472 + ep->dwc_ep.sent_zlp = 1;
16473 + }
16474 +
16475 + }
16476 + dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
16477 + }
16478 + }
16479 +
16480 + if ((req != 0) || prevented) {
16481 + ++pcd->request_pending;
16482 + list_add_tail(&req->queue, &ep->queue);
16483 + if (ep->dwc_ep.is_in && ep->stopped && !(GET_CORE_IF(pcd)->dma_enable)) {
16484 + /** @todo NGS Create a function for this. */
16485 + diepmsk_data_t diepmsk = { .d32 = 0};
16486 + diepmsk.b.intktxfemp = 1;
16487 + if(&GET_CORE_IF(pcd)->multiproc_int_enable) {
16488 + dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepeachintmsk[ep->dwc_ep.num],
16489 + 0, diepmsk.d32);
16490 + } else {
16491 + dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
16492 + }
16493 + }
16494 + }
16495 +
16496 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16497 + return 0;
16498 +}
16499 +
16500 +/**
16501 + * This function cancels an I/O request from an EP.
16502 + */
16503 +static int dwc_otg_pcd_ep_dequeue(struct usb_ep *usb_ep,
16504 + struct usb_request *usb_req)
16505 +{
16506 + dwc_otg_pcd_request_t *req;
16507 + dwc_otg_pcd_ep_t *ep;
16508 + dwc_otg_pcd_t *pcd;
16509 + unsigned long flags;
16510 +
16511 + DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, usb_req);
16512 +
16513 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16514 + if (!usb_ep || !usb_req || (!ep->desc && ep->dwc_ep.num != 0)) {
16515 + DWC_WARN("%s, bad argument\n", __func__);
16516 + return -EINVAL;
16517 + }
16518 + pcd = ep->pcd;
16519 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
16520 + DWC_WARN("%s, bogus device state\n", __func__);
16521 + return -ESHUTDOWN;
16522 + }
16523 +
16524 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
16525 + DWC_DEBUGPL(DBG_PCDV, "%s %s %s %p\n", __func__, usb_ep->name,
16526 + ep->dwc_ep.is_in ? "IN" : "OUT",
16527 + usb_req);
16528 +
16529 + /* make sure it's actually queued on this endpoint */
16530 + list_for_each_entry(req, &ep->queue, queue)
16531 + {
16532 + if (&req->req == usb_req) {
16533 + break;
16534 + }
16535 + }
16536 +
16537 + if (&req->req != usb_req) {
16538 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16539 + return -EINVAL;
16540 + }
16541 +
16542 + if (!list_empty(&req->queue)) {
16543 + dwc_otg_request_done(ep, req, -ECONNRESET);
16544 + }
16545 + else {
16546 + req = 0;
16547 + }
16548 +
16549 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
16550 +
16551 + return req ? 0 : -EOPNOTSUPP;
16552 +}
16553 +
16554 +/**
16555 + * usb_ep_set_halt stalls an endpoint.
16556 + *
16557 + * usb_ep_clear_halt clears an endpoint halt and resets its data
16558 + * toggle.
16559 + *
16560 + * Both of these functions are implemented with the same underlying
16561 + * function. The behavior depends on the value argument.
16562 + *
16563 + * @param[in] usb_ep the Endpoint to halt or clear halt.
16564 + * @param[in] value
16565 + * - 0 means clear_halt.
16566 + * - 1 means set_halt,
16567 + * - 2 means clear stall lock flag.
16568 + * - 3 means set stall lock flag.
16569 + */
16570 +static int dwc_otg_pcd_ep_set_halt(struct usb_ep *usb_ep, int value)
16571 +{
16572 + int retval = 0;
16573 + unsigned long flags;
16574 + dwc_otg_pcd_ep_t *ep = 0;
16575 +
16576 +
16577 + DWC_DEBUGPL(DBG_PCD,"HALT %s %d\n", usb_ep->name, value);
16578 +
16579 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
16580 +
16581 + if (!usb_ep || (!ep->desc && ep != &ep->pcd->ep0) ||
16582 + ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
16583 + DWC_WARN("%s, bad ep\n", __func__);
16584 + return -EINVAL;
16585 + }
16586 +
16587 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
16588 + if (!list_empty(&ep->queue)) {
16589 + DWC_WARN("%s() %s XFer In process\n", __func__, usb_ep->name);
16590 + retval = -EAGAIN;
16591 + }
16592 + else if (value == 0) {
16593 + dwc_otg_ep_clear_stall(ep->pcd->otg_dev->core_if,
16594 + &ep->dwc_ep);
16595 + }
16596 + else if(value == 1) {
16597 + if (ep->dwc_ep.is_in == 1 && ep->pcd->otg_dev->core_if->dma_desc_enable) {
16598 + dtxfsts_data_t txstatus;
16599 + fifosize_data_t txfifosize;
16600 +
16601 + txfifosize.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->core_global_regs->dptxfsiz_dieptxf[ep->dwc_ep.tx_fifo_num]);
16602 + txstatus.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->dtxfsts);
16603 +
16604 + if(txstatus.b.txfspcavail < txfifosize.b.depth) {
16605 + DWC_WARN("%s() %s Data In Tx Fifo\n", __func__, usb_ep->name);
16606 + retval = -EAGAIN;
16607 + }
16608 + else {
16609 + if (ep->dwc_ep.num == 0) {
16610 + ep->pcd->ep0state = EP0_STALL;
16611 + }
16612 +
16613 + ep->stopped = 1;
16614 + dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
16615 + &ep->dwc_ep);
16616 + }
16617 + }
16618 + else {
16619 + if (ep->dwc_ep.num == 0) {
16620 + ep->pcd->ep0state = EP0_STALL;
16621 + }
16622 +
16623 + ep->stopped = 1;
16624 + dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
16625 + &ep->dwc_ep);
16626 + }
16627 + }
16628 + else if (value == 2) {
16629 + ep->dwc_ep.stall_clear_flag = 0;
16630 + }
16631 + else if (value == 3) {
16632 + ep->dwc_ep.stall_clear_flag = 1;
16633 + }
16634 +
16635 + SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
16636 + return retval;
16637 +}
16638 +
16639 +/**
16640 + * This function allocates a DMA Descriptor chain for the Endpoint
16641 + * buffer to be used for a transfer to/from the specified endpoint.
16642 + */
16643 +dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count)
16644 +{
16645 +
16646 + return dma_alloc_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), dma_desc_addr, GFP_KERNEL);
16647 +}
16648 +
16649 +/**
16650 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
16651 + */
16652 +void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count)
16653 +{
16654 + dma_free_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), desc_addr, dma_desc_addr);
16655 +}
16656 +
16657 +#ifdef DWC_EN_ISOC
16658 +
16659 +/**
16660 + * This function initializes a descriptor chain for Isochronous transfer
16661 + *
16662 + * @param core_if Programming view of DWC_otg controller.
16663 + * @param dwc_ep The EP to start the transfer on.
16664 + *
16665 + */
16666 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
16667 +{
16668 +
16669 + dsts_data_t dsts = { .d32 = 0};
16670 + depctl_data_t depctl = { .d32 = 0 };
16671 + volatile uint32_t *addr;
16672 + int i, j;
16673 +
16674 + if(dwc_ep->is_in)
16675 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
16676 + else
16677 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
16678 +
16679 +
16680 + /** Allocate descriptors for double buffering */
16681 + dwc_ep->iso_desc_addr = dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,dwc_ep->desc_cnt*2);
16682 + if(dwc_ep->desc_addr) {
16683 + DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
16684 + return;
16685 + }
16686 +
16687 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
16688 +
16689 + /** ISO OUT EP */
16690 + if(dwc_ep->is_in == 0) {
16691 + desc_sts_data_t sts = { .d32 =0 };
16692 + dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
16693 + dma_addr_t dma_ad;
16694 + uint32_t data_per_desc;
16695 + dwc_otg_dev_out_ep_regs_t *out_regs =
16696 + core_if->dev_if->out_ep_regs[dwc_ep->num];
16697 + int offset;
16698 +
16699 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
16700 + dma_ad = (dma_addr_t)dwc_read_reg32(&(out_regs->doepdma));
16701 +
16702 + /** Buffer 0 descriptors setup */
16703 + dma_ad = dwc_ep->dma_addr0;
16704 +
16705 + sts.b_iso_out.bs = BS_HOST_READY;
16706 + sts.b_iso_out.rxsts = 0;
16707 + sts.b_iso_out.l = 0;
16708 + sts.b_iso_out.sp = 0;
16709 + sts.b_iso_out.ioc = 0;
16710 + sts.b_iso_out.pid = 0;
16711 + sts.b_iso_out.framenum = 0;
16712 +
16713 + offset = 0;
16714 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
16715 + {
16716 +
16717 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
16718 + {
16719 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16720 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16721 +
16722 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16723 + sts.b_iso_out.rxbytes = data_per_desc;
16724 + writel((uint32_t)dma_ad, &dma_desc->buf);
16725 + writel(sts.d32, &dma_desc->status);
16726 +
16727 + offset += data_per_desc;
16728 + dma_desc ++;
16729 + (uint32_t)dma_ad += data_per_desc;
16730 + }
16731 + }
16732 +
16733 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
16734 + {
16735 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16736 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16737 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16738 + sts.b_iso_out.rxbytes = data_per_desc;
16739 + writel((uint32_t)dma_ad, &dma_desc->buf);
16740 + writel(sts.d32, &dma_desc->status);
16741 +
16742 + offset += data_per_desc;
16743 + dma_desc ++;
16744 + (uint32_t)dma_ad += data_per_desc;
16745 + }
16746 +
16747 + sts.b_iso_out.ioc = 1;
16748 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16749 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16750 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16751 + sts.b_iso_out.rxbytes = data_per_desc;
16752 +
16753 + writel((uint32_t)dma_ad, &dma_desc->buf);
16754 + writel(sts.d32, &dma_desc->status);
16755 + dma_desc ++;
16756 +
16757 + /** Buffer 1 descriptors setup */
16758 + sts.b_iso_out.ioc = 0;
16759 + dma_ad = dwc_ep->dma_addr1;
16760 +
16761 + offset = 0;
16762 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
16763 + {
16764 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
16765 + {
16766 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16767 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16768 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16769 + sts.b_iso_out.rxbytes = data_per_desc;
16770 + writel((uint32_t)dma_ad, &dma_desc->buf);
16771 + writel(sts.d32, &dma_desc->status);
16772 +
16773 + offset += data_per_desc;
16774 + dma_desc ++;
16775 + (uint32_t)dma_ad += data_per_desc;
16776 + }
16777 + }
16778 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
16779 + {
16780 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16781 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16782 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16783 + sts.b_iso_out.rxbytes = data_per_desc;
16784 + writel((uint32_t)dma_ad, &dma_desc->buf);
16785 + writel(sts.d32, &dma_desc->status);
16786 +
16787 + offset += data_per_desc;
16788 + dma_desc ++;
16789 + (uint32_t)dma_ad += data_per_desc;
16790 + }
16791 +
16792 + sts.b_iso_out.ioc = 1;
16793 + sts.b_iso_out.l = 1;
16794 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
16795 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
16796 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
16797 + sts.b_iso_out.rxbytes = data_per_desc;
16798 +
16799 + writel((uint32_t)dma_ad, &dma_desc->buf);
16800 + writel(sts.d32, &dma_desc->status);
16801 +
16802 + dwc_ep->next_frame = 0;
16803 +
16804 + /** Write dma_ad into DOEPDMA register */
16805 + dwc_write_reg32(&(out_regs->doepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
16806 +
16807 + }
16808 + /** ISO IN EP */
16809 + else {
16810 + desc_sts_data_t sts = { .d32 =0 };
16811 + dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
16812 + dma_addr_t dma_ad;
16813 + dwc_otg_dev_in_ep_regs_t *in_regs =
16814 + core_if->dev_if->in_ep_regs[dwc_ep->num];
16815 + unsigned int frmnumber;
16816 + fifosize_data_t txfifosize,rxfifosize;
16817 +
16818 + txfifosize.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->dtxfsts);
16819 + rxfifosize.d32 = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
16820 +
16821 +
16822 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
16823 +
16824 + dma_ad = dwc_ep->dma_addr0;
16825 +
16826 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
16827 +
16828 + sts.b_iso_in.bs = BS_HOST_READY;
16829 + sts.b_iso_in.txsts = 0;
16830 + sts.b_iso_in.sp = (dwc_ep->data_per_frame % dwc_ep->maxpacket)? 1 : 0;
16831 + sts.b_iso_in.ioc = 0;
16832 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
16833 +
16834 +
16835 + frmnumber = dwc_ep->next_frame;
16836 +
16837 + sts.b_iso_in.framenum = frmnumber;
16838 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
16839 + sts.b_iso_in.l = 0;
16840 +
16841 + /** Buffer 0 descriptors setup */
16842 + for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
16843 + {
16844 + writel((uint32_t)dma_ad, &dma_desc->buf);
16845 + writel(sts.d32, &dma_desc->status);
16846 + dma_desc ++;
16847 +
16848 + (uint32_t)dma_ad += dwc_ep->data_per_frame;
16849 + sts.b_iso_in.framenum += dwc_ep->bInterval;
16850 + }
16851 +
16852 + sts.b_iso_in.ioc = 1;
16853 + writel((uint32_t)dma_ad, &dma_desc->buf);
16854 + writel(sts.d32, &dma_desc->status);
16855 + ++dma_desc;
16856 +
16857 + /** Buffer 1 descriptors setup */
16858 + sts.b_iso_in.ioc = 0;
16859 + dma_ad = dwc_ep->dma_addr1;
16860 +
16861 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
16862 + {
16863 + writel((uint32_t)dma_ad, &dma_desc->buf);
16864 + writel(sts.d32, &dma_desc->status);
16865 + dma_desc ++;
16866 +
16867 + (uint32_t)dma_ad += dwc_ep->data_per_frame;
16868 + sts.b_iso_in.framenum += dwc_ep->bInterval;
16869 +
16870 + sts.b_iso_in.ioc = 0;
16871 + }
16872 + sts.b_iso_in.ioc = 1;
16873 + sts.b_iso_in.l = 1;
16874 +
16875 + writel((uint32_t)dma_ad, &dma_desc->buf);
16876 + writel(sts.d32, &dma_desc->status);
16877 +
16878 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
16879 +
16880 + /** Write dma_ad into diepdma register */
16881 + dwc_write_reg32(&(in_regs->diepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
16882 + }
16883 + /** Enable endpoint, clear nak */
16884 + depctl.d32 = 0;
16885 + depctl.b.epena = 1;
16886 + depctl.b.usbactep = 1;
16887 + depctl.b.cnak = 1;
16888 +
16889 + dwc_modify_reg32(addr, depctl.d32,depctl.d32);
16890 + depctl.d32 = dwc_read_reg32(addr);
16891 +}
16892 +
16893 +/**
16894 + * This function initializes a descriptor chain for Isochronous transfer
16895 + *
16896 + * @param core_if Programming view of DWC_otg controller.
16897 + * @param ep The EP to start the transfer on.
16898 + *
16899 + */
16900 +
16901 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
16902 +{
16903 + depctl_data_t depctl = { .d32 = 0 };
16904 + volatile uint32_t *addr;
16905 +
16906 +
16907 + if(ep->is_in) {
16908 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
16909 + } else {
16910 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
16911 + }
16912 +
16913 +
16914 + if(core_if->dma_enable == 0 || core_if->dma_desc_enable!= 0) {
16915 + return;
16916 + } else {
16917 + deptsiz_data_t deptsiz = { .d32 = 0 };
16918 +
16919 + ep->xfer_len = ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
16920 + ep->pkt_cnt = (ep->xfer_len - 1 + ep->maxpacket) /
16921 + ep->maxpacket;
16922 + ep->xfer_count = 0;
16923 + ep->xfer_buff = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
16924 + ep->dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
16925 +
16926 + if(ep->is_in) {
16927 + /* Program the transfer size and packet count
16928 + * as follows: xfersize = N * maxpacket +
16929 + * short_packet pktcnt = N + (short_packet
16930 + * exist ? 1 : 0)
16931 + */
16932 + deptsiz.b.mc = ep->pkt_per_frm;
16933 + deptsiz.b.xfersize = ep->xfer_len;
16934 + deptsiz.b.pktcnt =
16935 + (ep->xfer_len - 1 + ep->maxpacket) /
16936 + ep->maxpacket;
16937 + dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
16938 +
16939 + /* Write the DMA register */
16940 + dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
16941 +
16942 + } else {
16943 + deptsiz.b.pktcnt =
16944 + (ep->xfer_len + (ep->maxpacket - 1)) /
16945 + ep->maxpacket;
16946 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
16947 +
16948 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
16949 +
16950 + /* Write the DMA register */
16951 + dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), (uint32_t)ep->dma_addr);
16952 +
16953 + }
16954 + /** Enable endpoint, clear nak */
16955 + depctl.d32 = 0;
16956 + dwc_modify_reg32(addr, depctl.d32,depctl.d32);
16957 +
16958 + depctl.b.epena = 1;
16959 + depctl.b.cnak = 1;
16960 +
16961 + dwc_modify_reg32(addr, depctl.d32,depctl.d32);
16962 + }
16963 +}
16964 +
16965 +
16966 +/**
16967 + * This function does the setup for a data transfer for an EP and
16968 + * starts the transfer. For an IN transfer, the packets will be
16969 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
16970 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
16971 + *
16972 + * @param core_if Programming view of DWC_otg controller.
16973 + * @param ep The EP to start the transfer on.
16974 + */
16975 +
16976 +void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
16977 +{
16978 + if(core_if->dma_enable) {
16979 + if(core_if->dma_desc_enable) {
16980 + if(ep->is_in) {
16981 + ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
16982 + } else {
16983 + ep->desc_cnt = ep->pkt_cnt;
16984 + }
16985 + dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
16986 + } else {
16987 + if(core_if->pti_enh_enable) {
16988 + dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
16989 + } else {
16990 + ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
16991 + ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
16992 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
16993 + }
16994 + }
16995 + } else {
16996 + ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
16997 + ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
16998 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
16999 + }
17000 +}
17001 +
17002 +/**
17003 + * This function does the setup for a data transfer for an EP and
17004 + * starts the transfer. For an IN transfer, the packets will be
17005 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
17006 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
17007 + *
17008 + * @param core_if Programming view of DWC_otg controller.
17009 + * @param ep The EP to start the transfer on.
17010 + */
17011 +
17012 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
17013 +{
17014 + depctl_data_t depctl = { .d32 = 0 };
17015 + volatile uint32_t *addr;
17016 +
17017 + if(ep->is_in == 1) {
17018 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
17019 + }
17020 + else {
17021 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
17022 + }
17023 +
17024 + /* disable the ep */
17025 + depctl.d32 = dwc_read_reg32(addr);
17026 +
17027 + depctl.b.epdis = 1;
17028 + depctl.b.snak = 1;
17029 +
17030 + dwc_write_reg32(addr, depctl.d32);
17031 +
17032 + if(core_if->dma_desc_enable &&
17033 + ep->iso_desc_addr && ep->iso_dma_desc_addr) {
17034 + dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,ep->iso_dma_desc_addr,ep->desc_cnt * 2);
17035 + }
17036 +
17037 + /* reset varibales */
17038 + ep->dma_addr0 = 0;
17039 + ep->dma_addr1 = 0;
17040 + ep->xfer_buff0 = 0;
17041 + ep->xfer_buff1 = 0;
17042 + ep->data_per_frame = 0;
17043 + ep->data_pattern_frame = 0;
17044 + ep->sync_frame = 0;
17045 + ep->buf_proc_intrvl = 0;
17046 + ep->bInterval = 0;
17047 + ep->proc_buf_num = 0;
17048 + ep->pkt_per_frm = 0;
17049 + ep->pkt_per_frm = 0;
17050 + ep->desc_cnt = 0;
17051 + ep->iso_desc_addr = 0;
17052 + ep->iso_dma_desc_addr = 0;
17053 +}
17054 +
17055 +
17056 +/**
17057 + * This function is used to submit an ISOC Transfer Request to an EP.
17058 + *
17059 + * - Every time a sync period completes the request's completion callback
17060 + * is called to provide data to the gadget driver.
17061 + * - Once submitted the request cannot be modified.
17062 + * - Each request is turned into periodic data packets untill ISO
17063 + * Transfer is stopped..
17064 + */
17065 +static int dwc_otg_pcd_iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
17066 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
17067 + int gfp_flags
17068 +#else
17069 + gfp_t gfp_flags
17070 +#endif
17071 +)
17072 +{
17073 + dwc_otg_pcd_ep_t *ep;
17074 + dwc_otg_pcd_t *pcd;
17075 + dwc_ep_t *dwc_ep;
17076 + unsigned long flags = 0;
17077 + int32_t frm_data;
17078 + dwc_otg_core_if_t *core_if;
17079 + dcfg_data_t dcfg;
17080 + dsts_data_t dsts;
17081 +
17082 +
17083 + if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
17084 + DWC_WARN("%s, bad params\n", __func__);
17085 + return -EINVAL;
17086 + }
17087 +
17088 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
17089 +
17090 + if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
17091 + DWC_WARN("%s, bad ep\n", __func__);
17092 + return -EINVAL;
17093 + }
17094 +
17095 + pcd = ep->pcd;
17096 + core_if = GET_CORE_IF(pcd);
17097 +
17098 + dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
17099 +
17100 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
17101 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
17102 + DWC_WARN("%s, bogus device state\n", __func__);
17103 + return -ESHUTDOWN;
17104 + }
17105 +
17106 + SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
17107 +
17108 + dwc_ep = &ep->dwc_ep;
17109 +
17110 + if(ep->iso_req) {
17111 + DWC_WARN("%s, iso request in progress\n", __func__);
17112 + }
17113 + req->status = -EINPROGRESS;
17114 +
17115 + dwc_ep->dma_addr0 = req->dma0;
17116 + dwc_ep->dma_addr1 = req->dma1;
17117 +
17118 + dwc_ep->xfer_buff0 = req->buf0;
17119 + dwc_ep->xfer_buff1 = req->buf1;
17120 +
17121 + ep->iso_req = req;
17122 +
17123 + dwc_ep->data_per_frame = req->data_per_frame;
17124 +
17125 + /** @todo - pattern data support is to be implemented in the future */
17126 + dwc_ep->data_pattern_frame = req->data_pattern_frame;
17127 + dwc_ep->sync_frame = req->sync_frame;
17128 +
17129 + dwc_ep->buf_proc_intrvl = req->buf_proc_intrvl;
17130 +
17131 + dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
17132 +
17133 + dwc_ep->proc_buf_num = 0;
17134 +
17135 + dwc_ep->pkt_per_frm = 0;
17136 + frm_data = ep->dwc_ep.data_per_frame;
17137 + while(frm_data > 0) {
17138 + dwc_ep->pkt_per_frm++;
17139 + frm_data -= ep->dwc_ep.maxpacket;
17140 + }
17141 +
17142 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
17143 +
17144 + if(req->flags & USB_REQ_ISO_ASAP) {
17145 + dwc_ep->next_frame = dsts.b.soffn + 1;
17146 + if(dwc_ep->bInterval != 1){
17147 + dwc_ep->next_frame = dwc_ep->next_frame + (dwc_ep->bInterval - 1 - dwc_ep->next_frame % dwc_ep->bInterval);
17148 + }
17149 + } else {
17150 + dwc_ep->next_frame = req->start_frame;
17151 + }
17152 +
17153 +
17154 + if(!core_if->pti_enh_enable) {
17155 + dwc_ep->pkt_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
17156 + } else {
17157 + dwc_ep->pkt_cnt =
17158 + (dwc_ep->data_per_frame * (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
17159 + - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
17160 + }
17161 +
17162 + if(core_if->dma_desc_enable) {
17163 + dwc_ep->desc_cnt =
17164 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
17165 + }
17166 +
17167 + dwc_ep->pkt_info = kmalloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt, GFP_KERNEL);
17168 + if(!dwc_ep->pkt_info) {
17169 + return -ENOMEM;
17170 + }
17171 + if(core_if->pti_enh_enable) {
17172 + memset(dwc_ep->pkt_info, 0, sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
17173 + }
17174 +
17175 + dwc_ep->cur_pkt = 0;
17176 +
17177 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
17178 +
17179 + dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
17180 +
17181 + return 0;
17182 +}
17183 +
17184 +/**
17185 + * This function stops ISO EP Periodic Data Transfer.
17186 + */
17187 +static int dwc_otg_pcd_iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
17188 +{
17189 + dwc_otg_pcd_ep_t *ep;
17190 + dwc_otg_pcd_t *pcd;
17191 + dwc_ep_t *dwc_ep;
17192 + unsigned long flags;
17193 +
17194 + ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
17195 +
17196 + if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
17197 + DWC_WARN("%s, bad ep\n", __func__);
17198 + return -EINVAL;
17199 + }
17200 +
17201 + pcd = ep->pcd;
17202 +
17203 + if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
17204 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
17205 + DWC_WARN("%s, bogus device state\n", __func__);
17206 + return -ESHUTDOWN;
17207 + }
17208 +
17209 + dwc_ep = &ep->dwc_ep;
17210 +
17211 + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
17212 +
17213 + kfree(dwc_ep->pkt_info);
17214 +
17215 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
17216 +
17217 + if(ep->iso_req != req) {
17218 + return -EINVAL;
17219 + }
17220 +
17221 + req->status = -ECONNRESET;
17222 +
17223 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
17224 +
17225 +
17226 + ep->iso_req = 0;
17227 +
17228 + return 0;
17229 +}
17230 +
17231 +/**
17232 + * This function is used for perodical data exchnage between PCD and gadget drivers.
17233 + * for Isochronous EPs
17234 + *
17235 + * - Every time a sync period completes this function is called to
17236 + * perform data exchange between PCD and gadget
17237 + */
17238 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req)
17239 +{
17240 + int i;
17241 + struct usb_gadget_iso_packet_descriptor *iso_packet;
17242 + dwc_ep_t *dwc_ep;
17243 +
17244 + dwc_ep = &ep->dwc_ep;
17245 +
17246 + if(ep->iso_req->status == -ECONNRESET) {
17247 + DWC_PRINT("Device has already disconnected\n");
17248 + /*Device has been disconnected*/
17249 + return;
17250 + }
17251 +
17252 + if(dwc_ep->proc_buf_num != 0) {
17253 + iso_packet = ep->iso_req->iso_packet_desc0;
17254 + }
17255 +
17256 + else {
17257 + iso_packet = ep->iso_req->iso_packet_desc1;
17258 + }
17259 +
17260 + /* Fill in ISOC packets descriptors & pass to gadget driver*/
17261 +
17262 + for(i = 0; i < dwc_ep->pkt_cnt; ++i) {
17263 + iso_packet[i].status = dwc_ep->pkt_info[i].status;
17264 + iso_packet[i].offset = dwc_ep->pkt_info[i].offset;
17265 + iso_packet[i].actual_length = dwc_ep->pkt_info[i].length;
17266 + dwc_ep->pkt_info[i].status = 0;
17267 + dwc_ep->pkt_info[i].offset = 0;
17268 + dwc_ep->pkt_info[i].length = 0;
17269 + }
17270 +
17271 + /* Call callback function to process data buffer */
17272 + ep->iso_req->status = 0;/* success */
17273 +
17274 + SPIN_UNLOCK(&ep->pcd->lock);
17275 + ep->iso_req->process_buffer(&ep->ep, ep->iso_req);
17276 + SPIN_LOCK(&ep->pcd->lock);
17277 +}
17278 +
17279 +
17280 +static struct usb_iso_request *dwc_otg_pcd_alloc_iso_request(struct usb_ep *ep,int packets,
17281 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
17282 + int gfp_flags
17283 +#else
17284 + gfp_t gfp_flags
17285 +#endif
17286 +)
17287 +{
17288 + struct usb_iso_request *pReq = NULL;
17289 + uint32_t req_size;
17290 +
17291 +
17292 + req_size = sizeof(struct usb_iso_request);
17293 + req_size += (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
17294 +
17295 +
17296 + pReq = kmalloc(req_size, gfp_flags);
17297 + if (!pReq) {
17298 + DWC_WARN("%s, can't allocate Iso Request\n", __func__);
17299 + return 0;
17300 + }
17301 + pReq->iso_packet_desc0 = (void*) (pReq + 1);
17302 +
17303 + pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
17304 +
17305 + return pReq;
17306 +}
17307 +
17308 +static void dwc_otg_pcd_free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
17309 +{
17310 + kfree(req);
17311 +}
17312 +
17313 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops =
17314 +{
17315 + .ep_ops =
17316 + {
17317 + .enable = dwc_otg_pcd_ep_enable,
17318 + .disable = dwc_otg_pcd_ep_disable,
17319 +
17320 + .alloc_request = dwc_otg_pcd_alloc_request,
17321 + .free_request = dwc_otg_pcd_free_request,
17322 +
17323 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
17324 + .alloc_buffer = dwc_otg_pcd_alloc_buffer,
17325 + .free_buffer = dwc_otg_pcd_free_buffer,
17326 +#endif
17327 +
17328 + .queue = dwc_otg_pcd_ep_queue,
17329 + .dequeue = dwc_otg_pcd_ep_dequeue,
17330 +
17331 + .set_halt = dwc_otg_pcd_ep_set_halt,
17332 + .fifo_status = 0,
17333 + .fifo_flush = 0,
17334 + },
17335 + .iso_ep_start = dwc_otg_pcd_iso_ep_start,
17336 + .iso_ep_stop = dwc_otg_pcd_iso_ep_stop,
17337 + .alloc_iso_request = dwc_otg_pcd_alloc_iso_request,
17338 + .free_iso_request = dwc_otg_pcd_free_iso_request,
17339 +};
17340 +
17341 +#else
17342 +
17343 +
17344 +static struct usb_ep_ops dwc_otg_pcd_ep_ops =
17345 +{
17346 + .enable = dwc_otg_pcd_ep_enable,
17347 + .disable = dwc_otg_pcd_ep_disable,
17348 +
17349 + .alloc_request = dwc_otg_pcd_alloc_request,
17350 + .free_request = dwc_otg_pcd_free_request,
17351 +
17352 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
17353 + .alloc_buffer = dwc_otg_pcd_alloc_buffer,
17354 + .free_buffer = dwc_otg_pcd_free_buffer,
17355 +#endif
17356 +
17357 + .queue = dwc_otg_pcd_ep_queue,
17358 + .dequeue = dwc_otg_pcd_ep_dequeue,
17359 +
17360 + .set_halt = dwc_otg_pcd_ep_set_halt,
17361 + .fifo_status = 0,
17362 + .fifo_flush = 0,
17363 +
17364 +
17365 +};
17366 +
17367 +#endif /* DWC_EN_ISOC */
17368 +/* Gadget Operations */
17369 +/**
17370 + * The following gadget operations will be implemented in the DWC_otg
17371 + * PCD. Functions in the API that are not described below are not
17372 + * implemented.
17373 + *
17374 + * The Gadget API provides wrapper functions for each of the function
17375 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
17376 + * wrapper function, which then calls the underlying PCD function. The
17377 + * following sections are named according to the wrapper functions
17378 + * (except for ioctl, which doesn't have a wrapper function). Within
17379 + * each section, the corresponding DWC_otg PCD function name is
17380 + * specified.
17381 + *
17382 + */
17383 +
17384 +/**
17385 + *Gets the USB Frame number of the last SOF.
17386 + */
17387 +static int dwc_otg_pcd_get_frame(struct usb_gadget *gadget)
17388 +{
17389 + dwc_otg_pcd_t *pcd;
17390 +
17391 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
17392 +
17393 + if (gadget == 0) {
17394 + return -ENODEV;
17395 + }
17396 + else {
17397 + pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
17398 + dwc_otg_get_frame_number(GET_CORE_IF(pcd));
17399 + }
17400 +
17401 + return 0;
17402 +}
17403 +
17404 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd)
17405 +{
17406 + uint32_t *addr = (uint32_t *)&(GET_CORE_IF(pcd)->core_global_regs->gotgctl);
17407 + gotgctl_data_t mem;
17408 + gotgctl_data_t val;
17409 +
17410 + val.d32 = dwc_read_reg32(addr);
17411 + if (val.b.sesreq) {
17412 + DWC_ERROR("Session Request Already active!\n");
17413 + return;
17414 + }
17415 +
17416 + DWC_NOTICE("Session Request Initated\n");
17417 + mem.d32 = dwc_read_reg32(addr);
17418 + mem.b.sesreq = 1;
17419 + dwc_write_reg32(addr, mem.d32);
17420 +
17421 + /* Start the SRP timer */
17422 + dwc_otg_pcd_start_srp_timer(pcd);
17423 + return;
17424 +}
17425 +
17426 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set)
17427 +{
17428 + dctl_data_t dctl = {.d32=0};
17429 + volatile uint32_t *addr = &(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dctl);
17430 +
17431 + if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
17432 + if (pcd->remote_wakeup_enable) {
17433 + if (set) {
17434 + dctl.b.rmtwkupsig = 1;
17435 + dwc_modify_reg32(addr, 0, dctl.d32);
17436 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
17437 + mdelay(1);
17438 + dwc_modify_reg32(addr, dctl.d32, 0);
17439 + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
17440 + }
17441 + else {
17442 + }
17443 + }
17444 + else {
17445 + DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
17446 + }
17447 + }
17448 + return;
17449 +}
17450 +
17451 +/**
17452 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
17453 + * session is in progress. If a session is already in progress, but
17454 + * the device is suspended, remote wakeup signaling is started.
17455 + *
17456 + */
17457 +static int dwc_otg_pcd_wakeup(struct usb_gadget *gadget)
17458 +{
17459 + unsigned long flags;
17460 + dwc_otg_pcd_t *pcd;
17461 + dsts_data_t dsts;
17462 + gotgctl_data_t gotgctl;
17463 +
17464 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
17465 +
17466 + if (gadget == 0) {
17467 + return -ENODEV;
17468 + }
17469 + else {
17470 + pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
17471 + }
17472 + SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
17473 +
17474 + /*
17475 + * This function starts the Protocol if no session is in progress. If
17476 + * a session is already in progress, but the device is suspended,
17477 + * remote wakeup signaling is started.
17478 + */
17479 +
17480 + /* Check if valid session */
17481 + gotgctl.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
17482 + if (gotgctl.b.bsesvld) {
17483 + /* Check if suspend state */
17484 + dsts.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts));
17485 + if (dsts.b.suspsts) {
17486 + dwc_otg_pcd_remote_wakeup(pcd, 1);
17487 + }
17488 + }
17489 + else {
17490 + dwc_otg_pcd_initiate_srp(pcd);
17491 + }
17492 +
17493 + SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
17494 + return 0;
17495 +}
17496 +
17497 +static const struct usb_gadget_ops dwc_otg_pcd_ops =
17498 +{
17499 + .get_frame = dwc_otg_pcd_get_frame,
17500 + .wakeup = dwc_otg_pcd_wakeup,
17501 + // current versions must always be self-powered
17502 +};
17503 +
17504 +/**
17505 + * This function updates the otg values in the gadget structure.
17506 + */
17507 +void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset)
17508 +{
17509 +
17510 + if (!pcd->gadget.is_otg)
17511 + return;
17512 +
17513 + if (reset) {
17514 + pcd->b_hnp_enable = 0;
17515 + pcd->a_hnp_support = 0;
17516 + pcd->a_alt_hnp_support = 0;
17517 + }
17518 +
17519 + pcd->gadget.b_hnp_enable = pcd->b_hnp_enable;
17520 + pcd->gadget.a_hnp_support = pcd->a_hnp_support;
17521 + pcd->gadget.a_alt_hnp_support = pcd->a_alt_hnp_support;
17522 +}
17523 +
17524 +/**
17525 + * This function is the top level PCD interrupt handler.
17526 + */
17527 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev
17528 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
17529 + , struct pt_regs *r
17530 +#endif
17531 + )
17532 +{
17533 + dwc_otg_pcd_t *pcd = dev;
17534 + int32_t retval = IRQ_NONE;
17535 +
17536 + retval = dwc_otg_pcd_handle_intr(pcd);
17537 + return IRQ_RETVAL(retval);
17538 +}
17539 +
17540 +/**
17541 + * PCD Callback function for initializing the PCD when switching to
17542 + * device mode.
17543 + *
17544 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17545 + */
17546 +static int32_t dwc_otg_pcd_start_cb(void *p)
17547 +{
17548 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17549 +
17550 + /*
17551 + * Initialized the Core for Device mode.
17552 + */
17553 + if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
17554 + dwc_otg_core_dev_init(GET_CORE_IF(pcd));
17555 + }
17556 + return 1;
17557 +}
17558 +
17559 +/**
17560 + * PCD Callback function for stopping the PCD when switching to Host
17561 + * mode.
17562 + *
17563 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17564 + */
17565 +static int32_t dwc_otg_pcd_stop_cb(void *p)
17566 +{
17567 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17568 + extern void dwc_otg_pcd_stop(dwc_otg_pcd_t *_pcd);
17569 +
17570 + dwc_otg_pcd_stop(pcd);
17571 + return 1;
17572 +}
17573 +
17574 +
17575 +/**
17576 + * PCD Callback function for notifying the PCD when resuming from
17577 + * suspend.
17578 + *
17579 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17580 + */
17581 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
17582 +{
17583 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17584 +
17585 + if (pcd->driver && pcd->driver->resume) {
17586 + SPIN_UNLOCK(&pcd->lock);
17587 + pcd->driver->suspend(&pcd->gadget);
17588 + SPIN_LOCK(&pcd->lock);
17589 + }
17590 +
17591 + return 1;
17592 +}
17593 +
17594 +
17595 +/**
17596 + * PCD Callback function for notifying the PCD when resuming from
17597 + * suspend.
17598 + *
17599 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
17600 + */
17601 +static int32_t dwc_otg_pcd_resume_cb(void *p)
17602 +{
17603 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
17604 +
17605 + if (pcd->driver && pcd->driver->resume) {
17606 + SPIN_UNLOCK(&pcd->lock);
17607 + pcd->driver->resume(&pcd->gadget);
17608 + SPIN_LOCK(&pcd->lock);
17609 + }
17610 +
17611 + /* Stop the SRP timeout timer. */
17612 + if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ||
17613 + (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
17614 + if (GET_CORE_IF(pcd)->srp_timer_started) {
17615 + GET_CORE_IF(pcd)->srp_timer_started = 0;
17616 + del_timer(&pcd->srp_timer);
17617 + }
17618 + }
17619 + return 1;
17620 +}
17621 +
17622 +
17623 +/**
17624 + * PCD Callback structure for handling mode switching.
17625 + */
17626 +static dwc_otg_cil_callbacks_t pcd_callbacks =
17627 +{
17628 + .start = dwc_otg_pcd_start_cb,
17629 + .stop = dwc_otg_pcd_stop_cb,
17630 + .suspend = dwc_otg_pcd_suspend_cb,
17631 + .resume_wakeup = dwc_otg_pcd_resume_cb,
17632 + .p = 0, /* Set at registration */
17633 +};
17634 +
17635 +/**
17636 + * This function is called when the SRP timer expires. The SRP should
17637 + * complete within 6 seconds.
17638 + */
17639 +static void srp_timeout(unsigned long ptr)
17640 +{
17641 + gotgctl_data_t gotgctl;
17642 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)ptr;
17643 + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
17644 +
17645 + gotgctl.d32 = dwc_read_reg32(addr);
17646 +
17647 + core_if->srp_timer_started = 0;
17648 +
17649 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
17650 + (core_if->core_params->i2c_enable)) {
17651 + DWC_PRINT("SRP Timeout\n");
17652 +
17653 + if ((core_if->srp_success) &&
17654 + (gotgctl.b.bsesvld)) {
17655 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
17656 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
17657 + }
17658 +
17659 + /* Clear Session Request */
17660 + gotgctl.d32 = 0;
17661 + gotgctl.b.sesreq = 1;
17662 + dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
17663 + gotgctl.d32, 0);
17664 +
17665 + core_if->srp_success = 0;
17666 + }
17667 + else {
17668 + DWC_ERROR("Device not connected/responding\n");
17669 + gotgctl.b.sesreq = 0;
17670 + dwc_write_reg32(addr, gotgctl.d32);
17671 + }
17672 + }
17673 + else if (gotgctl.b.sesreq) {
17674 + DWC_PRINT("SRP Timeout\n");
17675 +
17676 + DWC_ERROR("Device not connected/responding\n");
17677 + gotgctl.b.sesreq = 0;
17678 + dwc_write_reg32(addr, gotgctl.d32);
17679 + }
17680 + else {
17681 + DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl.d32);
17682 + }
17683 +}
17684 +
17685 +/**
17686 + * Start the SRP timer to detect when the SRP does not complete within
17687 + * 6 seconds.
17688 + *
17689 + * @param pcd the pcd structure.
17690 + */
17691 +void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd)
17692 +{
17693 + struct timer_list *srp_timer = &pcd->srp_timer;
17694 + GET_CORE_IF(pcd)->srp_timer_started = 1;
17695 + init_timer(srp_timer);
17696 + srp_timer->function = srp_timeout;
17697 + srp_timer->data = (unsigned long)GET_CORE_IF(pcd);
17698 + srp_timer->expires = jiffies + (HZ*6);
17699 + add_timer(srp_timer);
17700 +}
17701 +
17702 +/**
17703 + * Tasklet
17704 + *
17705 + */
17706 +extern void start_next_request(dwc_otg_pcd_ep_t *ep);
17707 +
17708 +static void start_xfer_tasklet_func (unsigned long data)
17709 +{
17710 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t*)data;
17711 + dwc_otg_core_if_t *core_if = pcd->otg_dev->core_if;
17712 +
17713 + int i;
17714 + depctl_data_t diepctl;
17715 +
17716 + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
17717 +
17718 + diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
17719 +
17720 + if (pcd->ep0.queue_sof) {
17721 + pcd->ep0.queue_sof = 0;
17722 + start_next_request (&pcd->ep0);
17723 + // break;
17724 + }
17725 +
17726 + for (i=0; i<core_if->dev_if->num_in_eps; i++)
17727 + {
17728 + depctl_data_t diepctl;
17729 + diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
17730 +
17731 + if (pcd->in_ep[i].queue_sof) {
17732 + pcd->in_ep[i].queue_sof = 0;
17733 + start_next_request (&pcd->in_ep[i]);
17734 + // break;
17735 + }
17736 + }
17737 +
17738 + return;
17739 +}
17740 +
17741 +
17742 +
17743 +
17744 +
17745 +
17746 +
17747 +static struct tasklet_struct start_xfer_tasklet = {
17748 + .next = NULL,
17749 + .state = 0,
17750 + .count = ATOMIC_INIT(0),
17751 + .func = start_xfer_tasklet_func,
17752 + .data = 0,
17753 +};
17754 +/**
17755 + * This function initialized the pcd Dp structures to there default
17756 + * state.
17757 + *
17758 + * @param pcd the pcd structure.
17759 + */
17760 +void dwc_otg_pcd_reinit(dwc_otg_pcd_t *pcd)
17761 +{
17762 + static const char * names[] =
17763 + {
17764 +
17765 + "ep0",
17766 + "ep1in",
17767 + "ep2in",
17768 + "ep3in",
17769 + "ep4in",
17770 + "ep5in",
17771 + "ep6in",
17772 + "ep7in",
17773 + "ep8in",
17774 + "ep9in",
17775 + "ep10in",
17776 + "ep11in",
17777 + "ep12in",
17778 + "ep13in",
17779 + "ep14in",
17780 + "ep15in",
17781 + "ep1out",
17782 + "ep2out",
17783 + "ep3out",
17784 + "ep4out",
17785 + "ep5out",
17786 + "ep6out",
17787 + "ep7out",
17788 + "ep8out",
17789 + "ep9out",
17790 + "ep10out",
17791 + "ep11out",
17792 + "ep12out",
17793 + "ep13out",
17794 + "ep14out",
17795 + "ep15out"
17796 +
17797 + };
17798 +
17799 + int i;
17800 + int in_ep_cntr, out_ep_cntr;
17801 + uint32_t hwcfg1;
17802 + uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
17803 + uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
17804 + dwc_otg_pcd_ep_t *ep;
17805 +
17806 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
17807 +
17808 + INIT_LIST_HEAD (&pcd->gadget.ep_list);
17809 + pcd->gadget.ep0 = &pcd->ep0.ep;
17810 + pcd->gadget.speed = USB_SPEED_UNKNOWN;
17811 +
17812 + INIT_LIST_HEAD (&pcd->gadget.ep0->ep_list);
17813 +
17814 + /**
17815 + * Initialize the EP0 structure.
17816 + */
17817 + ep = &pcd->ep0;
17818 +
17819 + /* Init EP structure */
17820 + ep->desc = 0;
17821 + ep->pcd = pcd;
17822 + ep->stopped = 1;
17823 +
17824 + /* Init DWC ep structure */
17825 + ep->dwc_ep.num = 0;
17826 + ep->dwc_ep.active = 0;
17827 + ep->dwc_ep.tx_fifo_num = 0;
17828 + /* Control until ep is actvated */
17829 + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17830 + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
17831 + ep->dwc_ep.dma_addr = 0;
17832 + ep->dwc_ep.start_xfer_buff = 0;
17833 + ep->dwc_ep.xfer_buff = 0;
17834 + ep->dwc_ep.xfer_len = 0;
17835 + ep->dwc_ep.xfer_count = 0;
17836 + ep->dwc_ep.sent_zlp = 0;
17837 + ep->dwc_ep.total_len = 0;
17838 + ep->queue_sof = 0;
17839 + ep->dwc_ep.desc_addr = 0;
17840 + ep->dwc_ep.dma_desc_addr = 0;
17841 +
17842 +
17843 + /* Init the usb_ep structure. */
17844 + ep->ep.name = names[0];
17845 + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
17846 +
17847 + /**
17848 + * @todo NGS: What should the max packet size be set to
17849 + * here? Before EP type is set?
17850 + */
17851 + ep->ep.maxpacket = MAX_PACKET_SIZE;
17852 +
17853 + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
17854 +
17855 + INIT_LIST_HEAD (&ep->queue);
17856 + /**
17857 + * Initialize the EP structures.
17858 + */
17859 + in_ep_cntr = 0;
17860 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
17861 +
17862 + for (i = 1; in_ep_cntr < num_in_eps; i++)
17863 + {
17864 + if((hwcfg1 & 0x1) == 0) {
17865 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
17866 + in_ep_cntr ++;
17867 +
17868 + /* Init EP structure */
17869 + ep->desc = 0;
17870 + ep->pcd = pcd;
17871 + ep->stopped = 1;
17872 +
17873 + /* Init DWC ep structure */
17874 + ep->dwc_ep.is_in = 1;
17875 + ep->dwc_ep.num = i;
17876 + ep->dwc_ep.active = 0;
17877 + ep->dwc_ep.tx_fifo_num = 0;
17878 +
17879 + /* Control until ep is actvated */
17880 + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17881 + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
17882 + ep->dwc_ep.dma_addr = 0;
17883 + ep->dwc_ep.start_xfer_buff = 0;
17884 + ep->dwc_ep.xfer_buff = 0;
17885 + ep->dwc_ep.xfer_len = 0;
17886 + ep->dwc_ep.xfer_count = 0;
17887 + ep->dwc_ep.sent_zlp = 0;
17888 + ep->dwc_ep.total_len = 0;
17889 + ep->queue_sof = 0;
17890 + ep->dwc_ep.desc_addr = 0;
17891 + ep->dwc_ep.dma_desc_addr = 0;
17892 +
17893 + /* Init the usb_ep structure. */
17894 + ep->ep.name = names[i];
17895 + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
17896 +
17897 + /**
17898 + * @todo NGS: What should the max packet size be set to
17899 + * here? Before EP type is set?
17900 + */
17901 + ep->ep.maxpacket = MAX_PACKET_SIZE;
17902 +
17903 + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
17904 +
17905 + INIT_LIST_HEAD (&ep->queue);
17906 + }
17907 + hwcfg1 >>= 2;
17908 + }
17909 +
17910 + out_ep_cntr = 0;
17911 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
17912 +
17913 + for (i = 1; out_ep_cntr < num_out_eps; i++)
17914 + {
17915 + if((hwcfg1 & 0x1) == 0) {
17916 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
17917 + out_ep_cntr++;
17918 +
17919 + /* Init EP structure */
17920 + ep->desc = 0;
17921 + ep->pcd = pcd;
17922 + ep->stopped = 1;
17923 +
17924 + /* Init DWC ep structure */
17925 + ep->dwc_ep.is_in = 0;
17926 + ep->dwc_ep.num = i;
17927 + ep->dwc_ep.active = 0;
17928 + ep->dwc_ep.tx_fifo_num = 0;
17929 + /* Control until ep is actvated */
17930 + ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17931 + ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
17932 + ep->dwc_ep.dma_addr = 0;
17933 + ep->dwc_ep.start_xfer_buff = 0;
17934 + ep->dwc_ep.xfer_buff = 0;
17935 + ep->dwc_ep.xfer_len = 0;
17936 + ep->dwc_ep.xfer_count = 0;
17937 + ep->dwc_ep.sent_zlp = 0;
17938 + ep->dwc_ep.total_len = 0;
17939 + ep->queue_sof = 0;
17940 +
17941 + /* Init the usb_ep structure. */
17942 + ep->ep.name = names[15 + i];
17943 + ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
17944 + /**
17945 + * @todo NGS: What should the max packet size be set to
17946 + * here? Before EP type is set?
17947 + */
17948 + ep->ep.maxpacket = MAX_PACKET_SIZE;
17949 +
17950 + list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
17951 +
17952 + INIT_LIST_HEAD (&ep->queue);
17953 + }
17954 + hwcfg1 >>= 2;
17955 + }
17956 +
17957 + /* remove ep0 from the list. There is a ep0 pointer.*/
17958 + list_del_init (&pcd->ep0.ep.ep_list);
17959 +
17960 + pcd->ep0state = EP0_DISCONNECT;
17961 + pcd->ep0.ep.maxpacket = MAX_EP0_SIZE;
17962 + pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
17963 + pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
17964 +}
17965 +
17966 +/**
17967 + * This function releases the Gadget device.
17968 + * required by device_unregister().
17969 + *
17970 + * @todo Should this do something? Should it free the PCD?
17971 + */
17972 +static void dwc_otg_pcd_gadget_release(struct device *dev)
17973 +{
17974 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, dev);
17975 +}
17976 +
17977 +
17978 +
17979 +/**
17980 + * This function initialized the PCD portion of the driver.
17981 + *
17982 + */
17983 +
17984 +int dwc_otg_pcd_init(struct device *dev)
17985 +{
17986 + static char pcd_name[] = "dwc_otg_pcd";
17987 + dwc_otg_pcd_t *pcd;
17988 + dwc_otg_core_if_t* core_if;
17989 + dwc_otg_dev_if_t* dev_if;
17990 + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
17991 + int retval = 0;
17992 +
17993 +
17994 + DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n",__func__, dev);
17995 + /*
17996 + * Allocate PCD structure
17997 + */
17998 + pcd = kmalloc(sizeof(dwc_otg_pcd_t), GFP_KERNEL);
17999 +
18000 + if (pcd == 0) {
18001 + return -ENOMEM;
18002 + }
18003 +
18004 + memset(pcd, 0, sizeof(dwc_otg_pcd_t));
18005 + spin_lock_init(&pcd->lock);
18006 +
18007 + otg_dev->pcd = pcd;
18008 + s_pcd = pcd;
18009 + pcd->gadget.name = pcd_name;
18010 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
18011 + strcpy(pcd->gadget.dev.bus_id, "gadget");
18012 +#else
18013 + dev_set_name(&pcd->gadget.dev, "%s", "gadget");
18014 +#endif
18015 +
18016 + pcd->otg_dev = dev_get_drvdata(dev);
18017 +
18018 + pcd->gadget.dev.parent = dev;
18019 + pcd->gadget.dev.release = dwc_otg_pcd_gadget_release;
18020 + pcd->gadget.ops = &dwc_otg_pcd_ops;
18021 +
18022 + core_if = GET_CORE_IF(pcd);
18023 + dev_if = core_if->dev_if;
18024 +
18025 + if(core_if->hwcfg4.b.ded_fifo_en) {
18026 + DWC_PRINT("Dedicated Tx FIFOs mode\n");
18027 + }
18028 + else {
18029 + DWC_PRINT("Shared Tx FIFO mode\n");
18030 + }
18031 +
18032 + /* If the module is set to FS or if the PHY_TYPE is FS then the gadget
18033 + * should not report as dual-speed capable. replace the following line
18034 + * with the block of code below it once the software is debugged for
18035 + * this. If is_dualspeed = 0 then the gadget driver should not report
18036 + * a device qualifier descriptor when queried. */
18037 + if ((GET_CORE_IF(pcd)->core_params->speed == DWC_SPEED_PARAM_FULL) ||
18038 + ((GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == 2) &&
18039 + (GET_CORE_IF(pcd)->hwcfg2.b.fs_phy_type == 1) &&
18040 + (GET_CORE_IF(pcd)->core_params->ulpi_fs_ls))) {
18041 + pcd->gadget.is_dualspeed = 0;
18042 + }
18043 + else {
18044 + pcd->gadget.is_dualspeed = 1;
18045 + }
18046 +
18047 + if ((otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE) ||
18048 + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST) ||
18049 + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
18050 + (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
18051 + pcd->gadget.is_otg = 0;
18052 + }
18053 + else {
18054 + pcd->gadget.is_otg = 1;
18055 + }
18056 +
18057 +
18058 + pcd->driver = 0;
18059 + /* Register the gadget device */
18060 + retval = device_register(&pcd->gadget.dev);
18061 + if (retval != 0) {
18062 + kfree (pcd);
18063 + return retval;
18064 + }
18065 +
18066 +
18067 + /*
18068 + * Initialized the Core for Device mode.
18069 + */
18070 + if (dwc_otg_is_device_mode(core_if)) {
18071 + dwc_otg_core_dev_init(core_if);
18072 + }
18073 +
18074 + /*
18075 + * Initialize EP structures
18076 + */
18077 + dwc_otg_pcd_reinit(pcd);
18078 +
18079 + /*
18080 + * Register the PCD Callbacks.
18081 + */
18082 + dwc_otg_cil_register_pcd_callbacks(otg_dev->core_if, &pcd_callbacks,
18083 + pcd);
18084 + /*
18085 + * Setup interupt handler
18086 + */
18087 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", otg_dev->irq);
18088 + retval = request_irq(otg_dev->irq, dwc_otg_pcd_irq,
18089 + IRQF_SHARED, pcd->gadget.name, pcd);
18090 + if (retval != 0) {
18091 + DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
18092 + device_unregister(&pcd->gadget.dev);
18093 + kfree (pcd);
18094 + return -EBUSY;
18095 + }
18096 +
18097 + /*
18098 + * Initialize the DMA buffer for SETUP packets
18099 + */
18100 + if (GET_CORE_IF(pcd)->dma_enable) {
18101 + pcd->setup_pkt = dma_alloc_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, &pcd->setup_pkt_dma_handle, 0);
18102 + if (pcd->setup_pkt == 0) {
18103 + free_irq(otg_dev->irq, pcd);
18104 + device_unregister(&pcd->gadget.dev);
18105 + kfree (pcd);
18106 + return -ENOMEM;
18107 + }
18108 +
18109 + pcd->status_buf = dma_alloc_coherent (NULL, sizeof (uint16_t), &pcd->status_buf_dma_handle, 0);
18110 + if (pcd->status_buf == 0) {
18111 + dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
18112 + free_irq(otg_dev->irq, pcd);
18113 + device_unregister(&pcd->gadget.dev);
18114 + kfree (pcd);
18115 + return -ENOMEM;
18116 + }
18117 +
18118 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
18119 + dev_if->setup_desc_addr[0] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[0], 1);
18120 + dev_if->setup_desc_addr[1] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[1], 1);
18121 + dev_if->in_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_in_desc_addr, 1);
18122 + dev_if->out_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_out_desc_addr, 1);
18123 +
18124 + if(dev_if->setup_desc_addr[0] == 0
18125 + || dev_if->setup_desc_addr[1] == 0
18126 + || dev_if->in_desc_addr == 0
18127 + || dev_if->out_desc_addr == 0 ) {
18128 +
18129 + if(dev_if->out_desc_addr)
18130 + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
18131 + if(dev_if->in_desc_addr)
18132 + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
18133 + if(dev_if->setup_desc_addr[1])
18134 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
18135 + if(dev_if->setup_desc_addr[0])
18136 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
18137 +
18138 +
18139 + dma_free_coherent(NULL, sizeof(*pcd->status_buf), pcd->status_buf, pcd->setup_pkt_dma_handle);
18140 + dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
18141 +
18142 + free_irq(otg_dev->irq, pcd);
18143 + device_unregister(&pcd->gadget.dev);
18144 + kfree (pcd);
18145 +
18146 + return -ENOMEM;
18147 + }
18148 + }
18149 + }
18150 + else {
18151 + pcd->setup_pkt = kmalloc (sizeof (*pcd->setup_pkt) * 5, GFP_KERNEL);
18152 + if (pcd->setup_pkt == 0) {
18153 + free_irq(otg_dev->irq, pcd);
18154 + device_unregister(&pcd->gadget.dev);
18155 + kfree (pcd);
18156 + return -ENOMEM;
18157 + }
18158 +
18159 + pcd->status_buf = kmalloc (sizeof (uint16_t), GFP_KERNEL);
18160 + if (pcd->status_buf == 0) {
18161 + kfree(pcd->setup_pkt);
18162 + free_irq(otg_dev->irq, pcd);
18163 + device_unregister(&pcd->gadget.dev);
18164 + kfree (pcd);
18165 + return -ENOMEM;
18166 + }
18167 + }
18168 +
18169 +
18170 + /* Initialize tasklet */
18171 + start_xfer_tasklet.data = (unsigned long)pcd;
18172 + pcd->start_xfer_tasklet = &start_xfer_tasklet;
18173 +
18174 + return 0;
18175 +}
18176 +
18177 +/**
18178 + * Cleanup the PCD.
18179 + */
18180 +void dwc_otg_pcd_remove(struct device *dev)
18181 +{
18182 + dwc_otg_device_t *otg_dev = dev_get_drvdata(dev);
18183 + dwc_otg_pcd_t *pcd = otg_dev->pcd;
18184 + dwc_otg_dev_if_t* dev_if = GET_CORE_IF(pcd)->dev_if;
18185 +
18186 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
18187 +
18188 + /*
18189 + * Free the IRQ
18190 + */
18191 + free_irq(otg_dev->irq, pcd);
18192 +
18193 + /* start with the driver above us */
18194 + if (pcd->driver) {
18195 + /* should have been done already by driver model core */
18196 + DWC_WARN("driver '%s' is still registered\n",
18197 + pcd->driver->driver.name);
18198 + usb_gadget_unregister_driver(pcd->driver);
18199 + }
18200 + device_unregister(&pcd->gadget.dev);
18201 +
18202 + if (GET_CORE_IF(pcd)->dma_enable) {
18203 + dma_free_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, pcd->setup_pkt, pcd->setup_pkt_dma_handle);
18204 + dma_free_coherent (NULL, sizeof (uint16_t), pcd->status_buf, pcd->status_buf_dma_handle);
18205 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
18206 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
18207 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
18208 + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
18209 + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
18210 + }
18211 + }
18212 + else {
18213 + kfree (pcd->setup_pkt);
18214 + kfree (pcd->status_buf);
18215 + }
18216 +
18217 + kfree(pcd);
18218 + otg_dev->pcd = 0;
18219 +}
18220 +
18221 +/**
18222 + * This function registers a gadget driver with the PCD.
18223 + *
18224 + * When a driver is successfully registered, it will receive control
18225 + * requests including set_configuration(), which enables non-control
18226 + * requests. then usb traffic follows until a disconnect is reported.
18227 + * then a host may connect again, or the driver might get unbound.
18228 + *
18229 + * @param driver The driver being registered
18230 + */
18231 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)
18232 +int usb_gadget_probe_driver(struct usb_gadget_driver *driver, int (*bind)(struct usb_gadget *))
18233 +#else
18234 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
18235 +#endif
18236 +{
18237 + int retval;
18238 + int (*d_bind)(struct usb_gadget *);
18239 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)
18240 + d_bind = bind;
18241 +#else
18242 + d_bind = driver->bind;
18243 +#endif
18244 +
18245 + DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", driver->driver.name);
18246 +
18247 + if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
18248 + !d_bind ||
18249 + !driver->unbind ||
18250 + !driver->disconnect ||
18251 + !driver->setup) {
18252 + DWC_DEBUGPL(DBG_PCDV,"EINVAL\n");
18253 + return -EINVAL;
18254 + }
18255 + if (s_pcd == 0) {
18256 + DWC_DEBUGPL(DBG_PCDV,"ENODEV\n");
18257 + return -ENODEV;
18258 + }
18259 + if (s_pcd->driver != 0) {
18260 + DWC_DEBUGPL(DBG_PCDV,"EBUSY (%p)\n", s_pcd->driver);
18261 + return -EBUSY;
18262 + }
18263 +
18264 + /* hook up the driver */
18265 + s_pcd->driver = driver;
18266 + s_pcd->gadget.dev.driver = &driver->driver;
18267 +
18268 + DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
18269 + retval = d_bind(&s_pcd->gadget);
18270 + if (retval) {
18271 + DWC_ERROR("bind to driver %s --> error %d\n",
18272 + driver->driver.name, retval);
18273 + s_pcd->driver = 0;
18274 + s_pcd->gadget.dev.driver = 0;
18275 + return retval;
18276 + }
18277 + DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
18278 + driver->driver.name);
18279 + return 0;
18280 +}
18281 +
18282 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)
18283 +EXPORT_SYMBOL(usb_gadget_probe_driver);
18284 +#else
18285 +EXPORT_SYMBOL(usb_gadget_register_driver);
18286 +#endif
18287 +
18288 +/**
18289 + * This function unregisters a gadget driver
18290 + *
18291 + * @param driver The driver being unregistered
18292 + */
18293 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
18294 +{
18295 + //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
18296 +
18297 + if (s_pcd == 0) {
18298 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
18299 + -ENODEV);
18300 + return -ENODEV;
18301 + }
18302 + if (driver == 0 || driver != s_pcd->driver) {
18303 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
18304 + -EINVAL);
18305 + return -EINVAL;
18306 + }
18307 +
18308 + driver->unbind(&s_pcd->gadget);
18309 + s_pcd->driver = 0;
18310 +
18311 + DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n",
18312 + driver->driver.name);
18313 + return 0;
18314 +}
18315 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
18316 +
18317 +#endif /* DWC_HOST_ONLY */
18318 diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.h b/drivers/usb/dwc_otg/dwc_otg_pcd.h
18319 new file mode 100644
18320 index 0000000..48de957
18321 --- /dev/null
18322 +++ b/drivers/usb/dwc_otg/dwc_otg_pcd.h
18323 @@ -0,0 +1,248 @@
18324 +/* ==========================================================================
18325 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
18326 + * $Revision: 1.2 $
18327 + * $Date: 2008-11-21 05:39:15 $
18328 + * $Change: 1103515 $
18329 + *
18330 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18331 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18332 + * otherwise expressly agreed to in writing between Synopsys and you.
18333 + *
18334 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18335 + * any End User Software License Agreement or Agreement for Licensed Product
18336 + * with Synopsys or any supplement thereto. You are permitted to use and
18337 + * redistribute this Software in source and binary forms, with or without
18338 + * modification, provided that redistributions of source code must retain this
18339 + * notice. You may not view, use, disclose, copy or distribute this file or
18340 + * any information contained herein except pursuant to this license grant from
18341 + * Synopsys. If you do not agree with this notice, including the disclaimer
18342 + * below, then you are not authorized to use the Software.
18343 + *
18344 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18345 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18346 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18347 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18348 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18349 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18350 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18351 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18352 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18353 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18354 + * DAMAGE.
18355 + * ========================================================================== */
18356 +#ifndef DWC_HOST_ONLY
18357 +#if !defined(__DWC_PCD_H__)
18358 +#define __DWC_PCD_H__
18359 +
18360 +#include <linux/types.h>
18361 +#include <linux/list.h>
18362 +#include <linux/errno.h>
18363 +#include <linux/device.h>
18364 +
18365 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
18366 +# include <linux/usb/ch9.h>
18367 +#else
18368 +# include <linux/usb_ch9.h>
18369 +#endif
18370 +
18371 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
18372 +#include <linux/usb/gadget.h>
18373 +#else
18374 +#include <linux/usb_gadget.h>
18375 +#endif
18376 +#include <linux/interrupt.h>
18377 +#include <linux/dma-mapping.h>
18378 +
18379 +struct dwc_otg_device;
18380 +
18381 +#include "dwc_otg_cil.h"
18382 +
18383 +/**
18384 + * @file
18385 + *
18386 + * This file contains the structures, constants, and interfaces for
18387 + * the Perpherial Contoller Driver (PCD).
18388 + *
18389 + * The Peripheral Controller Driver (PCD) for Linux will implement the
18390 + * Gadget API, so that the existing Gadget drivers can be used. For
18391 + * the Mass Storage Function driver the File-backed USB Storage Gadget
18392 + * (FBS) driver will be used. The FBS driver supports the
18393 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
18394 + * transports.
18395 + *
18396 + */
18397 +
18398 +/** Invalid DMA Address */
18399 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
18400 +/** Maxpacket size for EP0 */
18401 +#define MAX_EP0_SIZE 64
18402 +/** Maxpacket size for any EP */
18403 +#define MAX_PACKET_SIZE 1024
18404 +
18405 +/** Max Transfer size for any EP */
18406 +#define MAX_TRANSFER_SIZE 65535
18407 +
18408 +/** Max DMA Descriptor count for any EP */
18409 +#define MAX_DMA_DESC_CNT 64
18410 +
18411 +/**
18412 + * Get the pointer to the core_if from the pcd pointer.
18413 + */
18414 +#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if)
18415 +
18416 +/**
18417 + * States of EP0.
18418 + */
18419 +typedef enum ep0_state
18420 +{
18421 + EP0_DISCONNECT, /* no host */
18422 + EP0_IDLE,
18423 + EP0_IN_DATA_PHASE,
18424 + EP0_OUT_DATA_PHASE,
18425 + EP0_IN_STATUS_PHASE,
18426 + EP0_OUT_STATUS_PHASE,
18427 + EP0_STALL,
18428 +} ep0state_e;
18429 +
18430 +/** Fordward declaration.*/
18431 +struct dwc_otg_pcd;
18432 +
18433 +/** DWC_otg iso request structure.
18434 + *
18435 + */
18436 +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
18437 +
18438 +/** PCD EP structure.
18439 + * This structure describes an EP, there is an array of EPs in the PCD
18440 + * structure.
18441 + */
18442 +typedef struct dwc_otg_pcd_ep
18443 +{
18444 + /** USB EP data */
18445 + struct usb_ep ep;
18446 + /** USB EP Descriptor */
18447 + const struct usb_endpoint_descriptor *desc;
18448 +
18449 + /** queue of dwc_otg_pcd_requests. */
18450 + struct list_head queue;
18451 + unsigned stopped : 1;
18452 + unsigned disabling : 1;
18453 + unsigned dma : 1;
18454 + unsigned queue_sof : 1;
18455 +
18456 +#ifdef DWC_EN_ISOC
18457 + /** DWC_otg Isochronous Transfer */
18458 + struct usb_iso_request* iso_req;
18459 +#endif //DWC_EN_ISOC
18460 +
18461 + /** DWC_otg ep data. */
18462 + dwc_ep_t dwc_ep;
18463 +
18464 + /** Pointer to PCD */
18465 + struct dwc_otg_pcd *pcd;
18466 +}dwc_otg_pcd_ep_t;
18467 +
18468 +
18469 +
18470 +/** DWC_otg PCD Structure.
18471 + * This structure encapsulates the data for the dwc_otg PCD.
18472 + */
18473 +typedef struct dwc_otg_pcd
18474 +{
18475 + /** USB gadget */
18476 + struct usb_gadget gadget;
18477 + /** USB gadget driver pointer*/
18478 + struct usb_gadget_driver *driver;
18479 + /** The DWC otg device pointer. */
18480 + struct dwc_otg_device *otg_dev;
18481 +
18482 + /** State of EP0 */
18483 + ep0state_e ep0state;
18484 + /** EP0 Request is pending */
18485 + unsigned ep0_pending : 1;
18486 + /** Indicates when SET CONFIGURATION Request is in process */
18487 + unsigned request_config : 1;
18488 + /** The state of the Remote Wakeup Enable. */
18489 + unsigned remote_wakeup_enable : 1;
18490 + /** The state of the B-Device HNP Enable. */
18491 + unsigned b_hnp_enable : 1;
18492 + /** The state of A-Device HNP Support. */
18493 + unsigned a_hnp_support : 1;
18494 + /** The state of the A-Device Alt HNP support. */
18495 + unsigned a_alt_hnp_support : 1;
18496 + /** Count of pending Requests */
18497 + unsigned request_pending;
18498 +
18499 + /** SETUP packet for EP0
18500 + * This structure is allocated as a DMA buffer on PCD initialization
18501 + * with enough space for up to 3 setup packets.
18502 + */
18503 + union
18504 + {
18505 + struct usb_ctrlrequest req;
18506 + uint32_t d32[2];
18507 + } *setup_pkt;
18508 +
18509 + dma_addr_t setup_pkt_dma_handle;
18510 +
18511 + /** 2-byte dma buffer used to return status from GET_STATUS */
18512 + uint16_t *status_buf;
18513 + dma_addr_t status_buf_dma_handle;
18514 +
18515 + /** EP0 */
18516 + dwc_otg_pcd_ep_t ep0;
18517 +
18518 + /** Array of IN EPs. */
18519 + dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1];
18520 + /** Array of OUT EPs. */
18521 + dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1];
18522 + /** number of valid EPs in the above array. */
18523 +// unsigned num_eps : 4;
18524 + spinlock_t lock;
18525 + /** Timer for SRP. If it expires before SRP is successful
18526 + * clear the SRP. */
18527 + struct timer_list srp_timer;
18528 +
18529 + /** Tasklet to defer starting of TEST mode transmissions until
18530 + * Status Phase has been completed.
18531 + */
18532 + struct tasklet_struct test_mode_tasklet;
18533 +
18534 + /** Tasklet to delay starting of xfer in DMA mode */
18535 + struct tasklet_struct *start_xfer_tasklet;
18536 +
18537 + /** The test mode to enter when the tasklet is executed. */
18538 + unsigned test_mode;
18539 +
18540 +} dwc_otg_pcd_t;
18541 +
18542 +
18543 +/** DWC_otg request structure.
18544 + * This structure is a list of requests.
18545 + */
18546 +typedef struct
18547 +{
18548 + struct usb_request req; /**< USB Request. */
18549 + struct list_head queue; /**< queue of these requests. */
18550 +} dwc_otg_pcd_request_t;
18551 +
18552 +
18553 +extern int dwc_otg_pcd_init(struct device *dev);
18554 +
18555 +//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev );
18556 +extern void dwc_otg_pcd_remove( struct device *dev);
18557 +extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd );
18558 +extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd );
18559 +
18560 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd);
18561 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set);
18562 +
18563 +extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req);
18564 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req,
18565 + int status);
18566 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep);
18567 +extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd,
18568 + const unsigned reset);
18569 +
18570 +#endif
18571 +#endif /* DWC_HOST_ONLY */
18572 diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c b/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
18573 new file mode 100644
18574 index 0000000..fd44fd8
18575 --- /dev/null
18576 +++ b/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
18577 @@ -0,0 +1,3654 @@
18578 +/* ==========================================================================
18579 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
18580 + * $Revision: 1.2 $
18581 + * $Date: 2008-11-21 05:39:15 $
18582 + * $Change: 1115682 $
18583 + *
18584 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18585 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18586 + * otherwise expressly agreed to in writing between Synopsys and you.
18587 + *
18588 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18589 + * any End User Software License Agreement or Agreement for Licensed Product
18590 + * with Synopsys or any supplement thereto. You are permitted to use and
18591 + * redistribute this Software in source and binary forms, with or without
18592 + * modification, provided that redistributions of source code must retain this
18593 + * notice. You may not view, use, disclose, copy or distribute this file or
18594 + * any information contained herein except pursuant to this license grant from
18595 + * Synopsys. If you do not agree with this notice, including the disclaimer
18596 + * below, then you are not authorized to use the Software.
18597 + *
18598 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18599 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18600 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18601 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18602 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18603 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18604 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18605 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18606 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18607 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18608 + * DAMAGE.
18609 + * ========================================================================== */
18610 +#ifndef DWC_HOST_ONLY
18611 +#include <linux/interrupt.h>
18612 +#include <linux/dma-mapping.h>
18613 +#include <linux/version.h>
18614 +
18615 +#include "dwc_otg_driver.h"
18616 +#include "dwc_otg_pcd.h"
18617 +
18618 +
18619 +#define DEBUG_EP0
18620 +
18621 +/* request functions defined in "dwc_otg_pcd.c" */
18622 +
18623 +/** @file
18624 + * This file contains the implementation of the PCD Interrupt handlers.
18625 + *
18626 + * The PCD handles the device interrupts. Many conditions can cause a
18627 + * device interrupt. When an interrupt occurs, the device interrupt
18628 + * service routine determines the cause of the interrupt and
18629 + * dispatches handling to the appropriate function. These interrupt
18630 + * handling functions are described below.
18631 + * All interrupt registers are processed from LSB to MSB.
18632 + */
18633 +
18634 +
18635 +/**
18636 + * This function prints the ep0 state for debug purposes.
18637 + */
18638 +static inline void print_ep0_state(dwc_otg_pcd_t *pcd)
18639 +{
18640 +#ifdef DEBUG
18641 + char str[40];
18642 +
18643 + switch (pcd->ep0state) {
18644 + case EP0_DISCONNECT:
18645 + strcpy(str, "EP0_DISCONNECT");
18646 + break;
18647 + case EP0_IDLE:
18648 + strcpy(str, "EP0_IDLE");
18649 + break;
18650 + case EP0_IN_DATA_PHASE:
18651 + strcpy(str, "EP0_IN_DATA_PHASE");
18652 + break;
18653 + case EP0_OUT_DATA_PHASE:
18654 + strcpy(str, "EP0_OUT_DATA_PHASE");
18655 + break;
18656 + case EP0_IN_STATUS_PHASE:
18657 + strcpy(str,"EP0_IN_STATUS_PHASE");
18658 + break;
18659 + case EP0_OUT_STATUS_PHASE:
18660 + strcpy(str,"EP0_OUT_STATUS_PHASE");
18661 + break;
18662 + case EP0_STALL:
18663 + strcpy(str,"EP0_STALL");
18664 + break;
18665 + default:
18666 + strcpy(str,"EP0_INVALID");
18667 + }
18668 +
18669 + DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
18670 +#endif
18671 +}
18672 +
18673 +/**
18674 + * This function returns pointer to in ep struct with number ep_num
18675 + */
18676 +static inline dwc_otg_pcd_ep_t* get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
18677 +{
18678 + int i;
18679 + int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
18680 + if(ep_num == 0) {
18681 + return &pcd->ep0;
18682 + }
18683 + else {
18684 + for(i = 0; i < num_in_eps; ++i)
18685 + {
18686 + if(pcd->in_ep[i].dwc_ep.num == ep_num)
18687 + return &pcd->in_ep[i];
18688 + }
18689 + return 0;
18690 + }
18691 +}
18692 +/**
18693 + * This function returns pointer to out ep struct with number ep_num
18694 + */
18695 +static inline dwc_otg_pcd_ep_t* get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
18696 +{
18697 + int i;
18698 + int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
18699 + if(ep_num == 0) {
18700 + return &pcd->ep0;
18701 + }
18702 + else {
18703 + for(i = 0; i < num_out_eps; ++i)
18704 + {
18705 + if(pcd->out_ep[i].dwc_ep.num == ep_num)
18706 + return &pcd->out_ep[i];
18707 + }
18708 + return 0;
18709 + }
18710 +}
18711 +/**
18712 + * This functions gets a pointer to an EP from the wIndex address
18713 + * value of the control request.
18714 + */
18715 +static dwc_otg_pcd_ep_t *get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
18716 +{
18717 + dwc_otg_pcd_ep_t *ep;
18718 +
18719 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
18720 + return &pcd->ep0;
18721 + list_for_each_entry(ep, &pcd->gadget.ep_list, ep.ep_list)
18722 + {
18723 + u8 bEndpointAddress;
18724 +
18725 + if (!ep->desc)
18726 + continue;
18727 +
18728 + bEndpointAddress = ep->desc->bEndpointAddress;
18729 + if((wIndex & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK))
18730 + == (bEndpointAddress & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK)))
18731 + return ep;
18732 + }
18733 + return NULL;
18734 +}
18735 +
18736 +/**
18737 + * This function checks the EP request queue, if the queue is not
18738 + * empty the next request is started.
18739 + */
18740 +void start_next_request(dwc_otg_pcd_ep_t *ep)
18741 +{
18742 + dwc_otg_pcd_request_t *req = 0;
18743 + uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
18744 +
18745 + if (!list_empty(&ep->queue)) {
18746 + req = list_entry(ep->queue.next,
18747 + dwc_otg_pcd_request_t, queue);
18748 +
18749 + /* Setup and start the Transfer */
18750 + ep->dwc_ep.dma_addr = req->req.dma;
18751 + ep->dwc_ep.start_xfer_buff = req->req.buf;
18752 + ep->dwc_ep.xfer_buff = req->req.buf;
18753 + ep->dwc_ep.sent_zlp = 0;
18754 + ep->dwc_ep.total_len = req->req.length;
18755 + ep->dwc_ep.xfer_len = 0;
18756 + ep->dwc_ep.xfer_count = 0;
18757 +
18758 + if(max_transfer > MAX_TRANSFER_SIZE) {
18759 + ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
18760 + } else {
18761 + ep->dwc_ep.maxxfer = max_transfer;
18762 + }
18763 +
18764 + if(req->req.zero) {
18765 + if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
18766 + && (ep->dwc_ep.total_len != 0)) {
18767 + ep->dwc_ep.sent_zlp = 1;
18768 + }
18769 +
18770 + }
18771 +
18772 + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
18773 + }
18774 +}
18775 +
18776 +/**
18777 + * This function handles the SOF Interrupts. At this time the SOF
18778 + * Interrupt is disabled.
18779 + */
18780 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd)
18781 +{
18782 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18783 +
18784 + gintsts_data_t gintsts;
18785 +
18786 + DWC_DEBUGPL(DBG_PCD, "SOF\n");
18787 +
18788 + /* Clear interrupt */
18789 + gintsts.d32 = 0;
18790 + gintsts.b.sofintr = 1;
18791 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
18792 +
18793 + return 1;
18794 +}
18795 +
18796 +
18797 +/**
18798 + * This function handles the Rx Status Queue Level Interrupt, which
18799 + * indicates that there is a least one packet in the Rx FIFO. The
18800 + * packets are moved from the FIFO to memory, where they will be
18801 + * processed when the Endpoint Interrupt Register indicates Transfer
18802 + * Complete or SETUP Phase Done.
18803 + *
18804 + * Repeat the following until the Rx Status Queue is empty:
18805 + * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
18806 + * info
18807 + * -# If Receive FIFO is empty then skip to step Clear the interrupt
18808 + * and exit
18809 + * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
18810 + * SETUP data to the buffer
18811 + * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
18812 + * to the destination buffer
18813 + */
18814 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd)
18815 +{
18816 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18817 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
18818 + gintmsk_data_t gintmask = {.d32=0};
18819 + device_grxsts_data_t status;
18820 + dwc_otg_pcd_ep_t *ep;
18821 + gintsts_data_t gintsts;
18822 +#ifdef DEBUG
18823 + static char *dpid_str[] ={ "D0", "D2", "D1", "MDATA" };
18824 +#endif
18825 +
18826 + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
18827 + /* Disable the Rx Status Queue Level interrupt */
18828 + gintmask.b.rxstsqlvl= 1;
18829 + dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
18830 +
18831 + /* Get the Status from the top of the FIFO */
18832 + status.d32 = dwc_read_reg32(&global_regs->grxstsp);
18833 +
18834 + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
18835 + "pktsts:%x Frame:%d(0x%0x)\n",
18836 + status.b.epnum, status.b.bcnt,
18837 + dpid_str[status.b.dpid],
18838 + status.b.pktsts, status.b.fn, status.b.fn);
18839 + /* Get pointer to EP structure */
18840 + ep = get_out_ep(pcd, status.b.epnum);
18841 +
18842 + switch (status.b.pktsts) {
18843 + case DWC_DSTS_GOUT_NAK:
18844 + DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
18845 + break;
18846 + case DWC_STS_DATA_UPDT:
18847 + DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
18848 + if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
18849 + /** @todo NGS Check for buffer overflow? */
18850 + dwc_otg_read_packet(core_if,
18851 + ep->dwc_ep.xfer_buff,
18852 + status.b.bcnt);
18853 + ep->dwc_ep.xfer_count += status.b.bcnt;
18854 + ep->dwc_ep.xfer_buff += status.b.bcnt;
18855 + }
18856 + break;
18857 + case DWC_STS_XFER_COMP:
18858 + DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
18859 + break;
18860 + case DWC_DSTS_SETUP_COMP:
18861 +#ifdef DEBUG_EP0
18862 + DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
18863 +#endif
18864 + break;
18865 +case DWC_DSTS_SETUP_UPDT:
18866 + dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
18867 +#ifdef DEBUG_EP0
18868 + DWC_DEBUGPL(DBG_PCD,
18869 + "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
18870 + pcd->setup_pkt->req.bRequestType,
18871 + pcd->setup_pkt->req.bRequest,
18872 + pcd->setup_pkt->req.wValue,
18873 + pcd->setup_pkt->req.wIndex,
18874 + pcd->setup_pkt->req.wLength);
18875 +#endif
18876 + ep->dwc_ep.xfer_count += status.b.bcnt;
18877 + break;
18878 + default:
18879 + DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
18880 + status.b.pktsts);
18881 + break;
18882 + }
18883 +
18884 + /* Enable the Rx Status Queue Level interrupt */
18885 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
18886 + /* Clear interrupt */
18887 + gintsts.d32 = 0;
18888 + gintsts.b.rxstsqlvl = 1;
18889 + dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
18890 +
18891 + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
18892 + return 1;
18893 +}
18894 +/**
18895 + * This function examines the Device IN Token Learning Queue to
18896 + * determine the EP number of the last IN token received. This
18897 + * implementation is for the Mass Storage device where there are only
18898 + * 2 IN EPs (Control-IN and BULK-IN).
18899 + *
18900 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
18901 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
18902 + *
18903 + * @param core_if Programming view of DWC_otg controller.
18904 + *
18905 + */
18906 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if)
18907 +{
18908 + dwc_otg_device_global_regs_t *dev_global_regs =
18909 + core_if->dev_if->dev_global_regs;
18910 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
18911 + /* Number of Token Queue Registers */
18912 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
18913 + dtknq1_data_t dtknqr1;
18914 + uint32_t in_tkn_epnums[4];
18915 + int ndx = 0;
18916 + int i = 0;
18917 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
18918 + int epnum = 0;
18919 +
18920 + //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
18921 +
18922 +
18923 + /* Read the DTKNQ Registers */
18924 + for (i = 0; i < DTKNQ_REG_CNT; i++)
18925 + {
18926 + in_tkn_epnums[ i ] = dwc_read_reg32(addr);
18927 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i+1,
18928 + in_tkn_epnums[i]);
18929 + if (addr == &dev_global_regs->dvbusdis) {
18930 + addr = &dev_global_regs->dtknqr3_dthrctl;
18931 + }
18932 + else {
18933 + ++addr;
18934 + }
18935 +
18936 + }
18937 +
18938 + /* Copy the DTKNQR1 data to the bit field. */
18939 + dtknqr1.d32 = in_tkn_epnums[0];
18940 + /* Get the EP numbers */
18941 + in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
18942 + ndx = dtknqr1.b.intknwptr - 1;
18943 +
18944 + //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
18945 + if (ndx == -1) {
18946 + /** @todo Find a simpler way to calculate the max
18947 + * queue position.*/
18948 + int cnt = TOKEN_Q_DEPTH;
18949 + if (TOKEN_Q_DEPTH <= 6) {
18950 + cnt = TOKEN_Q_DEPTH - 1;
18951 + }
18952 + else if (TOKEN_Q_DEPTH <= 14) {
18953 + cnt = TOKEN_Q_DEPTH - 7;
18954 + }
18955 + else if (TOKEN_Q_DEPTH <= 22) {
18956 + cnt = TOKEN_Q_DEPTH - 15;
18957 + }
18958 + else {
18959 + cnt = TOKEN_Q_DEPTH - 23;
18960 + }
18961 + epnum = (in_tkn_epnums[ DTKNQ_REG_CNT - 1 ] >> (cnt * 4)) & 0xF;
18962 + }
18963 + else {
18964 + if (ndx <= 5) {
18965 + epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
18966 + }
18967 + else if (ndx <= 13) {
18968 + ndx -= 6;
18969 + epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
18970 + }
18971 + else if (ndx <= 21) {
18972 + ndx -= 14;
18973 + epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
18974 + }
18975 + else if (ndx <= 29) {
18976 + ndx -= 22;
18977 + epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
18978 + }
18979 + }
18980 + //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
18981 + return epnum;
18982 +}
18983 +
18984 +/**
18985 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
18986 + * The active request is checked for the next packet to be loaded into
18987 + * the non-periodic Tx FIFO.
18988 + */
18989 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
18990 +{
18991 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18992 + dwc_otg_core_global_regs_t *global_regs =
18993 + core_if->core_global_regs;
18994 + dwc_otg_dev_in_ep_regs_t *ep_regs;
18995 + gnptxsts_data_t txstatus = {.d32 = 0};
18996 + gintsts_data_t gintsts;
18997 +
18998 + int epnum = 0;
18999 + dwc_otg_pcd_ep_t *ep = 0;
19000 + uint32_t len = 0;
19001 + int dwords;
19002 +
19003 + /* Get the epnum from the IN Token Learning Queue. */
19004 + epnum = get_ep_of_last_in_token(core_if);
19005 + ep = get_in_ep(pcd, epnum);
19006 +
19007 + DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
19008 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
19009 +
19010 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
19011 + if (len > ep->dwc_ep.maxpacket) {
19012 + len = ep->dwc_ep.maxpacket;
19013 + }
19014 + dwords = (len + 3)/4;
19015 +
19016 +
19017 + /* While there is space in the queue and space in the FIFO and
19018 + * More data to tranfer, Write packets to the Tx FIFO */
19019 + txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
19020 + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n",txstatus.d32);
19021 +
19022 + while (txstatus.b.nptxqspcavail > 0 &&
19023 + txstatus.b.nptxfspcavail > dwords &&
19024 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
19025 + /* Write the FIFO */
19026 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
19027 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
19028 +
19029 + if (len > ep->dwc_ep.maxpacket) {
19030 + len = ep->dwc_ep.maxpacket;
19031 + }
19032 +
19033 + dwords = (len + 3)/4;
19034 + txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
19035 + DWC_DEBUGPL(DBG_PCDV,"GNPTXSTS=0x%08x\n",txstatus.d32);
19036 + }
19037 +
19038 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
19039 + dwc_read_reg32(&global_regs->gnptxsts));
19040 +
19041 + /* Clear interrupt */
19042 + gintsts.d32 = 0;
19043 + gintsts.b.nptxfempty = 1;
19044 + dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
19045 +
19046 + return 1;
19047 +}
19048 +
19049 +/**
19050 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
19051 + * The active request is checked for the next packet to be loaded into
19052 + * apropriate Tx FIFO.
19053 + */
19054 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
19055 +{
19056 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19057 + dwc_otg_dev_if_t* dev_if = core_if->dev_if;
19058 + dwc_otg_dev_in_ep_regs_t *ep_regs;
19059 + dtxfsts_data_t txstatus = {.d32 = 0};
19060 + dwc_otg_pcd_ep_t *ep = 0;
19061 + uint32_t len = 0;
19062 + int dwords;
19063 +
19064 + ep = get_in_ep(pcd, epnum);
19065 +
19066 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
19067 +
19068 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
19069 +
19070 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
19071 +
19072 + if (len > ep->dwc_ep.maxpacket) {
19073 + len = ep->dwc_ep.maxpacket;
19074 + }
19075 +
19076 + dwords = (len + 3)/4;
19077 +
19078 + /* While there is space in the queue and space in the FIFO and
19079 + * More data to tranfer, Write packets to the Tx FIFO */
19080 + txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
19081 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,txstatus.d32);
19082 +
19083 + while (txstatus.b.txfspcavail > dwords &&
19084 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
19085 + ep->dwc_ep.xfer_len != 0) {
19086 + /* Write the FIFO */
19087 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
19088 +
19089 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
19090 + if (len > ep->dwc_ep.maxpacket) {
19091 + len = ep->dwc_ep.maxpacket;
19092 + }
19093 +
19094 + dwords = (len + 3)/4;
19095 + txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
19096 + DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
19097 + }
19098 +
19099 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
19100 +
19101 + return 1;
19102 +}
19103 +
19104 +
19105 +/**
19106 + * This function is called when the Device is disconnected. It stops
19107 + * any active requests and informs the Gadget driver of the
19108 + * disconnect.
19109 + */
19110 +void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd)
19111 +{
19112 + int i, num_in_eps, num_out_eps;
19113 + dwc_otg_pcd_ep_t *ep;
19114 +
19115 + gintmsk_data_t intr_mask = {.d32 = 0};
19116 +
19117 + num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
19118 + num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
19119 +
19120 + DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
19121 + /* don't disconnect drivers more than once */
19122 + if (pcd->ep0state == EP0_DISCONNECT) {
19123 + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
19124 + return;
19125 + }
19126 + pcd->ep0state = EP0_DISCONNECT;
19127 +
19128 + /* Reset the OTG state. */
19129 + dwc_otg_pcd_update_otg(pcd, 1);
19130 +
19131 + /* Disable the NP Tx Fifo Empty Interrupt. */
19132 + intr_mask.b.nptxfempty = 1;
19133 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19134 + intr_mask.d32, 0);
19135 +
19136 + /* Flush the FIFOs */
19137 + /**@todo NGS Flush Periodic FIFOs */
19138 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
19139 + dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
19140 +
19141 + /* prevent new request submissions, kill any outstanding requests */
19142 + ep = &pcd->ep0;
19143 + dwc_otg_request_nuke(ep);
19144 + /* prevent new request submissions, kill any outstanding requests */
19145 + for (i = 0; i < num_in_eps; i++)
19146 + {
19147 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
19148 + dwc_otg_request_nuke(ep);
19149 + }
19150 + /* prevent new request submissions, kill any outstanding requests */
19151 + for (i = 0; i < num_out_eps; i++)
19152 + {
19153 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
19154 + dwc_otg_request_nuke(ep);
19155 + }
19156 +
19157 + /* report disconnect; the driver is already quiesced */
19158 + if (pcd->driver && pcd->driver->disconnect) {
19159 + SPIN_UNLOCK(&pcd->lock);
19160 + pcd->driver->disconnect(&pcd->gadget);
19161 + SPIN_LOCK(&pcd->lock);
19162 + }
19163 +}
19164 +
19165 +/**
19166 + * This interrupt indicates that ...
19167 + */
19168 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd)
19169 +{
19170 + gintmsk_data_t intr_mask = { .d32 = 0};
19171 + gintsts_data_t gintsts;
19172 +
19173 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "i2cintr");
19174 + intr_mask.b.i2cintr = 1;
19175 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19176 + intr_mask.d32, 0);
19177 +
19178 + /* Clear interrupt */
19179 + gintsts.d32 = 0;
19180 + gintsts.b.i2cintr = 1;
19181 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19182 + gintsts.d32);
19183 + return 1;
19184 +}
19185 +
19186 +
19187 +/**
19188 + * This interrupt indicates that ...
19189 + */
19190 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd)
19191 +{
19192 + gintsts_data_t gintsts;
19193 +#if defined(VERBOSE)
19194 + DWC_PRINT("Early Suspend Detected\n");
19195 +#endif
19196 + /* Clear interrupt */
19197 + gintsts.d32 = 0;
19198 + gintsts.b.erlysuspend = 1;
19199 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19200 + gintsts.d32);
19201 + return 1;
19202 +}
19203 +
19204 +/**
19205 + * This function configures EPO to receive SETUP packets.
19206 + *
19207 + * @todo NGS: Update the comments from the HW FS.
19208 + *
19209 + * -# Program the following fields in the endpoint specific registers
19210 + * for Control OUT EP 0, in order to receive a setup packet
19211 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
19212 + * setup packets)
19213 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
19214 + * to back setup packets)
19215 + * - In DMA mode, DOEPDMA0 Register with a memory address to
19216 + * store any setup packets received
19217 + *
19218 + * @param core_if Programming view of DWC_otg controller.
19219 + * @param pcd Programming view of the PCD.
19220 + */
19221 +static inline void ep0_out_start(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
19222 +{
19223 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19224 + deptsiz0_data_t doeptsize0 = { .d32 = 0};
19225 + dwc_otg_dma_desc_t* dma_desc;
19226 + depctl_data_t doepctl = { .d32 = 0 };
19227 +
19228 +#ifdef VERBOSE
19229 + DWC_DEBUGPL(DBG_PCDV,"%s() doepctl0=%0x\n", __func__,
19230 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
19231 +#endif
19232 +
19233 + doeptsize0.b.supcnt = 3;
19234 + doeptsize0.b.pktcnt = 1;
19235 + doeptsize0.b.xfersize = 8*3;
19236 +
19237 +
19238 + if (core_if->dma_enable) {
19239 + if (!core_if->dma_desc_enable) {
19240 + /** put here as for Hermes mode deptisz register should not be written */
19241 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
19242 + doeptsize0.d32);
19243 +
19244 + /** @todo dma needs to handle multiple setup packets (up to 3) */
19245 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
19246 + pcd->setup_pkt_dma_handle);
19247 + } else {
19248 + dev_if->setup_desc_index = (dev_if->setup_desc_index + 1) & 1;
19249 + dma_desc = dev_if->setup_desc_addr[dev_if->setup_desc_index];
19250 +
19251 + /** DMA Descriptor Setup */
19252 + dma_desc->status.b.bs = BS_HOST_BUSY;
19253 + dma_desc->status.b.l = 1;
19254 + dma_desc->status.b.ioc = 1;
19255 + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
19256 + dma_desc->buf = pcd->setup_pkt_dma_handle;
19257 + dma_desc->status.b.bs = BS_HOST_READY;
19258 +
19259 + /** DOEPDMA0 Register write */
19260 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]);
19261 + }
19262 +
19263 + } else {
19264 + /** put here as for Hermes mode deptisz register should not be written */
19265 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
19266 + doeptsize0.d32);
19267 + }
19268 +
19269 + /** DOEPCTL0 Register write */
19270 + doepctl.b.epena = 1;
19271 + doepctl.b.cnak = 1;
19272 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
19273 +
19274 +#ifdef VERBOSE
19275 + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
19276 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
19277 + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
19278 + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
19279 +#endif
19280 +}
19281 +
19282 +
19283 +/**
19284 + * This interrupt occurs when a USB Reset is detected. When the USB
19285 + * Reset Interrupt occurs the device state is set to DEFAULT and the
19286 + * EP0 state is set to IDLE.
19287 + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
19288 + * -# Unmask the following interrupt bits
19289 + * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
19290 + * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
19291 + * - DOEPMSK.SETUP = 1
19292 + * - DOEPMSK.XferCompl = 1
19293 + * - DIEPMSK.XferCompl = 1
19294 + * - DIEPMSK.TimeOut = 1
19295 + * -# Program the following fields in the endpoint specific registers
19296 + * for Control OUT EP 0, in order to receive a setup packet
19297 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
19298 + * setup packets)
19299 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
19300 + * to back setup packets)
19301 + * - In DMA mode, DOEPDMA0 Register with a memory address to
19302 + * store any setup packets received
19303 + * At this point, all the required initialization, except for enabling
19304 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
19305 + */
19306 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
19307 +{
19308 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19309 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19310 + depctl_data_t doepctl = { .d32 = 0};
19311 +
19312 + daint_data_t daintmsk = { .d32 = 0};
19313 + doepmsk_data_t doepmsk = { .d32 = 0};
19314 + diepmsk_data_t diepmsk = { .d32 = 0};
19315 +
19316 + dcfg_data_t dcfg = { .d32=0 };
19317 + grstctl_t resetctl = { .d32=0 };
19318 + dctl_data_t dctl = {.d32=0};
19319 + int i = 0;
19320 + gintsts_data_t gintsts;
19321 +
19322 + DWC_PRINT("USB RESET\n");
19323 +#ifdef DWC_EN_ISOC
19324 + for(i = 1;i < 16; ++i)
19325 + {
19326 + dwc_otg_pcd_ep_t *ep;
19327 + dwc_ep_t *dwc_ep;
19328 + ep = get_in_ep(pcd,i);
19329 + if(ep != 0){
19330 + dwc_ep = &ep->dwc_ep;
19331 + dwc_ep->next_frame = 0xffffffff;
19332 + }
19333 + }
19334 +#endif /* DWC_EN_ISOC */
19335 +
19336 + /* reset the HNP settings */
19337 + dwc_otg_pcd_update_otg(pcd, 1);
19338 +
19339 + /* Clear the Remote Wakeup Signalling */
19340 + dctl.b.rmtwkupsig = 1;
19341 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
19342 + dctl.d32, 0);
19343 +
19344 + /* Set NAK for all OUT EPs */
19345 + doepctl.b.snak = 1;
19346 + for (i=0; i <= dev_if->num_out_eps; i++)
19347 + {
19348 + dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl,
19349 + doepctl.d32);
19350 + }
19351 +
19352 + /* Flush the NP Tx FIFO */
19353 + dwc_otg_flush_tx_fifo(core_if, 0x10);
19354 + /* Flush the Learning Queue */
19355 + resetctl.b.intknqflsh = 1;
19356 + dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
19357 +
19358 + if(core_if->multiproc_int_enable) {
19359 + daintmsk.b.inep0 = 1;
19360 + daintmsk.b.outep0 = 1;
19361 + dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, daintmsk.d32);
19362 +
19363 + doepmsk.b.setup = 1;
19364 + doepmsk.b.xfercompl = 1;
19365 + doepmsk.b.ahberr = 1;
19366 + doepmsk.b.epdisabled = 1;
19367 +
19368 + if(core_if->dma_desc_enable) {
19369 + doepmsk.b.stsphsercvd = 1;
19370 + doepmsk.b.bna = 1;
19371 + }
19372 +/*
19373 + doepmsk.b.babble = 1;
19374 + doepmsk.b.nyet = 1;
19375 +
19376 + if(core_if->dma_enable) {
19377 + doepmsk.b.nak = 1;
19378 + }
19379 +*/
19380 + dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], doepmsk.d32);
19381 +
19382 + diepmsk.b.xfercompl = 1;
19383 + diepmsk.b.timeout = 1;
19384 + diepmsk.b.epdisabled = 1;
19385 + diepmsk.b.ahberr = 1;
19386 + diepmsk.b.intknepmis = 1;
19387 +
19388 + if(core_if->dma_desc_enable) {
19389 + diepmsk.b.bna = 1;
19390 + }
19391 +/*
19392 + if(core_if->dma_enable) {
19393 + diepmsk.b.nak = 1;
19394 + }
19395 +*/
19396 + dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], diepmsk.d32);
19397 + } else{
19398 + daintmsk.b.inep0 = 1;
19399 + daintmsk.b.outep0 = 1;
19400 + dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, daintmsk.d32);
19401 +
19402 + doepmsk.b.setup = 1;
19403 + doepmsk.b.xfercompl = 1;
19404 + doepmsk.b.ahberr = 1;
19405 + doepmsk.b.epdisabled = 1;
19406 +
19407 + if(core_if->dma_desc_enable) {
19408 + doepmsk.b.stsphsercvd = 1;
19409 + doepmsk.b.bna = 1;
19410 + }
19411 +/*
19412 + doepmsk.b.babble = 1;
19413 + doepmsk.b.nyet = 1;
19414 + doepmsk.b.nak = 1;
19415 +*/
19416 + dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
19417 +
19418 + diepmsk.b.xfercompl = 1;
19419 + diepmsk.b.timeout = 1;
19420 + diepmsk.b.epdisabled = 1;
19421 + diepmsk.b.ahberr = 1;
19422 + diepmsk.b.intknepmis = 1;
19423 +
19424 + if(core_if->dma_desc_enable) {
19425 + diepmsk.b.bna = 1;
19426 + }
19427 +
19428 +// diepmsk.b.nak = 1;
19429 +
19430 + dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
19431 + }
19432 +
19433 + /* Reset Device Address */
19434 + dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
19435 + dcfg.b.devaddr = 0;
19436 + dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
19437 +
19438 + /* setup EP0 to receive SETUP packets */
19439 + ep0_out_start(core_if, pcd);
19440 +
19441 + /* Clear interrupt */
19442 + gintsts.d32 = 0;
19443 + gintsts.b.usbreset = 1;
19444 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
19445 +
19446 + return 1;
19447 +}
19448 +
19449 +/**
19450 + * Get the device speed from the device status register and convert it
19451 + * to USB speed constant.
19452 + *
19453 + * @param core_if Programming view of DWC_otg controller.
19454 + */
19455 +static int get_device_speed(dwc_otg_core_if_t *core_if)
19456 +{
19457 + dsts_data_t dsts;
19458 + enum usb_device_speed speed = USB_SPEED_UNKNOWN;
19459 + dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
19460 +
19461 + switch (dsts.b.enumspd) {
19462 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
19463 + speed = USB_SPEED_HIGH;
19464 + break;
19465 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
19466 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
19467 + speed = USB_SPEED_FULL;
19468 + break;
19469 +
19470 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
19471 + speed = USB_SPEED_LOW;
19472 + break;
19473 + }
19474 +
19475 + return speed;
19476 +}
19477 +
19478 +/**
19479 + * Read the device status register and set the device speed in the
19480 + * data structure.
19481 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
19482 + */
19483 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd)
19484 +{
19485 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19486 + gintsts_data_t gintsts;
19487 + gusbcfg_data_t gusbcfg;
19488 + dwc_otg_core_global_regs_t *global_regs =
19489 + GET_CORE_IF(pcd)->core_global_regs;
19490 + uint8_t utmi16b, utmi8b;
19491 + DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
19492 +
19493 + if (GET_CORE_IF(pcd)->snpsid >= 0x4F54260A) {
19494 + utmi16b = 6;
19495 + utmi8b = 9;
19496 + } else {
19497 + utmi16b = 4;
19498 + utmi8b = 8;
19499 + }
19500 + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
19501 +
19502 +#ifdef DEBUG_EP0
19503 + print_ep0_state(pcd);
19504 +#endif
19505 +
19506 + if (pcd->ep0state == EP0_DISCONNECT) {
19507 + pcd->ep0state = EP0_IDLE;
19508 + }
19509 + else if (pcd->ep0state == EP0_STALL) {
19510 + pcd->ep0state = EP0_IDLE;
19511 + }
19512 +
19513 + pcd->ep0state = EP0_IDLE;
19514 +
19515 + ep0->stopped = 0;
19516 +
19517 + pcd->gadget.speed = get_device_speed(GET_CORE_IF(pcd));
19518 +
19519 + /* Set USB turnaround time based on device speed and PHY interface. */
19520 + gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
19521 + if (pcd->gadget.speed == USB_SPEED_HIGH) {
19522 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
19523 + /* ULPI interface */
19524 + gusbcfg.b.usbtrdtim = 9;
19525 + }
19526 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
19527 + /* UTMI+ interface */
19528 + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
19529 + gusbcfg.b.usbtrdtim = utmi8b;
19530 + }
19531 + else if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 1) {
19532 + gusbcfg.b.usbtrdtim = utmi16b;
19533 + }
19534 + else if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 8) {
19535 + gusbcfg.b.usbtrdtim = utmi8b;
19536 + }
19537 + else {
19538 + gusbcfg.b.usbtrdtim = utmi16b;
19539 + }
19540 + }
19541 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
19542 + /* UTMI+ OR ULPI interface */
19543 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
19544 + /* ULPI interface */
19545 + gusbcfg.b.usbtrdtim = 9;
19546 + }
19547 + else {
19548 + /* UTMI+ interface */
19549 + if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 16) {
19550 + gusbcfg.b.usbtrdtim = utmi16b;
19551 + }
19552 + else {
19553 + gusbcfg.b.usbtrdtim = utmi8b;
19554 + }
19555 + }
19556 + }
19557 + }
19558 + else {
19559 + /* Full or low speed */
19560 + gusbcfg.b.usbtrdtim = 9;
19561 + }
19562 + dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
19563 +
19564 + /* Clear interrupt */
19565 + gintsts.d32 = 0;
19566 + gintsts.b.enumdone = 1;
19567 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19568 + gintsts.d32);
19569 + return 1;
19570 +}
19571 +
19572 +/**
19573 + * This interrupt indicates that the ISO OUT Packet was dropped due to
19574 + * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
19575 + * read all the data from the Rx FIFO.
19576 + */
19577 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd)
19578 +{
19579 + gintmsk_data_t intr_mask = { .d32 = 0};
19580 + gintsts_data_t gintsts;
19581 +
19582 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
19583 + "ISOC Out Dropped");
19584 +
19585 + intr_mask.b.isooutdrop = 1;
19586 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19587 + intr_mask.d32, 0);
19588 +
19589 + /* Clear interrupt */
19590 +
19591 + gintsts.d32 = 0;
19592 + gintsts.b.isooutdrop = 1;
19593 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
19594 + gintsts.d32);
19595 +
19596 + return 1;
19597 +}
19598 +
19599 +/**
19600 + * This interrupt indicates the end of the portion of the micro-frame
19601 + * for periodic transactions. If there is a periodic transaction for
19602 + * the next frame, load the packets into the EP periodic Tx FIFO.
19603 + */
19604 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd)
19605 +{
19606 + gintmsk_data_t intr_mask = { .d32 = 0};
19607 + gintsts_data_t gintsts;
19608 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "EOP");
19609 +
19610 + intr_mask.b.eopframe = 1;
19611 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
19612 + intr_mask.d32, 0);
19613 +
19614 + /* Clear interrupt */
19615 + gintsts.d32 = 0;
19616 + gintsts.b.eopframe = 1;
19617 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, gintsts.d32);
19618 +
19619 + return 1;
19620 +}
19621 +
19622 +/**
19623 + * This interrupt indicates that EP of the packet on the top of the
19624 + * non-periodic Tx FIFO does not match EP of the IN Token received.
19625 + *
19626 + * The "Device IN Token Queue" Registers are read to determine the
19627 + * order the IN Tokens have been received. The non-periodic Tx FIFO
19628 + * is flushed, so it can be reloaded in the order seen in the IN Token
19629 + * Queue.
19630 + */
19631 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t *core_if)
19632 +{
19633 + gintsts_data_t gintsts;
19634 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
19635 +
19636 + /* Clear interrupt */
19637 + gintsts.d32 = 0;
19638 + gintsts.b.epmismatch = 1;
19639 + dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
19640 +
19641 + return 1;
19642 +}
19643 +
19644 +/**
19645 + * This funcion stalls EP0.
19646 + */
19647 +static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
19648 +{
19649 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19650 + struct usb_ctrlrequest *ctrl = &pcd->setup_pkt->req;
19651 + DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
19652 + ctrl->bRequestType, ctrl->bRequest, err_val);
19653 +
19654 + ep0->dwc_ep.is_in = 1;
19655 + dwc_otg_ep_set_stall(pcd->otg_dev->core_if, &ep0->dwc_ep);
19656 + pcd->ep0.stopped = 1;
19657 + pcd->ep0state = EP0_IDLE;
19658 + ep0_out_start(GET_CORE_IF(pcd), pcd);
19659 +}
19660 +
19661 +/**
19662 + * This functions delegates the setup command to the gadget driver.
19663 + */
19664 +static inline void do_gadget_setup(dwc_otg_pcd_t *pcd,
19665 + struct usb_ctrlrequest * ctrl)
19666 +{
19667 + int ret = 0;
19668 + if (pcd->driver && pcd->driver->setup) {
19669 + SPIN_UNLOCK(&pcd->lock);
19670 + ret = pcd->driver->setup(&pcd->gadget, ctrl);
19671 + SPIN_LOCK(&pcd->lock);
19672 + if (ret < 0) {
19673 + ep0_do_stall(pcd, ret);
19674 + }
19675 +
19676 + /** @todo This is a g_file_storage gadget driver specific
19677 + * workaround: a DELAYED_STATUS result from the fsg_setup
19678 + * routine will result in the gadget queueing a EP0 IN status
19679 + * phase for a two-stage control transfer. Exactly the same as
19680 + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
19681 + * specific request. Need a generic way to know when the gadget
19682 + * driver will queue the status phase. Can we assume when we
19683 + * call the gadget driver setup() function that it will always
19684 + * queue and require the following flag? Need to look into
19685 + * this.
19686 + */
19687 +
19688 + if (ret == 256 + 999) {
19689 + pcd->request_config = 1;
19690 + }
19691 + }
19692 +}
19693 +
19694 +/**
19695 + * This function starts the Zero-Length Packet for the IN status phase
19696 + * of a 2 stage control transfer.
19697 + */
19698 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd)
19699 +{
19700 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19701 + if (pcd->ep0state == EP0_STALL) {
19702 + return;
19703 + }
19704 +
19705 + pcd->ep0state = EP0_IN_STATUS_PHASE;
19706 +
19707 + /* Prepare for more SETUP Packets */
19708 + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
19709 + ep0->dwc_ep.xfer_len = 0;
19710 + ep0->dwc_ep.xfer_count = 0;
19711 + ep0->dwc_ep.is_in = 1;
19712 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
19713 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
19714 +
19715 + /* Prepare for more SETUP Packets */
19716 +// if(GET_CORE_IF(pcd)->dma_enable == 0) ep0_out_start(GET_CORE_IF(pcd), pcd);
19717 +}
19718 +
19719 +/**
19720 + * This function starts the Zero-Length Packet for the OUT status phase
19721 + * of a 2 stage control transfer.
19722 + */
19723 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd)
19724 +{
19725 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19726 + if (pcd->ep0state == EP0_STALL) {
19727 + DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
19728 + return;
19729 + }
19730 + pcd->ep0state = EP0_OUT_STATUS_PHASE;
19731 +
19732 + DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
19733 + ep0->dwc_ep.xfer_len = 0;
19734 + ep0->dwc_ep.xfer_count = 0;
19735 + ep0->dwc_ep.is_in = 0;
19736 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
19737 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
19738 +
19739 + /* Prepare for more SETUP Packets */
19740 + if(GET_CORE_IF(pcd)->dma_enable == 0) {
19741 + ep0_out_start(GET_CORE_IF(pcd), pcd);
19742 + }
19743 +}
19744 +
19745 +/**
19746 + * Clear the EP halt (STALL) and if pending requests start the
19747 + * transfer.
19748 + */
19749 +static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
19750 +{
19751 + if(ep->dwc_ep.stall_clear_flag == 0)
19752 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
19753 +
19754 + /* Reactive the EP */
19755 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
19756 + if (ep->stopped) {
19757 + ep->stopped = 0;
19758 + /* If there is a request in the EP queue start it */
19759 +
19760 + /** @todo FIXME: this causes an EP mismatch in DMA mode.
19761 + * epmismatch not yet implemented. */
19762 +
19763 + /*
19764 + * Above fixme is solved by implmenting a tasklet to call the
19765 + * start_next_request(), outside of interrupt context at some
19766 + * time after the current time, after a clear-halt setup packet.
19767 + * Still need to implement ep mismatch in the future if a gadget
19768 + * ever uses more than one endpoint at once
19769 + */
19770 + ep->queue_sof = 1;
19771 + tasklet_schedule (pcd->start_xfer_tasklet);
19772 + }
19773 + /* Start Control Status Phase */
19774 + do_setup_in_status_phase(pcd);
19775 +}
19776 +
19777 +/**
19778 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
19779 + * is sent from the host. The Device Control register is written with
19780 + * the Test Mode bits set to the specified Test Mode. This is done as
19781 + * a tasklet so that the "Status" phase of the control transfer
19782 + * completes before transmitting the TEST packets.
19783 + *
19784 + * @todo This has not been tested since the tasklet struct was put
19785 + * into the PCD struct!
19786 + *
19787 + */
19788 +static void do_test_mode(unsigned long data)
19789 +{
19790 + dctl_data_t dctl;
19791 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)data;
19792 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19793 + int test_mode = pcd->test_mode;
19794 +
19795 +
19796 +// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
19797 +
19798 + dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
19799 + switch (test_mode) {
19800 + case 1: // TEST_J
19801 + dctl.b.tstctl = 1;
19802 + break;
19803 +
19804 + case 2: // TEST_K
19805 + dctl.b.tstctl = 2;
19806 + break;
19807 +
19808 + case 3: // TEST_SE0_NAK
19809 + dctl.b.tstctl = 3;
19810 + break;
19811 +
19812 + case 4: // TEST_PACKET
19813 + dctl.b.tstctl = 4;
19814 + break;
19815 +
19816 + case 5: // TEST_FORCE_ENABLE
19817 + dctl.b.tstctl = 5;
19818 + break;
19819 + }
19820 + dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
19821 +}
19822 +
19823 +/**
19824 + * This function process the GET_STATUS Setup Commands.
19825 + */
19826 +static inline void do_get_status(dwc_otg_pcd_t *pcd)
19827 +{
19828 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
19829 + dwc_otg_pcd_ep_t *ep;
19830 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19831 + uint16_t *status = pcd->status_buf;
19832 +
19833 +#ifdef DEBUG_EP0
19834 + DWC_DEBUGPL(DBG_PCD,
19835 + "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
19836 + ctrl.bRequestType, ctrl.bRequest,
19837 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
19838 +#endif
19839 +
19840 + switch (ctrl.bRequestType & USB_RECIP_MASK) {
19841 + case USB_RECIP_DEVICE:
19842 + *status = 0x1; /* Self powered */
19843 + *status |= pcd->remote_wakeup_enable << 1;
19844 + break;
19845 +
19846 + case USB_RECIP_INTERFACE:
19847 + *status = 0;
19848 + break;
19849 +
19850 + case USB_RECIP_ENDPOINT:
19851 + ep = get_ep_by_addr(pcd, ctrl.wIndex);
19852 + if (ep == 0 || ctrl.wLength > 2) {
19853 + ep0_do_stall(pcd, -EOPNOTSUPP);
19854 + return;
19855 + }
19856 + /** @todo check for EP stall */
19857 + *status = ep->stopped;
19858 + break;
19859 + }
19860 + pcd->ep0_pending = 1;
19861 + ep0->dwc_ep.start_xfer_buff = (uint8_t *)status;
19862 + ep0->dwc_ep.xfer_buff = (uint8_t *)status;
19863 + ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
19864 + ep0->dwc_ep.xfer_len = 2;
19865 + ep0->dwc_ep.xfer_count = 0;
19866 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
19867 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
19868 +}
19869 +/**
19870 + * This function process the SET_FEATURE Setup Commands.
19871 + */
19872 +static inline void do_set_feature(dwc_otg_pcd_t *pcd)
19873 +{
19874 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19875 + dwc_otg_core_global_regs_t *global_regs =
19876 + core_if->core_global_regs;
19877 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
19878 + dwc_otg_pcd_ep_t *ep = 0;
19879 + int32_t otg_cap_param = core_if->core_params->otg_cap;
19880 + gotgctl_data_t gotgctl = { .d32 = 0 };
19881 +
19882 + DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
19883 + ctrl.bRequestType, ctrl.bRequest,
19884 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
19885 + DWC_DEBUGPL(DBG_PCD,"otg_cap=%d\n", otg_cap_param);
19886 +
19887 +
19888 + switch (ctrl.bRequestType & USB_RECIP_MASK) {
19889 + case USB_RECIP_DEVICE:
19890 + switch (ctrl.wValue) {
19891 + case USB_DEVICE_REMOTE_WAKEUP:
19892 + pcd->remote_wakeup_enable = 1;
19893 + break;
19894 +
19895 + case USB_DEVICE_TEST_MODE:
19896 + /* Setup the Test Mode tasklet to do the Test
19897 + * Packet generation after the SETUP Status
19898 + * phase has completed. */
19899 +
19900 + /** @todo This has not been tested since the
19901 + * tasklet struct was put into the PCD
19902 + * struct! */
19903 + pcd->test_mode_tasklet.next = 0;
19904 + pcd->test_mode_tasklet.state = 0;
19905 + atomic_set(&pcd->test_mode_tasklet.count, 0);
19906 + pcd->test_mode_tasklet.func = do_test_mode;
19907 + pcd->test_mode_tasklet.data = (unsigned long)pcd;
19908 + pcd->test_mode = ctrl.wIndex >> 8;
19909 + tasklet_schedule(&pcd->test_mode_tasklet);
19910 + break;
19911 +
19912 + case USB_DEVICE_B_HNP_ENABLE:
19913 + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
19914 +
19915 + /* dev may initiate HNP */
19916 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
19917 + pcd->b_hnp_enable = 1;
19918 + dwc_otg_pcd_update_otg(pcd, 0);
19919 + DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
19920 + /**@todo Is the gotgctl.devhnpen cleared
19921 + * by a USB Reset? */
19922 + gotgctl.b.devhnpen = 1;
19923 + gotgctl.b.hnpreq = 1;
19924 + dwc_write_reg32(&global_regs->gotgctl, gotgctl.d32);
19925 + }
19926 + else {
19927 + ep0_do_stall(pcd, -EOPNOTSUPP);
19928 + }
19929 + break;
19930 +
19931 + case USB_DEVICE_A_HNP_SUPPORT:
19932 + /* RH port supports HNP */
19933 + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
19934 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
19935 + pcd->a_hnp_support = 1;
19936 + dwc_otg_pcd_update_otg(pcd, 0);
19937 + }
19938 + else {
19939 + ep0_do_stall(pcd, -EOPNOTSUPP);
19940 + }
19941 + break;
19942 +
19943 + case USB_DEVICE_A_ALT_HNP_SUPPORT:
19944 + /* other RH port does */
19945 + DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
19946 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
19947 + pcd->a_alt_hnp_support = 1;
19948 + dwc_otg_pcd_update_otg(pcd, 0);
19949 + }
19950 + else {
19951 + ep0_do_stall(pcd, -EOPNOTSUPP);
19952 + }
19953 + break;
19954 + }
19955 + do_setup_in_status_phase(pcd);
19956 + break;
19957 +
19958 + case USB_RECIP_INTERFACE:
19959 + do_gadget_setup(pcd, &ctrl);
19960 + break;
19961 +
19962 + case USB_RECIP_ENDPOINT:
19963 + if (ctrl.wValue == USB_ENDPOINT_HALT) {
19964 + ep = get_ep_by_addr(pcd, ctrl.wIndex);
19965 + if (ep == 0) {
19966 + ep0_do_stall(pcd, -EOPNOTSUPP);
19967 + return;
19968 + }
19969 + ep->stopped = 1;
19970 + dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
19971 + }
19972 + do_setup_in_status_phase(pcd);
19973 + break;
19974 + }
19975 +}
19976 +
19977 +/**
19978 + * This function process the CLEAR_FEATURE Setup Commands.
19979 + */
19980 +static inline void do_clear_feature(dwc_otg_pcd_t *pcd)
19981 +{
19982 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
19983 + dwc_otg_pcd_ep_t *ep = 0;
19984 +
19985 + DWC_DEBUGPL(DBG_PCD,
19986 + "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
19987 + ctrl.bRequestType, ctrl.bRequest,
19988 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
19989 +
19990 + switch (ctrl.bRequestType & USB_RECIP_MASK) {
19991 + case USB_RECIP_DEVICE:
19992 + switch (ctrl.wValue) {
19993 + case USB_DEVICE_REMOTE_WAKEUP:
19994 + pcd->remote_wakeup_enable = 0;
19995 + break;
19996 +
19997 + case USB_DEVICE_TEST_MODE:
19998 + /** @todo Add CLEAR_FEATURE for TEST modes. */
19999 + break;
20000 + }
20001 + do_setup_in_status_phase(pcd);
20002 + break;
20003 +
20004 + case USB_RECIP_ENDPOINT:
20005 + ep = get_ep_by_addr(pcd, ctrl.wIndex);
20006 + if (ep == 0) {
20007 + ep0_do_stall(pcd, -EOPNOTSUPP);
20008 + return;
20009 + }
20010 +
20011 + pcd_clear_halt(pcd, ep);
20012 +
20013 + break;
20014 + }
20015 +}
20016 +
20017 +/**
20018 + * This function process the SET_ADDRESS Setup Commands.
20019 + */
20020 +static inline void do_set_address(dwc_otg_pcd_t *pcd)
20021 +{
20022 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
20023 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
20024 +
20025 + if (ctrl.bRequestType == USB_RECIP_DEVICE) {
20026 + dcfg_data_t dcfg = {.d32=0};
20027 +
20028 +#ifdef DEBUG_EP0
20029 +// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
20030 +#endif
20031 + dcfg.b.devaddr = ctrl.wValue;
20032 + dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
20033 + do_setup_in_status_phase(pcd);
20034 + }
20035 +}
20036 +
20037 +/**
20038 + * This function processes SETUP commands. In Linux, the USB Command
20039 + * processing is done in two places - the first being the PCD and the
20040 + * second in the Gadget Driver (for example, the File-Backed Storage
20041 + * Gadget Driver).
20042 + *
20043 + * <table>
20044 + * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
20045 + *
20046 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
20047 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
20048 + * </td></tr>
20049 + *
20050 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
20051 + * requests are the ENDPOINT_HALT feature is procesed, all others the
20052 + * interface requests are ignored.</td></tr>
20053 + *
20054 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
20055 + * requests are processed by the PCD. Interface requests are passed
20056 + * to the Gadget Driver.</td></tr>
20057 + *
20058 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
20059 + * with device address received </td></tr>
20060 + *
20061 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
20062 + * requested descriptor</td></tr>
20063 + *
20064 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
20065 + * not implemented by any of the existing Gadget Drivers.</td></tr>
20066 + *
20067 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
20068 + * all EPs and enable EPs for new configuration.</td></tr>
20069 + *
20070 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
20071 + * the current configuration</td></tr>
20072 + *
20073 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
20074 + * EPs and enable EPs for new configuration.</td></tr>
20075 + *
20076 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
20077 + * current interface.</td></tr>
20078 + *
20079 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
20080 + * message.</td></tr>
20081 + * </table>
20082 + *
20083 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
20084 + * processed by pcd_setup. Calling the Function Driver's setup function from
20085 + * pcd_setup processes the gadget SETUP commands.
20086 + */
20087 +static inline void pcd_setup(dwc_otg_pcd_t *pcd)
20088 +{
20089 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20090 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
20091 + struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
20092 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
20093 +
20094 + deptsiz0_data_t doeptsize0 = { .d32 = 0};
20095 +
20096 +#ifdef DEBUG_EP0
20097 + DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
20098 + ctrl.bRequestType, ctrl.bRequest,
20099 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
20100 +#endif
20101 +
20102 + doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
20103 +
20104 + /** @todo handle > 1 setup packet , assert error for now */
20105 +
20106 + if (core_if->dma_enable && core_if->dma_desc_enable == 0 && (doeptsize0.b.supcnt < 2)) {
20107 + DWC_ERROR ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
20108 + }
20109 +
20110 + /* Clean up the request queue */
20111 + dwc_otg_request_nuke(ep0);
20112 + ep0->stopped = 0;
20113 +
20114 + if (ctrl.bRequestType & USB_DIR_IN) {
20115 + ep0->dwc_ep.is_in = 1;
20116 + pcd->ep0state = EP0_IN_DATA_PHASE;
20117 + }
20118 + else {
20119 + ep0->dwc_ep.is_in = 0;
20120 + pcd->ep0state = EP0_OUT_DATA_PHASE;
20121 + }
20122 +
20123 + if(ctrl.wLength == 0) {
20124 + ep0->dwc_ep.is_in = 1;
20125 + pcd->ep0state = EP0_IN_STATUS_PHASE;
20126 + }
20127 +
20128 + if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) {
20129 + /* handle non-standard (class/vendor) requests in the gadget driver */
20130 + do_gadget_setup(pcd, &ctrl);
20131 + return;
20132 + }
20133 +
20134 + /** @todo NGS: Handle bad setup packet? */
20135 +
20136 +///////////////////////////////////////////
20137 +//// --- Standard Request handling --- ////
20138 +
20139 + switch (ctrl.bRequest) {
20140 + case USB_REQ_GET_STATUS:
20141 + do_get_status(pcd);
20142 + break;
20143 +
20144 + case USB_REQ_CLEAR_FEATURE:
20145 + do_clear_feature(pcd);
20146 + break;
20147 +
20148 + case USB_REQ_SET_FEATURE:
20149 + do_set_feature(pcd);
20150 + break;
20151 +
20152 + case USB_REQ_SET_ADDRESS:
20153 + do_set_address(pcd);
20154 + break;
20155 +
20156 + case USB_REQ_SET_INTERFACE:
20157 + case USB_REQ_SET_CONFIGURATION:
20158 +// _pcd->request_config = 1; /* Configuration changed */
20159 + do_gadget_setup(pcd, &ctrl);
20160 + break;
20161 +
20162 + case USB_REQ_SYNCH_FRAME:
20163 + do_gadget_setup(pcd, &ctrl);
20164 + break;
20165 +
20166 + default:
20167 + /* Call the Gadget Driver's setup functions */
20168 + do_gadget_setup(pcd, &ctrl);
20169 + break;
20170 + }
20171 +}
20172 +
20173 +/**
20174 + * This function completes the ep0 control transfer.
20175 + */
20176 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep)
20177 +{
20178 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
20179 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
20180 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
20181 + dev_if->in_ep_regs[ep->dwc_ep.num];
20182 +#ifdef DEBUG_EP0
20183 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
20184 + dev_if->out_ep_regs[ep->dwc_ep.num];
20185 +#endif
20186 + deptsiz0_data_t deptsiz;
20187 + desc_sts_data_t desc_sts;
20188 + dwc_otg_pcd_request_t *req;
20189 + int is_last = 0;
20190 + dwc_otg_pcd_t *pcd = ep->pcd;
20191 +
20192 + //DWC_DEBUGPL(DBG_PCDV, "%s() %s\n", __func__, _ep->ep.name);
20193 +
20194 + if (pcd->ep0_pending && list_empty(&ep->queue)) {
20195 + if (ep->dwc_ep.is_in) {
20196 +#ifdef DEBUG_EP0
20197 + DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
20198 +#endif
20199 + do_setup_out_status_phase(pcd);
20200 + }
20201 + else {
20202 +#ifdef DEBUG_EP0
20203 + DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
20204 +#endif
20205 + do_setup_in_status_phase(pcd);
20206 + }
20207 + pcd->ep0_pending = 0;
20208 + return 1;
20209 + }
20210 +
20211 + if (list_empty(&ep->queue)) {
20212 + return 0;
20213 + }
20214 + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, queue);
20215 +
20216 +
20217 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) {
20218 + is_last = 1;
20219 + }
20220 + else if (ep->dwc_ep.is_in) {
20221 + deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
20222 + if(core_if->dma_desc_enable != 0)
20223 + desc_sts.d32 = readl(dev_if->in_desc_addr);
20224 +#ifdef DEBUG_EP0
20225 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
20226 + ep->ep.name, ep->dwc_ep.xfer_len,
20227 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
20228 +#endif
20229 +
20230 + if (((core_if->dma_desc_enable == 0) && (deptsiz.b.xfersize == 0)) ||
20231 + ((core_if->dma_desc_enable != 0) && (desc_sts.b.bytes == 0))) {
20232 + req->req.actual = ep->dwc_ep.xfer_count;
20233 + /* Is a Zero Len Packet needed? */
20234 + if (req->req.zero) {
20235 +#ifdef DEBUG_EP0
20236 + DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
20237 +#endif
20238 + req->req.zero = 0;
20239 + }
20240 + do_setup_out_status_phase(pcd);
20241 + }
20242 + }
20243 + else {
20244 + /* ep0-OUT */
20245 +#ifdef DEBUG_EP0
20246 + deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
20247 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xsize=%d pktcnt=%d\n",
20248 + ep->ep.name, ep->dwc_ep.xfer_len,
20249 + deptsiz.b.xfersize,
20250 + deptsiz.b.pktcnt);
20251 +#endif
20252 + req->req.actual = ep->dwc_ep.xfer_count;
20253 + /* Is a Zero Len Packet needed? */
20254 + if (req->req.zero) {
20255 +#ifdef DEBUG_EP0
20256 + DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
20257 +#endif
20258 + req->req.zero = 0;
20259 + }
20260 + if(core_if->dma_desc_enable == 0)
20261 + do_setup_in_status_phase(pcd);
20262 + }
20263 +
20264 + /* Complete the request */
20265 + if (is_last) {
20266 + dwc_otg_request_done(ep, req, 0);
20267 + ep->dwc_ep.start_xfer_buff = 0;
20268 + ep->dwc_ep.xfer_buff = 0;
20269 + ep->dwc_ep.xfer_len = 0;
20270 + return 1;
20271 + }
20272 + return 0;
20273 +}
20274 +
20275 +/**
20276 + * This function completes the request for the EP. If there are
20277 + * additional requests for the EP in the queue they will be started.
20278 + */
20279 +static void complete_ep(dwc_otg_pcd_ep_t *ep)
20280 +{
20281 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
20282 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
20283 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
20284 + dev_if->in_ep_regs[ep->dwc_ep.num];
20285 + deptsiz_data_t deptsiz;
20286 + desc_sts_data_t desc_sts;
20287 + dwc_otg_pcd_request_t *req = 0;
20288 + dwc_otg_dma_desc_t* dma_desc;
20289 + uint32_t byte_count = 0;
20290 + int is_last = 0;
20291 + int i;
20292 +
20293 + DWC_DEBUGPL(DBG_PCDV,"%s() %s-%s\n", __func__, ep->ep.name,
20294 + (ep->dwc_ep.is_in?"IN":"OUT"));
20295 +
20296 + /* Get any pending requests */
20297 + if (!list_empty(&ep->queue)) {
20298 + req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
20299 + queue);
20300 + if (!req) {
20301 + printk("complete_ep 0x%p, req = NULL!\n", ep);
20302 + return;
20303 + }
20304 + }
20305 + else {
20306 + printk("complete_ep 0x%p, ep->queue empty!\n", ep);
20307 + return;
20308 + }
20309 + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
20310 +
20311 + if (ep->dwc_ep.is_in) {
20312 + deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
20313 +
20314 + if (core_if->dma_enable) {
20315 + if(core_if->dma_desc_enable == 0) {
20316 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
20317 + byte_count = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
20318 +
20319 + ep->dwc_ep.xfer_buff += byte_count;
20320 + ep->dwc_ep.dma_addr += byte_count;
20321 + ep->dwc_ep.xfer_count += byte_count;
20322 +
20323 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
20324 + ep->ep.name, ep->dwc_ep.xfer_len,
20325 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
20326 +
20327 +
20328 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20329 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20330 + } else if(ep->dwc_ep.sent_zlp) {
20331 + /*
20332 + * This fragment of code should initiate 0
20333 + * length trasfer in case if it is queued
20334 + * a trasfer with size divisible to EPs max
20335 + * packet size and with usb_request zero field
20336 + * is set, which means that after data is transfered,
20337 + * it is also should be transfered
20338 + * a 0 length packet at the end. For Slave and
20339 + * Buffer DMA modes in this case SW has
20340 + * to initiate 2 transfers one with transfer size,
20341 + * and the second with 0 size. For Desriptor
20342 + * DMA mode SW is able to initiate a transfer,
20343 + * which will handle all the packets including
20344 + * the last 0 legth.
20345 + */
20346 + ep->dwc_ep.sent_zlp = 0;
20347 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20348 + } else {
20349 + is_last = 1;
20350 + }
20351 + } else {
20352 + DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
20353 + ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
20354 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
20355 + }
20356 + } else {
20357 + dma_desc = ep->dwc_ep.desc_addr;
20358 + byte_count = 0;
20359 + ep->dwc_ep.sent_zlp = 0;
20360 +
20361 + for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
20362 + desc_sts.d32 = readl(dma_desc);
20363 + byte_count += desc_sts.b.bytes;
20364 + dma_desc++;
20365 + }
20366 +
20367 + if(byte_count == 0) {
20368 + ep->dwc_ep.xfer_count = ep->dwc_ep.total_len;
20369 + is_last = 1;
20370 + } else {
20371 + DWC_WARN("Incomplete transfer\n");
20372 + }
20373 + }
20374 + } else {
20375 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
20376 + /* Check if the whole transfer was completed,
20377 + * if no, setup transfer for next portion of data
20378 + */
20379 + DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
20380 + ep->ep.name, ep->dwc_ep.xfer_len,
20381 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
20382 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20383 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20384 + } else if(ep->dwc_ep.sent_zlp) {
20385 + /*
20386 + * This fragment of code should initiate 0
20387 + * length trasfer in case if it is queued
20388 + * a trasfer with size divisible to EPs max
20389 + * packet size and with usb_request zero field
20390 + * is set, which means that after data is transfered,
20391 + * it is also should be transfered
20392 + * a 0 length packet at the end. For Slave and
20393 + * Buffer DMA modes in this case SW has
20394 + * to initiate 2 transfers one with transfer size,
20395 + * and the second with 0 size. For Desriptor
20396 + * DMA mode SW is able to initiate a transfer,
20397 + * which will handle all the packets including
20398 + * the last 0 legth.
20399 + */
20400 + ep->dwc_ep.sent_zlp = 0;
20401 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20402 + } else {
20403 + is_last = 1;
20404 + }
20405 + }
20406 + else {
20407 + DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
20408 + ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
20409 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
20410 + }
20411 + }
20412 + } else {
20413 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
20414 + dev_if->out_ep_regs[ep->dwc_ep.num];
20415 + desc_sts.d32 = 0;
20416 + if(core_if->dma_enable) {
20417 + if(core_if->dma_desc_enable) {
20418 + dma_desc = ep->dwc_ep.desc_addr;
20419 + byte_count = 0;
20420 + ep->dwc_ep.sent_zlp = 0;
20421 + for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
20422 + desc_sts.d32 = readl(dma_desc);
20423 + byte_count += desc_sts.b.bytes;
20424 + dma_desc++;
20425 + }
20426 +
20427 + ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
20428 + - byte_count + ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
20429 + is_last = 1;
20430 + } else {
20431 + deptsiz.d32 = 0;
20432 + deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
20433 +
20434 + byte_count = (ep->dwc_ep.xfer_len -
20435 + ep->dwc_ep.xfer_count - deptsiz.b.xfersize);
20436 + ep->dwc_ep.xfer_buff += byte_count;
20437 + ep->dwc_ep.dma_addr += byte_count;
20438 + ep->dwc_ep.xfer_count += byte_count;
20439 +
20440 + /* Check if the whole transfer was completed,
20441 + * if no, setup transfer for next portion of data
20442 + */
20443 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20444 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20445 + }
20446 + else if(ep->dwc_ep.sent_zlp) {
20447 + /*
20448 + * This fragment of code should initiate 0
20449 + * length trasfer in case if it is queued
20450 + * a trasfer with size divisible to EPs max
20451 + * packet size and with usb_request zero field
20452 + * is set, which means that after data is transfered,
20453 + * it is also should be transfered
20454 + * a 0 length packet at the end. For Slave and
20455 + * Buffer DMA modes in this case SW has
20456 + * to initiate 2 transfers one with transfer size,
20457 + * and the second with 0 size. For Desriptor
20458 + * DMA mode SW is able to initiate a transfer,
20459 + * which will handle all the packets including
20460 + * the last 0 legth.
20461 + */
20462 + ep->dwc_ep.sent_zlp = 0;
20463 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20464 + } else {
20465 + is_last = 1;
20466 + }
20467 + }
20468 + } else {
20469 + /* Check if the whole transfer was completed,
20470 + * if no, setup transfer for next portion of data
20471 + */
20472 + if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
20473 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
20474 + }
20475 + else if(ep->dwc_ep.sent_zlp) {
20476 + /*
20477 + * This fragment of code should initiate 0
20478 + * length trasfer in case if it is queued
20479 + * a trasfer with size divisible to EPs max
20480 + * packet size and with usb_request zero field
20481 + * is set, which means that after data is transfered,
20482 + * it is also should be transfered
20483 + * a 0 length packet at the end. For Slave and
20484 + * Buffer DMA modes in this case SW has
20485 + * to initiate 2 transfers one with transfer size,
20486 + * and the second with 0 size. For Desriptor
20487 + * DMA mode SW is able to initiate a transfer,
20488 + * which will handle all the packets including
20489 + * the last 0 legth.
20490 + */
20491 + ep->dwc_ep.sent_zlp = 0;
20492 + dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
20493 + } else {
20494 + is_last = 1;
20495 + }
20496 + }
20497 +
20498 +#ifdef DEBUG
20499 +
20500 + DWC_DEBUGPL(DBG_PCDV, "addr %p, %s len=%d cnt=%d xsize=%d pktcnt=%d\n",
20501 + &out_ep_regs->doeptsiz, ep->ep.name, ep->dwc_ep.xfer_len,
20502 + ep->dwc_ep.xfer_count,
20503 + deptsiz.b.xfersize,
20504 + deptsiz.b.pktcnt);
20505 +#endif
20506 + }
20507 +
20508 + /* Complete the request */
20509 + if (is_last) {
20510 + req->req.actual = ep->dwc_ep.xfer_count;
20511 +
20512 + dwc_otg_request_done(ep, req, 0);
20513 +
20514 + ep->dwc_ep.start_xfer_buff = 0;
20515 + ep->dwc_ep.xfer_buff = 0;
20516 + ep->dwc_ep.xfer_len = 0;
20517 +
20518 + /* If there is a request in the queue start it.*/
20519 + start_next_request(ep);
20520 + }
20521 +}
20522 +
20523 +
20524 +#ifdef DWC_EN_ISOC
20525 +
20526 +/**
20527 + * This function BNA interrupt for Isochronous EPs
20528 + *
20529 + */
20530 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep)
20531 +{
20532 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
20533 + volatile uint32_t *addr;
20534 + depctl_data_t depctl = {.d32 = 0};
20535 + dwc_otg_pcd_t *pcd = ep->pcd;
20536 + dwc_otg_dma_desc_t *dma_desc;
20537 + int i;
20538 +
20539 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
20540 +
20541 + if(dwc_ep->is_in) {
20542 + desc_sts_data_t sts = {.d32 = 0};
20543 + for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
20544 + {
20545 + sts.d32 = readl(&dma_desc->status);
20546 + sts.b_iso_in.bs = BS_HOST_READY;
20547 + writel(sts.d32,&dma_desc->status);
20548 + }
20549 + }
20550 + else {
20551 + desc_sts_data_t sts = {.d32 = 0};
20552 + for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
20553 + {
20554 + sts.d32 = readl(&dma_desc->status);
20555 + sts.b_iso_out.bs = BS_HOST_READY;
20556 + writel(sts.d32,&dma_desc->status);
20557 + }
20558 + }
20559 +
20560 + if(dwc_ep->is_in == 0){
20561 + addr = &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
20562 + }
20563 + else{
20564 + addr = &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
20565 + }
20566 + depctl.b.epena = 1;
20567 + dwc_modify_reg32(addr,depctl.d32,depctl.d32);
20568 +}
20569 +
20570 +/**
20571 + * This function sets latest iso packet information(non-PTI mode)
20572 + *
20573 + * @param core_if Programming view of DWC_otg controller.
20574 + * @param ep The EP to start the transfer on.
20575 + *
20576 + */
20577 +void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
20578 +{
20579 + deptsiz_data_t deptsiz = { .d32 = 0 };
20580 + dma_addr_t dma_addr;
20581 + uint32_t offset;
20582 +
20583 + if(ep->proc_buf_num)
20584 + dma_addr = ep->dma_addr1;
20585 + else
20586 + dma_addr = ep->dma_addr0;
20587 +
20588 +
20589 + if(ep->is_in) {
20590 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
20591 + offset = ep->data_per_frame;
20592 + } else {
20593 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
20594 + offset = ep->data_per_frame + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
20595 + }
20596 +
20597 + if(!deptsiz.b.xfersize) {
20598 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
20599 + ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
20600 + ep->pkt_info[ep->cur_pkt].status = 0;
20601 + } else {
20602 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
20603 + ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
20604 + ep->pkt_info[ep->cur_pkt].status = -ENODATA;
20605 + }
20606 + ep->cur_pkt_addr += offset;
20607 + ep->cur_pkt_dma_addr += offset;
20608 + ep->cur_pkt++;
20609 +}
20610 +
20611 +/**
20612 + * This function sets latest iso packet information(DDMA mode)
20613 + *
20614 + * @param core_if Programming view of DWC_otg controller.
20615 + * @param dwc_ep The EP to start the transfer on.
20616 + *
20617 + */
20618 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
20619 +{
20620 + dwc_otg_dma_desc_t* dma_desc;
20621 + desc_sts_data_t sts = {.d32 = 0};
20622 + iso_pkt_info_t *iso_packet;
20623 + uint32_t data_per_desc;
20624 + uint32_t offset;
20625 + int i, j;
20626 +
20627 + iso_packet = dwc_ep->pkt_info;
20628 +
20629 + /** Reinit closed DMA Descriptors*/
20630 + /** ISO OUT EP */
20631 + if(dwc_ep->is_in == 0) {
20632 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20633 + offset = 0;
20634 +
20635 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
20636 + {
20637 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
20638 + {
20639 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20640 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20641 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20642 +
20643 + sts.d32 = readl(&dma_desc->status);
20644 +
20645 + /* Write status in iso_packet_decsriptor */
20646 + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
20647 + if(iso_packet->status) {
20648 + iso_packet->status = -ENODATA;
20649 + }
20650 +
20651 + /* Received data length */
20652 + if(!sts.b_iso_out.rxbytes){
20653 + iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes;
20654 + } else {
20655 + iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes +
20656 + (4 - dwc_ep->data_per_frame % 4);
20657 + }
20658 +
20659 + iso_packet->offset = offset;
20660 +
20661 + offset += data_per_desc;
20662 + dma_desc ++;
20663 + iso_packet ++;
20664 + }
20665 + }
20666 +
20667 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
20668 + {
20669 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20670 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20671 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20672 +
20673 + sts.d32 = readl(&dma_desc->status);
20674 +
20675 + /* Write status in iso_packet_decsriptor */
20676 + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
20677 + if(iso_packet->status) {
20678 + iso_packet->status = -ENODATA;
20679 + }
20680 +
20681 + /* Received data length */
20682 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
20683 +
20684 + iso_packet->offset = offset;
20685 +
20686 + offset += data_per_desc;
20687 + iso_packet++;
20688 + dma_desc++;
20689 + }
20690 +
20691 + sts.d32 = readl(&dma_desc->status);
20692 +
20693 + /* Write status in iso_packet_decsriptor */
20694 + iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
20695 + if(iso_packet->status) {
20696 + iso_packet->status = -ENODATA;
20697 + }
20698 + /* Received data length */
20699 + if(!sts.b_iso_out.rxbytes){
20700 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
20701 + } else {
20702 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
20703 + (4 - dwc_ep->data_per_frame % 4);
20704 + }
20705 +
20706 + iso_packet->offset = offset;
20707 + }
20708 + else /** ISO IN EP */
20709 + {
20710 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20711 +
20712 + for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
20713 + {
20714 + sts.d32 = readl(&dma_desc->status);
20715 +
20716 + /* Write status in iso packet descriptor */
20717 + iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
20718 + if(iso_packet->status != 0) {
20719 + iso_packet->status = -ENODATA;
20720 +
20721 + }
20722 + /* Bytes has been transfered */
20723 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
20724 +
20725 + dma_desc ++;
20726 + iso_packet++;
20727 + }
20728 +
20729 + sts.d32 = readl(&dma_desc->status);
20730 + while(sts.b_iso_in.bs == BS_DMA_BUSY) {
20731 + sts.d32 = readl(&dma_desc->status);
20732 + }
20733 +
20734 + /* Write status in iso packet descriptor ??? do be done with ERROR codes*/
20735 + iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
20736 + if(iso_packet->status != 0) {
20737 + iso_packet->status = -ENODATA;
20738 + }
20739 +
20740 + /* Bytes has been transfered */
20741 + iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
20742 + }
20743 +}
20744 +
20745 +/**
20746 + * This function reinitialize DMA Descriptors for Isochronous transfer
20747 + *
20748 + * @param core_if Programming view of DWC_otg controller.
20749 + * @param dwc_ep The EP to start the transfer on.
20750 + *
20751 + */
20752 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
20753 +{
20754 + int i, j;
20755 + dwc_otg_dma_desc_t* dma_desc;
20756 + dma_addr_t dma_ad;
20757 + volatile uint32_t *addr;
20758 + desc_sts_data_t sts = { .d32 =0 };
20759 + uint32_t data_per_desc;
20760 +
20761 + if(dwc_ep->is_in == 0) {
20762 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
20763 + }
20764 + else {
20765 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
20766 + }
20767 +
20768 +
20769 + if(dwc_ep->proc_buf_num == 0) {
20770 + /** Buffer 0 descriptors setup */
20771 + dma_ad = dwc_ep->dma_addr0;
20772 + }
20773 + else {
20774 + /** Buffer 1 descriptors setup */
20775 + dma_ad = dwc_ep->dma_addr1;
20776 + }
20777 +
20778 +
20779 + /** Reinit closed DMA Descriptors*/
20780 + /** ISO OUT EP */
20781 + if(dwc_ep->is_in == 0) {
20782 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20783 +
20784 + sts.b_iso_out.bs = BS_HOST_READY;
20785 + sts.b_iso_out.rxsts = 0;
20786 + sts.b_iso_out.l = 0;
20787 + sts.b_iso_out.sp = 0;
20788 + sts.b_iso_out.ioc = 0;
20789 + sts.b_iso_out.pid = 0;
20790 + sts.b_iso_out.framenum = 0;
20791 +
20792 + for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
20793 + {
20794 + for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
20795 + {
20796 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20797 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20798 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20799 + sts.b_iso_out.rxbytes = data_per_desc;
20800 + writel((uint32_t)dma_ad, &dma_desc->buf);
20801 + writel(sts.d32, &dma_desc->status);
20802 +
20803 + (uint32_t)dma_ad += data_per_desc;
20804 + dma_desc ++;
20805 + }
20806 + }
20807 +
20808 + for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
20809 + {
20810 +
20811 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20812 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20813 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20814 + sts.b_iso_out.rxbytes = data_per_desc;
20815 +
20816 + writel((uint32_t)dma_ad, &dma_desc->buf);
20817 + writel(sts.d32, &dma_desc->status);
20818 +
20819 + dma_desc++;
20820 + (uint32_t)dma_ad += data_per_desc;
20821 + }
20822 +
20823 + sts.b_iso_out.ioc = 1;
20824 + sts.b_iso_out.l = dwc_ep->proc_buf_num;
20825 +
20826 + data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
20827 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
20828 + data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
20829 + sts.b_iso_out.rxbytes = data_per_desc;
20830 +
20831 + writel((uint32_t)dma_ad, &dma_desc->buf);
20832 + writel(sts.d32, &dma_desc->status);
20833 + }
20834 + else /** ISO IN EP */
20835 + {
20836 + dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
20837 +
20838 + sts.b_iso_in.bs = BS_HOST_READY;
20839 + sts.b_iso_in.txsts = 0;
20840 + sts.b_iso_in.sp = 0;
20841 + sts.b_iso_in.ioc = 0;
20842 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
20843 + sts.b_iso_in.framenum = dwc_ep->next_frame;
20844 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
20845 + sts.b_iso_in.l = 0;
20846 +
20847 + for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
20848 + {
20849 + writel((uint32_t)dma_ad, &dma_desc->buf);
20850 + writel(sts.d32, &dma_desc->status);
20851 +
20852 + sts.b_iso_in.framenum += dwc_ep->bInterval;
20853 + (uint32_t)dma_ad += dwc_ep->data_per_frame;
20854 + dma_desc ++;
20855 + }
20856 +
20857 + sts.b_iso_in.ioc = 1;
20858 + sts.b_iso_in.l = dwc_ep->proc_buf_num;
20859 +
20860 + writel((uint32_t)dma_ad, &dma_desc->buf);
20861 + writel(sts.d32, &dma_desc->status);
20862 +
20863 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
20864 + }
20865 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20866 +}
20867 +
20868 +
20869 +/**
20870 + * This function is to handle Iso EP transfer complete interrupt
20871 + * in case Iso out packet was dropped
20872 + *
20873 + * @param core_if Programming view of DWC_otg controller.
20874 + * @param dwc_ep The EP for wihich transfer complete was asserted
20875 + *
20876 + */
20877 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
20878 +{
20879 + uint32_t dma_addr;
20880 + uint32_t drp_pkt;
20881 + uint32_t drp_pkt_cnt;
20882 + deptsiz_data_t deptsiz = { .d32 = 0 };
20883 + depctl_data_t depctl = { .d32 = 0 };
20884 + int i;
20885 +
20886 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
20887 +
20888 + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
20889 + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
20890 +
20891 + /* Setting dropped packets status */
20892 + for(i = 0; i < drp_pkt_cnt; ++i) {
20893 + dwc_ep->pkt_info[drp_pkt].status = -ENODATA;
20894 + drp_pkt ++;
20895 + deptsiz.b.pktcnt--;
20896 + }
20897 +
20898 +
20899 + if(deptsiz.b.pktcnt > 0) {
20900 + deptsiz.b.xfersize = dwc_ep->xfer_len - (dwc_ep->pkt_cnt - deptsiz.b.pktcnt) * dwc_ep->maxpacket;
20901 + } else {
20902 + deptsiz.b.xfersize = 0;
20903 + deptsiz.b.pktcnt = 0;
20904 + }
20905 +
20906 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, deptsiz.d32);
20907 +
20908 + if(deptsiz.b.pktcnt > 0) {
20909 + if(dwc_ep->proc_buf_num) {
20910 + dma_addr = dwc_ep->dma_addr1 + dwc_ep->xfer_len - deptsiz.b.xfersize;
20911 + } else {
20912 + dma_addr = dwc_ep->dma_addr0 + dwc_ep->xfer_len - deptsiz.b.xfersize;;
20913 + }
20914 +
20915 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
20916 +
20917 + /** Re-enable endpoint, clear nak */
20918 + depctl.d32 = 0;
20919 + depctl.b.epena = 1;
20920 + depctl.b.cnak = 1;
20921 +
20922 + dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl,
20923 + depctl.d32,depctl.d32);
20924 + return 0;
20925 + } else {
20926 + return 1;
20927 + }
20928 +}
20929 +
20930 +/**
20931 + * This function sets iso packets information(PTI mode)
20932 + *
20933 + * @param core_if Programming view of DWC_otg controller.
20934 + * @param ep The EP to start the transfer on.
20935 + *
20936 + */
20937 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
20938 +{
20939 + int i, j;
20940 + dma_addr_t dma_ad;
20941 + iso_pkt_info_t *packet_info = ep->pkt_info;
20942 + uint32_t offset;
20943 + uint32_t frame_data;
20944 + deptsiz_data_t deptsiz;
20945 +
20946 + if(ep->proc_buf_num == 0) {
20947 + /** Buffer 0 descriptors setup */
20948 + dma_ad = ep->dma_addr0;
20949 + }
20950 + else {
20951 + /** Buffer 1 descriptors setup */
20952 + dma_ad = ep->dma_addr1;
20953 + }
20954 +
20955 +
20956 + if(ep->is_in) {
20957 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
20958 + } else {
20959 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
20960 + }
20961 +
20962 + if(!deptsiz.b.xfersize) {
20963 + offset = 0;
20964 + for(i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm)
20965 + {
20966 + frame_data = ep->data_per_frame;
20967 + for(j = 0; j < ep->pkt_per_frm; ++j) {
20968 +
20969 + /* Packet status - is not set as initially
20970 + * it is set to 0 and if packet was sent
20971 + successfully, status field will remain 0*/
20972 +
20973 +
20974 + /* Bytes has been transfered */
20975 + packet_info->length = (ep->maxpacket < frame_data) ?
20976 + ep->maxpacket : frame_data;
20977 +
20978 + /* Received packet offset */
20979 + packet_info->offset = offset;
20980 + offset += packet_info->length;
20981 + frame_data -= packet_info->length;
20982 +
20983 + packet_info ++;
20984 + }
20985 + }
20986 + return 1;
20987 + } else {
20988 + /* This is a workaround for in case of Transfer Complete with
20989 + * PktDrpSts interrupts merging - in this case Transfer complete
20990 + * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
20991 + * set and with DOEPTSIZ register non zero. Investigations showed,
20992 + * that this happens when Out packet is dropped, but because of
20993 + * interrupts merging during first interrupt handling PktDrpSts
20994 + * bit is cleared and for next merged interrupts it is not reset.
20995 + * In this case SW hadles the interrupt as if PktDrpSts bit is set.
20996 + */
20997 + if(ep->is_in) {
20998 + return 1;
20999 + } else {
21000 + return handle_iso_out_pkt_dropped(core_if, ep);
21001 + }
21002 + }
21003 +}
21004 +
21005 +/**
21006 + * This function is to handle Iso EP transfer complete interrupt
21007 + *
21008 + * @param ep The EP for which transfer complete was asserted
21009 + *
21010 + */
21011 +static void complete_iso_ep(dwc_otg_pcd_ep_t *ep)
21012 +{
21013 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
21014 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
21015 + uint8_t is_last = 0;
21016 +
21017 + if(core_if->dma_enable) {
21018 + if(core_if->dma_desc_enable) {
21019 + set_ddma_iso_pkts_info(core_if, dwc_ep);
21020 + reinit_ddma_iso_xfer(core_if, dwc_ep);
21021 + is_last = 1;
21022 + } else {
21023 + if(core_if->pti_enh_enable) {
21024 + if(set_iso_pkts_info(core_if, dwc_ep)) {
21025 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
21026 + dwc_otg_iso_ep_start_buf_transfer(core_if, dwc_ep);
21027 + is_last = 1;
21028 + }
21029 + } else {
21030 + set_current_pkt_info(core_if, dwc_ep);
21031 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
21032 + is_last = 1;
21033 + dwc_ep->cur_pkt = 0;
21034 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
21035 + if(dwc_ep->proc_buf_num) {
21036 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
21037 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
21038 + } else {
21039 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
21040 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
21041 + }
21042 +
21043 + }
21044 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
21045 + }
21046 + }
21047 + } else {
21048 + set_current_pkt_info(core_if, dwc_ep);
21049 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
21050 + is_last = 1;
21051 + dwc_ep->cur_pkt = 0;
21052 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
21053 + if(dwc_ep->proc_buf_num) {
21054 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
21055 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
21056 + } else {
21057 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
21058 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
21059 + }
21060 +
21061 + }
21062 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
21063 + }
21064 + if(is_last)
21065 + dwc_otg_iso_buffer_done(ep, ep->iso_req);
21066 +}
21067 +
21068 +#endif //DWC_EN_ISOC
21069 +
21070 +
21071 +/**
21072 + * This function handles EP0 Control transfers.
21073 + *
21074 + * The state of the control tranfers are tracked in
21075 + * <code>ep0state</code>.
21076 + */
21077 +static void handle_ep0(dwc_otg_pcd_t *pcd)
21078 +{
21079 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21080 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
21081 + desc_sts_data_t desc_sts;
21082 + deptsiz0_data_t deptsiz;
21083 + uint32_t byte_count;
21084 +
21085 +#ifdef DEBUG_EP0
21086 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
21087 + print_ep0_state(pcd);
21088 +#endif
21089 +
21090 + switch (pcd->ep0state) {
21091 + case EP0_DISCONNECT:
21092 + break;
21093 +
21094 + case EP0_IDLE:
21095 + pcd->request_config = 0;
21096 +
21097 + pcd_setup(pcd);
21098 + break;
21099 +
21100 + case EP0_IN_DATA_PHASE:
21101 +#ifdef DEBUG_EP0
21102 + DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
21103 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
21104 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
21105 +#endif
21106 +
21107 + if (core_if->dma_enable != 0) {
21108 + /*
21109 + * For EP0 we can only program 1 packet at a time so we
21110 + * need to do the make calculations after each complete.
21111 + * Call write_packet to make the calculations, as in
21112 + * slave mode, and use those values to determine if we
21113 + * can complete.
21114 + */
21115 + if(core_if->dma_desc_enable == 0) {
21116 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->dieptsiz);
21117 + byte_count = ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
21118 + }
21119 + else {
21120 + desc_sts.d32 = readl(core_if->dev_if->in_desc_addr);
21121 + byte_count = ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
21122 + }
21123 + ep0->dwc_ep.xfer_count += byte_count;
21124 + ep0->dwc_ep.xfer_buff += byte_count;
21125 + ep0->dwc_ep.dma_addr += byte_count;
21126 + }
21127 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
21128 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21129 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21130 + }
21131 + else if(ep0->dwc_ep.sent_zlp) {
21132 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21133 + ep0->dwc_ep.sent_zlp = 0;
21134 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21135 + }
21136 + else {
21137 + ep0_complete_request(ep0);
21138 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
21139 + }
21140 + break;
21141 + case EP0_OUT_DATA_PHASE:
21142 +#ifdef DEBUG_EP0
21143 + DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
21144 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
21145 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
21146 +#endif
21147 + if (core_if->dma_enable != 0) {
21148 + if(core_if->dma_desc_enable == 0) {
21149 + deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[0]->doeptsiz);
21150 + byte_count = ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
21151 + }
21152 + else {
21153 + desc_sts.d32 = readl(core_if->dev_if->out_desc_addr);
21154 + byte_count = ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
21155 + }
21156 + ep0->dwc_ep.xfer_count += byte_count;
21157 + ep0->dwc_ep.xfer_buff += byte_count;
21158 + ep0->dwc_ep.dma_addr += byte_count;
21159 + }
21160 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
21161 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21162 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21163 + }
21164 + else if(ep0->dwc_ep.sent_zlp) {
21165 + dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
21166 + ep0->dwc_ep.sent_zlp = 0;
21167 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
21168 + }
21169 + else {
21170 + ep0_complete_request(ep0);
21171 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
21172 + }
21173 + break;
21174 +
21175 +
21176 + case EP0_IN_STATUS_PHASE:
21177 + case EP0_OUT_STATUS_PHASE:
21178 + DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
21179 + ep0_complete_request(ep0);
21180 + pcd->ep0state = EP0_IDLE;
21181 + ep0->stopped = 1;
21182 + ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
21183 +
21184 + /* Prepare for more SETUP Packets */
21185 + if(core_if->dma_enable) {
21186 + ep0_out_start(core_if, pcd);
21187 + }
21188 + break;
21189 +
21190 + case EP0_STALL:
21191 + DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
21192 + break;
21193 + }
21194 +#ifdef DEBUG_EP0
21195 + print_ep0_state(pcd);
21196 +#endif
21197 +}
21198 +
21199 +
21200 +/**
21201 + * Restart transfer
21202 + */
21203 +static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
21204 +{
21205 + dwc_otg_core_if_t *core_if;
21206 + dwc_otg_dev_if_t *dev_if;
21207 + deptsiz_data_t dieptsiz = {.d32=0};
21208 + dwc_otg_pcd_ep_t *ep;
21209 +
21210 + ep = get_in_ep(pcd, epnum);
21211 +
21212 +#ifdef DWC_EN_ISOC
21213 + if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
21214 + return;
21215 + }
21216 +#endif /* DWC_EN_ISOC */
21217 +
21218 + core_if = GET_CORE_IF(pcd);
21219 + dev_if = core_if->dev_if;
21220 +
21221 + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
21222 +
21223 + DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x xfer_len=%0x"
21224 + " stopped=%d\n", ep->dwc_ep.xfer_buff,
21225 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
21226 + ep->stopped);
21227 + /*
21228 + * If xfersize is 0 and pktcnt in not 0, resend the last packet.
21229 + */
21230 + if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
21231 + ep->dwc_ep.start_xfer_buff != 0) {
21232 + if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
21233 + ep->dwc_ep.xfer_count = 0;
21234 + ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
21235 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
21236 + }
21237 + else {
21238 + ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
21239 + /* convert packet size to dwords. */
21240 + ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
21241 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
21242 + }
21243 + ep->stopped = 0;
21244 + DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x "
21245 + "xfer_len=%0x stopped=%d\n",
21246 + ep->dwc_ep.xfer_buff,
21247 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
21248 + ep->stopped
21249 + );
21250 + if (epnum == 0) {
21251 + dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
21252 + }
21253 + else {
21254 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
21255 + }
21256 + }
21257 +}
21258 +
21259 +
21260 +/**
21261 + * handle the IN EP disable interrupt.
21262 + */
21263 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd,
21264 + const uint32_t epnum)
21265 +{
21266 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21267 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21268 + deptsiz_data_t dieptsiz = {.d32=0};
21269 + dctl_data_t dctl = {.d32=0};
21270 + dwc_otg_pcd_ep_t *ep;
21271 + dwc_ep_t *dwc_ep;
21272 +
21273 + ep = get_in_ep(pcd, epnum);
21274 + dwc_ep = &ep->dwc_ep;
21275 +
21276 + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21277 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
21278 + return;
21279 + }
21280 +
21281 + DWC_DEBUGPL(DBG_PCD,"diepctl%d=%0x\n", epnum,
21282 + dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
21283 + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
21284 +
21285 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
21286 + dieptsiz.b.pktcnt,
21287 + dieptsiz.b.xfersize);
21288 +
21289 + if (ep->stopped) {
21290 + /* Flush the Tx FIFO */
21291 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
21292 + /* Clear the Global IN NP NAK */
21293 + dctl.d32 = 0;
21294 + dctl.b.cgnpinnak = 1;
21295 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
21296 + dctl.d32, 0);
21297 + /* Restart the transaction */
21298 + if (dieptsiz.b.pktcnt != 0 ||
21299 + dieptsiz.b.xfersize != 0) {
21300 + restart_transfer(pcd, epnum);
21301 + }
21302 + }
21303 + else {
21304 + /* Restart the transaction */
21305 + if (dieptsiz.b.pktcnt != 0 ||
21306 + dieptsiz.b.xfersize != 0) {
21307 + restart_transfer(pcd, epnum);
21308 + }
21309 + DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
21310 + }
21311 +}
21312 +
21313 +/**
21314 + * Handler for the IN EP timeout handshake interrupt.
21315 + */
21316 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
21317 + const uint32_t epnum)
21318 +{
21319 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21320 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21321 +
21322 +#ifdef DEBUG
21323 + deptsiz_data_t dieptsiz = {.d32=0};
21324 + uint32_t num = 0;
21325 +#endif
21326 + dctl_data_t dctl = {.d32=0};
21327 + dwc_otg_pcd_ep_t *ep;
21328 +
21329 + gintmsk_data_t intr_mask = {.d32 = 0};
21330 +
21331 + ep = get_in_ep(pcd, epnum);
21332 +
21333 + /* Disable the NP Tx Fifo Empty Interrrupt */
21334 + if (!core_if->dma_enable) {
21335 + intr_mask.b.nptxfempty = 1;
21336 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
21337 + }
21338 + /** @todo NGS Check EP type.
21339 + * Implement for Periodic EPs */
21340 + /*
21341 + * Non-periodic EP
21342 + */
21343 + /* Enable the Global IN NAK Effective Interrupt */
21344 + intr_mask.b.ginnakeff = 1;
21345 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
21346 + 0, intr_mask.d32);
21347 +
21348 + /* Set Global IN NAK */
21349 + dctl.b.sgnpinnak = 1;
21350 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
21351 + dctl.d32, dctl.d32);
21352 +
21353 + ep->stopped = 1;
21354 +
21355 +#ifdef DEBUG
21356 + dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
21357 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
21358 + dieptsiz.b.pktcnt,
21359 + dieptsiz.b.xfersize);
21360 +#endif
21361 +
21362 +#ifdef DISABLE_PERIODIC_EP
21363 + /*
21364 + * Set the NAK bit for this EP to
21365 + * start the disable process.
21366 + */
21367 + diepctl.d32 = 0;
21368 + diepctl.b.snak = 1;
21369 + dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, diepctl.d32);
21370 + ep->disabling = 1;
21371 + ep->stopped = 1;
21372 +#endif
21373 +}
21374 +
21375 +/**
21376 + * Handler for the IN EP NAK interrupt.
21377 + */
21378 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd,
21379 + const uint32_t epnum)
21380 +{
21381 + /** @todo implement ISR */
21382 + dwc_otg_core_if_t* core_if;
21383 + diepmsk_data_t intr_mask = { .d32 = 0};
21384 +
21385 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
21386 + core_if = GET_CORE_IF(pcd);
21387 + intr_mask.b.nak = 1;
21388 +
21389 + if(core_if->multiproc_int_enable) {
21390 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[epnum],
21391 + intr_mask.d32, 0);
21392 + } else {
21393 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
21394 + intr_mask.d32, 0);
21395 + }
21396 +
21397 + return 1;
21398 +}
21399 +
21400 +/**
21401 + * Handler for the OUT EP Babble interrupt.
21402 + */
21403 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd,
21404 + const uint32_t epnum)
21405 +{
21406 + /** @todo implement ISR */
21407 + dwc_otg_core_if_t* core_if;
21408 + doepmsk_data_t intr_mask = { .d32 = 0};
21409 +
21410 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP Babble");
21411 + core_if = GET_CORE_IF(pcd);
21412 + intr_mask.b.babble = 1;
21413 +
21414 + if(core_if->multiproc_int_enable) {
21415 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
21416 + intr_mask.d32, 0);
21417 + } else {
21418 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
21419 + intr_mask.d32, 0);
21420 + }
21421 +
21422 + return 1;
21423 +}
21424 +
21425 +/**
21426 + * Handler for the OUT EP NAK interrupt.
21427 + */
21428 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd,
21429 + const uint32_t epnum)
21430 +{
21431 + /** @todo implement ISR */
21432 + dwc_otg_core_if_t* core_if;
21433 + doepmsk_data_t intr_mask = { .d32 = 0};
21434 +
21435 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
21436 + core_if = GET_CORE_IF(pcd);
21437 + intr_mask.b.nak = 1;
21438 +
21439 + if(core_if->multiproc_int_enable) {
21440 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
21441 + intr_mask.d32, 0);
21442 + } else {
21443 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
21444 + intr_mask.d32, 0);
21445 + }
21446 +
21447 + return 1;
21448 +}
21449 +
21450 +/**
21451 + * Handler for the OUT EP NYET interrupt.
21452 + */
21453 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd,
21454 + const uint32_t epnum)
21455 +{
21456 + /** @todo implement ISR */
21457 + dwc_otg_core_if_t* core_if;
21458 + doepmsk_data_t intr_mask = { .d32 = 0};
21459 +
21460 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
21461 + core_if = GET_CORE_IF(pcd);
21462 + intr_mask.b.nyet = 1;
21463 +
21464 + if(core_if->multiproc_int_enable) {
21465 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
21466 + intr_mask.d32, 0);
21467 + } else {
21468 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
21469 + intr_mask.d32, 0);
21470 + }
21471 +
21472 + return 1;
21473 +}
21474 +
21475 +/**
21476 + * This interrupt indicates that an IN EP has a pending Interrupt.
21477 + * The sequence for handling the IN EP interrupt is shown below:
21478 + * -# Read the Device All Endpoint Interrupt register
21479 + * -# Repeat the following for each IN EP interrupt bit set (from
21480 + * LSB to MSB).
21481 + * -# Read the Device Endpoint Interrupt (DIEPINTn) register
21482 + * -# If "Transfer Complete" call the request complete function
21483 + * -# If "Endpoint Disabled" complete the EP disable procedure.
21484 + * -# If "AHB Error Interrupt" log error
21485 + * -# If "Time-out Handshake" log error
21486 + * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
21487 + * FIFO.
21488 + * -# If "IN Token EP Mismatch" (disable, this is handled by EP
21489 + * Mismatch Interrupt)
21490 + */
21491 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd)
21492 +{
21493 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
21494 +do { \
21495 + diepint_data_t diepint = {.d32=0}; \
21496 + diepint.b.__intr = 1; \
21497 + dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
21498 + diepint.d32); \
21499 +} while (0)
21500 +
21501 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21502 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21503 + diepint_data_t diepint = {.d32=0};
21504 + dctl_data_t dctl = {.d32=0};
21505 + depctl_data_t depctl = {.d32=0};
21506 + uint32_t ep_intr;
21507 + uint32_t epnum = 0;
21508 + dwc_otg_pcd_ep_t *ep;
21509 + dwc_ep_t *dwc_ep;
21510 + gintmsk_data_t intr_mask = {.d32 = 0};
21511 +
21512 +
21513 +
21514 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
21515 +
21516 + /* Read in the device interrupt bits */
21517 + ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
21518 +
21519 + /* Service the Device IN interrupts for each endpoint */
21520 + while(ep_intr) {
21521 + if (ep_intr&0x1) {
21522 + uint32_t empty_msk;
21523 + /* Get EP pointer */
21524 + ep = get_in_ep(pcd, epnum);
21525 + dwc_ep = &ep->dwc_ep;
21526 +
21527 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
21528 + empty_msk = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
21529 +
21530 + DWC_DEBUGPL(DBG_PCDV,
21531 + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
21532 + epnum,
21533 + empty_msk,
21534 + depctl.d32);
21535 +
21536 + DWC_DEBUGPL(DBG_PCD,
21537 + "EP%d-%s: type=%d, mps=%d\n",
21538 + dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
21539 + dwc_ep->type, dwc_ep->maxpacket);
21540 +
21541 + diepint.d32 = dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
21542 +
21543 + DWC_DEBUGPL(DBG_PCDV, "EP %d Interrupt Register - 0x%x\n", epnum, diepint.d32);
21544 + /* Transfer complete */
21545 + if (diepint.b.xfercompl) {
21546 + /* Disable the NP Tx FIFO Empty
21547 + * Interrrupt */
21548 + if(core_if->en_multiple_tx_fifo == 0) {
21549 + intr_mask.b.nptxfempty = 1;
21550 + dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
21551 + }
21552 + else {
21553 + /* Disable the Tx FIFO Empty Interrupt for this EP */
21554 + uint32_t fifoemptymsk = 0x1 << dwc_ep->num;
21555 + dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
21556 + fifoemptymsk, 0);
21557 + }
21558 + /* Clear the bit in DIEPINTn for this interrupt */
21559 + CLEAR_IN_EP_INTR(core_if,epnum,xfercompl);
21560 +
21561 + /* Complete the transfer */
21562 + if (epnum == 0) {
21563 + handle_ep0(pcd);
21564 + }
21565 +#ifdef DWC_EN_ISOC
21566 + else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21567 + if(!ep->stopped)
21568 + complete_iso_ep(ep);
21569 + }
21570 +#endif //DWC_EN_ISOC
21571 + else {
21572 +
21573 + complete_ep(ep);
21574 + }
21575 + }
21576 + /* Endpoint disable */
21577 + if (diepint.b.epdisabled) {
21578 + DWC_DEBUGPL(DBG_ANY,"EP%d IN disabled\n", epnum);
21579 + handle_in_ep_disable_intr(pcd, epnum);
21580 +
21581 + /* Clear the bit in DIEPINTn for this interrupt */
21582 + CLEAR_IN_EP_INTR(core_if,epnum,epdisabled);
21583 + }
21584 + /* AHB Error */
21585 + if (diepint.b.ahberr) {
21586 + DWC_DEBUGPL(DBG_ANY,"EP%d IN AHB Error\n", epnum);
21587 + /* Clear the bit in DIEPINTn for this interrupt */
21588 + CLEAR_IN_EP_INTR(core_if,epnum,ahberr);
21589 + }
21590 + /* TimeOUT Handshake (non-ISOC IN EPs) */
21591 + if (diepint.b.timeout) {
21592 + DWC_DEBUGPL(DBG_ANY,"EP%d IN Time-out\n", epnum);
21593 + handle_in_ep_timeout_intr(pcd, epnum);
21594 +
21595 + CLEAR_IN_EP_INTR(core_if,epnum,timeout);
21596 + }
21597 + /** IN Token received with TxF Empty */
21598 + if (diepint.b.intktxfemp) {
21599 + DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN TxFifo Empty\n",
21600 + epnum);
21601 + if (!ep->stopped && epnum != 0) {
21602 +
21603 + diepmsk_data_t diepmsk = { .d32 = 0};
21604 + diepmsk.b.intktxfemp = 1;
21605 +
21606 + if(core_if->multiproc_int_enable) {
21607 + dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[epnum],
21608 + diepmsk.d32, 0);
21609 + } else {
21610 + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32, 0);
21611 + }
21612 + start_next_request(ep);
21613 + }
21614 + else if(core_if->dma_desc_enable && epnum == 0 &&
21615 + pcd->ep0state == EP0_OUT_STATUS_PHASE) {
21616 + // EP0 IN set STALL
21617 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
21618 +
21619 + /* set the disable and stall bits */
21620 + if (depctl.b.epena) {
21621 + depctl.b.epdis = 1;
21622 + }
21623 + depctl.b.stall = 1;
21624 + dwc_write_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
21625 + }
21626 + CLEAR_IN_EP_INTR(core_if,epnum,intktxfemp);
21627 + }
21628 + /** IN Token Received with EP mismatch */
21629 + if (diepint.b.intknepmis) {
21630 + DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN EP Mismatch\n", epnum);
21631 + CLEAR_IN_EP_INTR(core_if,epnum,intknepmis);
21632 + }
21633 + /** IN Endpoint NAK Effective */
21634 + if (diepint.b.inepnakeff) {
21635 + DWC_DEBUGPL(DBG_ANY,"EP%d IN EP NAK Effective\n", epnum);
21636 + /* Periodic EP */
21637 + if (ep->disabling) {
21638 + depctl.d32 = 0;
21639 + depctl.b.snak = 1;
21640 + depctl.b.epdis = 1;
21641 + dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
21642 + }
21643 + CLEAR_IN_EP_INTR(core_if,epnum,inepnakeff);
21644 +
21645 + }
21646 +
21647 + /** IN EP Tx FIFO Empty Intr */
21648 + if (diepint.b.emptyintr) {
21649 + DWC_DEBUGPL(DBG_ANY,"EP%d Tx FIFO Empty Intr \n", epnum);
21650 + write_empty_tx_fifo(pcd, epnum);
21651 +
21652 + CLEAR_IN_EP_INTR(core_if,epnum,emptyintr);
21653 +
21654 + }
21655 +
21656 + /** IN EP BNA Intr */
21657 + if (diepint.b.bna) {
21658 + CLEAR_IN_EP_INTR(core_if,epnum,bna);
21659 + if(core_if->dma_desc_enable) {
21660 +#ifdef DWC_EN_ISOC
21661 + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21662 + /*
21663 + * This checking is performed to prevent first "false" BNA
21664 + * handling occuring right after reconnect
21665 + */
21666 + if(dwc_ep->next_frame != 0xffffffff)
21667 + dwc_otg_pcd_handle_iso_bna(ep);
21668 + }
21669 + else
21670 +#endif //DWC_EN_ISOC
21671 + {
21672 + dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
21673 +
21674 + /* If Global Continue on BNA is disabled - disable EP */
21675 + if(!dctl.b.gcontbna) {
21676 + depctl.d32 = 0;
21677 + depctl.b.snak = 1;
21678 + depctl.b.epdis = 1;
21679 + dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
21680 + } else {
21681 + start_next_request(ep);
21682 + }
21683 + }
21684 + }
21685 + }
21686 + /* NAK Interrutp */
21687 + if (diepint.b.nak) {
21688 + DWC_DEBUGPL(DBG_ANY,"EP%d IN NAK Interrupt\n", epnum);
21689 + handle_in_ep_nak_intr(pcd, epnum);
21690 +
21691 + CLEAR_IN_EP_INTR(core_if,epnum,nak);
21692 + }
21693 + }
21694 + epnum++;
21695 + ep_intr >>=1;
21696 + }
21697 +
21698 + return 1;
21699 +#undef CLEAR_IN_EP_INTR
21700 +}
21701 +
21702 +/**
21703 + * This interrupt indicates that an OUT EP has a pending Interrupt.
21704 + * The sequence for handling the OUT EP interrupt is shown below:
21705 + * -# Read the Device All Endpoint Interrupt register
21706 + * -# Repeat the following for each OUT EP interrupt bit set (from
21707 + * LSB to MSB).
21708 + * -# Read the Device Endpoint Interrupt (DOEPINTn) register
21709 + * -# If "Transfer Complete" call the request complete function
21710 + * -# If "Endpoint Disabled" complete the EP disable procedure.
21711 + * -# If "AHB Error Interrupt" log error
21712 + * -# If "Setup Phase Done" process Setup Packet (See Standard USB
21713 + * Command Processing)
21714 + */
21715 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd)
21716 +{
21717 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
21718 +do { \
21719 + doepint_data_t doepint = {.d32=0}; \
21720 + doepint.b.__intr = 1; \
21721 + dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
21722 + doepint.d32); \
21723 +} while (0)
21724 +
21725 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
21726 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
21727 + uint32_t ep_intr;
21728 + doepint_data_t doepint = {.d32=0};
21729 + dctl_data_t dctl = {.d32=0};
21730 + depctl_data_t doepctl = {.d32=0};
21731 + uint32_t epnum = 0;
21732 + dwc_otg_pcd_ep_t *ep;
21733 + dwc_ep_t *dwc_ep;
21734 +
21735 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
21736 +
21737 + /* Read in the device interrupt bits */
21738 + ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
21739 +
21740 + while(ep_intr) {
21741 + if (ep_intr&0x1) {
21742 + /* Get EP pointer */
21743 + ep = get_out_ep(pcd, epnum);
21744 + dwc_ep = &ep->dwc_ep;
21745 +
21746 +#ifdef VERBOSE
21747 + DWC_DEBUGPL(DBG_PCDV,
21748 + "EP%d-%s: type=%d, mps=%d\n",
21749 + dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
21750 + dwc_ep->type, dwc_ep->maxpacket);
21751 +#endif
21752 + doepint.d32 = dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
21753 +
21754 + /* Transfer complete */
21755 + if (doepint.b.xfercompl) {
21756 +
21757 + if (epnum == 0) {
21758 + /* Clear the bit in DOEPINTn for this interrupt */
21759 + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
21760 + if(core_if->dma_desc_enable == 0 || pcd->ep0state != EP0_IDLE)
21761 + handle_ep0(pcd);
21762 +#ifdef DWC_EN_ISOC
21763 + } else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21764 + if (doepint.b.pktdrpsts == 0) {
21765 + /* Clear the bit in DOEPINTn for this interrupt */
21766 + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
21767 + complete_iso_ep(ep);
21768 + } else {
21769 +
21770 + doepint_data_t doepint = {.d32=0};
21771 + doepint.b.xfercompl = 1;
21772 + doepint.b.pktdrpsts = 1;
21773 + dwc_write_reg32(&core_if->dev_if->out_ep_regs[epnum]->doepint,
21774 + doepint.d32);
21775 + if(handle_iso_out_pkt_dropped(core_if,dwc_ep)) {
21776 + complete_iso_ep(ep);
21777 + }
21778 + }
21779 +#endif //DWC_EN_ISOC
21780 + } else {
21781 + /* Clear the bit in DOEPINTn for this interrupt */
21782 + CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
21783 + complete_ep(ep);
21784 + }
21785 +
21786 + }
21787 +
21788 + /* Endpoint disable */
21789 + if (doepint.b.epdisabled) {
21790 +
21791 + /* Clear the bit in DOEPINTn for this interrupt */
21792 + CLEAR_OUT_EP_INTR(core_if,epnum,epdisabled);
21793 + }
21794 + /* AHB Error */
21795 + if (doepint.b.ahberr) {
21796 + DWC_DEBUGPL(DBG_PCD,"EP%d OUT AHB Error\n", epnum);
21797 + DWC_DEBUGPL(DBG_PCD,"EP DMA REG %d \n", core_if->dev_if->out_ep_regs[epnum]->doepdma);
21798 + CLEAR_OUT_EP_INTR(core_if,epnum,ahberr);
21799 + }
21800 + /* Setup Phase Done (contorl EPs) */
21801 + if (doepint.b.setup) {
21802 +#ifdef DEBUG_EP0
21803 + DWC_DEBUGPL(DBG_PCD,"EP%d SETUP Done\n",
21804 + epnum);
21805 +#endif
21806 + CLEAR_OUT_EP_INTR(core_if,epnum,setup);
21807 +
21808 + handle_ep0(pcd);
21809 + }
21810 +
21811 + /** OUT EP BNA Intr */
21812 + if (doepint.b.bna) {
21813 + CLEAR_OUT_EP_INTR(core_if,epnum,bna);
21814 + if(core_if->dma_desc_enable) {
21815 +#ifdef DWC_EN_ISOC
21816 + if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
21817 + /*
21818 + * This checking is performed to prevent first "false" BNA
21819 + * handling occuring right after reconnect
21820 + */
21821 + if(dwc_ep->next_frame != 0xffffffff)
21822 + dwc_otg_pcd_handle_iso_bna(ep);
21823 + }
21824 + else
21825 +#endif //DWC_EN_ISOC
21826 + {
21827 + dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
21828 +
21829 + /* If Global Continue on BNA is disabled - disable EP*/
21830 + if(!dctl.b.gcontbna) {
21831 + doepctl.d32 = 0;
21832 + doepctl.b.snak = 1;
21833 + doepctl.b.epdis = 1;
21834 + dwc_modify_reg32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32, doepctl.d32);
21835 + } else {
21836 + start_next_request(ep);
21837 + }
21838 + }
21839 + }
21840 + }
21841 + if (doepint.b.stsphsercvd) {
21842 + CLEAR_OUT_EP_INTR(core_if,epnum,stsphsercvd);
21843 + if(core_if->dma_desc_enable) {
21844 + do_setup_in_status_phase(pcd);
21845 + }
21846 + }
21847 + /* Babble Interrutp */
21848 + if (doepint.b.babble) {
21849 + DWC_DEBUGPL(DBG_ANY,"EP%d OUT Babble\n", epnum);
21850 + handle_out_ep_babble_intr(pcd, epnum);
21851 +
21852 + CLEAR_OUT_EP_INTR(core_if,epnum,babble);
21853 + }
21854 + /* NAK Interrutp */
21855 + if (doepint.b.nak) {
21856 + DWC_DEBUGPL(DBG_ANY,"EP%d OUT NAK\n", epnum);
21857 + handle_out_ep_nak_intr(pcd, epnum);
21858 +
21859 + CLEAR_OUT_EP_INTR(core_if,epnum,nak);
21860 + }
21861 + /* NYET Interrutp */
21862 + if (doepint.b.nyet) {
21863 + DWC_DEBUGPL(DBG_ANY,"EP%d OUT NYET\n", epnum);
21864 + handle_out_ep_nyet_intr(pcd, epnum);
21865 +
21866 + CLEAR_OUT_EP_INTR(core_if,epnum,nyet);
21867 + }
21868 + }
21869 +
21870 + epnum++;
21871 + ep_intr >>=1;
21872 + }
21873 +
21874 + return 1;
21875 +
21876 +#undef CLEAR_OUT_EP_INTR
21877 +}
21878 +
21879 +
21880 +/**
21881 + * Incomplete ISO IN Transfer Interrupt.
21882 + * This interrupt indicates one of the following conditions occurred
21883 + * while transmitting an ISOC transaction.
21884 + * - Corrupted IN Token for ISOC EP.
21885 + * - Packet not complete in FIFO.
21886 + * The follow actions will be taken:
21887 + * -# Determine the EP
21888 + * -# Set incomplete flag in dwc_ep structure
21889 + * -# Disable EP; when "Endpoint Disabled" interrupt is received
21890 + * Flush FIFO
21891 + */
21892 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd)
21893 +{
21894 + gintsts_data_t gintsts;
21895 +
21896 +
21897 +#ifdef DWC_EN_ISOC
21898 + dwc_otg_dev_if_t *dev_if;
21899 + deptsiz_data_t deptsiz = { .d32 = 0};
21900 + depctl_data_t depctl = { .d32 = 0};
21901 + dsts_data_t dsts = { .d32 = 0};
21902 + dwc_ep_t *dwc_ep;
21903 + int i;
21904 +
21905 + dev_if = GET_CORE_IF(pcd)->dev_if;
21906 +
21907 + for(i = 1; i <= dev_if->num_in_eps; ++i) {
21908 + dwc_ep = &pcd->in_ep[i].dwc_ep;
21909 + if(dwc_ep->active &&
21910 + dwc_ep->type == USB_ENDPOINT_XFER_ISOC)
21911 + {
21912 + deptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
21913 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
21914 +
21915 + if(depctl.b.epdis && deptsiz.d32) {
21916 + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
21917 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
21918 + dwc_ep->cur_pkt = 0;
21919 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
21920 +
21921 + if(dwc_ep->proc_buf_num) {
21922 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
21923 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
21924 + } else {
21925 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
21926 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
21927 + }
21928 +
21929 + }
21930 +
21931 + dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
21932 + dwc_ep->next_frame = dsts.b.soffn;
21933 +
21934 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
21935 + }
21936 + }
21937 + }
21938 +
21939 +#else
21940 + gintmsk_data_t intr_mask = { .d32 = 0};
21941 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
21942 + "IN ISOC Incomplete");
21943 +
21944 + intr_mask.b.incomplisoin = 1;
21945 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
21946 + intr_mask.d32, 0);
21947 +#endif //DWC_EN_ISOC
21948 +
21949 + /* Clear interrupt */
21950 + gintsts.d32 = 0;
21951 + gintsts.b.incomplisoin = 1;
21952 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
21953 + gintsts.d32);
21954 +
21955 + return 1;
21956 +}
21957 +
21958 +/**
21959 + * Incomplete ISO OUT Transfer Interrupt.
21960 + *
21961 + * This interrupt indicates that the core has dropped an ISO OUT
21962 + * packet. The following conditions can be the cause:
21963 + * - FIFO Full, the entire packet would not fit in the FIFO.
21964 + * - CRC Error
21965 + * - Corrupted Token
21966 + * The follow actions will be taken:
21967 + * -# Determine the EP
21968 + * -# Set incomplete flag in dwc_ep structure
21969 + * -# Read any data from the FIFO
21970 + * -# Disable EP. when "Endpoint Disabled" interrupt is received
21971 + * re-enable EP.
21972 + */
21973 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd)
21974 +{
21975 + /* @todo implement ISR */
21976 + gintsts_data_t gintsts;
21977 +
21978 +#ifdef DWC_EN_ISOC
21979 + dwc_otg_dev_if_t *dev_if;
21980 + deptsiz_data_t deptsiz = { .d32 = 0};
21981 + depctl_data_t depctl = { .d32 = 0};
21982 + dsts_data_t dsts = { .d32 = 0};
21983 + dwc_ep_t *dwc_ep;
21984 + int i;
21985 +
21986 + dev_if = GET_CORE_IF(pcd)->dev_if;
21987 +
21988 + for(i = 1; i <= dev_if->num_out_eps; ++i) {
21989 + dwc_ep = &pcd->in_ep[i].dwc_ep;
21990 + if(pcd->out_ep[i].dwc_ep.active &&
21991 + pcd->out_ep[i].dwc_ep.type == USB_ENDPOINT_XFER_ISOC)
21992 + {
21993 + deptsiz.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
21994 + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
21995 +
21996 + if(depctl.b.epdis && deptsiz.d32) {
21997 + set_current_pkt_info(GET_CORE_IF(pcd), &pcd->out_ep[i].dwc_ep);
21998 + if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
21999 + dwc_ep->cur_pkt = 0;
22000 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
22001 +
22002 + if(dwc_ep->proc_buf_num) {
22003 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
22004 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
22005 + } else {
22006 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
22007 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
22008 + }
22009 +
22010 + }
22011 +
22012 + dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
22013 + dwc_ep->next_frame = dsts.b.soffn;
22014 +
22015 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
22016 + }
22017 + }
22018 + }
22019 +#else
22020 + /** @todo implement ISR */
22021 + gintmsk_data_t intr_mask = { .d32 = 0};
22022 +
22023 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
22024 + "OUT ISOC Incomplete");
22025 +
22026 + intr_mask.b.incomplisoout = 1;
22027 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
22028 + intr_mask.d32, 0);
22029 +
22030 +#endif // DWC_EN_ISOC
22031 +
22032 + /* Clear interrupt */
22033 + gintsts.d32 = 0;
22034 + gintsts.b.incomplisoout = 1;
22035 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
22036 + gintsts.d32);
22037 +
22038 + return 1;
22039 +}
22040 +
22041 +/**
22042 + * This function handles the Global IN NAK Effective interrupt.
22043 + *
22044 + */
22045 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd)
22046 +{
22047 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
22048 + depctl_data_t diepctl = { .d32 = 0};
22049 + depctl_data_t diepctl_rd = { .d32 = 0};
22050 + gintmsk_data_t intr_mask = { .d32 = 0};
22051 + gintsts_data_t gintsts;
22052 + int i;
22053 +
22054 + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
22055 +
22056 + /* Disable all active IN EPs */
22057 + diepctl.b.epdis = 1;
22058 + diepctl.b.snak = 1;
22059 +
22060 + for (i=0; i <= dev_if->num_in_eps; i++)
22061 + {
22062 + diepctl_rd.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
22063 + if (diepctl_rd.b.epena) {
22064 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
22065 + diepctl.d32);
22066 + }
22067 + }
22068 + /* Disable the Global IN NAK Effective Interrupt */
22069 + intr_mask.b.ginnakeff = 1;
22070 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
22071 + intr_mask.d32, 0);
22072 +
22073 + /* Clear interrupt */
22074 + gintsts.d32 = 0;
22075 + gintsts.b.ginnakeff = 1;
22076 + dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
22077 + gintsts.d32);
22078 +
22079 + return 1;
22080 +}
22081 +
22082 +/**
22083 + * OUT NAK Effective.
22084 + *
22085 + */
22086 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd)
22087 +{
22088 + gintmsk_data_t intr_mask = { .d32 = 0};
22089 + gintsts_data_t gintsts;
22090 +
22091 + DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
22092 + "Global IN NAK Effective\n");
22093 + /* Disable the Global IN NAK Effective Interrupt */
22094 + intr_mask.b.goutnakeff = 1;
22095 + dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
22096 + intr_mask.d32, 0);
22097 +
22098 + /* Clear interrupt */
22099 + gintsts.d32 = 0;
22100 + gintsts.b.goutnakeff = 1;
22101 + dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
22102 + gintsts.d32);
22103 +
22104 + return 1;
22105 +}
22106 +
22107 +
22108 +/**
22109 + * PCD interrupt handler.
22110 + *
22111 + * The PCD handles the device interrupts. Many conditions can cause a
22112 + * device interrupt. When an interrupt occurs, the device interrupt
22113 + * service routine determines the cause of the interrupt and
22114 + * dispatches handling to the appropriate function. These interrupt
22115 + * handling functions are described below.
22116 + *
22117 + * All interrupt registers are processed from LSB to MSB.
22118 + *
22119 + */
22120 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd)
22121 +{
22122 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
22123 +#ifdef VERBOSE
22124 + dwc_otg_core_global_regs_t *global_regs =
22125 + core_if->core_global_regs;
22126 +#endif
22127 + gintsts_data_t gintr_status;
22128 + int32_t retval = 0;
22129 +
22130 +
22131 +#ifdef VERBOSE
22132 + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
22133 + __func__,
22134 + dwc_read_reg32(&global_regs->gintsts),
22135 + dwc_read_reg32(&global_regs->gintmsk));
22136 +#endif
22137 +
22138 + if (dwc_otg_is_device_mode(core_if)) {
22139 + SPIN_LOCK(&pcd->lock);
22140 +#ifdef VERBOSE
22141 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
22142 + __func__,
22143 + dwc_read_reg32(&global_regs->gintsts),
22144 + dwc_read_reg32(&global_regs->gintmsk));
22145 +#endif
22146 +
22147 + gintr_status.d32 = dwc_otg_read_core_intr(core_if);
22148 +
22149 +/*
22150 + if (!gintr_status.d32) {
22151 + SPIN_UNLOCK(&pcd->lock);
22152 + return 0;
22153 + }
22154 +*/
22155 + DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
22156 + __func__, gintr_status.d32);
22157 +
22158 + if (gintr_status.b.sofintr) {
22159 + retval |= dwc_otg_pcd_handle_sof_intr(pcd);
22160 + }
22161 + if (gintr_status.b.rxstsqlvl) {
22162 + retval |= dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
22163 + }
22164 + if (gintr_status.b.nptxfempty) {
22165 + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
22166 + }
22167 + if (gintr_status.b.ginnakeff) {
22168 + retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
22169 + }
22170 + if (gintr_status.b.goutnakeff) {
22171 + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
22172 + }
22173 + if (gintr_status.b.i2cintr) {
22174 + retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
22175 + }
22176 + if (gintr_status.b.erlysuspend) {
22177 + retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
22178 + }
22179 + if (gintr_status.b.usbreset) {
22180 + retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
22181 + }
22182 + if (gintr_status.b.enumdone) {
22183 + retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
22184 + }
22185 + if (gintr_status.b.isooutdrop) {
22186 + retval |= dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(pcd);
22187 + }
22188 + if (gintr_status.b.eopframe) {
22189 + retval |= dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
22190 + }
22191 + if (gintr_status.b.epmismatch) {
22192 + retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
22193 + }
22194 + if (gintr_status.b.inepint) {
22195 + if(!core_if->multiproc_int_enable) {
22196 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
22197 + }
22198 + }
22199 + if (gintr_status.b.outepintr) {
22200 + if(!core_if->multiproc_int_enable) {
22201 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
22202 + }
22203 + }
22204 + if (gintr_status.b.incomplisoin) {
22205 + retval |= dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
22206 + }
22207 + if (gintr_status.b.incomplisoout) {
22208 + retval |= dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
22209 + }
22210 +
22211 + /* In MPI mode De vice Endpoints intterrupts are asserted
22212 + * without setting outepintr and inepint bits set, so these
22213 + * Interrupt handlers are called without checking these bit-fields
22214 + */
22215 + if(core_if->multiproc_int_enable) {
22216 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
22217 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
22218 + }
22219 +#ifdef VERBOSE
22220 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
22221 + dwc_read_reg32(&global_regs->gintsts));
22222 +#endif
22223 + SPIN_UNLOCK(&pcd->lock);
22224 + }
22225 +
22226 + S3C2410X_CLEAR_EINTPEND();
22227 +
22228 + return retval;
22229 +}
22230 +
22231 +#endif /* DWC_HOST_ONLY */
22232 diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h
22233 new file mode 100644
22234 index 0000000..8265766
22235 --- /dev/null
22236 +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h
22237 @@ -0,0 +1,2075 @@
22238 +/* ==========================================================================
22239 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
22240 + * $Revision: 1.2 $
22241 + * $Date: 2008-11-21 05:39:15 $
22242 + * $Change: 1099526 $
22243 + *
22244 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
22245 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
22246 + * otherwise expressly agreed to in writing between Synopsys and you.
22247 + *
22248 + * The Software IS NOT an item of Licensed Software or Licensed Product under
22249 + * any End User Software License Agreement or Agreement for Licensed Product
22250 + * with Synopsys or any supplement thereto. You are permitted to use and
22251 + * redistribute this Software in source and binary forms, with or without
22252 + * modification, provided that redistributions of source code must retain this
22253 + * notice. You may not view, use, disclose, copy or distribute this file or
22254 + * any information contained herein except pursuant to this license grant from
22255 + * Synopsys. If you do not agree with this notice, including the disclaimer
22256 + * below, then you are not authorized to use the Software.
22257 + *
22258 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22259 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22260 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22261 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
22262 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22263 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22264 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22265 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22266 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22267 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
22268 + * DAMAGE.
22269 + * ========================================================================== */
22270 +
22271 +#ifndef __DWC_OTG_REGS_H__
22272 +#define __DWC_OTG_REGS_H__
22273 +
22274 +/**
22275 + * @file
22276 + *
22277 + * This file contains the data structures for accessing the DWC_otg core registers.
22278 + *
22279 + * The application interfaces with the HS OTG core by reading from and
22280 + * writing to the Control and Status Register (CSR) space through the
22281 + * AHB Slave interface. These registers are 32 bits wide, and the
22282 + * addresses are 32-bit-block aligned.
22283 + * CSRs are classified as follows:
22284 + * - Core Global Registers
22285 + * - Device Mode Registers
22286 + * - Device Global Registers
22287 + * - Device Endpoint Specific Registers
22288 + * - Host Mode Registers
22289 + * - Host Global Registers
22290 + * - Host Port CSRs
22291 + * - Host Channel Specific Registers
22292 + *
22293 + * Only the Core Global registers can be accessed in both Device and
22294 + * Host modes. When the HS OTG core is operating in one mode, either
22295 + * Device or Host, the application must not access registers from the
22296 + * other mode. When the core switches from one mode to another, the
22297 + * registers in the new mode of operation must be reprogrammed as they
22298 + * would be after a power-on reset.
22299 + */
22300 +
22301 +/** Maximum number of Periodic FIFOs */
22302 +#define MAX_PERIO_FIFOS 15
22303 +/** Maximum number of Transmit FIFOs */
22304 +#define MAX_TX_FIFOS 15
22305 +
22306 +/** Maximum number of Endpoints/HostChannels */
22307 +#define MAX_EPS_CHANNELS 16
22308 +
22309 +/****************************************************************************/
22310 +/** DWC_otg Core registers .
22311 + * The dwc_otg_core_global_regs structure defines the size
22312 + * and relative field offsets for the Core Global registers.
22313 + */
22314 +typedef struct dwc_otg_core_global_regs
22315 +{
22316 + /** OTG Control and Status Register. <i>Offset: 000h</i> */
22317 + volatile uint32_t gotgctl;
22318 + /** OTG Interrupt Register. <i>Offset: 004h</i> */
22319 + volatile uint32_t gotgint;
22320 + /**Core AHB Configuration Register. <i>Offset: 008h</i> */
22321 + volatile uint32_t gahbcfg;
22322 +
22323 +#define DWC_GLBINTRMASK 0x0001
22324 +#define DWC_DMAENABLE 0x0020
22325 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
22326 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
22327 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100
22328 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
22329 +
22330 + /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
22331 + volatile uint32_t gusbcfg;
22332 + /**Core Reset Register. <i>Offset: 010h</i> */
22333 + volatile uint32_t grstctl;
22334 + /**Core Interrupt Register. <i>Offset: 014h</i> */
22335 + volatile uint32_t gintsts;
22336 + /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
22337 + volatile uint32_t gintmsk;
22338 + /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
22339 + volatile uint32_t grxstsr;
22340 + /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
22341 + volatile uint32_t grxstsp;
22342 + /**Receive FIFO Size Register. <i>Offset: 024h</i> */
22343 + volatile uint32_t grxfsiz;
22344 + /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
22345 + volatile uint32_t gnptxfsiz;
22346 + /**Non Periodic Transmit FIFO/Queue Status Register (Read
22347 + * Only). <i>Offset: 02Ch</i> */
22348 + volatile uint32_t gnptxsts;
22349 + /**I2C Access Register. <i>Offset: 030h</i> */
22350 + volatile uint32_t gi2cctl;
22351 + /**PHY Vendor Control Register. <i>Offset: 034h</i> */
22352 + volatile uint32_t gpvndctl;
22353 + /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
22354 + volatile uint32_t ggpio;
22355 + /**User ID Register. <i>Offset: 03Ch</i> */
22356 + volatile uint32_t guid;
22357 + /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
22358 + volatile uint32_t gsnpsid;
22359 + /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
22360 + volatile uint32_t ghwcfg1;
22361 + /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
22362 + volatile uint32_t ghwcfg2;
22363 +#define DWC_SLAVE_ONLY_ARCH 0
22364 +#define DWC_EXT_DMA_ARCH 1
22365 +#define DWC_INT_DMA_ARCH 2
22366 +
22367 +#define DWC_MODE_HNP_SRP_CAPABLE 0
22368 +#define DWC_MODE_SRP_ONLY_CAPABLE 1
22369 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
22370 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3
22371 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
22372 +#define DWC_MODE_SRP_CAPABLE_HOST 5
22373 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
22374 +
22375 + /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
22376 + volatile uint32_t ghwcfg3;
22377 + /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
22378 + volatile uint32_t ghwcfg4;
22379 + /** Reserved <i>Offset: 054h-0FFh</i> */
22380 + volatile uint32_t reserved[43];
22381 + /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
22382 + volatile uint32_t hptxfsiz;
22383 + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
22384 + otherwise Device Transmit FIFO#n Register.
22385 + * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
22386 + volatile uint32_t dptxfsiz_dieptxf[15];
22387 +} dwc_otg_core_global_regs_t;
22388 +
22389 +/**
22390 + * This union represents the bit fields of the Core OTG Control
22391 + * and Status Register (GOTGCTL). Set the bits using the bit
22392 + * fields then write the <i>d32</i> value to the register.
22393 + */
22394 +typedef union gotgctl_data
22395 +{
22396 + /** raw register data */
22397 + uint32_t d32;
22398 + /** register bits */
22399 + struct
22400 + {
22401 + unsigned sesreqscs : 1;
22402 + unsigned sesreq : 1;
22403 + unsigned reserved2_7 : 6;
22404 + unsigned hstnegscs : 1;
22405 + unsigned hnpreq : 1;
22406 + unsigned hstsethnpen : 1;
22407 + unsigned devhnpen : 1;
22408 + unsigned reserved12_15 : 4;
22409 + unsigned conidsts : 1;
22410 + unsigned reserved17 : 1;
22411 + unsigned asesvld : 1;
22412 + unsigned bsesvld : 1;
22413 + unsigned currmod : 1;
22414 + unsigned reserved21_31 : 11;
22415 + } b;
22416 +} gotgctl_data_t;
22417 +
22418 +/**
22419 + * This union represents the bit fields of the Core OTG Interrupt Register
22420 + * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
22421 + * value to the register.
22422 + */
22423 +typedef union gotgint_data
22424 +{
22425 + /** raw register data */
22426 + uint32_t d32;
22427 + /** register bits */
22428 + struct
22429 + {
22430 + /** Current Mode */
22431 + unsigned reserved0_1 : 2;
22432 +
22433 + /** Session End Detected */
22434 + unsigned sesenddet : 1;
22435 +
22436 + unsigned reserved3_7 : 5;
22437 +
22438 + /** Session Request Success Status Change */
22439 + unsigned sesreqsucstschng : 1;
22440 + /** Host Negotiation Success Status Change */
22441 + unsigned hstnegsucstschng : 1;
22442 +
22443 + unsigned reserver10_16 : 7;
22444 +
22445 + /** Host Negotiation Detected */
22446 + unsigned hstnegdet : 1;
22447 + /** A-Device Timeout Change */
22448 + unsigned adevtoutchng : 1;
22449 + /** Debounce Done */
22450 + unsigned debdone : 1;
22451 +
22452 + unsigned reserved31_20 : 12;
22453 +
22454 + } b;
22455 +} gotgint_data_t;
22456 +
22457 +
22458 +/**
22459 + * This union represents the bit fields of the Core AHB Configuration
22460 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
22461 + * write the <i>d32</i> value to the register.
22462 + */
22463 +typedef union gahbcfg_data
22464 +{
22465 + /** raw register data */
22466 + uint32_t d32;
22467 + /** register bits */
22468 + struct
22469 + {
22470 + unsigned glblintrmsk : 1;
22471 +#define DWC_GAHBCFG_GLBINT_ENABLE 1
22472 +
22473 + unsigned hburstlen : 4;
22474 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
22475 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
22476 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
22477 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
22478 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
22479 +
22480 + unsigned dmaenable : 1;
22481 +#define DWC_GAHBCFG_DMAENABLE 1
22482 + unsigned reserved : 1;
22483 + unsigned nptxfemplvl_txfemplvl : 1;
22484 + unsigned ptxfemplvl : 1;
22485 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
22486 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
22487 + unsigned reserved9_31 : 23;
22488 + } b;
22489 +} gahbcfg_data_t;
22490 +
22491 +/**
22492 + * This union represents the bit fields of the Core USB Configuration
22493 + * Register (GUSBCFG). Set the bits using the bit fields then write
22494 + * the <i>d32</i> value to the register.
22495 + */
22496 +typedef union gusbcfg_data
22497 +{
22498 + /** raw register data */
22499 + uint32_t d32;
22500 + /** register bits */
22501 + struct
22502 + {
22503 + unsigned toutcal : 3;
22504 + unsigned phyif : 1;
22505 + unsigned ulpi_utmi_sel : 1;
22506 + unsigned fsintf : 1;
22507 + unsigned physel : 1;
22508 + unsigned ddrsel : 1;
22509 + unsigned srpcap : 1;
22510 + unsigned hnpcap : 1;
22511 + unsigned usbtrdtim : 4;
22512 + unsigned nptxfrwnden : 1;
22513 + unsigned phylpwrclksel : 1;
22514 + unsigned otgutmifssel : 1;
22515 + unsigned ulpi_fsls : 1;
22516 + unsigned ulpi_auto_res : 1;
22517 + unsigned ulpi_clk_sus_m : 1;
22518 + unsigned ulpi_ext_vbus_drv : 1;
22519 + unsigned ulpi_int_vbus_indicator : 1;
22520 + unsigned term_sel_dl_pulse : 1;
22521 + unsigned reserved23_27 : 5;
22522 + unsigned tx_end_delay : 1;
22523 + unsigned reserved29_31 : 3;
22524 + } b;
22525 +} gusbcfg_data_t;
22526 +
22527 +/**
22528 + * This union represents the bit fields of the Core Reset Register
22529 + * (GRSTCTL). Set/clear the bits using the bit fields then write the
22530 + * <i>d32</i> value to the register.
22531 + */
22532 +typedef union grstctl_data
22533 +{
22534 + /** raw register data */
22535 + uint32_t d32;
22536 + /** register bits */
22537 + struct
22538 + {
22539 + /** Core Soft Reset (CSftRst) (Device and Host)
22540 + *
22541 + * The application can flush the control logic in the
22542 + * entire core using this bit. This bit resets the
22543 + * pipelines in the AHB Clock domain as well as the
22544 + * PHY Clock domain.
22545 + *
22546 + * The state machines are reset to an IDLE state, the
22547 + * control bits in the CSRs are cleared, all the
22548 + * transmit FIFOs and the receive FIFO are flushed.
22549 + *
22550 + * The status mask bits that control the generation of
22551 + * the interrupt, are cleared, to clear the
22552 + * interrupt. The interrupt status bits are not
22553 + * cleared, so the application can get the status of
22554 + * any events that occurred in the core after it has
22555 + * set this bit.
22556 + *
22557 + * Any transactions on the AHB are terminated as soon
22558 + * as possible following the protocol. Any
22559 + * transactions on the USB are terminated immediately.
22560 + *
22561 + * The configuration settings in the CSRs are
22562 + * unchanged, so the software doesn't have to
22563 + * reprogram these registers (Device
22564 + * Configuration/Host Configuration/Core System
22565 + * Configuration/Core PHY Configuration).
22566 + *
22567 + * The application can write to this bit, any time it
22568 + * wants to reset the core. This is a self clearing
22569 + * bit and the core clears this bit after all the
22570 + * necessary logic is reset in the core, which may
22571 + * take several clocks, depending on the current state
22572 + * of the core.
22573 + */
22574 + unsigned csftrst : 1;
22575 + /** Hclk Soft Reset
22576 + *
22577 + * The application uses this bit to reset the control logic in
22578 + * the AHB clock domain. Only AHB clock domain pipelines are
22579 + * reset.
22580 + */
22581 + unsigned hsftrst : 1;
22582 + /** Host Frame Counter Reset (Host Only)<br>
22583 + *
22584 + * The application can reset the (micro)frame number
22585 + * counter inside the core, using this bit. When the
22586 + * (micro)frame counter is reset, the subsequent SOF
22587 + * sent out by the core, will have a (micro)frame
22588 + * number of 0.
22589 + */
22590 + unsigned hstfrm : 1;
22591 + /** In Token Sequence Learning Queue Flush
22592 + * (INTknQFlsh) (Device Only)
22593 + */
22594 + unsigned intknqflsh : 1;
22595 + /** RxFIFO Flush (RxFFlsh) (Device and Host)
22596 + *
22597 + * The application can flush the entire Receive FIFO
22598 + * using this bit. <p>The application must first
22599 + * ensure that the core is not in the middle of a
22600 + * transaction. <p>The application should write into
22601 + * this bit, only after making sure that neither the
22602 + * DMA engine is reading from the RxFIFO nor the MAC
22603 + * is writing the data in to the FIFO. <p>The
22604 + * application should wait until the bit is cleared
22605 + * before performing any other operations. This bit
22606 + * will takes 8 clocks (slowest of PHY or AHB clock)
22607 + * to clear.
22608 + */
22609 + unsigned rxfflsh : 1;
22610 + /** TxFIFO Flush (TxFFlsh) (Device and Host).
22611 + *
22612 + * This bit is used to selectively flush a single or
22613 + * all transmit FIFOs. The application must first
22614 + * ensure that the core is not in the middle of a
22615 + * transaction. <p>The application should write into
22616 + * this bit, only after making sure that neither the
22617 + * DMA engine is writing into the TxFIFO nor the MAC
22618 + * is reading the data out of the FIFO. <p>The
22619 + * application should wait until the core clears this
22620 + * bit, before performing any operations. This bit
22621 + * will takes 8 clocks (slowest of PHY or AHB clock)
22622 + * to clear.
22623 + */
22624 + unsigned txfflsh : 1;
22625 +
22626 + /** TxFIFO Number (TxFNum) (Device and Host).
22627 + *
22628 + * This is the FIFO number which needs to be flushed,
22629 + * using the TxFIFO Flush bit. This field should not
22630 + * be changed until the TxFIFO Flush bit is cleared by
22631 + * the core.
22632 + * - 0x0 : Non Periodic TxFIFO Flush
22633 + * - 0x1 : Periodic TxFIFO #1 Flush in device mode
22634 + * or Periodic TxFIFO in host mode
22635 + * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
22636 + * - ...
22637 + * - 0xF : Periodic TxFIFO #15 Flush in device mode
22638 + * - 0x10: Flush all the Transmit NonPeriodic and
22639 + * Transmit Periodic FIFOs in the core
22640 + */
22641 + unsigned txfnum : 5;
22642 + /** Reserved */
22643 + unsigned reserved11_29 : 19;
22644 + /** DMA Request Signal. Indicated DMA request is in
22645 + * probress. Used for debug purpose. */
22646 + unsigned dmareq : 1;
22647 + /** AHB Master Idle. Indicates the AHB Master State
22648 + * Machine is in IDLE condition. */
22649 + unsigned ahbidle : 1;
22650 + } b;
22651 +} grstctl_t;
22652 +
22653 +
22654 +/**
22655 + * This union represents the bit fields of the Core Interrupt Mask
22656 + * Register (GINTMSK). Set/clear the bits using the bit fields then
22657 + * write the <i>d32</i> value to the register.
22658 + */
22659 +typedef union gintmsk_data
22660 +{
22661 + /** raw register data */
22662 + uint32_t d32;
22663 + /** register bits */
22664 + struct
22665 + {
22666 + unsigned reserved0 : 1;
22667 + unsigned modemismatch : 1;
22668 + unsigned otgintr : 1;
22669 + unsigned sofintr : 1;
22670 + unsigned rxstsqlvl : 1;
22671 + unsigned nptxfempty : 1;
22672 + unsigned ginnakeff : 1;
22673 + unsigned goutnakeff : 1;
22674 + unsigned reserved8 : 1;
22675 + unsigned i2cintr : 1;
22676 + unsigned erlysuspend : 1;
22677 + unsigned usbsuspend : 1;
22678 + unsigned usbreset : 1;
22679 + unsigned enumdone : 1;
22680 + unsigned isooutdrop : 1;
22681 + unsigned eopframe : 1;
22682 + unsigned reserved16 : 1;
22683 + unsigned epmismatch : 1;
22684 + unsigned inepintr : 1;
22685 + unsigned outepintr : 1;
22686 + unsigned incomplisoin : 1;
22687 + unsigned incomplisoout : 1;
22688 + unsigned reserved22_23 : 2;
22689 + unsigned portintr : 1;
22690 + unsigned hcintr : 1;
22691 + unsigned ptxfempty : 1;
22692 + unsigned reserved27 : 1;
22693 + unsigned conidstschng : 1;
22694 + unsigned disconnect : 1;
22695 + unsigned sessreqintr : 1;
22696 + unsigned wkupintr : 1;
22697 + } b;
22698 +} gintmsk_data_t;
22699 +/**
22700 + * This union represents the bit fields of the Core Interrupt Register
22701 + * (GINTSTS). Set/clear the bits using the bit fields then write the
22702 + * <i>d32</i> value to the register.
22703 + */
22704 +typedef union gintsts_data
22705 +{
22706 + /** raw register data */
22707 + uint32_t d32;
22708 +#define DWC_SOF_INTR_MASK 0x0008
22709 + /** register bits */
22710 + struct
22711 + {
22712 +#define DWC_HOST_MODE 1
22713 + unsigned curmode : 1;
22714 + unsigned modemismatch : 1;
22715 + unsigned otgintr : 1;
22716 + unsigned sofintr : 1;
22717 + unsigned rxstsqlvl : 1;
22718 + unsigned nptxfempty : 1;
22719 + unsigned ginnakeff : 1;
22720 + unsigned goutnakeff : 1;
22721 + unsigned reserved8 : 1;
22722 + unsigned i2cintr : 1;
22723 + unsigned erlysuspend : 1;
22724 + unsigned usbsuspend : 1;
22725 + unsigned usbreset : 1;
22726 + unsigned enumdone : 1;
22727 + unsigned isooutdrop : 1;
22728 + unsigned eopframe : 1;
22729 + unsigned intokenrx : 1;
22730 + unsigned epmismatch : 1;
22731 + unsigned inepint: 1;
22732 + unsigned outepintr : 1;
22733 + unsigned incomplisoin : 1;
22734 + unsigned incomplisoout : 1;
22735 + unsigned reserved22_23 : 2;
22736 + unsigned portintr : 1;
22737 + unsigned hcintr : 1;
22738 + unsigned ptxfempty : 1;
22739 + unsigned reserved27 : 1;
22740 + unsigned conidstschng : 1;
22741 + unsigned disconnect : 1;
22742 + unsigned sessreqintr : 1;
22743 + unsigned wkupintr : 1;
22744 + } b;
22745 +} gintsts_data_t;
22746 +
22747 +
22748 +/**
22749 + * This union represents the bit fields in the Device Receive Status Read and
22750 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
22751 + * element then read out the bits using the <i>b</i>it elements.
22752 + */
22753 +typedef union device_grxsts_data
22754 +{
22755 + /** raw register data */
22756 + uint32_t d32;
22757 + /** register bits */
22758 + struct
22759 + {
22760 + unsigned epnum : 4;
22761 + unsigned bcnt : 11;
22762 + unsigned dpid : 2;
22763 +
22764 +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
22765 +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
22766 +
22767 +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
22768 +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
22769 +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
22770 + unsigned pktsts : 4;
22771 + unsigned fn : 4;
22772 + unsigned reserved : 7;
22773 + } b;
22774 +} device_grxsts_data_t;
22775 +
22776 +/**
22777 + * This union represents the bit fields in the Host Receive Status Read and
22778 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
22779 + * element then read out the bits using the <i>b</i>it elements.
22780 + */
22781 +typedef union host_grxsts_data
22782 +{
22783 + /** raw register data */
22784 + uint32_t d32;
22785 + /** register bits */
22786 + struct
22787 + {
22788 + unsigned chnum : 4;
22789 + unsigned bcnt : 11;
22790 + unsigned dpid : 2;
22791 +
22792 + unsigned pktsts : 4;
22793 +#define DWC_GRXSTS_PKTSTS_IN 0x2
22794 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
22795 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
22796 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
22797 +
22798 + unsigned reserved : 11;
22799 + } b;
22800 +} host_grxsts_data_t;
22801 +
22802 +/**
22803 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
22804 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
22805 + * read out the bits using the <i>b</i>it elements.
22806 + */
22807 +typedef union fifosize_data
22808 +{
22809 + /** raw register data */
22810 + uint32_t d32;
22811 + /** register bits */
22812 + struct
22813 + {
22814 + unsigned startaddr : 16;
22815 + unsigned depth : 16;
22816 + } b;
22817 +} fifosize_data_t;
22818 +
22819 +/**
22820 + * This union represents the bit fields in the Non-Periodic Transmit
22821 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
22822 + * <i>d32</i> element then read out the bits using the <i>b</i>it
22823 + * elements.
22824 + */
22825 +typedef union gnptxsts_data
22826 +{
22827 + /** raw register data */
22828 + uint32_t d32;
22829 + /** register bits */
22830 + struct
22831 + {
22832 + unsigned nptxfspcavail : 16;
22833 + unsigned nptxqspcavail : 8;
22834 + /** Top of the Non-Periodic Transmit Request Queue
22835 + * - bit 24 - Terminate (Last entry for the selected
22836 + * channel/EP)
22837 + * - bits 26:25 - Token Type
22838 + * - 2'b00 - IN/OUT
22839 + * - 2'b01 - Zero Length OUT
22840 + * - 2'b10 - PING/Complete Split
22841 + * - 2'b11 - Channel Halt
22842 + * - bits 30:27 - Channel/EP Number
22843 + */
22844 + unsigned nptxqtop_terminate : 1;
22845 + unsigned nptxqtop_token : 2;
22846 + unsigned nptxqtop_chnep : 4;
22847 + unsigned reserved : 1;
22848 + } b;
22849 +} gnptxsts_data_t;
22850 +
22851 +/**
22852 + * This union represents the bit fields in the Transmit
22853 + * FIFO Status Register (DTXFSTS). Read the register into the
22854 + * <i>d32</i> element then read out the bits using the <i>b</i>it
22855 + * elements.
22856 + */
22857 +typedef union dtxfsts_data
22858 +{
22859 + /** raw register data */
22860 + uint32_t d32;
22861 + /** register bits */
22862 + struct
22863 + {
22864 + unsigned txfspcavail : 16;
22865 + unsigned reserved : 16;
22866 + } b;
22867 +} dtxfsts_data_t;
22868 +
22869 +/**
22870 + * This union represents the bit fields in the I2C Control Register
22871 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
22872 + * bits using the <i>b</i>it elements.
22873 + */
22874 +typedef union gi2cctl_data
22875 +{
22876 + /** raw register data */
22877 + uint32_t d32;
22878 + /** register bits */
22879 + struct
22880 + {
22881 + unsigned rwdata : 8;
22882 + unsigned regaddr : 8;
22883 + unsigned addr : 7;
22884 + unsigned i2cen : 1;
22885 + unsigned ack : 1;
22886 + unsigned i2csuspctl : 1;
22887 + unsigned i2cdevaddr : 2;
22888 + unsigned reserved : 2;
22889 + unsigned rw : 1;
22890 + unsigned bsydne : 1;
22891 + } b;
22892 +} gi2cctl_data_t;
22893 +
22894 +/**
22895 + * This union represents the bit fields in the User HW Config1
22896 + * Register. Read the register into the <i>d32</i> element then read
22897 + * out the bits using the <i>b</i>it elements.
22898 + */
22899 +typedef union hwcfg1_data
22900 +{
22901 + /** raw register data */
22902 + uint32_t d32;
22903 + /** register bits */
22904 + struct
22905 + {
22906 + unsigned ep_dir0 : 2;
22907 + unsigned ep_dir1 : 2;
22908 + unsigned ep_dir2 : 2;
22909 + unsigned ep_dir3 : 2;
22910 + unsigned ep_dir4 : 2;
22911 + unsigned ep_dir5 : 2;
22912 + unsigned ep_dir6 : 2;
22913 + unsigned ep_dir7 : 2;
22914 + unsigned ep_dir8 : 2;
22915 + unsigned ep_dir9 : 2;
22916 + unsigned ep_dir10 : 2;
22917 + unsigned ep_dir11 : 2;
22918 + unsigned ep_dir12 : 2;
22919 + unsigned ep_dir13 : 2;
22920 + unsigned ep_dir14 : 2;
22921 + unsigned ep_dir15 : 2;
22922 + } b;
22923 +} hwcfg1_data_t;
22924 +
22925 +/**
22926 + * This union represents the bit fields in the User HW Config2
22927 + * Register. Read the register into the <i>d32</i> element then read
22928 + * out the bits using the <i>b</i>it elements.
22929 + */
22930 +typedef union hwcfg2_data
22931 +{
22932 + /** raw register data */
22933 + uint32_t d32;
22934 + /** register bits */
22935 + struct
22936 + {
22937 + /* GHWCFG2 */
22938 + unsigned op_mode : 3;
22939 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
22940 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
22941 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
22942 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
22943 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
22944 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
22945 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
22946 +
22947 + unsigned architecture : 2;
22948 + unsigned point2point : 1;
22949 + unsigned hs_phy_type : 2;
22950 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
22951 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
22952 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
22953 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
22954 +
22955 + unsigned fs_phy_type : 2;
22956 + unsigned num_dev_ep : 4;
22957 + unsigned num_host_chan : 4;
22958 + unsigned perio_ep_supported : 1;
22959 + unsigned dynamic_fifo : 1;
22960 + unsigned multi_proc_int : 1;
22961 + unsigned reserved21 : 1;
22962 + unsigned nonperio_tx_q_depth : 2;
22963 + unsigned host_perio_tx_q_depth : 2;
22964 + unsigned dev_token_q_depth : 5;
22965 + unsigned reserved31 : 1;
22966 + } b;
22967 +} hwcfg2_data_t;
22968 +
22969 +/**
22970 + * This union represents the bit fields in the User HW Config3
22971 + * Register. Read the register into the <i>d32</i> element then read
22972 + * out the bits using the <i>b</i>it elements.
22973 + */
22974 +typedef union hwcfg3_data
22975 +{
22976 + /** raw register data */
22977 + uint32_t d32;
22978 + /** register bits */
22979 + struct
22980 + {
22981 + /* GHWCFG3 */
22982 + unsigned xfer_size_cntr_width : 4;
22983 + unsigned packet_size_cntr_width : 3;
22984 + unsigned otg_func : 1;
22985 + unsigned i2c : 1;
22986 + unsigned vendor_ctrl_if : 1;
22987 + unsigned optional_features : 1;
22988 + unsigned synch_reset_type : 1;
22989 + unsigned ahb_phy_clock_synch : 1;
22990 + unsigned reserved15_13 : 3;
22991 + unsigned dfifo_depth : 16;
22992 + } b;
22993 +} hwcfg3_data_t;
22994 +
22995 +/**
22996 + * This union represents the bit fields in the User HW Config4
22997 + * Register. Read the register into the <i>d32</i> element then read
22998 + * out the bits using the <i>b</i>it elements.
22999 + */
23000 +typedef union hwcfg4_data
23001 +{
23002 + /** raw register data */
23003 + uint32_t d32;
23004 + /** register bits */
23005 + struct
23006 + {
23007 + unsigned num_dev_perio_in_ep : 4;
23008 + unsigned power_optimiz : 1;
23009 + unsigned min_ahb_freq : 9;
23010 + unsigned utmi_phy_data_width : 2;
23011 + unsigned num_dev_mode_ctrl_ep : 4;
23012 + unsigned iddig_filt_en : 1;
23013 + unsigned vbus_valid_filt_en : 1;
23014 + unsigned a_valid_filt_en : 1;
23015 + unsigned b_valid_filt_en : 1;
23016 + unsigned session_end_filt_en : 1;
23017 + unsigned ded_fifo_en : 1;
23018 + unsigned num_in_eps : 4;
23019 + unsigned desc_dma : 1;
23020 + unsigned desc_dma_dyn : 1;
23021 + } b;
23022 +} hwcfg4_data_t;
23023 +
23024 +////////////////////////////////////////////
23025 +// Device Registers
23026 +/**
23027 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
23028 + *
23029 + * The following structures define the size and relative field offsets
23030 + * for the Device Mode Registers.
23031 + *
23032 + * <i>These registers are visible only in Device mode and must not be
23033 + * accessed in Host mode, as the results are unknown.</i>
23034 + */
23035 +typedef struct dwc_otg_dev_global_regs
23036 +{
23037 + /** Device Configuration Register. <i>Offset 800h</i> */
23038 + volatile uint32_t dcfg;
23039 + /** Device Control Register. <i>Offset: 804h</i> */
23040 + volatile uint32_t dctl;
23041 + /** Device Status Register (Read Only). <i>Offset: 808h</i> */
23042 + volatile uint32_t dsts;
23043 + /** Reserved. <i>Offset: 80Ch</i> */
23044 + uint32_t unused;
23045 + /** Device IN Endpoint Common Interrupt Mask
23046 + * Register. <i>Offset: 810h</i> */
23047 + volatile uint32_t diepmsk;
23048 + /** Device OUT Endpoint Common Interrupt Mask
23049 + * Register. <i>Offset: 814h</i> */
23050 + volatile uint32_t doepmsk;
23051 + /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
23052 + volatile uint32_t daint;
23053 + /** Device All Endpoints Interrupt Mask Register. <i>Offset:
23054 + * 81Ch</i> */
23055 + volatile uint32_t daintmsk;
23056 + /** Device IN Token Queue Read Register-1 (Read Only).
23057 + * <i>Offset: 820h</i> */
23058 + volatile uint32_t dtknqr1;
23059 + /** Device IN Token Queue Read Register-2 (Read Only).
23060 + * <i>Offset: 824h</i> */
23061 + volatile uint32_t dtknqr2;
23062 + /** Device VBUS discharge Register. <i>Offset: 828h</i> */
23063 + volatile uint32_t dvbusdis;
23064 + /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
23065 + volatile uint32_t dvbuspulse;
23066 + /** Device IN Token Queue Read Register-3 (Read Only). /
23067 + * Device Thresholding control register (Read/Write)
23068 + * <i>Offset: 830h</i> */
23069 + volatile uint32_t dtknqr3_dthrctl;
23070 + /** Device IN Token Queue Read Register-4 (Read Only). /
23071 + * Device IN EPs empty Inr. Mask Register (Read/Write)
23072 + * <i>Offset: 834h</i> */
23073 + volatile uint32_t dtknqr4_fifoemptymsk;
23074 + /** Device Each Endpoint Interrupt Register (Read Only). /
23075 + * <i>Offset: 838h</i> */
23076 + volatile uint32_t deachint;
23077 + /** Device Each Endpoint Interrupt mask Register (Read/Write). /
23078 + * <i>Offset: 83Ch</i> */
23079 + volatile uint32_t deachintmsk;
23080 + /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
23081 + * <i>Offset: 840h</i> */
23082 + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
23083 + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
23084 + * <i>Offset: 880h</i> */
23085 + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
23086 +} dwc_otg_device_global_regs_t;
23087 +
23088 +/**
23089 + * This union represents the bit fields in the Device Configuration
23090 + * Register. Read the register into the <i>d32</i> member then
23091 + * set/clear the bits using the <i>b</i>it elements. Write the
23092 + * <i>d32</i> member to the dcfg register.
23093 + */
23094 +typedef union dcfg_data
23095 +{
23096 + /** raw register data */
23097 + uint32_t d32;
23098 + /** register bits */
23099 + struct
23100 + {
23101 + /** Device Speed */
23102 + unsigned devspd : 2;
23103 + /** Non Zero Length Status OUT Handshake */
23104 + unsigned nzstsouthshk : 1;
23105 +#define DWC_DCFG_SEND_STALL 1
23106 +
23107 + unsigned reserved3 : 1;
23108 + /** Device Addresses */
23109 + unsigned devaddr : 7;
23110 + /** Periodic Frame Interval */
23111 + unsigned perfrint : 2;
23112 +#define DWC_DCFG_FRAME_INTERVAL_80 0
23113 +#define DWC_DCFG_FRAME_INTERVAL_85 1
23114 +#define DWC_DCFG_FRAME_INTERVAL_90 2
23115 +#define DWC_DCFG_FRAME_INTERVAL_95 3
23116 +
23117 + unsigned reserved13_17 : 5;
23118 + /** In Endpoint Mis-match count */
23119 + unsigned epmscnt : 5;
23120 + /** Enable Descriptor DMA in Device mode */
23121 + unsigned descdma : 1;
23122 + } b;
23123 +} dcfg_data_t;
23124 +
23125 +/**
23126 + * This union represents the bit fields in the Device Control
23127 + * Register. Read the register into the <i>d32</i> member then
23128 + * set/clear the bits using the <i>b</i>it elements.
23129 + */
23130 +typedef union dctl_data
23131 +{
23132 + /** raw register data */
23133 + uint32_t d32;
23134 + /** register bits */
23135 + struct
23136 + {
23137 + /** Remote Wakeup */
23138 + unsigned rmtwkupsig : 1;
23139 + /** Soft Disconnect */
23140 + unsigned sftdiscon : 1;
23141 + /** Global Non-Periodic IN NAK Status */
23142 + unsigned gnpinnaksts : 1;
23143 + /** Global OUT NAK Status */
23144 + unsigned goutnaksts : 1;
23145 + /** Test Control */
23146 + unsigned tstctl : 3;
23147 + /** Set Global Non-Periodic IN NAK */
23148 + unsigned sgnpinnak : 1;
23149 + /** Clear Global Non-Periodic IN NAK */
23150 + unsigned cgnpinnak : 1;
23151 + /** Set Global OUT NAK */
23152 + unsigned sgoutnak : 1;
23153 + /** Clear Global OUT NAK */
23154 + unsigned cgoutnak : 1;
23155 +
23156 + /** Power-On Programming Done */
23157 + unsigned pwronprgdone : 1;
23158 + /** Global Continue on BNA */
23159 + unsigned gcontbna : 1;
23160 + /** Global Multi Count */
23161 + unsigned gmc : 2;
23162 + /** Ignore Frame Number for ISOC EPs */
23163 + unsigned ifrmnum : 1;
23164 + /** NAK on Babble */
23165 + unsigned nakonbble : 1;
23166 +
23167 + unsigned reserved16_31 : 16;
23168 + } b;
23169 +} dctl_data_t;
23170 +
23171 +/**
23172 + * This union represents the bit fields in the Device Status
23173 + * Register. Read the register into the <i>d32</i> member then
23174 + * set/clear the bits using the <i>b</i>it elements.
23175 + */
23176 +typedef union dsts_data
23177 +{
23178 + /** raw register data */
23179 + uint32_t d32;
23180 + /** register bits */
23181 + struct
23182 + {
23183 + /** Suspend Status */
23184 + unsigned suspsts : 1;
23185 + /** Enumerated Speed */
23186 + unsigned enumspd : 2;
23187 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
23188 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
23189 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
23190 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
23191 + /** Erratic Error */
23192 + unsigned errticerr : 1;
23193 + unsigned reserved4_7: 4;
23194 + /** Frame or Microframe Number of the received SOF */
23195 + unsigned soffn : 14;
23196 + unsigned reserved22_31 : 10;
23197 + } b;
23198 +} dsts_data_t;
23199 +
23200 +
23201 +/**
23202 + * This union represents the bit fields in the Device IN EP Interrupt
23203 + * Register and the Device IN EP Common Mask Register.
23204 + *
23205 + * - Read the register into the <i>d32</i> member then set/clear the
23206 + * bits using the <i>b</i>it elements.
23207 + */
23208 +typedef union diepint_data
23209 +{
23210 + /** raw register data */
23211 + uint32_t d32;
23212 + /** register bits */
23213 + struct
23214 + {
23215 + /** Transfer complete mask */
23216 + unsigned xfercompl : 1;
23217 + /** Endpoint disable mask */
23218 + unsigned epdisabled : 1;
23219 + /** AHB Error mask */
23220 + unsigned ahberr : 1;
23221 + /** TimeOUT Handshake mask (non-ISOC EPs) */
23222 + unsigned timeout : 1;
23223 + /** IN Token received with TxF Empty mask */
23224 + unsigned intktxfemp : 1;
23225 + /** IN Token Received with EP mismatch mask */
23226 + unsigned intknepmis : 1;
23227 + /** IN Endpoint HAK Effective mask */
23228 + unsigned inepnakeff : 1;
23229 + /** IN Endpoint HAK Effective mask */
23230 + unsigned emptyintr : 1;
23231 +
23232 + unsigned txfifoundrn : 1;
23233 +
23234 + /** BNA Interrupt mask */
23235 + unsigned bna : 1;
23236 +
23237 + unsigned reserved10_12 : 3;
23238 + /** BNA Interrupt mask */
23239 + unsigned nak : 1;
23240 +
23241 + unsigned reserved14_31 : 18;
23242 + } b;
23243 +} diepint_data_t;
23244 +
23245 +/**
23246 + * This union represents the bit fields in the Device IN EP
23247 + * Common/Dedicated Interrupt Mask Register.
23248 + */
23249 +typedef union diepint_data diepmsk_data_t;
23250 +
23251 +/**
23252 + * This union represents the bit fields in the Device OUT EP Interrupt
23253 + * Registerand Device OUT EP Common Interrupt Mask Register.
23254 + *
23255 + * - Read the register into the <i>d32</i> member then set/clear the
23256 + * bits using the <i>b</i>it elements.
23257 + */
23258 +typedef union doepint_data
23259 +{
23260 + /** raw register data */
23261 + uint32_t d32;
23262 + /** register bits */
23263 + struct
23264 + {
23265 + /** Transfer complete */
23266 + unsigned xfercompl : 1;
23267 + /** Endpoint disable */
23268 + unsigned epdisabled : 1;
23269 + /** AHB Error */
23270 + unsigned ahberr : 1;
23271 + /** Setup Phase Done (contorl EPs) */
23272 + unsigned setup : 1;
23273 + /** OUT Token Received when Endpoint Disabled */
23274 + unsigned outtknepdis : 1;
23275 +
23276 + unsigned stsphsercvd : 1;
23277 + /** Back-to-Back SETUP Packets Received */
23278 + unsigned back2backsetup : 1;
23279 +
23280 + unsigned reserved7 : 1;
23281 + /** OUT packet Error */
23282 + unsigned outpkterr : 1;
23283 + /** BNA Interrupt */
23284 + unsigned bna : 1;
23285 +
23286 + unsigned reserved10 : 1;
23287 + /** Packet Drop Status */
23288 + unsigned pktdrpsts : 1;
23289 + /** Babble Interrupt */
23290 + unsigned babble : 1;
23291 + /** NAK Interrupt */
23292 + unsigned nak : 1;
23293 + /** NYET Interrupt */
23294 + unsigned nyet : 1;
23295 +
23296 + unsigned reserved15_31 : 17;
23297 + } b;
23298 +} doepint_data_t;
23299 +
23300 +/**
23301 + * This union represents the bit fields in the Device OUT EP
23302 + * Common/Dedicated Interrupt Mask Register.
23303 + */
23304 +typedef union doepint_data doepmsk_data_t;
23305 +
23306 +/**
23307 + * This union represents the bit fields in the Device All EP Interrupt
23308 + * and Mask Registers.
23309 + * - Read the register into the <i>d32</i> member then set/clear the
23310 + * bits using the <i>b</i>it elements.
23311 + */
23312 +typedef union daint_data
23313 +{
23314 + /** raw register data */
23315 + uint32_t d32;
23316 + /** register bits */
23317 + struct
23318 + {
23319 + /** IN Endpoint bits */
23320 + unsigned in : 16;
23321 + /** OUT Endpoint bits */
23322 + unsigned out : 16;
23323 + } ep;
23324 + struct
23325 + {
23326 + /** IN Endpoint bits */
23327 + unsigned inep0 : 1;
23328 + unsigned inep1 : 1;
23329 + unsigned inep2 : 1;
23330 + unsigned inep3 : 1;
23331 + unsigned inep4 : 1;
23332 + unsigned inep5 : 1;
23333 + unsigned inep6 : 1;
23334 + unsigned inep7 : 1;
23335 + unsigned inep8 : 1;
23336 + unsigned inep9 : 1;
23337 + unsigned inep10 : 1;
23338 + unsigned inep11 : 1;
23339 + unsigned inep12 : 1;
23340 + unsigned inep13 : 1;
23341 + unsigned inep14 : 1;
23342 + unsigned inep15 : 1;
23343 + /** OUT Endpoint bits */
23344 + unsigned outep0 : 1;
23345 + unsigned outep1 : 1;
23346 + unsigned outep2 : 1;
23347 + unsigned outep3 : 1;
23348 + unsigned outep4 : 1;
23349 + unsigned outep5 : 1;
23350 + unsigned outep6 : 1;
23351 + unsigned outep7 : 1;
23352 + unsigned outep8 : 1;
23353 + unsigned outep9 : 1;
23354 + unsigned outep10 : 1;
23355 + unsigned outep11 : 1;
23356 + unsigned outep12 : 1;
23357 + unsigned outep13 : 1;
23358 + unsigned outep14 : 1;
23359 + unsigned outep15 : 1;
23360 + } b;
23361 +} daint_data_t;
23362 +
23363 +/**
23364 + * This union represents the bit fields in the Device IN Token Queue
23365 + * Read Registers.
23366 + * - Read the register into the <i>d32</i> member.
23367 + * - READ-ONLY Register
23368 + */
23369 +typedef union dtknq1_data
23370 +{
23371 + /** raw register data */
23372 + uint32_t d32;
23373 + /** register bits */
23374 + struct
23375 + {
23376 + /** In Token Queue Write Pointer */
23377 + unsigned intknwptr : 5;
23378 + /** Reserved */
23379 + unsigned reserved05_06 : 2;
23380 + /** write pointer has wrapped. */
23381 + unsigned wrap_bit : 1;
23382 + /** EP Numbers of IN Tokens 0 ... 4 */
23383 + unsigned epnums0_5 : 24;
23384 + }b;
23385 +} dtknq1_data_t;
23386 +
23387 +/**
23388 + * This union represents Threshold control Register
23389 + * - Read and write the register into the <i>d32</i> member.
23390 + * - READ-WRITABLE Register
23391 + */
23392 +typedef union dthrctl_data
23393 +{
23394 + /** raw register data */
23395 + uint32_t d32;
23396 + /** register bits */
23397 + struct
23398 + {
23399 + /** non ISO Tx Thr. Enable */
23400 + unsigned non_iso_thr_en : 1;
23401 + /** ISO Tx Thr. Enable */
23402 + unsigned iso_thr_en : 1;
23403 + /** Tx Thr. Length */
23404 + unsigned tx_thr_len : 9;
23405 + /** Reserved */
23406 + unsigned reserved11_15 : 5;
23407 + /** Rx Thr. Enable */
23408 + unsigned rx_thr_en : 1;
23409 + /** Rx Thr. Length */
23410 + unsigned rx_thr_len : 9;
23411 + /** Reserved */
23412 + unsigned reserved26_31 : 6;
23413 + }b;
23414 +} dthrctl_data_t;
23415 +
23416 +
23417 +/**
23418 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
23419 + * 900h-AFCh</i>
23420 + *
23421 + * There will be one set of endpoint registers per logical endpoint
23422 + * implemented.
23423 + *
23424 + * <i>These registers are visible only in Device mode and must not be
23425 + * accessed in Host mode, as the results are unknown.</i>
23426 + */
23427 +typedef struct dwc_otg_dev_in_ep_regs
23428 +{
23429 + /** Device IN Endpoint Control Register. <i>Offset:900h +
23430 + * (ep_num * 20h) + 00h</i> */
23431 + volatile uint32_t diepctl;
23432 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
23433 + uint32_t reserved04;
23434 + /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
23435 + * (ep_num * 20h) + 08h</i> */
23436 + volatile uint32_t diepint;
23437 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
23438 + uint32_t reserved0C;
23439 + /** Device IN Endpoint Transfer Size
23440 + * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
23441 + volatile uint32_t dieptsiz;
23442 + /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
23443 + * (ep_num * 20h) + 14h</i> */
23444 + volatile uint32_t diepdma;
23445 + /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
23446 + * (ep_num * 20h) + 18h</i> */
23447 + volatile uint32_t dtxfsts;
23448 + /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
23449 + * (ep_num * 20h) + 1Ch</i> */
23450 + volatile uint32_t diepdmab;
23451 +} dwc_otg_dev_in_ep_regs_t;
23452 +
23453 +/**
23454 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
23455 + * B00h-CFCh</i>
23456 + *
23457 + * There will be one set of endpoint registers per logical endpoint
23458 + * implemented.
23459 + *
23460 + * <i>These registers are visible only in Device mode and must not be
23461 + * accessed in Host mode, as the results are unknown.</i>
23462 + */
23463 +typedef struct dwc_otg_dev_out_ep_regs
23464 +{
23465 + /** Device OUT Endpoint Control Register. <i>Offset:B00h +
23466 + * (ep_num * 20h) + 00h</i> */
23467 + volatile uint32_t doepctl;
23468 + /** Device OUT Endpoint Frame number Register. <i>Offset:
23469 + * B00h + (ep_num * 20h) + 04h</i> */
23470 + volatile uint32_t doepfn;
23471 + /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
23472 + * (ep_num * 20h) + 08h</i> */
23473 + volatile uint32_t doepint;
23474 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
23475 + uint32_t reserved0C;
23476 + /** Device OUT Endpoint Transfer Size Register. <i>Offset:
23477 + * B00h + (ep_num * 20h) + 10h</i> */
23478 + volatile uint32_t doeptsiz;
23479 + /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
23480 + * + (ep_num * 20h) + 14h</i> */
23481 + volatile uint32_t doepdma;
23482 + /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 1Ch</i> */
23483 + uint32_t unused;
23484 + /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
23485 + * + (ep_num * 20h) + 1Ch</i> */
23486 + uint32_t doepdmab;
23487 +} dwc_otg_dev_out_ep_regs_t;
23488 +
23489 +/**
23490 + * This union represents the bit fields in the Device EP Control
23491 + * Register. Read the register into the <i>d32</i> member then
23492 + * set/clear the bits using the <i>b</i>it elements.
23493 + */
23494 +typedef union depctl_data
23495 +{
23496 + /** raw register data */
23497 + uint32_t d32;
23498 + /** register bits */
23499 + struct
23500 + {
23501 + /** Maximum Packet Size
23502 + * IN/OUT EPn
23503 + * IN/OUT EP0 - 2 bits
23504 + * 2'b00: 64 Bytes
23505 + * 2'b01: 32
23506 + * 2'b10: 16
23507 + * 2'b11: 8 */
23508 + unsigned mps : 11;
23509 +#define DWC_DEP0CTL_MPS_64 0
23510 +#define DWC_DEP0CTL_MPS_32 1
23511 +#define DWC_DEP0CTL_MPS_16 2
23512 +#define DWC_DEP0CTL_MPS_8 3
23513 +
23514 + /** Next Endpoint
23515 + * IN EPn/IN EP0
23516 + * OUT EPn/OUT EP0 - reserved */
23517 + unsigned nextep : 4;
23518 +
23519 + /** USB Active Endpoint */
23520 + unsigned usbactep : 1;
23521 +
23522 + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
23523 + * This field contains the PID of the packet going to
23524 + * be received or transmitted on this endpoint. The
23525 + * application should program the PID of the first
23526 + * packet going to be received or transmitted on this
23527 + * endpoint , after the endpoint is
23528 + * activated. Application use the SetD1PID and
23529 + * SetD0PID fields of this register to program either
23530 + * D0 or D1 PID.
23531 + *
23532 + * The encoding for this field is
23533 + * - 0: D0
23534 + * - 1: D1
23535 + */
23536 + unsigned dpid : 1;
23537 +
23538 + /** NAK Status */
23539 + unsigned naksts : 1;
23540 +
23541 + /** Endpoint Type
23542 + * 2'b00: Control
23543 + * 2'b01: Isochronous
23544 + * 2'b10: Bulk
23545 + * 2'b11: Interrupt */
23546 + unsigned eptype : 2;
23547 +
23548 + /** Snoop Mode
23549 + * OUT EPn/OUT EP0
23550 + * IN EPn/IN EP0 - reserved */
23551 + unsigned snp : 1;
23552 +
23553 + /** Stall Handshake */
23554 + unsigned stall : 1;
23555 +
23556 + /** Tx Fifo Number
23557 + * IN EPn/IN EP0
23558 + * OUT EPn/OUT EP0 - reserved */
23559 + unsigned txfnum : 4;
23560 +
23561 + /** Clear NAK */
23562 + unsigned cnak : 1;
23563 + /** Set NAK */
23564 + unsigned snak : 1;
23565 + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
23566 + * Writing to this field sets the Endpoint DPID (DPID)
23567 + * field in this register to DATA0. Set Even
23568 + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
23569 + * Writing to this field sets the Even/Odd
23570 + * (micro)frame (EO_FrNum) field to even (micro)
23571 + * frame.
23572 + */
23573 + unsigned setd0pid : 1;
23574 + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
23575 + * Writing to this field sets the Endpoint DPID (DPID)
23576 + * field in this register to DATA1 Set Odd
23577 + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
23578 + * Writing to this field sets the Even/Odd
23579 + * (micro)frame (EO_FrNum) field to odd (micro) frame.
23580 + */
23581 + unsigned setd1pid : 1;
23582 +
23583 + /** Endpoint Disable */
23584 + unsigned epdis : 1;
23585 + /** Endpoint Enable */
23586 + unsigned epena : 1;
23587 + } b;
23588 +} depctl_data_t;
23589 +
23590 +/**
23591 + * This union represents the bit fields in the Device EP Transfer
23592 + * Size Register. Read the register into the <i>d32</i> member then
23593 + * set/clear the bits using the <i>b</i>it elements.
23594 + */
23595 +typedef union deptsiz_data
23596 +{
23597 + /** raw register data */
23598 + uint32_t d32;
23599 + /** register bits */
23600 + struct {
23601 + /** Transfer size */
23602 + unsigned xfersize : 19;
23603 + /** Packet Count */
23604 + unsigned pktcnt : 10;
23605 + /** Multi Count - Periodic IN endpoints */
23606 + unsigned mc : 2;
23607 + unsigned reserved : 1;
23608 + } b;
23609 +} deptsiz_data_t;
23610 +
23611 +/**
23612 + * This union represents the bit fields in the Device EP 0 Transfer
23613 + * Size Register. Read the register into the <i>d32</i> member then
23614 + * set/clear the bits using the <i>b</i>it elements.
23615 + */
23616 +typedef union deptsiz0_data
23617 +{
23618 + /** raw register data */
23619 + uint32_t d32;
23620 + /** register bits */
23621 + struct {
23622 + /** Transfer size */
23623 + unsigned xfersize : 7;
23624 + /** Reserved */
23625 + unsigned reserved7_18 : 12;
23626 + /** Packet Count */
23627 + unsigned pktcnt : 1;
23628 + /** Reserved */
23629 + unsigned reserved20_28 : 9;
23630 + /**Setup Packet Count (DOEPTSIZ0 Only) */
23631 + unsigned supcnt : 2;
23632 + unsigned reserved31;
23633 + } b;
23634 +} deptsiz0_data_t;
23635 +
23636 +
23637 +/////////////////////////////////////////////////
23638 +// DMA Descriptor Specific Structures
23639 +//
23640 +
23641 +/** Buffer status definitions */
23642 +
23643 +#define BS_HOST_READY 0x0
23644 +#define BS_DMA_BUSY 0x1
23645 +#define BS_DMA_DONE 0x2
23646 +#define BS_HOST_BUSY 0x3
23647 +
23648 +/** Receive/Transmit status definitions */
23649 +
23650 +#define RTS_SUCCESS 0x0
23651 +#define RTS_BUFFLUSH 0x1
23652 +#define RTS_RESERVED 0x2
23653 +#define RTS_BUFERR 0x3
23654 +
23655 +
23656 +/**
23657 + * This union represents the bit fields in the DMA Descriptor
23658 + * status quadlet. Read the quadlet into the <i>d32</i> member then
23659 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
23660 + * <i>b_iso_in</i> elements.
23661 + */
23662 +typedef union desc_sts_data
23663 +{
23664 + /** raw register data */
23665 + uint32_t d32;
23666 + /** quadlet bits */
23667 + struct {
23668 + /** Received number of bytes */
23669 + unsigned bytes : 16;
23670 +
23671 + unsigned reserved16_22 : 7;
23672 + /** Multiple Transfer - only for OUT EPs */
23673 + unsigned mtrf : 1;
23674 + /** Setup Packet received - only for OUT EPs */
23675 + unsigned sr : 1;
23676 + /** Interrupt On Complete */
23677 + unsigned ioc : 1;
23678 + /** Short Packet */
23679 + unsigned sp : 1;
23680 + /** Last */
23681 + unsigned l : 1;
23682 + /** Receive Status */
23683 + unsigned sts : 2;
23684 + /** Buffer Status */
23685 + unsigned bs : 2;
23686 + } b;
23687 +
23688 +#ifdef DWC_EN_ISOC
23689 + /** iso out quadlet bits */
23690 + struct {
23691 + /** Received number of bytes */
23692 + unsigned rxbytes : 11;
23693 +
23694 + unsigned reserved11 : 1;
23695 + /** Frame Number */
23696 + unsigned framenum : 11;
23697 + /** Received ISO Data PID */
23698 + unsigned pid : 2;
23699 + /** Interrupt On Complete */
23700 + unsigned ioc : 1;
23701 + /** Short Packet */
23702 + unsigned sp : 1;
23703 + /** Last */
23704 + unsigned l : 1;
23705 + /** Receive Status */
23706 + unsigned rxsts : 2;
23707 + /** Buffer Status */
23708 + unsigned bs : 2;
23709 + } b_iso_out;
23710 +
23711 + /** iso in quadlet bits */
23712 + struct {
23713 + /** Transmited number of bytes */
23714 + unsigned txbytes : 12;
23715 + /** Frame Number */
23716 + unsigned framenum : 11;
23717 + /** Transmited ISO Data PID */
23718 + unsigned pid : 2;
23719 + /** Interrupt On Complete */
23720 + unsigned ioc : 1;
23721 + /** Short Packet */
23722 + unsigned sp : 1;
23723 + /** Last */
23724 + unsigned l : 1;
23725 + /** Transmit Status */
23726 + unsigned txsts : 2;
23727 + /** Buffer Status */
23728 + unsigned bs : 2;
23729 + } b_iso_in;
23730 +#endif //DWC_EN_ISOC
23731 +} desc_sts_data_t;
23732 +
23733 +/**
23734 + * DMA Descriptor structure
23735 + *
23736 + * DMA Descriptor structure contains two quadlets:
23737 + * Status quadlet and Data buffer pointer.
23738 + */
23739 +typedef struct dwc_otg_dma_desc
23740 +{
23741 + /** DMA Descriptor status quadlet */
23742 + desc_sts_data_t status;
23743 + /** DMA Descriptor data buffer pointer */
23744 + dma_addr_t buf;
23745 +} dwc_otg_dma_desc_t;
23746 +
23747 +/**
23748 + * The dwc_otg_dev_if structure contains information needed to manage
23749 + * the DWC_otg controller acting in device mode. It represents the
23750 + * programming view of the device-specific aspects of the controller.
23751 + */
23752 +typedef struct dwc_otg_dev_if
23753 +{
23754 + /** Pointer to device Global registers.
23755 + * Device Global Registers starting at offset 800h
23756 + */
23757 + dwc_otg_device_global_regs_t *dev_global_regs;
23758 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
23759 +
23760 + /**
23761 + * Device Logical IN Endpoint-Specific Registers 900h-AFCh
23762 + */
23763 + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
23764 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
23765 +#define DWC_EP_REG_OFFSET 0x20
23766 +
23767 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
23768 + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
23769 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
23770 +
23771 + /* Device configuration information*/
23772 + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
23773 + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
23774 + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
23775 +
23776 + /** Size of periodic FIFOs (Bytes) */
23777 + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
23778 +
23779 + /** Size of Tx FIFOs (Bytes) */
23780 + uint16_t tx_fifo_size[MAX_TX_FIFOS];
23781 +
23782 + /** Thresholding enable flags and length varaiables **/
23783 + uint16_t rx_thr_en;
23784 + uint16_t iso_tx_thr_en;
23785 + uint16_t non_iso_tx_thr_en;
23786 +
23787 + uint16_t rx_thr_length;
23788 + uint16_t tx_thr_length;
23789 +
23790 + /**
23791 + * Pointers to the DMA Descriptors for EP0 Control
23792 + * transfers (virtual and physical)
23793 + */
23794 +
23795 + /** 2 descriptors for SETUP packets */
23796 + uint32_t dma_setup_desc_addr[2];
23797 + dwc_otg_dma_desc_t* setup_desc_addr[2];
23798 +
23799 + /** Pointer to Descriptor with latest SETUP packet */
23800 + dwc_otg_dma_desc_t* psetup;
23801 +
23802 + /** Index of current SETUP handler descriptor */
23803 + uint32_t setup_desc_index;
23804 +
23805 + /** Descriptor for Data In or Status In phases */
23806 + uint32_t dma_in_desc_addr;
23807 + dwc_otg_dma_desc_t* in_desc_addr;;
23808 +
23809 + /** Descriptor for Data Out or Status Out phases */
23810 + uint32_t dma_out_desc_addr;
23811 + dwc_otg_dma_desc_t* out_desc_addr;
23812 +
23813 +} dwc_otg_dev_if_t;
23814 +
23815 +
23816 +
23817 +
23818 +/////////////////////////////////////////////////
23819 +// Host Mode Register Structures
23820 +//
23821 +/**
23822 + * The Host Global Registers structure defines the size and relative
23823 + * field offsets for the Host Mode Global Registers. Host Global
23824 + * Registers offsets 400h-7FFh.
23825 +*/
23826 +typedef struct dwc_otg_host_global_regs
23827 +{
23828 + /** Host Configuration Register. <i>Offset: 400h</i> */
23829 + volatile uint32_t hcfg;
23830 + /** Host Frame Interval Register. <i>Offset: 404h</i> */
23831 + volatile uint32_t hfir;
23832 + /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
23833 + volatile uint32_t hfnum;
23834 + /** Reserved. <i>Offset: 40Ch</i> */
23835 + uint32_t reserved40C;
23836 + /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
23837 + volatile uint32_t hptxsts;
23838 + /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
23839 + volatile uint32_t haint;
23840 + /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
23841 + volatile uint32_t haintmsk;
23842 +} dwc_otg_host_global_regs_t;
23843 +
23844 +/**
23845 + * This union represents the bit fields in the Host Configuration Register.
23846 + * Read the register into the <i>d32</i> member then set/clear the bits using
23847 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
23848 + */
23849 +typedef union hcfg_data
23850 +{
23851 + /** raw register data */
23852 + uint32_t d32;
23853 +
23854 + /** register bits */
23855 + struct
23856 + {
23857 + /** FS/LS Phy Clock Select */
23858 + unsigned fslspclksel : 2;
23859 +#define DWC_HCFG_30_60_MHZ 0
23860 +#define DWC_HCFG_48_MHZ 1
23861 +#define DWC_HCFG_6_MHZ 2
23862 +
23863 + /** FS/LS Only Support */
23864 + unsigned fslssupp : 1;
23865 + } b;
23866 +} hcfg_data_t;
23867 +
23868 +/**
23869 + * This union represents the bit fields in the Host Frame Remaing/Number
23870 + * Register.
23871 + */
23872 +typedef union hfir_data
23873 +{
23874 + /** raw register data */
23875 + uint32_t d32;
23876 +
23877 + /** register bits */
23878 + struct
23879 + {
23880 + unsigned frint : 16;
23881 + unsigned reserved : 16;
23882 + } b;
23883 +} hfir_data_t;
23884 +
23885 +/**
23886 + * This union represents the bit fields in the Host Frame Remaing/Number
23887 + * Register.
23888 + */
23889 +typedef union hfnum_data
23890 +{
23891 + /** raw register data */
23892 + uint32_t d32;
23893 +
23894 + /** register bits */
23895 + struct
23896 + {
23897 + unsigned frnum : 16;
23898 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
23899 + unsigned frrem : 16;
23900 + } b;
23901 +} hfnum_data_t;
23902 +
23903 +typedef union hptxsts_data
23904 +{
23905 + /** raw register data */
23906 + uint32_t d32;
23907 +
23908 + /** register bits */
23909 + struct
23910 + {
23911 + unsigned ptxfspcavail : 16;
23912 + unsigned ptxqspcavail : 8;
23913 + /** Top of the Periodic Transmit Request Queue
23914 + * - bit 24 - Terminate (last entry for the selected channel)
23915 + * - bits 26:25 - Token Type
23916 + * - 2'b00 - Zero length
23917 + * - 2'b01 - Ping
23918 + * - 2'b10 - Disable
23919 + * - bits 30:27 - Channel Number
23920 + * - bit 31 - Odd/even microframe
23921 + */
23922 + unsigned ptxqtop_terminate : 1;
23923 + unsigned ptxqtop_token : 2;
23924 + unsigned ptxqtop_chnum : 4;
23925 + unsigned ptxqtop_odd : 1;
23926 + } b;
23927 +} hptxsts_data_t;
23928 +
23929 +/**
23930 + * This union represents the bit fields in the Host Port Control and Status
23931 + * Register. Read the register into the <i>d32</i> member then set/clear the
23932 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
23933 + * hprt0 register.
23934 + */
23935 +typedef union hprt0_data
23936 +{
23937 + /** raw register data */
23938 + uint32_t d32;
23939 + /** register bits */
23940 + struct
23941 + {
23942 + unsigned prtconnsts : 1;
23943 + unsigned prtconndet : 1;
23944 + unsigned prtena : 1;
23945 + unsigned prtenchng : 1;
23946 + unsigned prtovrcurract : 1;
23947 + unsigned prtovrcurrchng : 1;
23948 + unsigned prtres : 1;
23949 + unsigned prtsusp : 1;
23950 + unsigned prtrst : 1;
23951 + unsigned reserved9 : 1;
23952 + unsigned prtlnsts : 2;
23953 + unsigned prtpwr : 1;
23954 + unsigned prttstctl : 4;
23955 + unsigned prtspd : 2;
23956 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
23957 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
23958 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
23959 + unsigned reserved19_31 : 13;
23960 + } b;
23961 +} hprt0_data_t;
23962 +
23963 +/**
23964 + * This union represents the bit fields in the Host All Interrupt
23965 + * Register.
23966 + */
23967 +typedef union haint_data
23968 +{
23969 + /** raw register data */
23970 + uint32_t d32;
23971 + /** register bits */
23972 + struct
23973 + {
23974 + unsigned ch0 : 1;
23975 + unsigned ch1 : 1;
23976 + unsigned ch2 : 1;
23977 + unsigned ch3 : 1;
23978 + unsigned ch4 : 1;
23979 + unsigned ch5 : 1;
23980 + unsigned ch6 : 1;
23981 + unsigned ch7 : 1;
23982 + unsigned ch8 : 1;
23983 + unsigned ch9 : 1;
23984 + unsigned ch10 : 1;
23985 + unsigned ch11 : 1;
23986 + unsigned ch12 : 1;
23987 + unsigned ch13 : 1;
23988 + unsigned ch14 : 1;
23989 + unsigned ch15 : 1;
23990 + unsigned reserved : 16;
23991 + } b;
23992 +
23993 + struct
23994 + {
23995 + unsigned chint : 16;
23996 + unsigned reserved : 16;
23997 + } b2;
23998 +} haint_data_t;
23999 +
24000 +/**
24001 + * This union represents the bit fields in the Host All Interrupt
24002 + * Register.
24003 + */
24004 +typedef union haintmsk_data
24005 +{
24006 + /** raw register data */
24007 + uint32_t d32;
24008 + /** register bits */
24009 + struct
24010 + {
24011 + unsigned ch0 : 1;
24012 + unsigned ch1 : 1;
24013 + unsigned ch2 : 1;
24014 + unsigned ch3 : 1;
24015 + unsigned ch4 : 1;
24016 + unsigned ch5 : 1;
24017 + unsigned ch6 : 1;
24018 + unsigned ch7 : 1;
24019 + unsigned ch8 : 1;
24020 + unsigned ch9 : 1;
24021 + unsigned ch10 : 1;
24022 + unsigned ch11 : 1;
24023 + unsigned ch12 : 1;
24024 + unsigned ch13 : 1;
24025 + unsigned ch14 : 1;
24026 + unsigned ch15 : 1;
24027 + unsigned reserved : 16;
24028 + } b;
24029 +
24030 + struct
24031 + {
24032 + unsigned chint : 16;
24033 + unsigned reserved : 16;
24034 + } b2;
24035 +} haintmsk_data_t;
24036 +
24037 +/**
24038 + * Host Channel Specific Registers. <i>500h-5FCh</i>
24039 + */
24040 +typedef struct dwc_otg_hc_regs
24041 +{
24042 + /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
24043 + volatile uint32_t hcchar;
24044 + /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
24045 + volatile uint32_t hcsplt;
24046 + /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
24047 + volatile uint32_t hcint;
24048 + /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
24049 + volatile uint32_t hcintmsk;
24050 + /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
24051 + volatile uint32_t hctsiz;
24052 + /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
24053 + volatile uint32_t hcdma;
24054 + /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
24055 + uint32_t reserved[2];
24056 +} dwc_otg_hc_regs_t;
24057 +
24058 +/**
24059 + * This union represents the bit fields in the Host Channel Characteristics
24060 + * Register. Read the register into the <i>d32</i> member then set/clear the
24061 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
24062 + * hcchar register.
24063 + */
24064 +typedef union hcchar_data
24065 +{
24066 + /** raw register data */
24067 + uint32_t d32;
24068 +
24069 + /** register bits */
24070 + struct
24071 + {
24072 + /** Maximum packet size in bytes */
24073 + unsigned mps : 11;
24074 +
24075 + /** Endpoint number */
24076 + unsigned epnum : 4;
24077 +
24078 + /** 0: OUT, 1: IN */
24079 + unsigned epdir : 1;
24080 +
24081 + unsigned reserved : 1;
24082 +
24083 + /** 0: Full/high speed device, 1: Low speed device */
24084 + unsigned lspddev : 1;
24085 +
24086 + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
24087 + unsigned eptype : 2;
24088 +
24089 + /** Packets per frame for periodic transfers. 0 is reserved. */
24090 + unsigned multicnt : 2;
24091 +
24092 + /** Device address */
24093 + unsigned devaddr : 7;
24094 +
24095 + /**
24096 + * Frame to transmit periodic transaction.
24097 + * 0: even, 1: odd
24098 + */
24099 + unsigned oddfrm : 1;
24100 +
24101 + /** Channel disable */
24102 + unsigned chdis : 1;
24103 +
24104 + /** Channel enable */
24105 + unsigned chen : 1;
24106 + } b;
24107 +} hcchar_data_t;
24108 +
24109 +typedef union hcsplt_data
24110 +{
24111 + /** raw register data */
24112 + uint32_t d32;
24113 +
24114 + /** register bits */
24115 + struct
24116 + {
24117 + /** Port Address */
24118 + unsigned prtaddr : 7;
24119 +
24120 + /** Hub Address */
24121 + unsigned hubaddr : 7;
24122 +
24123 + /** Transaction Position */
24124 + unsigned xactpos : 2;
24125 +#define DWC_HCSPLIT_XACTPOS_MID 0
24126 +#define DWC_HCSPLIT_XACTPOS_END 1
24127 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
24128 +#define DWC_HCSPLIT_XACTPOS_ALL 3
24129 +
24130 + /** Do Complete Split */
24131 + unsigned compsplt : 1;
24132 +
24133 + /** Reserved */
24134 + unsigned reserved : 14;
24135 +
24136 + /** Split Enble */
24137 + unsigned spltena : 1;
24138 + } b;
24139 +} hcsplt_data_t;
24140 +
24141 +
24142 +/**
24143 + * This union represents the bit fields in the Host All Interrupt
24144 + * Register.
24145 + */
24146 +typedef union hcint_data
24147 +{
24148 + /** raw register data */
24149 + uint32_t d32;
24150 + /** register bits */
24151 + struct
24152 + {
24153 + /** Transfer Complete */
24154 + unsigned xfercomp : 1;
24155 + /** Channel Halted */
24156 + unsigned chhltd : 1;
24157 + /** AHB Error */
24158 + unsigned ahberr : 1;
24159 + /** STALL Response Received */
24160 + unsigned stall : 1;
24161 + /** NAK Response Received */
24162 + unsigned nak : 1;
24163 + /** ACK Response Received */
24164 + unsigned ack : 1;
24165 + /** NYET Response Received */
24166 + unsigned nyet : 1;
24167 + /** Transaction Err */
24168 + unsigned xacterr : 1;
24169 + /** Babble Error */
24170 + unsigned bblerr : 1;
24171 + /** Frame Overrun */
24172 + unsigned frmovrun : 1;
24173 + /** Data Toggle Error */
24174 + unsigned datatglerr : 1;
24175 + /** Reserved */
24176 + unsigned reserved : 21;
24177 + } b;
24178 +} hcint_data_t;
24179 +
24180 +/**
24181 + * This union represents the bit fields in the Host Channel Transfer Size
24182 + * Register. Read the register into the <i>d32</i> member then set/clear the
24183 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
24184 + * hcchar register.
24185 + */
24186 +typedef union hctsiz_data
24187 +{
24188 + /** raw register data */
24189 + uint32_t d32;
24190 +
24191 + /** register bits */
24192 + struct
24193 + {
24194 + /** Total transfer size in bytes */
24195 + unsigned xfersize : 19;
24196 +
24197 + /** Data packets to transfer */
24198 + unsigned pktcnt : 10;
24199 +
24200 + /**
24201 + * Packet ID for next data packet
24202 + * 0: DATA0
24203 + * 1: DATA2
24204 + * 2: DATA1
24205 + * 3: MDATA (non-Control), SETUP (Control)
24206 + */
24207 + unsigned pid : 2;
24208 +#define DWC_HCTSIZ_DATA0 0
24209 +#define DWC_HCTSIZ_DATA1 2
24210 +#define DWC_HCTSIZ_DATA2 1
24211 +#define DWC_HCTSIZ_MDATA 3
24212 +#define DWC_HCTSIZ_SETUP 3
24213 +
24214 + /** Do PING protocol when 1 */
24215 + unsigned dopng : 1;
24216 + } b;
24217 +} hctsiz_data_t;
24218 +
24219 +/**
24220 + * This union represents the bit fields in the Host Channel Interrupt Mask
24221 + * Register. Read the register into the <i>d32</i> member then set/clear the
24222 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
24223 + * hcintmsk register.
24224 + */
24225 +typedef union hcintmsk_data
24226 +{
24227 + /** raw register data */
24228 + uint32_t d32;
24229 +
24230 + /** register bits */
24231 + struct
24232 + {
24233 + unsigned xfercompl : 1;
24234 + unsigned chhltd : 1;
24235 + unsigned ahberr : 1;
24236 + unsigned stall : 1;
24237 + unsigned nak : 1;
24238 + unsigned ack : 1;
24239 + unsigned nyet : 1;
24240 + unsigned xacterr : 1;
24241 + unsigned bblerr : 1;
24242 + unsigned frmovrun : 1;
24243 + unsigned datatglerr : 1;
24244 + unsigned reserved : 21;
24245 + } b;
24246 +} hcintmsk_data_t;
24247 +
24248 +/** OTG Host Interface Structure.
24249 + *
24250 + * The OTG Host Interface Structure structure contains information
24251 + * needed to manage the DWC_otg controller acting in host mode. It
24252 + * represents the programming view of the host-specific aspects of the
24253 + * controller.
24254 + */
24255 +typedef struct dwc_otg_host_if
24256 +{
24257 + /** Host Global Registers starting at offset 400h.*/
24258 + dwc_otg_host_global_regs_t *host_global_regs;
24259 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
24260 +
24261 + /** Host Port 0 Control and Status Register */
24262 + volatile uint32_t *hprt0;
24263 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
24264 +
24265 +
24266 + /** Host Channel Specific Registers at offsets 500h-5FCh. */
24267 + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
24268 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
24269 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
24270 +
24271 +
24272 + /* Host configuration information */
24273 + /** Number of Host Channels (range: 1-16) */
24274 + uint8_t num_host_channels;
24275 + /** Periodic EPs supported (0: no, 1: yes) */
24276 + uint8_t perio_eps_supported;
24277 + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
24278 + uint16_t perio_tx_fifo_size;
24279 +
24280 +} dwc_otg_host_if_t;
24281 +
24282 +
24283 +/**
24284 + * This union represents the bit fields in the Power and Clock Gating Control
24285 + * Register. Read the register into the <i>d32</i> member then set/clear the
24286 + * bits using the <i>b</i>it elements.
24287 + */
24288 +typedef union pcgcctl_data
24289 +{
24290 + /** raw register data */
24291 + uint32_t d32;
24292 +
24293 + /** register bits */
24294 + struct
24295 + {
24296 + /** Stop Pclk */
24297 + unsigned stoppclk : 1;
24298 + /** Gate Hclk */
24299 + unsigned gatehclk : 1;
24300 + /** Power Clamp */
24301 + unsigned pwrclmp : 1;
24302 + /** Reset Power Down Modules */
24303 + unsigned rstpdwnmodule : 1;
24304 + /** PHY Suspended */
24305 + unsigned physuspended : 1;
24306 +
24307 + unsigned reserved : 27;
24308 + } b;
24309 +} pcgcctl_data_t;
24310 +
24311 +
24312 +#endif
24313 diff --git a/drivers/usb/dwc_otg/linux/dwc_otg_plat.h b/drivers/usb/dwc_otg/linux/dwc_otg_plat.h
24314 new file mode 100644
24315 index 0000000..618151b
24316 --- /dev/null
24317 +++ b/drivers/usb/dwc_otg/linux/dwc_otg_plat.h
24318 @@ -0,0 +1,260 @@
24319 +/* ==========================================================================
24320 + * $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $
24321 + * $Revision: 1.2 $
24322 + * $Date: 2008-11-21 05:39:16 $
24323 + * $Change: 1064915 $
24324 + *
24325 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
24326 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
24327 + * otherwise expressly agreed to in writing between Synopsys and you.
24328 + *
24329 + * The Software IS NOT an item of Licensed Software or Licensed Product under
24330 + * any End User Software License Agreement or Agreement for Licensed Product
24331 + * with Synopsys or any supplement thereto. You are permitted to use and
24332 + * redistribute this Software in source and binary forms, with or without
24333 + * modification, provided that redistributions of source code must retain this
24334 + * notice. You may not view, use, disclose, copy or distribute this file or
24335 + * any information contained herein except pursuant to this license grant from
24336 + * Synopsys. If you do not agree with this notice, including the disclaimer
24337 + * below, then you are not authorized to use the Software.
24338 + *
24339 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
24340 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24341 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24342 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
24343 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24344 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24345 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
24346 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24347 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24348 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
24349 + * DAMAGE.
24350 + * ========================================================================== */
24351 +
24352 +#if !defined(__DWC_OTG_PLAT_H__)
24353 +#define __DWC_OTG_PLAT_H__
24354 +
24355 +#include <linux/types.h>
24356 +#include <linux/slab.h>
24357 +#include <linux/list.h>
24358 +#include <linux/delay.h>
24359 +#include <asm/io.h>
24360 +
24361 +/**
24362 + * @file
24363 + *
24364 + * This file contains the Platform Specific constants, interfaces
24365 + * (functions and macros) for Linux.
24366 + *
24367 + */
24368 +//#if !defined(__LINUX_ARM_ARCH__)
24369 +//#error "The contents of this file is Linux specific!!!"
24370 +//#endif
24371 +
24372 +/**
24373 + * Reads the content of a register.
24374 + *
24375 + * @param reg address of register to read.
24376 + * @return contents of the register.
24377 + *
24378 +
24379 + * Usage:<br>
24380 + * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
24381 + */
24382 +static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg)
24383 +{
24384 + return readl(reg);
24385 +};
24386 +
24387 +/**
24388 + * Writes a register with a 32 bit value.
24389 + *
24390 + * @param reg address of register to read.
24391 + * @param value to write to _reg.
24392 + *
24393 + * Usage:<br>
24394 + * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
24395 + */
24396 +static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value)
24397 +{
24398 + writel( value, reg );
24399 +};
24400 +
24401 +/**
24402 + * This function modifies bit values in a register. Using the
24403 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
24404 + *
24405 + * @param reg address of register to read.
24406 + * @param clear_mask bit mask to be cleared.
24407 + * @param set_mask bit mask to be set.
24408 + *
24409 + * Usage:<br>
24410 + * <code> // Clear the SOF Interrupt Mask bit and <br>
24411 + * // set the OTG Interrupt mask bit, leaving all others as they were.
24412 + * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
24413 + */
24414 +static __inline__
24415 + void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask)
24416 +{
24417 + writel( (readl(reg) & ~clear_mask) | set_mask, reg );
24418 +};
24419 +
24420 +
24421 +/**
24422 + * Wrapper for the OS micro-second delay function.
24423 + * @param[in] usecs Microseconds of delay
24424 + */
24425 +static __inline__ void UDELAY( const uint32_t usecs )
24426 +{
24427 + udelay( usecs );
24428 +}
24429 +
24430 +/**
24431 + * Wrapper for the OS milli-second delay function.
24432 + * @param[in] msecs milliseconds of delay
24433 + */
24434 +static __inline__ void MDELAY( const uint32_t msecs )
24435 +{
24436 + mdelay( msecs );
24437 +}
24438 +
24439 +/**
24440 + * Wrapper for the Linux spin_lock. On the ARM (Integrator)
24441 + * spin_lock() is a nop.
24442 + *
24443 + * @param lock Pointer to the spinlock.
24444 + */
24445 +static __inline__ void SPIN_LOCK( spinlock_t *lock )
24446 +{
24447 + spin_lock(lock);
24448 +}
24449 +
24450 +/**
24451 + * Wrapper for the Linux spin_unlock. On the ARM (Integrator)
24452 + * spin_lock() is a nop.
24453 + *
24454 + * @param lock Pointer to the spinlock.
24455 + */
24456 +static __inline__ void SPIN_UNLOCK( spinlock_t *lock )
24457 +{
24458 + spin_unlock(lock);
24459 +}
24460 +
24461 +/**
24462 + * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
24463 + * (Integrator) spin_lock() is a nop.
24464 + *
24465 + * @param l Pointer to the spinlock.
24466 + * @param f unsigned long for irq flags storage.
24467 + */
24468 +#define SPIN_LOCK_IRQSAVE( l, f ) spin_lock_irqsave(l,f);
24469 +
24470 +/**
24471 + * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
24472 + * (Integrator) spin_lock() is a nop.
24473 + *
24474 + * @param l Pointer to the spinlock.
24475 + * @param f unsigned long for irq flags storage.
24476 + */
24477 +#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f);
24478 +
24479 +/*
24480 + * Debugging support vanishes in non-debug builds.
24481 + */
24482 +
24483 +
24484 +/**
24485 + * The Debug Level bit-mask variable.
24486 + */
24487 +extern uint32_t g_dbg_lvl;
24488 +/**
24489 + * Set the Debug Level variable.
24490 + */
24491 +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new )
24492 +{
24493 + uint32_t old = g_dbg_lvl;
24494 + g_dbg_lvl = new;
24495 + return old;
24496 +}
24497 +
24498 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
24499 +#define DBG_CIL (0x2)
24500 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
24501 + * messages */
24502 +#define DBG_CILV (0x20)
24503 +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
24504 + * messages */
24505 +#define DBG_PCD (0x4)
24506 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
24507 + * messages */
24508 +#define DBG_PCDV (0x40)
24509 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
24510 +#define DBG_HCD (0x8)
24511 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
24512 + * messages */
24513 +#define DBG_HCDV (0x80)
24514 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
24515 + * mode. */
24516 +#define DBG_HCD_URB (0x800)
24517 +
24518 +/** When debug level has any bit set, display debug messages */
24519 +#define DBG_ANY (0xFF)
24520 +
24521 +/** All debug messages off */
24522 +#define DBG_OFF 0
24523 +
24524 +/** Prefix string for DWC_DEBUG print macros. */
24525 +#define USB_DWC "dwc_otg: "
24526 +
24527 +/**
24528 + * Print a debug message when the Global debug level variable contains
24529 + * the bit defined in <code>lvl</code>.
24530 + *
24531 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
24532 + * @param[in] x - like printf
24533 + *
24534 + * Example:<p>
24535 + * <code>
24536 + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
24537 + * </code>
24538 + * <br>
24539 + * results in:<br>
24540 + * <code>
24541 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
24542 + * </code>
24543 + */
24544 +#ifdef DEBUG
24545 +
24546 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
24547 +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
24548 +
24549 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
24550 +
24551 +#else
24552 +
24553 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
24554 +# define DWC_DEBUGP(x...)
24555 +
24556 +# define CHK_DEBUG_LEVEL(level) (0)
24557 +
24558 +#endif /*DEBUG*/
24559 +
24560 +/**
24561 + * Print an Error message.
24562 + */
24563 +#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
24564 +/**
24565 + * Print a Warning message.
24566 + */
24567 +#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
24568 +/**
24569 + * Print a notice (normal but significant message).
24570 + */
24571 +#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
24572 +/**
24573 + * Basic message printing.
24574 + */
24575 +#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
24576 +
24577 +#endif
24578 +
24579 --
24580 1.7.10.4
24581
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