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[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.9 / 0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From 1efe3ce91ab951090ac8db1872f0de32e0a88de8 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 31 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
20 drivers/net/ethernet/ralink/mdio.c | 245 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 746 ++++++++++
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
26 drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
27 drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
28 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
29 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
30 drivers/watchdog/rt2880_wdt.c | 9 +-
31 21 files changed, 4622 insertions(+), 4 deletions(-)
32 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
33 create mode 100644 drivers/net/ethernet/ralink/Kconfig
34 create mode 100644 drivers/net/ethernet/ralink/Makefile
35 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
36 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
37 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
38 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
39 create mode 100644 drivers/net/ethernet/ralink/mdio.c
40 create mode 100644 drivers/net/ethernet/ralink/mdio.h
41 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
42 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
43 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
44 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
45 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
46 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
47 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
48 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
49
50 diff --git a/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
51 new file mode 100644
52 index 0000000..2098c5c
53 --- /dev/null
54 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
55 @@ -0,0 +1,27 @@
56 +/*
57 + * Ralink RT305x SoC platform device registration
58 + *
59 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
60 + *
61 + * This program is free software; you can redistribute it and/or modify it
62 + * under the terms of the GNU General Public License version 2 as published
63 + * by the Free Software Foundation.
64 + */
65 +
66 +#ifndef _RT305X_ESW_PLATFORM_H
67 +#define _RT305X_ESW_PLATFORM_H
68 +
69 +enum {
70 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
71 + RT305X_ESW_VLAN_CONFIG_LLLLW,
72 + RT305X_ESW_VLAN_CONFIG_WLLLL,
73 +};
74 +
75 +struct rt305x_esw_platform_data
76 +{
77 + u8 vlan_config;
78 + u32 reg_initval_fct2;
79 + u32 reg_initval_fpa2;
80 +};
81 +
82 +#endif /* _RT305X_ESW_PLATFORM_H */
83 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
84 index ca7ee3a..1a6b458 100644
85 --- a/arch/mips/ralink/rt305x.c
86 +++ b/arch/mips/ralink/rt305x.c
87 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
88 }
89
90 ralink_clk_add("cpu", cpu_rate);
91 + ralink_clk_add("sys", sys_rate);
92 ralink_clk_add("10000b00.spi", sys_rate);
93 ralink_clk_add("10000100.timer", wdt_rate);
94 ralink_clk_add("10000120.watchdog", wdt_rate);
95 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
96 index ed956e0..0b3caa1 100644
97 --- a/drivers/net/ethernet/Kconfig
98 +++ b/drivers/net/ethernet/Kconfig
99 @@ -135,6 +135,7 @@ config ETHOC
100 source "drivers/net/ethernet/packetengines/Kconfig"
101 source "drivers/net/ethernet/pasemi/Kconfig"
102 source "drivers/net/ethernet/qlogic/Kconfig"
103 +source "drivers/net/ethernet/ralink/Kconfig"
104 source "drivers/net/ethernet/realtek/Kconfig"
105 source "drivers/net/ethernet/renesas/Kconfig"
106 source "drivers/net/ethernet/rdc/Kconfig"
107 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
108 index 8268d85..508c494 100644
109 --- a/drivers/net/ethernet/Makefile
110 +++ b/drivers/net/ethernet/Makefile
111 @@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
112 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
113 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
114 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
115 +obj-$(CONFIG_NET_RALINK) += ralink/
116 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
117 obj-$(CONFIG_SH_ETH) += renesas/
118 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
119 diff --git a/drivers/net/ethernet/ralink/Kconfig b/drivers/net/ethernet/ralink/Kconfig
120 new file mode 100644
121 index 0000000..ca2c9ad
122 --- /dev/null
123 +++ b/drivers/net/ethernet/ralink/Kconfig
124 @@ -0,0 +1,31 @@
125 +config NET_RALINK
126 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
127 + depends on RALINK
128 + help
129 + This driver supports the ethernet mac inside the ralink wisocs
130 +
131 +if NET_RALINK
132 +
133 +config NET_RALINK_MDIO
134 + def_bool NET_RALINK
135 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
136 + select PHYLIB
137 +
138 +config NET_RALINK_MDIO_RT2880
139 + def_bool NET_RALINK
140 + depends on (SOC_RT288X || SOC_RT3883)
141 + select NET_RALINK_MDIO
142 +
143 +config NET_RALINK_ESW_RT3052
144 + def_bool NET_RALINK
145 + depends on SOC_RT305X
146 + select PHYLIB
147 + select SWCONFIG
148 +
149 +config NET_RALINK_GSW_MT7620
150 + def_bool NET_RALINK
151 + depends on SOC_MT7620
152 + select NET_RALINK_MDIO
153 + select PHYLIB
154 + select SWCONFIG
155 +endif
156 diff --git a/drivers/net/ethernet/ralink/Makefile b/drivers/net/ethernet/ralink/Makefile
157 new file mode 100644
158 index 0000000..a38fa21
159 --- /dev/null
160 +++ b/drivers/net/ethernet/ralink/Makefile
161 @@ -0,0 +1,18 @@
162 +#
163 +# Makefile for the Ralink SoCs built-in ethernet macs
164 +#
165 +
166 +ralink-eth-y += ralink_soc_eth.o
167 +
168 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
169 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
170 +
171 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
172 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o
173 +
174 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
175 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
176 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
177 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
178 +
179 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
180 diff --git a/drivers/net/ethernet/ralink/esw_rt3052.c b/drivers/net/ethernet/ralink/esw_rt3052.c
181 new file mode 100644
182 index 0000000..b937062
183 --- /dev/null
184 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
185 @@ -0,0 +1,1463 @@
186 +/*
187 + * This program is free software; you can redistribute it and/or modify
188 + * it under the terms of the GNU General Public License as published by
189 + * the Free Software Foundation; version 2 of the License
190 + *
191 + * This program is distributed in the hope that it will be useful,
192 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
193 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
194 + * GNU General Public License for more details.
195 + *
196 + * You should have received a copy of the GNU General Public License
197 + * along with this program; if not, write to the Free Software
198 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
199 + *
200 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
201 + */
202 +
203 +#include <linux/module.h>
204 +#include <linux/kernel.h>
205 +#include <linux/types.h>
206 +#include <linux/dma-mapping.h>
207 +#include <linux/init.h>
208 +#include <linux/skbuff.h>
209 +#include <linux/etherdevice.h>
210 +#include <linux/ethtool.h>
211 +#include <linux/platform_device.h>
212 +#include <linux/of_device.h>
213 +#include <linux/clk.h>
214 +#include <linux/of_net.h>
215 +#include <linux/of_mdio.h>
216 +
217 +#include <asm/mach-ralink/ralink_regs.h>
218 +
219 +#include "ralink_soc_eth.h"
220 +
221 +#include <linux/ioport.h>
222 +#include <linux/switch.h>
223 +#include <linux/mii.h>
224 +
225 +#include <ralink_regs.h>
226 +#include <asm/mach-ralink/rt305x.h>
227 +#include <asm/mach-ralink/rt305x_esw_platform.h>
228 +
229 +/*
230 + * HW limitations for this switch:
231 + * - No large frame support (PKT_MAX_LEN at most 1536)
232 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
233 + * though this might be possible using the undocumented PPE.
234 + */
235 +
236 +#define RT305X_ESW_REG_ISR 0x00
237 +#define RT305X_ESW_REG_IMR 0x04
238 +#define RT305X_ESW_REG_FCT0 0x08
239 +#define RT305X_ESW_REG_PFC1 0x14
240 +#define RT305X_ESW_REG_ATS 0x24
241 +#define RT305X_ESW_REG_ATS0 0x28
242 +#define RT305X_ESW_REG_ATS1 0x2c
243 +#define RT305X_ESW_REG_ATS2 0x30
244 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
245 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
246 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
247 +#define RT305X_ESW_REG_POA 0x80
248 +#define RT305X_ESW_REG_FPA 0x84
249 +#define RT305X_ESW_REG_SOCPC 0x8c
250 +#define RT305X_ESW_REG_POC0 0x90
251 +#define RT305X_ESW_REG_POC1 0x94
252 +#define RT305X_ESW_REG_POC2 0x98
253 +#define RT305X_ESW_REG_SGC 0x9c
254 +#define RT305X_ESW_REG_STRT 0xa0
255 +#define RT305X_ESW_REG_PCR0 0xc0
256 +#define RT305X_ESW_REG_PCR1 0xc4
257 +#define RT305X_ESW_REG_FPA2 0xc8
258 +#define RT305X_ESW_REG_FCT2 0xcc
259 +#define RT305X_ESW_REG_SGC2 0xe4
260 +#define RT305X_ESW_REG_P0LED 0xa4
261 +#define RT305X_ESW_REG_P1LED 0xa8
262 +#define RT305X_ESW_REG_P2LED 0xac
263 +#define RT305X_ESW_REG_P3LED 0xb0
264 +#define RT305X_ESW_REG_P4LED 0xb4
265 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
266 +#define RT305X_ESW_REG_P1PC 0xec
267 +#define RT305X_ESW_REG_P2PC 0xf0
268 +#define RT305X_ESW_REG_P3PC 0xf4
269 +#define RT305X_ESW_REG_P4PC 0xf8
270 +#define RT305X_ESW_REG_P5PC 0xfc
271 +
272 +#define RT305X_ESW_LED_LINK 0
273 +#define RT305X_ESW_LED_100M 1
274 +#define RT305X_ESW_LED_DUPLEX 2
275 +#define RT305X_ESW_LED_ACTIVITY 3
276 +#define RT305X_ESW_LED_COLLISION 4
277 +#define RT305X_ESW_LED_LINKACT 5
278 +#define RT305X_ESW_LED_DUPLCOLL 6
279 +#define RT305X_ESW_LED_10MACT 7
280 +#define RT305X_ESW_LED_100MACT 8
281 +/* Additional led states not in datasheet: */
282 +#define RT305X_ESW_LED_BLINK 10
283 +#define RT305X_ESW_LED_ON 12
284 +
285 +#define RT305X_ESW_LINK_S 25
286 +#define RT305X_ESW_DUPLEX_S 9
287 +#define RT305X_ESW_SPD_S 0
288 +
289 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
290 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
291 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
292 +
293 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
294 +
295 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
296 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
297 +
298 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
299 +#define RT305X_ESW_PVIDC_PVID_S 12
300 +
301 +#define RT305X_ESW_VLANI_VID_M 0xfff
302 +#define RT305X_ESW_VLANI_VID_S 12
303 +
304 +#define RT305X_ESW_VMSC_MSC_M 0xff
305 +#define RT305X_ESW_VMSC_MSC_S 8
306 +
307 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
308 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
309 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
310 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
311 +
312 +#define RT305X_ESW_POC0_EN_BP_S 0
313 +#define RT305X_ESW_POC0_EN_FC_S 8
314 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
315 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
316 +#define RT305X_ESW_POC0_DIS_PORT_S 23
317 +
318 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
319 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
320 +#define RT305X_ESW_POC2_ENAGING_S 8
321 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
322 +
323 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
324 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
325 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
326 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
327 +
328 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
329 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
330 +#define RT305X_ESW_PFC1_EN_TOS_S 24
331 +
332 +#define RT305X_ESW_VLAN_NONE 0xfff
333 +
334 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
335 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
336 +
337 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
338 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
339 +
340 +#define RT305X_ESW_POA_LINK_MASK 0x1f
341 +#define RT305X_ESW_POA_LINK_SHIFT 25
342 +
343 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
344 +#define RT305X_ESW_PORT0 0
345 +#define RT305X_ESW_PORT1 1
346 +#define RT305X_ESW_PORT2 2
347 +#define RT305X_ESW_PORT3 3
348 +#define RT305X_ESW_PORT4 4
349 +#define RT305X_ESW_PORT5 5
350 +#define RT305X_ESW_PORT6 6
351 +
352 +#define RT305X_ESW_PORTS_NONE 0
353 +
354 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
355 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
356 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
357 +
358 +#define RT305X_ESW_PORTS_INTERNAL \
359 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
360 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
361 + BIT(RT305X_ESW_PORT4))
362 +
363 +#define RT305X_ESW_PORTS_NOCPU \
364 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
365 +
366 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
367 +
368 +#define RT305X_ESW_PORTS_ALL \
369 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
370 +
371 +#define RT305X_ESW_NUM_VLANS 16
372 +#define RT305X_ESW_NUM_VIDS 4096
373 +#define RT305X_ESW_NUM_PORTS 7
374 +#define RT305X_ESW_NUM_LANWAN 6
375 +#define RT305X_ESW_NUM_LEDS 5
376 +
377 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
378 +#define RT5350_EWS_REG_LED_POLARITY 0x168
379 +#define RT5350_RESET_EPHY BIT(24)
380 +#define SYSC_REG_RESET_CTRL 0x34
381 +
382 +enum {
383 + /* Global attributes. */
384 + RT305X_ESW_ATTR_ENABLE_VLAN,
385 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
386 + RT305X_ESW_ATTR_BC_STATUS,
387 + RT305X_ESW_ATTR_LED_FREQ,
388 + /* Port attributes. */
389 + RT305X_ESW_ATTR_PORT_DISABLE,
390 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
391 + RT305X_ESW_ATTR_PORT_UNTAG,
392 + RT305X_ESW_ATTR_PORT_LED,
393 + RT305X_ESW_ATTR_PORT_LAN,
394 + RT305X_ESW_ATTR_PORT_RECV_BAD,
395 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
396 + RT5350_ESW_ATTR_PORT_TR_BAD,
397 + RT5350_ESW_ATTR_PORT_TR_GOOD,
398 +};
399 +
400 +struct esw_port {
401 + bool disable;
402 + bool doubletag;
403 + bool untag;
404 + u8 led;
405 + u16 pvid;
406 +};
407 +
408 +struct esw_vlan {
409 + u8 ports;
410 + u16 vid;
411 +};
412 +
413 +struct rt305x_esw {
414 + struct device *dev;
415 + void __iomem *base;
416 + int irq;
417 + const struct rt305x_esw_platform_data *pdata;
418 + /* Protects against concurrent register rmw operations. */
419 + spinlock_t reg_rw_lock;
420 +
421 + unsigned char port_map;
422 + unsigned int reg_initval_fct2;
423 + unsigned int reg_initval_fpa2;
424 + unsigned int reg_led_polarity;
425 +
426 +
427 + struct switch_dev swdev;
428 + bool global_vlan_enable;
429 + bool alt_vlan_disable;
430 + int bc_storm_protect;
431 + int led_frequency;
432 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
433 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
434 +
435 +};
436 +
437 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
438 +{
439 + __raw_writel(val, esw->base + reg);
440 +}
441 +
442 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
443 +{
444 + return __raw_readl(esw->base + reg);
445 +}
446 +
447 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
448 + unsigned long val)
449 +{
450 + unsigned long t;
451 +
452 + t = __raw_readl(esw->base + reg) & ~mask;
453 + __raw_writel(t | val, esw->base + reg);
454 +}
455 +
456 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
457 + unsigned long val)
458 +{
459 + unsigned long flags;
460 +
461 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
462 + esw_rmw_raw(esw, reg, mask, val);
463 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
464 +}
465 +
466 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
467 + u32 write_data)
468 +{
469 + unsigned long t_start = jiffies;
470 + int ret = 0;
471 +
472 + while (1) {
473 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
474 + RT305X_ESW_PCR1_WT_DONE))
475 + break;
476 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
477 + ret = 1;
478 + goto out;
479 + }
480 + }
481 +
482 + write_data &= 0xffff;
483 + esw_w32(esw,
484 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
485 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
486 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
487 + RT305X_ESW_REG_PCR0);
488 +
489 + t_start = jiffies;
490 + while (1) {
491 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
492 + RT305X_ESW_PCR1_WT_DONE)
493 + break;
494 +
495 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
496 + ret = 1;
497 + break;
498 + }
499 + }
500 +out:
501 + if (ret)
502 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
503 + return ret;
504 +}
505 +
506 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
507 +{
508 + unsigned s;
509 + unsigned val;
510 +
511 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
512 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
513 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
514 +
515 + return val;
516 +}
517 +
518 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
519 +{
520 + unsigned s;
521 +
522 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
523 + esw_rmw(esw,
524 + RT305X_ESW_REG_VLANI(vlan / 2),
525 + RT305X_ESW_VLANI_VID_M << s,
526 + (vid & RT305X_ESW_VLANI_VID_M) << s);
527 +}
528 +
529 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
530 +{
531 + unsigned s, val;
532 +
533 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
534 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
535 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
536 +}
537 +
538 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
539 +{
540 + unsigned s;
541 +
542 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
543 + esw_rmw(esw,
544 + RT305X_ESW_REG_PVIDC(port / 2),
545 + RT305X_ESW_PVIDC_PVID_M << s,
546 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
547 +}
548 +
549 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
550 +{
551 + unsigned s, val;
552 +
553 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
554 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
555 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
556 +
557 + return val;
558 +}
559 +
560 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
561 +{
562 + unsigned s;
563 +
564 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
565 + esw_rmw(esw,
566 + RT305X_ESW_REG_VMSC(vlan / 4),
567 + RT305X_ESW_VMSC_MSC_M << s,
568 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
569 +}
570 +
571 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
572 +{
573 + unsigned reg;
574 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
575 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
576 + RT305X_ESW_POC0_DIS_PORT_M;
577 +}
578 +
579 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
580 +{
581 + unsigned old_mask;
582 + unsigned enable_mask;
583 + unsigned changed;
584 + int i;
585 +
586 + old_mask = esw_get_port_disable(esw);
587 + changed = old_mask ^ disable_mask;
588 + enable_mask = old_mask & disable_mask;
589 +
590 + /* enable before writing to MII */
591 + esw_rmw(esw, RT305X_ESW_REG_POC0,
592 + (RT305X_ESW_POC0_DIS_PORT_M <<
593 + RT305X_ESW_POC0_DIS_PORT_S),
594 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
595 +
596 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
597 + if (!(changed & (1 << i)))
598 + continue;
599 + if (disable_mask & (1 << i)) {
600 + /* disable */
601 + rt305x_mii_write(esw, i, MII_BMCR,
602 + BMCR_PDOWN);
603 + } else {
604 + /* enable */
605 + rt305x_mii_write(esw, i, MII_BMCR,
606 + BMCR_FULLDPLX |
607 + BMCR_ANENABLE |
608 + BMCR_ANRESTART |
609 + BMCR_SPEED100);
610 + }
611 + }
612 +
613 + /* disable after writing to MII */
614 + esw_rmw(esw, RT305X_ESW_REG_POC0,
615 + (RT305X_ESW_POC0_DIS_PORT_M <<
616 + RT305X_ESW_POC0_DIS_PORT_S),
617 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
618 +}
619 +
620 +static void esw_set_gsc(struct rt305x_esw *esw)
621 +{
622 + esw_rmw(esw, RT305X_ESW_REG_SGC,
623 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
624 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
625 + esw_rmw(esw, RT305X_ESW_REG_SGC,
626 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
627 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
628 +}
629 +
630 +static int esw_apply_config(struct switch_dev *dev);
631 +
632 +static void esw_hw_init(struct rt305x_esw *esw)
633 +{
634 + int i;
635 + u8 port_disable = 0;
636 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
637 +
638 + /* vodoo from original driver */
639 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
640 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
641 + /* Port priority 1 for all ports, vlan enabled. */
642 + esw_w32(esw, 0x00005555 |
643 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
644 + RT305X_ESW_REG_PFC1);
645 +
646 + /* Enable Back Pressure, and Flow Control */
647 + esw_w32(esw,
648 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
649 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
650 + RT305X_ESW_REG_POC0);
651 +
652 + /* Enable Aging, and VLAN TAG removal */
653 + esw_w32(esw,
654 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
655 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
656 + RT305X_ESW_REG_POC2);
657 +
658 + if (esw->reg_initval_fct2)
659 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
660 + else
661 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
662 +
663 + /*
664 + * 300s aging timer, max packet len 1536, broadcast storm prevention
665 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
666 + * pressure jam, GMII disable was_transmit, back pressure disabled,
667 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
668 + * ports.
669 + */
670 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
671 +
672 + /* Setup SoC Port control register */
673 + esw_w32(esw,
674 + (RT305X_ESW_SOCPC_CRC_PADDING |
675 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
676 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
677 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
678 + RT305X_ESW_REG_SOCPC);
679 +
680 + if (esw->reg_initval_fpa2)
681 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
682 + else
683 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
684 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
685 +
686 + /* Force Link/Activity on ports */
687 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
688 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
689 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
690 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
691 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
692 +
693 + /* Copy disabled port configuration from bootloader setup */
694 + port_disable = esw_get_port_disable(esw);
695 + for (i = 0; i < 6; i++)
696 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
697 +
698 + if (soc_is_rt3352()) {
699 + /* reset EPHY */
700 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
701 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
702 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
703 +
704 + rt305x_mii_write(esw, 0, 31, 0x8000);
705 + for (i = 0; i < 5; i++) {
706 + if (esw->ports[i].disable) {
707 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
708 + } else {
709 + rt305x_mii_write(esw, i, MII_BMCR,
710 + BMCR_FULLDPLX |
711 + BMCR_ANENABLE |
712 + BMCR_SPEED100);
713 + }
714 + /* TX10 waveform coefficient LSB=0 disable PHY */
715 + rt305x_mii_write(esw, i, 26, 0x1601);
716 + /* TX100/TX10 AD/DA current bias */
717 + rt305x_mii_write(esw, i, 29, 0x7016);
718 + /* TX100 slew rate control */
719 + rt305x_mii_write(esw, i, 30, 0x0038);
720 + }
721 +
722 + /* select global register */
723 + rt305x_mii_write(esw, 0, 31, 0x0);
724 + /* enlarge agcsel threshold 3 and threshold 2 */
725 + rt305x_mii_write(esw, 0, 1, 0x4a40);
726 + /* enlarge agcsel threshold 5 and threshold 4 */
727 + rt305x_mii_write(esw, 0, 2, 0x6254);
728 + /* enlarge agcsel threshold */
729 + rt305x_mii_write(esw, 0, 3, 0xa17f);
730 + rt305x_mii_write(esw, 0,12, 0x7eaa);
731 + /* longer TP_IDL tail length */
732 + rt305x_mii_write(esw, 0, 14, 0x65);
733 + /* increased squelch pulse count threshold. */
734 + rt305x_mii_write(esw, 0, 16, 0x0684);
735 + /* set TX10 signal amplitude threshold to minimum */
736 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
737 + /* set squelch amplitude to higher threshold */
738 + rt305x_mii_write(esw, 0, 18, 0x40ba);
739 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
740 + rt305x_mii_write(esw, 0, 22, 0x253f);
741 + /* set PLL/Receive bias current are calibrated */
742 + rt305x_mii_write(esw, 0, 27, 0x2fda);
743 + /* change PLL/Receive bias current to internal(RT3350) */
744 + rt305x_mii_write(esw, 0, 28, 0xc410);
745 + /* change PLL bias current to internal(RT3052_MP3) */
746 + rt305x_mii_write(esw, 0, 29, 0x598b);
747 + /* select local register */
748 + rt305x_mii_write(esw, 0, 31, 0x8000);
749 + } else if (soc_is_rt5350()) {
750 + /* reset EPHY */
751 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
752 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
753 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
754 +
755 + /* set the led polarity */
756 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
757 +
758 + /* local registers */
759 + rt305x_mii_write(esw, 0, 31, 0x8000);
760 + for (i = 0; i < 5; i++) {
761 + if (esw->ports[i].disable) {
762 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
763 + } else {
764 + rt305x_mii_write(esw, i, MII_BMCR,
765 + BMCR_FULLDPLX |
766 + BMCR_ANENABLE |
767 + BMCR_SPEED100);
768 + }
769 + /* TX10 waveform coefficient LSB=0 disable PHY */
770 + rt305x_mii_write(esw, i, 26, 0x1601);
771 + /* TX100/TX10 AD/DA current bias */
772 + rt305x_mii_write(esw, i, 29, 0x7015);
773 + /* TX100 slew rate control */
774 + rt305x_mii_write(esw, i, 30, 0x0038);
775 + }
776 +
777 + /* global registers */
778 + rt305x_mii_write(esw, 0, 31, 0x0);
779 + /* enlarge agcsel threshold 3 and threshold 2 */
780 + rt305x_mii_write(esw, 0, 1, 0x4a40);
781 + /* enlarge agcsel threshold 5 and threshold 4 */
782 + rt305x_mii_write(esw, 0, 2, 0x6254);
783 + /* enlarge agcsel threshold 6 */
784 + rt305x_mii_write(esw, 0, 3, 0xa17f);
785 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
786 + /* longer TP_IDL tail length */
787 + rt305x_mii_write(esw, 0, 14, 0x65);
788 + /* increased squelch pulse count threshold. */
789 + rt305x_mii_write(esw, 0, 16, 0x0684);
790 + /* set TX10 signal amplitude threshold to minimum */
791 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
792 + /* set squelch amplitude to higher threshold */
793 + rt305x_mii_write(esw, 0, 18, 0x40ba);
794 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
795 + rt305x_mii_write(esw, 0, 22, 0x253f);
796 + /* set PLL/Receive bias current are calibrated */
797 + rt305x_mii_write(esw, 0, 27, 0x2fda);
798 + /* change PLL/Receive bias current to internal(RT3350) */
799 + rt305x_mii_write(esw, 0, 28, 0xc410);
800 + /* change PLL bias current to internal(RT3052_MP3) */
801 + rt305x_mii_write(esw, 0, 29, 0x598b);
802 + /* select local register */
803 + rt305x_mii_write(esw, 0, 31, 0x8000);
804 + } else {
805 + rt305x_mii_write(esw, 0, 31, 0x8000);
806 + for (i = 0; i < 5; i++) {
807 + if (esw->ports[i].disable) {
808 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
809 + } else {
810 + rt305x_mii_write(esw, i, MII_BMCR,
811 + BMCR_FULLDPLX |
812 + BMCR_ANENABLE |
813 + BMCR_SPEED100);
814 + }
815 + /* TX10 waveform coefficient */
816 + rt305x_mii_write(esw, i, 26, 0x1601);
817 + /* TX100/TX10 AD/DA current bias */
818 + rt305x_mii_write(esw, i, 29, 0x7058);
819 + /* TX100 slew rate control */
820 + rt305x_mii_write(esw, i, 30, 0x0018);
821 + }
822 +
823 + /* PHY IOT */
824 + /* select global register */
825 + rt305x_mii_write(esw, 0, 31, 0x0);
826 + /* tune TP_IDL tail and head waveform */
827 + rt305x_mii_write(esw, 0, 22, 0x052f);
828 + /* set TX10 signal amplitude threshold to minimum */
829 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
830 + /* set squelch amplitude to higher threshold */
831 + rt305x_mii_write(esw, 0, 18, 0x40ba);
832 + /* longer TP_IDL tail length */
833 + rt305x_mii_write(esw, 0, 14, 0x65);
834 + /* select local register */
835 + rt305x_mii_write(esw, 0, 31, 0x8000);
836 + }
837 +
838 + if (esw->port_map)
839 + port_map = esw->port_map;
840 + else
841 + port_map = RT305X_ESW_PMAP_LLLLLL;
842 +
843 + /*
844 + * Unused HW feature, but still nice to be consistent here...
845 + * This is also exported to userspace ('lan' attribute) so it's
846 + * conveniently usable to decide which ports go into the wan vlan by
847 + * default.
848 + */
849 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
850 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
851 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
852 +
853 + /* make the switch leds blink */
854 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
855 + esw->ports[i].led = 0x05;
856 +
857 + /* Apply the empty config. */
858 + esw_apply_config(&esw->swdev);
859 +
860 + /* Only unmask the port change interrupt */
861 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
862 +}
863 +
864 +static irqreturn_t esw_interrupt(int irq, void *_esw)
865 +{
866 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
867 + u32 status;
868 +
869 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
870 + if (status & RT305X_ESW_PORT_ST_CHG) {
871 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
872 + link >>= RT305X_ESW_POA_LINK_SHIFT;
873 + link &= RT305X_ESW_POA_LINK_MASK;
874 + dev_info(esw->dev, "link changed 0x%02X\n", link);
875 + }
876 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
877 +
878 + return IRQ_HANDLED;
879 +}
880 +
881 +static int esw_apply_config(struct switch_dev *dev)
882 +{
883 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
884 + int i;
885 + u8 disable = 0;
886 + u8 doubletag = 0;
887 + u8 en_vlan = 0;
888 + u8 untag = 0;
889 +
890 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
891 + u32 vid, vmsc;
892 + if (esw->global_vlan_enable) {
893 + vid = esw->vlans[i].vid;
894 + vmsc = esw->vlans[i].ports;
895 + } else {
896 + vid = RT305X_ESW_VLAN_NONE;
897 + vmsc = RT305X_ESW_PORTS_NONE;
898 + }
899 + esw_set_vlan_id(esw, i, vid);
900 + esw_set_vmsc(esw, i, vmsc);
901 + }
902 +
903 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
904 + u32 pvid;
905 + disable |= esw->ports[i].disable << i;
906 + if (esw->global_vlan_enable) {
907 + doubletag |= esw->ports[i].doubletag << i;
908 + en_vlan |= 1 << i;
909 + untag |= esw->ports[i].untag << i;
910 + pvid = esw->ports[i].pvid;
911 + } else {
912 + int x = esw->alt_vlan_disable ? 0 : 1;
913 + doubletag |= x << i;
914 + en_vlan |= x << i;
915 + untag |= x << i;
916 + pvid = 0;
917 + }
918 + esw_set_pvid(esw, i, pvid);
919 + if (i < RT305X_ESW_NUM_LEDS)
920 + esw_w32(esw, esw->ports[i].led,
921 + RT305X_ESW_REG_P0LED + 4*i);
922 + }
923 +
924 + esw_set_gsc(esw);
925 + esw_set_port_disable(esw, disable);
926 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
927 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
928 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
929 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
930 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
931 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
932 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
933 + esw_rmw(esw, RT305X_ESW_REG_POC2,
934 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
935 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
936 +
937 + if (!esw->global_vlan_enable) {
938 + /*
939 + * Still need to put all ports into vlan 0 or they'll be
940 + * isolated.
941 + * NOTE: vlan 0 is special, no vlan tag is prepended
942 + */
943 + esw_set_vlan_id(esw, 0, 0);
944 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
945 + }
946 +
947 + return 0;
948 +}
949 +
950 +static int esw_reset_switch(struct switch_dev *dev)
951 +{
952 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
953 +
954 + esw->global_vlan_enable = 0;
955 + memset(esw->ports, 0, sizeof(esw->ports));
956 + memset(esw->vlans, 0, sizeof(esw->vlans));
957 + esw_hw_init(esw);
958 +
959 + return 0;
960 +}
961 +
962 +static int esw_get_vlan_enable(struct switch_dev *dev,
963 + const struct switch_attr *attr,
964 + struct switch_val *val)
965 +{
966 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
967 +
968 + val->value.i = esw->global_vlan_enable;
969 +
970 + return 0;
971 +}
972 +
973 +static int esw_set_vlan_enable(struct switch_dev *dev,
974 + const struct switch_attr *attr,
975 + struct switch_val *val)
976 +{
977 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
978 +
979 + esw->global_vlan_enable = val->value.i != 0;
980 +
981 + return 0;
982 +}
983 +
984 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
985 + const struct switch_attr *attr,
986 + struct switch_val *val)
987 +{
988 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
989 +
990 + val->value.i = esw->alt_vlan_disable;
991 +
992 + return 0;
993 +}
994 +
995 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
996 + const struct switch_attr *attr,
997 + struct switch_val *val)
998 +{
999 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1000 +
1001 + esw->alt_vlan_disable = val->value.i != 0;
1002 +
1003 + return 0;
1004 +}
1005 +
1006 +static int
1007 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1008 + const struct switch_attr *attr,
1009 + struct switch_val *val)
1010 +{
1011 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1012 +
1013 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1014 +
1015 + return 0;
1016 +}
1017 +
1018 +static int
1019 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1020 + const struct switch_attr *attr,
1021 + struct switch_val *val)
1022 +{
1023 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1024 +
1025 + val->value.i = esw->bc_storm_protect;
1026 +
1027 + return 0;
1028 +}
1029 +
1030 +static int
1031 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1032 + const struct switch_attr *attr,
1033 + struct switch_val *val)
1034 +{
1035 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1036 +
1037 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1038 +
1039 + return 0;
1040 +}
1041 +
1042 +static int
1043 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1044 + const struct switch_attr *attr,
1045 + struct switch_val *val)
1046 +{
1047 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1048 +
1049 + val->value.i = esw->led_frequency;
1050 +
1051 + return 0;
1052 +}
1053 +
1054 +static int esw_get_port_link(struct switch_dev *dev,
1055 + int port,
1056 + struct switch_port_link *link)
1057 +{
1058 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1059 + u32 speed, poa;
1060 +
1061 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1062 + return -EINVAL;
1063 +
1064 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1065 +
1066 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1067 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1068 + if (port < RT305X_ESW_NUM_LEDS) {
1069 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1070 + } else {
1071 + if (port == RT305X_ESW_NUM_PORTS - 1)
1072 + poa >>= 1;
1073 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1074 + }
1075 + switch (speed) {
1076 + case 0:
1077 + link->speed = SWITCH_PORT_SPEED_10;
1078 + break;
1079 + case 1:
1080 + link->speed = SWITCH_PORT_SPEED_100;
1081 + break;
1082 + case 2:
1083 + case 3: /* forced gige speed can be 2 or 3 */
1084 + link->speed = SWITCH_PORT_SPEED_1000;
1085 + break;
1086 + default:
1087 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1088 + break;
1089 + }
1090 +
1091 + return 0;
1092 +}
1093 +
1094 +static int esw_get_port_bool(struct switch_dev *dev,
1095 + const struct switch_attr *attr,
1096 + struct switch_val *val)
1097 +{
1098 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1099 + int idx = val->port_vlan;
1100 + u32 x, reg, shift;
1101 +
1102 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1103 + return -EINVAL;
1104 +
1105 + switch (attr->id) {
1106 + case RT305X_ESW_ATTR_PORT_DISABLE:
1107 + reg = RT305X_ESW_REG_POC0;
1108 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1109 + break;
1110 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1111 + reg = RT305X_ESW_REG_SGC2;
1112 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1113 + break;
1114 + case RT305X_ESW_ATTR_PORT_UNTAG:
1115 + reg = RT305X_ESW_REG_POC2;
1116 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1117 + break;
1118 + case RT305X_ESW_ATTR_PORT_LAN:
1119 + reg = RT305X_ESW_REG_SGC2;
1120 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1121 + if (idx >= RT305X_ESW_NUM_LANWAN)
1122 + return -EINVAL;
1123 + break;
1124 + default:
1125 + return -EINVAL;
1126 + }
1127 +
1128 + x = esw_r32(esw, reg);
1129 + val->value.i = (x >> (idx + shift)) & 1;
1130 +
1131 + return 0;
1132 +}
1133 +
1134 +static int esw_set_port_bool(struct switch_dev *dev,
1135 + const struct switch_attr *attr,
1136 + struct switch_val *val)
1137 +{
1138 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1139 + int idx = val->port_vlan;
1140 +
1141 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1142 + val->value.i < 0 || val->value.i > 1)
1143 + return -EINVAL;
1144 +
1145 + switch (attr->id) {
1146 + case RT305X_ESW_ATTR_PORT_DISABLE:
1147 + esw->ports[idx].disable = val->value.i;
1148 + break;
1149 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1150 + esw->ports[idx].doubletag = val->value.i;
1151 + break;
1152 + case RT305X_ESW_ATTR_PORT_UNTAG:
1153 + esw->ports[idx].untag = val->value.i;
1154 + break;
1155 + default:
1156 + return -EINVAL;
1157 + }
1158 +
1159 + return 0;
1160 +}
1161 +
1162 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1163 + const struct switch_attr *attr,
1164 + struct switch_val *val)
1165 +{
1166 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1167 + int idx = val->port_vlan;
1168 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1169 + u32 reg;
1170 +
1171 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1172 + return -EINVAL;
1173 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1174 + val->value.i = (reg >> shift) & 0xffff;
1175 +
1176 + return 0;
1177 +}
1178 +
1179 +static int
1180 +esw_get_port_tr_badgood(struct switch_dev *dev,
1181 + const struct switch_attr *attr,
1182 + struct switch_val *val)
1183 +{
1184 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1185 +
1186 + int idx = val->port_vlan;
1187 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1188 + u32 reg;
1189 +
1190 + if (!soc_is_rt5350())
1191 + return -EINVAL;
1192 +
1193 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1194 + return -EINVAL;
1195 +
1196 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1197 + val->value.i = (reg >> shift) & 0xffff;
1198 +
1199 + return 0;
1200 +}
1201 +
1202 +static int esw_get_port_led(struct switch_dev *dev,
1203 + const struct switch_attr *attr,
1204 + struct switch_val *val)
1205 +{
1206 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1207 + int idx = val->port_vlan;
1208 +
1209 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1210 + idx >= RT305X_ESW_NUM_LEDS)
1211 + return -EINVAL;
1212 +
1213 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1214 +
1215 + return 0;
1216 +}
1217 +
1218 +static int esw_set_port_led(struct switch_dev *dev,
1219 + const struct switch_attr *attr,
1220 + struct switch_val *val)
1221 +{
1222 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1223 + int idx = val->port_vlan;
1224 +
1225 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1226 + return -EINVAL;
1227 +
1228 + esw->ports[idx].led = val->value.i;
1229 +
1230 + return 0;
1231 +}
1232 +
1233 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1234 +{
1235 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1236 +
1237 + if (port >= RT305X_ESW_NUM_PORTS)
1238 + return -EINVAL;
1239 +
1240 + *val = esw_get_pvid(esw, port);
1241 +
1242 + return 0;
1243 +}
1244 +
1245 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1246 +{
1247 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1248 +
1249 + if (port >= RT305X_ESW_NUM_PORTS)
1250 + return -EINVAL;
1251 +
1252 + esw->ports[port].pvid = val;
1253 +
1254 + return 0;
1255 +}
1256 +
1257 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1258 +{
1259 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1260 + u32 vmsc, poc2;
1261 + int vlan_idx = -1;
1262 + int i;
1263 +
1264 + val->len = 0;
1265 +
1266 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1267 + return -EINVAL;
1268 +
1269 + /* valid vlan? */
1270 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1271 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1272 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1273 + vlan_idx = i;
1274 + break;
1275 + }
1276 + }
1277 +
1278 + if (vlan_idx == -1)
1279 + return -EINVAL;
1280 +
1281 + vmsc = esw_get_vmsc(esw, vlan_idx);
1282 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1283 +
1284 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1285 + struct switch_port *p;
1286 + int port_mask = 1 << i;
1287 +
1288 + if (!(vmsc & port_mask))
1289 + continue;
1290 +
1291 + p = &val->value.ports[val->len++];
1292 + p->id = i;
1293 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1294 + p->flags = 0;
1295 + else
1296 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1297 + }
1298 +
1299 + return 0;
1300 +}
1301 +
1302 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1303 +{
1304 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1305 + int ports;
1306 + int vlan_idx = -1;
1307 + int i;
1308 +
1309 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1310 + val->len > RT305X_ESW_NUM_PORTS)
1311 + return -EINVAL;
1312 +
1313 + /* one of the already defined vlans? */
1314 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1315 + if (esw->vlans[i].vid == val->port_vlan &&
1316 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1317 + vlan_idx = i;
1318 + break;
1319 + }
1320 + }
1321 +
1322 + /* select a free slot */
1323 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1324 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1325 + vlan_idx = i;
1326 + }
1327 +
1328 + /* bail if all slots are in use */
1329 + if (vlan_idx == -1)
1330 + return -EINVAL;
1331 +
1332 + ports = RT305X_ESW_PORTS_NONE;
1333 + for (i = 0; i < val->len; i++) {
1334 + struct switch_port *p = &val->value.ports[i];
1335 + int port_mask = 1 << p->id;
1336 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1337 +
1338 + if (p->id >= RT305X_ESW_NUM_PORTS)
1339 + return -EINVAL;
1340 +
1341 + ports |= port_mask;
1342 + esw->ports[p->id].untag = untagged;
1343 + }
1344 + esw->vlans[vlan_idx].ports = ports;
1345 + if (ports == RT305X_ESW_PORTS_NONE)
1346 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1347 + else
1348 + esw->vlans[vlan_idx].vid = val->port_vlan;
1349 +
1350 + return 0;
1351 +}
1352 +
1353 +static const struct switch_attr esw_global[] = {
1354 + {
1355 + .type = SWITCH_TYPE_INT,
1356 + .name = "enable_vlan",
1357 + .description = "VLAN mode (1:enabled)",
1358 + .max = 1,
1359 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1360 + .get = esw_get_vlan_enable,
1361 + .set = esw_set_vlan_enable,
1362 + },
1363 + {
1364 + .type = SWITCH_TYPE_INT,
1365 + .name = "alternate_vlan_disable",
1366 + .description = "Use en_vlan instead of doubletag to disable"
1367 + " VLAN mode",
1368 + .max = 1,
1369 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1370 + .get = esw_get_alt_vlan_disable,
1371 + .set = esw_set_alt_vlan_disable,
1372 + },
1373 + {
1374 + .type = SWITCH_TYPE_INT,
1375 + .name = "bc_storm_protect",
1376 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1377 + .max = 3,
1378 + .id = RT305X_ESW_ATTR_BC_STATUS,
1379 + .get = rt305x_esw_get_bc_status,
1380 + .set = rt305x_esw_set_bc_status,
1381 + },
1382 + {
1383 + .type = SWITCH_TYPE_INT,
1384 + .name = "led_frequency",
1385 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1386 + .max = 3,
1387 + .id = RT305X_ESW_ATTR_LED_FREQ,
1388 + .get = rt305x_esw_get_led_freq,
1389 + .set = rt305x_esw_set_led_freq,
1390 + }
1391 +};
1392 +
1393 +static const struct switch_attr esw_port[] = {
1394 + {
1395 + .type = SWITCH_TYPE_INT,
1396 + .name = "disable",
1397 + .description = "Port state (1:disabled)",
1398 + .max = 1,
1399 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1400 + .get = esw_get_port_bool,
1401 + .set = esw_set_port_bool,
1402 + },
1403 + {
1404 + .type = SWITCH_TYPE_INT,
1405 + .name = "doubletag",
1406 + .description = "Double tagging for incoming vlan packets "
1407 + "(1:enabled)",
1408 + .max = 1,
1409 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1410 + .get = esw_get_port_bool,
1411 + .set = esw_set_port_bool,
1412 + },
1413 + {
1414 + .type = SWITCH_TYPE_INT,
1415 + .name = "untag",
1416 + .description = "Untag (1:strip outgoing vlan tag)",
1417 + .max = 1,
1418 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1419 + .get = esw_get_port_bool,
1420 + .set = esw_set_port_bool,
1421 + },
1422 + {
1423 + .type = SWITCH_TYPE_INT,
1424 + .name = "led",
1425 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1426 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1427 + " 8:100mact, 10:blink, 11:off, 12:on)",
1428 + .max = 15,
1429 + .id = RT305X_ESW_ATTR_PORT_LED,
1430 + .get = esw_get_port_led,
1431 + .set = esw_set_port_led,
1432 + },
1433 + {
1434 + .type = SWITCH_TYPE_INT,
1435 + .name = "lan",
1436 + .description = "HW port group (0:wan, 1:lan)",
1437 + .max = 1,
1438 + .id = RT305X_ESW_ATTR_PORT_LAN,
1439 + .get = esw_get_port_bool,
1440 + },
1441 + {
1442 + .type = SWITCH_TYPE_INT,
1443 + .name = "recv_bad",
1444 + .description = "Receive bad packet counter",
1445 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1446 + .get = esw_get_port_recv_badgood,
1447 + },
1448 + {
1449 + .type = SWITCH_TYPE_INT,
1450 + .name = "recv_good",
1451 + .description = "Receive good packet counter",
1452 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1453 + .get = esw_get_port_recv_badgood,
1454 + },
1455 + {
1456 + .type = SWITCH_TYPE_INT,
1457 + .name = "tr_bad",
1458 +
1459 + .description = "Transmit bad packet counter. rt5350 only",
1460 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1461 + .get = esw_get_port_tr_badgood,
1462 + },
1463 + {
1464 + .type = SWITCH_TYPE_INT,
1465 + .name = "tr_good",
1466 +
1467 + .description = "Transmit good packet counter. rt5350 only",
1468 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1469 + .get = esw_get_port_tr_badgood,
1470 + },
1471 +};
1472 +
1473 +static const struct switch_attr esw_vlan[] = {
1474 +};
1475 +
1476 +static const struct switch_dev_ops esw_ops = {
1477 + .attr_global = {
1478 + .attr = esw_global,
1479 + .n_attr = ARRAY_SIZE(esw_global),
1480 + },
1481 + .attr_port = {
1482 + .attr = esw_port,
1483 + .n_attr = ARRAY_SIZE(esw_port),
1484 + },
1485 + .attr_vlan = {
1486 + .attr = esw_vlan,
1487 + .n_attr = ARRAY_SIZE(esw_vlan),
1488 + },
1489 + .get_vlan_ports = esw_get_vlan_ports,
1490 + .set_vlan_ports = esw_set_vlan_ports,
1491 + .get_port_pvid = esw_get_port_pvid,
1492 + .set_port_pvid = esw_set_port_pvid,
1493 + .get_port_link = esw_get_port_link,
1494 + .apply_config = esw_apply_config,
1495 + .reset_switch = esw_reset_switch,
1496 +};
1497 +
1498 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1499 + /* All ports are LAN ports. */
1500 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1501 + .reg_initval_fct2 = 0x00d6500c,
1502 + /*
1503 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1504 + * turbo mii off, rgmi 3.3v off
1505 + * port5: disabled
1506 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1507 + */
1508 + .reg_initval_fpa2 = 0x3f502b28,
1509 +};
1510 +
1511 +static const struct of_device_id ralink_esw_match[] = {
1512 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1513 + {},
1514 +};
1515 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1516 +
1517 +static int esw_probe(struct platform_device *pdev)
1518 +{
1519 + struct device_node *np = pdev->dev.of_node;
1520 + const struct rt305x_esw_platform_data *pdata;
1521 + const __be32 *port_map, *reg_init;
1522 + struct rt305x_esw *esw;
1523 + struct switch_dev *swdev;
1524 + struct resource *res, *irq;
1525 + int err;
1526 +
1527 + pdata = pdev->dev.platform_data;
1528 + if (!pdata) {
1529 + const struct of_device_id *match;
1530 + match = of_match_device(ralink_esw_match, &pdev->dev);
1531 + if (match)
1532 + pdata = (struct rt305x_esw_platform_data *) match->data;
1533 + }
1534 + if (!pdata)
1535 + return -EINVAL;
1536 +
1537 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1538 + if (!res) {
1539 + dev_err(&pdev->dev, "no memory resource found\n");
1540 + return -ENOMEM;
1541 + }
1542 +
1543 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1544 + if (!irq) {
1545 + dev_err(&pdev->dev, "no irq resource found\n");
1546 + return -ENOMEM;
1547 + }
1548 +
1549 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1550 + if (!esw) {
1551 + dev_err(&pdev->dev, "no memory for private data\n");
1552 + return -ENOMEM;
1553 + }
1554 +
1555 + esw->dev = &pdev->dev;
1556 + esw->irq = irq->start;
1557 + esw->base = ioremap(res->start, resource_size(res));
1558 + if (!esw->base) {
1559 + dev_err(&pdev->dev, "ioremap failed\n");
1560 + err = -ENOMEM;
1561 + goto free_esw;
1562 + }
1563 +
1564 + port_map = of_get_property(np, "ralink,portmap", NULL);
1565 + if (port_map)
1566 + esw->port_map = be32_to_cpu(*port_map);
1567 +
1568 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1569 + if (reg_init)
1570 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1571 +
1572 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1573 + if (reg_init)
1574 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1575 +
1576 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1577 + if (reg_init)
1578 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1579 +
1580 + swdev = &esw->swdev;
1581 + swdev->of_node = pdev->dev.of_node;
1582 + swdev->name = "rt305x-esw";
1583 + swdev->alias = "rt305x";
1584 + swdev->cpu_port = RT305X_ESW_PORT6;
1585 + swdev->ports = RT305X_ESW_NUM_PORTS;
1586 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1587 + swdev->ops = &esw_ops;
1588 +
1589 + err = register_switch(swdev, NULL);
1590 + if (err < 0) {
1591 + dev_err(&pdev->dev, "register_switch failed\n");
1592 + goto unmap_base;
1593 + }
1594 +
1595 + platform_set_drvdata(pdev, esw);
1596 +
1597 + esw->pdata = pdata;
1598 + spin_lock_init(&esw->reg_rw_lock);
1599 +
1600 + esw_hw_init(esw);
1601 +
1602 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1603 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1604 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1605 +
1606 + return 0;
1607 +
1608 +unmap_base:
1609 + iounmap(esw->base);
1610 +free_esw:
1611 + kfree(esw);
1612 + return err;
1613 +}
1614 +
1615 +static int esw_remove(struct platform_device *pdev)
1616 +{
1617 + struct rt305x_esw *esw;
1618 +
1619 + esw = platform_get_drvdata(pdev);
1620 + if (esw) {
1621 + unregister_switch(&esw->swdev);
1622 + platform_set_drvdata(pdev, NULL);
1623 + iounmap(esw->base);
1624 + kfree(esw);
1625 + }
1626 +
1627 + return 0;
1628 +}
1629 +
1630 +static struct platform_driver esw_driver = {
1631 + .probe = esw_probe,
1632 + .remove = esw_remove,
1633 + .driver = {
1634 + .name = "rt305x-esw",
1635 + .owner = THIS_MODULE,
1636 + .of_match_table = ralink_esw_match,
1637 + },
1638 +};
1639 +
1640 +int __init rtesw_init(void)
1641 +{
1642 + return platform_driver_register(&esw_driver);
1643 +}
1644 +
1645 +void rtesw_exit(void)
1646 +{
1647 + platform_driver_unregister(&esw_driver);
1648 +}
1649 diff --git a/drivers/net/ethernet/ralink/esw_rt3052.h b/drivers/net/ethernet/ralink/esw_rt3052.h
1650 new file mode 100644
1651 index 0000000..2ced3dff
1652 --- /dev/null
1653 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1654 @@ -0,0 +1,32 @@
1655 +/*
1656 + * This program is free software; you can redistribute it and/or modify
1657 + * it under the terms of the GNU General Public License as published by
1658 + * the Free Software Foundation; version 2 of the License
1659 + *
1660 + * This program is distributed in the hope that it will be useful,
1661 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1662 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1663 + * GNU General Public License for more details.
1664 + *
1665 + * You should have received a copy of the GNU General Public License
1666 + * along with this program; if not, write to the Free Software
1667 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1668 + *
1669 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1670 + */
1671 +
1672 +#ifndef _RALINK_ESW_RT3052_H__
1673 +#define _RALINK_ESW_RT3052_H__
1674 +
1675 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1676 +
1677 +int __init rtesw_init(void);
1678 +void rtesw_exit(void);
1679 +
1680 +#else
1681 +
1682 +static inline int __init rtesw_init(void) { return 0; }
1683 +static inline void rtesw_exit(void) { }
1684 +
1685 +#endif
1686 +#endif
1687 diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.c b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1688 new file mode 100644
1689 index 0000000..9fa6a54
1690 --- /dev/null
1691 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1692 @@ -0,0 +1,1027 @@
1693 +/*
1694 + * This program is free software; you can redistribute it and/or modify
1695 + * it under the terms of the GNU General Public License as published by
1696 + * the Free Software Foundation; version 2 of the License
1697 + *
1698 + * This program is distributed in the hope that it will be useful,
1699 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1700 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1701 + * GNU General Public License for more details.
1702 + *
1703 + * You should have received a copy of the GNU General Public License
1704 + * along with this program; if not, write to the Free Software
1705 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1706 + *
1707 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1708 + */
1709 +
1710 +#include <linux/module.h>
1711 +#include <linux/kernel.h>
1712 +#include <linux/types.h>
1713 +#include <linux/dma-mapping.h>
1714 +#include <linux/init.h>
1715 +#include <linux/skbuff.h>
1716 +#include <linux/etherdevice.h>
1717 +#include <linux/ethtool.h>
1718 +#include <linux/platform_device.h>
1719 +#include <linux/of_device.h>
1720 +#include <linux/clk.h>
1721 +#include <linux/of_net.h>
1722 +#include <linux/of_mdio.h>
1723 +#include <linux/of_irq.h>
1724 +#include <linux/of_address.h>
1725 +#include <linux/switch.h>
1726 +
1727 +#include <asm/mach-ralink/ralink_regs.h>
1728 +
1729 +#include "ralink_soc_eth.h"
1730 +
1731 +#include <linux/ioport.h>
1732 +#include <linux/switch.h>
1733 +#include <linux/mii.h>
1734 +
1735 +#include <ralink_regs.h>
1736 +#include <asm/mach-ralink/mt7620.h>
1737 +
1738 +#include "ralink_soc_eth.h"
1739 +#include "gsw_mt7620a.h"
1740 +#include "mdio.h"
1741 +
1742 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1743 +
1744 +#define MT7620A_GSW_REG_PIAC 0x7004
1745 +
1746 +#define GSW_NUM_VLANS 16
1747 +#define GSW_NUM_VIDS 4096
1748 +#define GSW_NUM_PORTS 7
1749 +#define GSW_PORT6 6
1750 +
1751 +#define GSW_MDIO_ACCESS BIT(31)
1752 +#define GSW_MDIO_READ BIT(19)
1753 +#define GSW_MDIO_WRITE BIT(18)
1754 +#define GSW_MDIO_START BIT(16)
1755 +#define GSW_MDIO_ADDR_SHIFT 20
1756 +#define GSW_MDIO_REG_SHIFT 25
1757 +
1758 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1759 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1760 +#define GSW_REG_SMACCR0 0x3fE4
1761 +#define GSW_REG_SMACCR1 0x3fE8
1762 +#define GSW_REG_CKGCR 0x3ff0
1763 +
1764 +#define GSW_REG_IMR 0x7008
1765 +#define GSW_REG_ISR 0x700c
1766 +
1767 +#define SYSC_REG_CFG1 0x14
1768 +
1769 +#define PORT_IRQ_ST_CHG 0x7f
1770 +
1771 +#define GSW_VLAN_VTCR 0x90
1772 +#define GSW_VLAN_VTCR_VID_M 0xfff
1773 +#define GSW_VLAN_ID(_x) (0x100 + (4 * (_x)))
1774 +#define GSW_VLAN_ID_VID_S 12
1775 +#define GSW_VLAN_ID_VID_M 0xfff
1776 +
1777 +#define GSW_VAWD1 0x94
1778 +#define GSW_VAWD1_VTAG_EN BIT(28)
1779 +#define GSW_VAWD1_PORTM_S 16
1780 +#define GSW_VAWD1_PORTM_M 0xff
1781 +
1782 +#define GSW_VAWD2 0x98
1783 +#define GSW_VAWD2_PORTT_S 16
1784 +#define GSW_VAWD2_PORTT_M 0xff
1785 +
1786 +#define GSW_VTIM(_x) (0x100 + (4 * (_x)))
1787 +#define GSW_VTIM_M 0xfff
1788 +#define GSW_VTIM_S 12
1789 +
1790 +#define GSW_REG_PCR(x) (0x2004 + (x * 0x100))
1791 +#define GSW_REG_PCR_EG_TAG_S 28
1792 +#define GSW_REG_PCR_EG_TAG_M 0x3
1793 +
1794 +#define SYSCFG1 0x14
1795 +
1796 +#define ESW_PHY_POLLING 0x7000
1797 +
1798 +#define PMCR_IPG BIT(18)
1799 +#define PMCR_MAC_MODE BIT(16)
1800 +#define PMCR_FORCE BIT(15)
1801 +#define PMCR_TX_EN BIT(14)
1802 +#define PMCR_RX_EN BIT(13)
1803 +#define PMCR_BACKOFF BIT(9)
1804 +#define PMCR_BACKPRES BIT(8)
1805 +#define PMCR_RX_FC BIT(5)
1806 +#define PMCR_TX_FC BIT(4)
1807 +#define PMCR_SPEED(_x) (_x << 2)
1808 +#define PMCR_DUPLEX BIT(1)
1809 +#define PMCR_LINK BIT(0)
1810 +
1811 +#define PHY_AN_EN BIT(31)
1812 +#define PHY_PRE_EN BIT(30)
1813 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1814 +
1815 +enum {
1816 + /* Global attributes. */
1817 + GSW_ATTR_ENABLE_VLAN,
1818 + /* Port attributes. */
1819 + GSW_ATTR_PORT_UNTAG,
1820 +};
1821 +
1822 +enum {
1823 + PORT4_EPHY = 0,
1824 + PORT4_EXT,
1825 +};
1826 +
1827 +struct gsw_port {
1828 + bool disable;
1829 + bool untag;
1830 + u16 pvid;
1831 +};
1832 +
1833 +struct gsw_vlan {
1834 + u8 ports;
1835 + u16 vid;
1836 +};
1837 +
1838 +struct mt7620_gsw {
1839 + struct device *dev;
1840 + void __iomem *base;
1841 + int irq;
1842 +
1843 + struct switch_dev swdev;
1844 + bool global_vlan_enable;
1845 + struct gsw_vlan vlans[GSW_NUM_VLANS];
1846 + struct gsw_port ports[GSW_NUM_PORTS];
1847 + long unsigned int autopoll;
1848 + int port4;
1849 +};
1850 +
1851 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1852 +{
1853 + iowrite32(val, gsw->base + reg);
1854 +}
1855 +
1856 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1857 +{
1858 + return ioread32(gsw->base + reg);
1859 +}
1860 +
1861 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1862 +{
1863 + unsigned long t_start = jiffies;
1864 +
1865 + while (1) {
1866 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1867 + return 0;
1868 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1869 + break;
1870 + }
1871 + }
1872 +
1873 + printk(KERN_ERR "mdio: MDIO timeout\n");
1874 + return -1;
1875 +}
1876 +
1877 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1878 + u32 write_data)
1879 +{
1880 + if (mt7620_mii_busy_wait(gsw))
1881 + return -1;
1882 +
1883 + write_data &= 0xffff;
1884 +
1885 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1886 + (phy_register << GSW_MDIO_REG_SHIFT) |
1887 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1888 + MT7620A_GSW_REG_PIAC);
1889 +
1890 + if (mt7620_mii_busy_wait(gsw))
1891 + return -1;
1892 +
1893 + return 0;
1894 +}
1895 +
1896 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1897 +{
1898 + struct fe_priv *priv = bus->priv;
1899 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1900 +
1901 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1902 +}
1903 +
1904 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1905 +{
1906 + struct fe_priv *priv = bus->priv;
1907 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1908 + u32 d;
1909 +
1910 + if (mt7620_mii_busy_wait(gsw))
1911 + return 0xffff;
1912 +
1913 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1914 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1915 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1916 + MT7620A_GSW_REG_PIAC);
1917 +
1918 + if (mt7620_mii_busy_wait(gsw))
1919 + return 0xffff;
1920 +
1921 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1922 +
1923 + return d;
1924 +}
1925 +
1926 +static unsigned char *fe_speed_str(int speed)
1927 +{
1928 + switch (speed) {
1929 + case 2:
1930 + case SPEED_1000:
1931 + return "1000";
1932 + case 1:
1933 + case SPEED_100:
1934 + return "100";
1935 + case 0:
1936 + case SPEED_10:
1937 + return "10";
1938 + }
1939 +
1940 + return "? ";
1941 +}
1942 +
1943 +int mt7620a_has_carrier(struct fe_priv *priv)
1944 +{
1945 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1946 + int i;
1947 +
1948 + for (i = 0; i < GSW_PORT6; i++)
1949 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1950 + return 1;
1951 + return 0;
1952 +}
1953 +
1954 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1955 +{
1956 + if (!priv->phy)
1957 + return;
1958 +
1959 + if (mt7620a_has_carrier(priv))
1960 + netif_carrier_on(priv->netdev);
1961 + else
1962 + netif_carrier_off(priv->netdev);
1963 +}
1964 +
1965 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1966 +{
1967 + if (priv->link[port])
1968 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1969 + port, fe_speed_str(priv->phy->speed[port]),
1970 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1971 + else
1972 + netdev_info(priv->netdev, "port %d link down\n", port);
1973 + mt7620a_handle_carrier(priv);
1974 +}
1975 +
1976 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1977 +{
1978 + struct fe_priv *priv = (struct fe_priv *) _priv;
1979 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1980 + u32 status;
1981 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1982 +
1983 + status = gsw_r32(gsw, GSW_REG_ISR);
1984 + if (status & PORT_IRQ_ST_CHG)
1985 + for (i = 0; i <= max; i++) {
1986 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1987 + int link = status & 0x1;
1988 +
1989 + if (link != priv->link[i]) {
1990 + if (link)
1991 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1992 + i, fe_speed_str((status >> 2) & 3),
1993 + (status & 0x2) ? "Full" : "Half");
1994 + else
1995 + netdev_info(priv->netdev, "port %d link down\n", i);
1996 + }
1997 +
1998 + priv->link[i] = link;
1999 + }
2000 + mt7620a_handle_carrier(priv);
2001 +
2002 + gsw_w32(gsw, status, GSW_REG_ISR);
2003 +
2004 + return IRQ_HANDLED;
2005 +}
2006 +
2007 +static int mt7620_is_bga(void)
2008 +{
2009 + u32 bga = rt_sysc_r32(0x0c);
2010 +
2011 + return (bga >> 16) & 1;
2012 +}
2013 +
2014 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
2015 +{
2016 + int phy;
2017 + int lsb = -1, msb = 0;
2018 +
2019 + for_each_set_bit(phy, &gsw->autopoll, 32) {
2020 + if (lsb < 0)
2021 + lsb = phy;
2022 + msb = phy;
2023 + }
2024 +
2025 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
2026 +}
2027 +
2028 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
2029 +{
2030 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2031 + const __be32 *_id = of_get_property(np, "reg", NULL);
2032 + int phy_mode, size, id;
2033 + int shift = 12;
2034 + u32 val, mask = 0;
2035 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2036 +
2037 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2038 + if (_id)
2039 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2040 + else
2041 + pr_err("%s: invalid port id\n", np->name);
2042 + return;
2043 + }
2044 +
2045 + id = be32_to_cpu(*_id);
2046 +
2047 + if (id == 4)
2048 + shift = 14;
2049 +
2050 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2051 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2052 + pr_err("%s: invalid fixed link property\n", np->name);
2053 + priv->phy->phy_fixed[id] = NULL;
2054 + return;
2055 + }
2056 +
2057 + phy_mode = of_get_phy_mode(np);
2058 + switch (phy_mode) {
2059 + case PHY_INTERFACE_MODE_RGMII:
2060 + mask = 0;
2061 + break;
2062 + case PHY_INTERFACE_MODE_MII:
2063 + mask = 1;
2064 + break;
2065 + case PHY_INTERFACE_MODE_RMII:
2066 + mask = 2;
2067 + break;
2068 + default:
2069 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]);
2070 + return;
2071 + }
2072 +
2073 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2074 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2075 + return;
2076 +
2077 + val = rt_sysc_r32(SYSCFG1);
2078 + val &= ~(3 << shift);
2079 + val |= mask << shift;
2080 + rt_sysc_w32(val, SYSCFG1);
2081 +
2082 + if (priv->phy->phy_fixed[id]) {
2083 + const __be32 *link = priv->phy->phy_fixed[id];
2084 + int tx_fc = be32_to_cpup(link++);
2085 + int rx_fc = be32_to_cpup(link++);
2086 + u32 val = 0;
2087 +
2088 + priv->phy->speed[id] = be32_to_cpup(link++);
2089 + priv->phy->duplex[id] = be32_to_cpup(link++);
2090 + priv->link[id] = 1;
2091 +
2092 + switch (priv->phy->speed[id]) {
2093 + case SPEED_10:
2094 + val = 0;
2095 + break;
2096 + case SPEED_100:
2097 + val = 1;
2098 + break;
2099 + case SPEED_1000:
2100 + val = 2;
2101 + break;
2102 + default:
2103 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2104 + priv->phy->phy_fixed[id] = 0;
2105 + return;
2106 + }
2107 + val = PMCR_SPEED(val);
2108 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2109 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2110 + if (tx_fc)
2111 + val |= PMCR_TX_FC;
2112 + if (rx_fc)
2113 + val |= PMCR_RX_FC;
2114 + if (priv->phy->duplex[id])
2115 + val |= PMCR_DUPLEX;
2116 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2117 + dev_info(priv->device, "using fixed link parameters\n");
2118 + return;
2119 + }
2120 +
2121 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2122 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2123 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2124 +
2125 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2126 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2127 + gsw->autopoll |= BIT(id);
2128 + gsw_auto_poll(gsw);
2129 + return;
2130 + }
2131 +}
2132 +
2133 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2134 +{
2135 + u32 is_BGA = mt7620_is_bga();
2136 +
2137 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2138 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2139 +
2140 + /*correct PHY setting L3.0 BGA*/
2141 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2142 +
2143 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2144 + if (is_BGA)
2145 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2146 + else
2147 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2148 +
2149 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2150 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2151 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2152 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2153 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2154 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2155 +
2156 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2157 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2158 +
2159 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2160 + if (is_BGA) {
2161 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2162 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2163 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2164 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2165 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2166 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2167 + } else {
2168 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2169 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2170 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2171 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2172 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2173 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2174 + }
2175 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2176 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2177 +
2178 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2179 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2180 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2181 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2182 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2183 +
2184 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2185 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2186 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2187 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2188 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2189 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2190 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2191 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2192 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2193 +
2194 + /* CPU Port6 Force Link 1G, FC ON */
2195 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2196 + /* Set Port6 CPU Port */
2197 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2198 +
2199 +// GSW_VAWD2
2200 +
2201 + /* setup port 4 */
2202 + if (gsw->port4 == PORT4_EPHY) {
2203 + u32 val = rt_sysc_r32(SYSCFG1);
2204 + val |= 3 << 14;
2205 + rt_sysc_w32(val, SYSCFG1);
2206 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2207 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2208 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2209 + pr_info("gsw: setting port4 to ephy mode\n");
2210 + }
2211 +}
2212 +
2213 +static int gsw_reset_switch(struct switch_dev *dev)
2214 +{
2215 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2216 +
2217 + gsw->global_vlan_enable = 0;
2218 + memset(gsw->ports, 0, sizeof(gsw->ports));
2219 + memset(gsw->vlans, 0, sizeof(gsw->vlans));
2220 + gsw_hw_init(gsw);
2221 +
2222 + return 0;
2223 +}
2224 +
2225 +static int gsw_get_vlan_enable(struct switch_dev *dev,
2226 + const struct switch_attr *attr,
2227 + struct switch_val *val)
2228 +{
2229 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2230 +
2231 + val->value.i = gsw->global_vlan_enable;
2232 +
2233 + return 0;
2234 +}
2235 +
2236 +static int gsw_set_vlan_enable(struct switch_dev *dev,
2237 + const struct switch_attr *attr,
2238 + struct switch_val *val)
2239 +{
2240 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2241 +
2242 + gsw->global_vlan_enable = val->value.i != 0;
2243 +
2244 + return 0;
2245 +}
2246 +
2247 +static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port)
2248 +{
2249 + unsigned s, val;
2250 +
2251 + s = GSW_VTIM_S * (port % 2);
2252 + val = gsw_r32(gsw, GSW_VTIM(port / 2));
2253 +
2254 + return (val >> s) & GSW_VTIM_M;
2255 +}
2256 +
2257 +static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid)
2258 +{
2259 + unsigned s, val;
2260 +
2261 + s = GSW_VTIM_S * (port % 2);
2262 + val = gsw_r32(gsw, GSW_VTIM(port / 2));
2263 + val &= ~(GSW_VTIM_M << s);
2264 + val |= (pvid && GSW_VTIM_M) << s;
2265 + gsw_w32(gsw, val, GSW_VTIM(port / 2));
2266 +}
2267 +
2268 +static int gsw_get_port_bool(struct switch_dev *dev,
2269 + const struct switch_attr *attr,
2270 + struct switch_val *val)
2271 +{
2272 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2273 + int idx = val->port_vlan;
2274 +
2275 + if (idx < 0 || idx >= GSW_NUM_PORTS)
2276 + return -EINVAL;
2277 +
2278 + switch (attr->id) {
2279 + case GSW_ATTR_PORT_UNTAG:
2280 + return gsw->ports[idx].untag;
2281 + }
2282 +
2283 + return -EINVAL;
2284 +}
2285 +
2286 +static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val)
2287 +{
2288 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2289 +
2290 + if (port >= GSW_NUM_PORTS)
2291 + return -EINVAL;
2292 +
2293 + *val = gsw_get_pvid(gsw, port);
2294 +
2295 + return 0;
2296 +}
2297 +
2298 +static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val)
2299 +{
2300 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2301 +
2302 + if (port >= GSW_NUM_PORTS)
2303 + return -EINVAL;
2304 +
2305 + gsw->ports[port].pvid = val;
2306 +
2307 + return 0;
2308 +}
2309 +
2310 +static void gsw_set_vtcr(struct switch_dev *dev, u32 vid)
2311 +{
2312 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2313 + int retry = 1000;
2314 +
2315 + gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2316 + while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2317 + ;
2318 +}
2319 +
2320 +static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid)
2321 +{
2322 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2323 + int retry = 1000;
2324 +
2325 + gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2326 + while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2327 + ;
2328 +}
2329 +
2330 +static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan)
2331 +{
2332 + unsigned s;
2333 + unsigned val;
2334 +
2335 + s = GSW_VLAN_ID_VID_S * (vlan % 2);
2336 + val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2337 + val = (val >> s) & GSW_VLAN_ID_VID_M;
2338 +
2339 + return val;
2340 +}
2341 +
2342 +static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid)
2343 +{
2344 + unsigned s;
2345 + unsigned val;
2346 +
2347 + s = GSW_VLAN_ID_VID_S * (vlan % 2);
2348 + val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2349 + val &= ~(GSW_VLAN_ID_VID_M << s);
2350 + val |= (vid << s);
2351 + gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2));
2352 +}
2353 +
2354 +static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable)
2355 +{
2356 + unsigned val;
2357 +
2358 + val = gsw_r32(gsw, GSW_VAWD1);
2359 + if (enable)
2360 + val |= GSW_VAWD1_VTAG_EN;
2361 + else
2362 + val &= ~GSW_VAWD1_VTAG_EN;
2363 + gsw_w32(gsw, val, GSW_VAWD1);
2364 +}
2365 +
2366 +static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan)
2367 +{
2368 + unsigned val;
2369 +
2370 + gsw_set_vtcr(&gsw->swdev, vlan);
2371 +
2372 + val = gsw_r32(gsw, GSW_VAWD1);
2373 + val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M;
2374 +
2375 + return val;
2376 +}
2377 +
2378 +static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member)
2379 +{
2380 + unsigned val;
2381 +
2382 + val = gsw_r32(gsw, GSW_VAWD1);
2383 + val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S);
2384 + val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S;
2385 + gsw_w32(gsw, val, GSW_VAWD1);
2386 +}
2387 +
2388 +static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port)
2389 +{
2390 + unsigned val;
2391 +
2392 + val = gsw_r32(gsw, GSW_REG_PCR(port));
2393 + val >>= GSW_REG_PCR_EG_TAG_S;
2394 + val &= GSW_REG_PCR_EG_TAG_M;
2395 +
2396 + return !!val;
2397 +}
2398 +
2399 +static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag)
2400 +{
2401 + unsigned val;
2402 +
2403 + val = gsw_r32(gsw, GSW_REG_PCR(port));
2404 + if (!untag)
2405 + untag = 0x2;
2406 + else
2407 + untag = 0;
2408 + val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S);
2409 + val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S;
2410 + gsw_w32(gsw, val, GSW_REG_PCR(port));
2411 +}
2412 +
2413 +static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2414 +{
2415 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2416 + int vlan_idx = -1;
2417 + u32 member;
2418 + int i;
2419 +
2420 + val->len = 0;
2421 +
2422 + if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS)
2423 + return -EINVAL;
2424 +
2425 + /* valid vlan? */
2426 + for (i = 0; i < GSW_NUM_VLANS; i++) {
2427 + if (gsw_get_vlan_id(gsw, i) != val->port_vlan)
2428 + continue;
2429 + member = gsw_get_port_member(gsw, i);
2430 + vlan_idx = i;
2431 + break;
2432 + }
2433 +
2434 + if (vlan_idx == -1)
2435 + return -EINVAL;
2436 +
2437 + for (i = 0; i < GSW_NUM_PORTS; i++) {
2438 + struct switch_port *p;
2439 + int port_mask = 1 << i;
2440 +
2441 + if (!(member & port_mask))
2442 + continue;
2443 +
2444 + p = &val->value.ports[val->len++];
2445 + p->id = i;
2446 + if (gsw_get_port_tag(gsw, i))
2447 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
2448 + else
2449 + p->flags = 0;
2450 + }
2451 +
2452 + return 0;
2453 +}
2454 +
2455 +static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2456 +{
2457 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2458 + int ports;
2459 + int vlan_idx = -1;
2460 + int i;
2461 +
2462 + if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS ||
2463 + val->len > GSW_NUM_PORTS)
2464 + return -EINVAL;
2465 +
2466 + /* one of the already defined vlans? */
2467 + for (i = 0; i < GSW_NUM_VLANS; i++) {
2468 + if (gsw->vlans[i].vid == val->port_vlan &&
2469 + gsw->vlans[i].ports) {
2470 + vlan_idx = i;
2471 + break;
2472 + }
2473 + }
2474 +
2475 + /* select a free slot */
2476 + for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) {
2477 + if (!gsw->vlans[i].ports)
2478 + vlan_idx = i;
2479 + }
2480 +
2481 + /* bail if all slots are in use */
2482 + if (vlan_idx == -1)
2483 + return -EINVAL;
2484 +
2485 + ports = 0;
2486 + for (i = 0; i < val->len; i++) {
2487 + struct switch_port *p = &val->value.ports[i];
2488 + int port_mask = 1 << p->id;
2489 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
2490 +
2491 + if (p->id >= GSW_NUM_PORTS)
2492 + return -EINVAL;
2493 +
2494 + ports |= port_mask;
2495 + gsw->ports[p->id].untag = untagged;
2496 + }
2497 + gsw->vlans[vlan_idx].ports = ports;
2498 + if (!ports)
2499 + gsw->vlans[vlan_idx].vid = 0xfff;
2500 + else
2501 + gsw->vlans[vlan_idx].vid = val->port_vlan;
2502 +
2503 + return 0;
2504 +}
2505 +
2506 +static int gsw_apply_config(struct switch_dev *dev)
2507 +{
2508 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2509 + int i;
2510 +
2511 + for (i = 0; i < GSW_NUM_VLANS; i++) {
2512 + gsw_set_vtcr(&gsw->swdev, i);
2513 + if (gsw->global_vlan_enable) {
2514 + gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid);
2515 + gsw_set_port_member(gsw, i, gsw->vlans[i].ports);
2516 + gsw_vlan_tagging_enable(gsw, i, 1);
2517 + } else {
2518 + gsw_set_vlan_id(gsw, i, 0xfff);
2519 + gsw_set_port_member(gsw, i, 0);
2520 + gsw_vlan_tagging_enable(gsw, i, 0);
2521 + }
2522 + gsw_apply_vtcr(&gsw->swdev, i);
2523 + }
2524 +
2525 + for (i = 0; i < GSW_NUM_PORTS; i++) {
2526 + if (gsw->global_vlan_enable) {
2527 + gsw_set_port_untag(gsw, i, !gsw->ports[i].untag);
2528 + gsw_set_pvid(gsw, i, gsw->ports[i].pvid);
2529 + } else {
2530 + gsw_set_port_untag(gsw, i, 0);
2531 + gsw_set_pvid(gsw, i, 0);
2532 + }
2533 + }
2534 +
2535 + if (!gsw->global_vlan_enable)
2536 + gsw_set_vlan_id(gsw, 0, 0);
2537 +
2538 + return 0;
2539 +}
2540 +
2541 +static int gsw_get_port_link(struct switch_dev *dev,
2542 + int port,
2543 + struct switch_port_link *link)
2544 +{
2545 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2546 + u32 status;
2547 +
2548 + if (port < 0 || port >= GSW_NUM_PORTS)
2549 + return -EINVAL;
2550 +
2551 + status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port));
2552 + link->link = status & 0x1;
2553 + link->duplex = (status >> 1) & 1;
2554 +
2555 + switch ((status >> 2) & 0x3) {
2556 + case 0:
2557 + link->speed = SWITCH_PORT_SPEED_10;
2558 + break;
2559 + case 1:
2560 + link->speed = SWITCH_PORT_SPEED_100;
2561 + break;
2562 + case 2:
2563 + case 3: // forced gige speed can be 2 or 3
2564 + link->speed = SWITCH_PORT_SPEED_1000;
2565 + break;
2566 + }
2567 +
2568 + return 0;
2569 +}
2570 +
2571 +static int gsw_set_port_bool(struct switch_dev *dev,
2572 + const struct switch_attr *attr,
2573 + struct switch_val *val)
2574 +{
2575 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2576 + int idx = val->port_vlan;
2577 +
2578 + if (idx < 0 || idx >= GSW_NUM_PORTS ||
2579 + val->value.i < 0 || val->value.i > 1)
2580 + return -EINVAL;
2581 +
2582 + switch (attr->id) {
2583 + case GSW_ATTR_PORT_UNTAG:
2584 + gsw->ports[idx].untag = val->value.i;
2585 + break;
2586 + default:
2587 + return -EINVAL;
2588 + }
2589 +
2590 + return 0;
2591 +}
2592 +
2593 +static const struct switch_attr gsw_global[] = {
2594 + {
2595 + .type = SWITCH_TYPE_INT,
2596 + .name = "enable_vlan",
2597 + .description = "VLAN mode (1:enabled)",
2598 + .max = 1,
2599 + .id = GSW_ATTR_ENABLE_VLAN,
2600 + .get = gsw_get_vlan_enable,
2601 + .set = gsw_set_vlan_enable,
2602 + },
2603 +};
2604 +
2605 +static const struct switch_attr gsw_port[] = {
2606 + {
2607 + .type = SWITCH_TYPE_INT,
2608 + .name = "untag",
2609 + .description = "Untag (1:strip outgoing vlan tag)",
2610 + .max = 1,
2611 + .id = GSW_ATTR_PORT_UNTAG,
2612 + .get = gsw_get_port_bool,
2613 + .set = gsw_set_port_bool,
2614 + },
2615 +};
2616 +
2617 +static const struct switch_attr gsw_vlan[] = {
2618 +};
2619 +
2620 +static const struct switch_dev_ops gsw_ops = {
2621 + .attr_global = {
2622 + .attr = gsw_global,
2623 + .n_attr = ARRAY_SIZE(gsw_global),
2624 + },
2625 + .attr_port = {
2626 + .attr = gsw_port,
2627 + .n_attr = ARRAY_SIZE(gsw_port),
2628 + },
2629 + .attr_vlan = {
2630 + .attr = gsw_vlan,
2631 + .n_attr = ARRAY_SIZE(gsw_vlan),
2632 + },
2633 + .get_vlan_ports = gsw_get_vlan_ports,
2634 + .set_vlan_ports = gsw_set_vlan_ports,
2635 + .get_port_pvid = gsw_get_port_pvid,
2636 + .set_port_pvid = gsw_set_port_pvid,
2637 + .get_port_link = gsw_get_port_link,
2638 + .apply_config = gsw_apply_config,
2639 + .reset_switch = gsw_reset_switch,
2640 +};
2641 +
2642 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2643 +{
2644 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2645 + unsigned long flags;
2646 +
2647 + spin_lock_irqsave(&priv->page_lock, flags);
2648 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2649 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2650 + GSW_REG_SMACCR0);
2651 + spin_unlock_irqrestore(&priv->page_lock, flags);
2652 +}
2653 +
2654 +static struct of_device_id gsw_match[] = {
2655 + { .compatible = "ralink,mt7620a-gsw" },
2656 + {}
2657 +};
2658 +
2659 +int mt7620_gsw_probe(struct fe_priv *priv)
2660 +{
2661 + struct mt7620_gsw *gsw;
2662 + struct device_node *np;
2663 + struct switch_dev *swdev;
2664 + const char *port4 = NULL;
2665 +
2666 + np = of_find_matching_node(NULL, gsw_match);
2667 + if (!np) {
2668 + dev_err(priv->device, "no gsw node found\n");
2669 + return -EINVAL;
2670 + }
2671 + np = of_node_get(np);
2672 +
2673 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2674 + if (!gsw) {
2675 + dev_err(priv->device, "no gsw memory for private data\n");
2676 + return -ENOMEM;
2677 + }
2678 +
2679 + gsw->irq = irq_of_parse_and_map(np, 0);
2680 + if (!gsw->irq) {
2681 + dev_err(priv->device, "no gsw irq resource found\n");
2682 + return -ENOMEM;
2683 + }
2684 +
2685 + gsw->base = of_iomap(np, 0);
2686 + if (!gsw->base) {
2687 + dev_err(priv->device, "gsw ioremap failed\n");
2688 + }
2689 +
2690 + gsw->dev = priv->device;
2691 + priv->soc->swpriv = gsw;
2692 +
2693 + swdev = &gsw->swdev;
2694 + swdev->of_node = np;
2695 + swdev->name = "mt7620a-gsw";
2696 + swdev->alias = "mt7620x";
2697 + swdev->cpu_port = GSW_PORT6;
2698 + swdev->ports = GSW_NUM_PORTS;
2699 + swdev->vlans = GSW_NUM_VLANS;
2700 + swdev->ops = &gsw_ops;
2701 +
2702 + if (register_switch(swdev, NULL))
2703 + dev_err(priv->device, "register_switch failed\n");
2704 +
2705 + of_property_read_string(np, "ralink,port4", &port4);
2706 + if (port4 && !strcmp(port4, "ephy"))
2707 + gsw->port4 = PORT4_EPHY;
2708 + else if (port4 && !strcmp(port4, "gmac"))
2709 + gsw->port4 = PORT4_EXT;
2710 + else
2711 + WARN_ON(port4);
2712 +
2713 + gsw_hw_init(gsw);
2714 +
2715 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2716 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2717 +
2718 + return 0;
2719 +}
2720 diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.h b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2721 new file mode 100644
2722 index 0000000..fd4add5
2723 --- /dev/null
2724 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2725 @@ -0,0 +1,29 @@
2726 +/*
2727 + * This program is free software; you can redistribute it and/or modify
2728 + * it under the terms of the GNU General Public License as published by
2729 + * the Free Software Foundation; version 2 of the License
2730 + *
2731 + * This program is distributed in the hope that it will be useful,
2732 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2733 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2734 + * GNU General Public License for more details.
2735 + *
2736 + * You should have received a copy of the GNU General Public License
2737 + * along with this program; if not, write to the Free Software
2738 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2739 + *
2740 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2741 + */
2742 +
2743 +#ifndef _RALINK_GSW_MT7620_H__
2744 +#define _RALINK_GSW_MT7620_H__
2745 +
2746 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2747 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2748 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2749 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2750 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2751 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2752 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2753 +
2754 +#endif
2755 diff --git a/drivers/net/ethernet/ralink/mdio.c b/drivers/net/ethernet/ralink/mdio.c
2756 new file mode 100644
2757 index 0000000..b265c75
2758 --- /dev/null
2759 +++ b/drivers/net/ethernet/ralink/mdio.c
2760 @@ -0,0 +1,245 @@
2761 +/*
2762 + * This program is free software; you can redistribute it and/or modify
2763 + * it under the terms of the GNU General Public License as published by
2764 + * the Free Software Foundation; version 2 of the License
2765 + *
2766 + * This program is distributed in the hope that it will be useful,
2767 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2768 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2769 + * GNU General Public License for more details.
2770 + *
2771 + * You should have received a copy of the GNU General Public License
2772 + * along with this program; if not, write to the Free Software
2773 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2774 + *
2775 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2776 + */
2777 +
2778 +#include <linux/module.h>
2779 +#include <linux/kernel.h>
2780 +#include <linux/types.h>
2781 +#include <linux/dma-mapping.h>
2782 +#include <linux/init.h>
2783 +#include <linux/skbuff.h>
2784 +#include <linux/etherdevice.h>
2785 +#include <linux/ethtool.h>
2786 +#include <linux/platform_device.h>
2787 +#include <linux/phy.h>
2788 +#include <linux/of_device.h>
2789 +#include <linux/clk.h>
2790 +#include <linux/of_net.h>
2791 +#include <linux/of_mdio.h>
2792 +
2793 +#include "ralink_soc_eth.h"
2794 +#include "mdio.h"
2795 +
2796 +static int fe_mdio_reset(struct mii_bus *bus)
2797 +{
2798 + /* TODO */
2799 + return 0;
2800 +}
2801 +
2802 +static void fe_phy_link_adjust(struct net_device *dev)
2803 +{
2804 + struct fe_priv *priv = netdev_priv(dev);
2805 + unsigned long flags;
2806 + int i;
2807 +
2808 + spin_lock_irqsave(&priv->phy->lock, flags);
2809 + for (i = 0; i < 8; i++) {
2810 + if (priv->phy->phy_node[i]) {
2811 + struct phy_device *phydev = priv->phy->phy[i];
2812 + int status_change = 0;
2813 +
2814 + if (phydev->link)
2815 + if (priv->phy->duplex[i] != phydev->duplex ||
2816 + priv->phy->speed[i] != phydev->speed)
2817 + status_change = 1;
2818 +
2819 + if (phydev->link != priv->link[i])
2820 + status_change = 1;
2821 +
2822 + switch (phydev->speed) {
2823 + case SPEED_1000:
2824 + case SPEED_100:
2825 + case SPEED_10:
2826 + priv->link[i] = phydev->link;
2827 + priv->phy->duplex[i] = phydev->duplex;
2828 + priv->phy->speed[i] = phydev->speed;
2829 +
2830 + if (status_change && priv->soc->mdio_adjust_link)
2831 + priv->soc->mdio_adjust_link(priv, i);
2832 + break;
2833 + }
2834 + }
2835 + }
2836 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2837 +}
2838 +
2839 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2840 +{
2841 + const __be32 *_port = NULL;
2842 + struct phy_device *phydev;
2843 + int phy_mode, port;
2844 +
2845 + _port = of_get_property(phy_node, "reg", NULL);
2846 +
2847 + if (!_port || (be32_to_cpu(*_port) >= 8)) {
2848 + pr_err("%s: invalid port id\n", phy_node->name);
2849 + return -EINVAL;
2850 + }
2851 + port = be32_to_cpu(*_port);
2852 + phy_mode = of_get_phy_mode(phy_node);
2853 + if (phy_mode < 0) {
2854 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2855 + priv->phy->phy_node[port] = NULL;
2856 + return -EINVAL;
2857 + }
2858 +
2859 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2860 + 0, phy_mode);
2861 + if (IS_ERR(phydev)) {
2862 + dev_err(priv->device, "could not connect to PHY\n");
2863 + priv->phy->phy_node[port] = NULL;
2864 + return PTR_ERR(phydev);
2865 + }
2866 +
2867 + phydev->supported &= PHY_GBIT_FEATURES;
2868 + phydev->advertising = phydev->supported;
2869 + phydev->no_auto_carrier_off = 1;
2870 +
2871 + dev_info(priv->device,
2872 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2873 + port, dev_name(&phydev->dev), phydev->phy_id,
2874 + phydev->drv->name);
2875 +
2876 + priv->phy->phy[port] = phydev;
2877 + priv->link[port] = 0;
2878 +
2879 + return 0;
2880 +}
2881 +
2882 +static int fe_phy_connect(struct fe_priv *priv)
2883 +{
2884 + return 0;
2885 +}
2886 +
2887 +static void fe_phy_disconnect(struct fe_priv *priv)
2888 +{
2889 + unsigned long flags;
2890 + int i;
2891 +
2892 + for (i = 0; i < 8; i++)
2893 + if (priv->phy->phy_fixed[i]) {
2894 + spin_lock_irqsave(&priv->phy->lock, flags);
2895 + priv->link[i] = 0;
2896 + if (priv->soc->mdio_adjust_link)
2897 + priv->soc->mdio_adjust_link(priv, i);
2898 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2899 + } else if (priv->phy->phy[i]) {
2900 + phy_disconnect(priv->phy->phy[i]);
2901 + }
2902 +}
2903 +
2904 +static void fe_phy_start(struct fe_priv *priv)
2905 +{
2906 + unsigned long flags;
2907 + int i;
2908 +
2909 + for (i = 0; i < 8; i++) {
2910 + if (priv->phy->phy_fixed[i]) {
2911 + spin_lock_irqsave(&priv->phy->lock, flags);
2912 + priv->link[i] = 1;
2913 + if (priv->soc->mdio_adjust_link)
2914 + priv->soc->mdio_adjust_link(priv, i);
2915 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2916 + } else if (priv->phy->phy[i]) {
2917 + phy_start(priv->phy->phy[i]);
2918 + }
2919 + }
2920 +}
2921 +
2922 +static void fe_phy_stop(struct fe_priv *priv)
2923 +{
2924 + unsigned long flags;
2925 + int i;
2926 +
2927 + for (i = 0; i < 8; i++)
2928 + if (priv->phy->phy_fixed[i]) {
2929 + spin_lock_irqsave(&priv->phy->lock, flags);
2930 + priv->link[i] = 0;
2931 + if (priv->soc->mdio_adjust_link)
2932 + priv->soc->mdio_adjust_link(priv, i);
2933 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2934 + } else if (priv->phy->phy[i]) {
2935 + phy_stop(priv->phy->phy[i]);
2936 + }
2937 +}
2938 +
2939 +static struct fe_phy phy_ralink = {
2940 + .connect = fe_phy_connect,
2941 + .disconnect = fe_phy_disconnect,
2942 + .start = fe_phy_start,
2943 + .stop = fe_phy_stop,
2944 +};
2945 +
2946 +int fe_mdio_init(struct fe_priv *priv)
2947 +{
2948 + struct device_node *mii_np;
2949 + int err;
2950 +
2951 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2952 + return 0;
2953 +
2954 + spin_lock_init(&phy_ralink.lock);
2955 + priv->phy = &phy_ralink;
2956 +
2957 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2958 + if (!mii_np) {
2959 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2960 + return -ENODEV;
2961 + }
2962 +
2963 + if (!of_device_is_available(mii_np)) {
2964 + err = 0;
2965 + goto err_put_node;
2966 + }
2967 +
2968 + priv->mii_bus = mdiobus_alloc();
2969 + if (priv->mii_bus == NULL) {
2970 + err = -ENOMEM;
2971 + goto err_put_node;
2972 + }
2973 +
2974 + priv->mii_bus->name = "mdio";
2975 + priv->mii_bus->read = priv->soc->mdio_read;
2976 + priv->mii_bus->write = priv->soc->mdio_write;
2977 + priv->mii_bus->reset = fe_mdio_reset;
2978 + priv->mii_bus->irq = priv->mii_irq;
2979 + priv->mii_bus->priv = priv;
2980 + priv->mii_bus->parent = priv->device;
2981 +
2982 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2983 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2984 + if (err)
2985 + goto err_free_bus;
2986 +
2987 + return 0;
2988 +
2989 +err_free_bus:
2990 + kfree(priv->mii_bus);
2991 +err_put_node:
2992 + of_node_put(mii_np);
2993 + priv->mii_bus = NULL;
2994 + return err;
2995 +}
2996 +
2997 +void fe_mdio_cleanup(struct fe_priv *priv)
2998 +{
2999 + if (!priv->mii_bus)
3000 + return;
3001 +
3002 + mdiobus_unregister(priv->mii_bus);
3003 + of_node_put(priv->mii_bus->dev.of_node);
3004 + kfree(priv->mii_bus);
3005 +}
3006 diff --git a/drivers/net/ethernet/ralink/mdio.h b/drivers/net/ethernet/ralink/mdio.h
3007 new file mode 100644
3008 index 0000000..c3910a0
3009 --- /dev/null
3010 +++ b/drivers/net/ethernet/ralink/mdio.h
3011 @@ -0,0 +1,29 @@
3012 +/*
3013 + * This program is free software; you can redistribute it and/or modify
3014 + * it under the terms of the GNU General Public License as published by
3015 + * the Free Software Foundation; version 2 of the License
3016 + *
3017 + * This program is distributed in the hope that it will be useful,
3018 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3019 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3020 + * GNU General Public License for more details.
3021 + *
3022 + * You should have received a copy of the GNU General Public License
3023 + * along with this program; if not, write to the Free Software
3024 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3025 + *
3026 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3027 + */
3028 +
3029 +#ifndef _RALINK_MDIO_H__
3030 +#define _RALINK_MDIO_H__
3031 +
3032 +#ifdef CONFIG_NET_RALINK_MDIO
3033 +extern int fe_mdio_init(struct fe_priv *priv);
3034 +extern void fe_mdio_cleanup(struct fe_priv *priv);
3035 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
3036 +#else
3037 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
3038 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
3039 +#endif
3040 +#endif
3041 diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.c b/drivers/net/ethernet/ralink/mdio_rt2880.c
3042 new file mode 100644
3043 index 0000000..701c7b6
3044 --- /dev/null
3045 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
3046 @@ -0,0 +1,232 @@
3047 +/*
3048 + * This program is free software; you can redistribute it and/or modify
3049 + * it under the terms of the GNU General Public License as published by
3050 + * the Free Software Foundation; version 2 of the License
3051 + *
3052 + * This program is distributed in the hope that it will be useful,
3053 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3054 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3055 + * GNU General Public License for more details.
3056 + *
3057 + * You should have received a copy of the GNU General Public License
3058 + * along with this program; if not, write to the Free Software
3059 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3060 + *
3061 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3062 + */
3063 +
3064 +#include <linux/module.h>
3065 +#include <linux/kernel.h>
3066 +#include <linux/types.h>
3067 +#include <linux/dma-mapping.h>
3068 +#include <linux/init.h>
3069 +#include <linux/skbuff.h>
3070 +#include <linux/etherdevice.h>
3071 +#include <linux/ethtool.h>
3072 +#include <linux/platform_device.h>
3073 +#include <linux/phy.h>
3074 +#include <linux/of_device.h>
3075 +#include <linux/clk.h>
3076 +#include <linux/of_net.h>
3077 +#include <linux/of_mdio.h>
3078 +
3079 +#include "ralink_soc_eth.h"
3080 +#include "mdio_rt2880.h"
3081 +#include "mdio.h"
3082 +
3083 +#define FE_MDIO_RETRY 1000
3084 +
3085 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
3086 +{
3087 + switch (priv->phy->speed[0]) {
3088 + case SPEED_1000:
3089 + return "1000";
3090 + case SPEED_100:
3091 + return "100";
3092 + case SPEED_10:
3093 + return "10";
3094 + }
3095 +
3096 + return "?";
3097 +}
3098 +
3099 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
3100 +{
3101 + u32 mdio_cfg;
3102 +
3103 + if (!priv->link[0]) {
3104 + netif_carrier_off(priv->netdev);
3105 + netdev_info(priv->netdev, "link down\n");
3106 + return;
3107 + }
3108 +
3109 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
3110 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
3111 + FE_MDIO_CFG_GP1_FRC_EN;
3112 +
3113 + if (priv->phy->duplex[0] == DUPLEX_FULL)
3114 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
3115 +
3116 + if (priv->phy->tx_fc[0])
3117 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
3118 +
3119 + if (priv->phy->rx_fc[0])
3120 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
3121 +
3122 + switch (priv->phy->speed[0]) {
3123 + case SPEED_10:
3124 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
3125 + break;
3126 + case SPEED_100:
3127 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
3128 + break;
3129 + case SPEED_1000:
3130 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
3131 + break;
3132 + default:
3133 + BUG();
3134 + }
3135 +
3136 + fe_w32(mdio_cfg, FE_MDIO_CFG);
3137 +
3138 + netif_carrier_on(priv->netdev);
3139 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
3140 + rt2880_speed_str(priv),
3141 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
3142 +}
3143 +
3144 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
3145 +{
3146 + int retries;
3147 +
3148 + retries = FE_MDIO_RETRY;
3149 + while (1) {
3150 + u32 t;
3151 +
3152 + t = fe_r32(FE_MDIO_ACCESS);
3153 + if ((t & (0x1 << 31)) == 0)
3154 + return 0;
3155 +
3156 + if (retries-- == 0)
3157 + break;
3158 +
3159 + udelay(1);
3160 + }
3161 +
3162 + dev_err(priv->device, "MDIO operation timed out\n");
3163 + return -ETIMEDOUT;
3164 +}
3165 +
3166 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
3167 +{
3168 + struct fe_priv *priv = bus->priv;
3169 + int err;
3170 + u32 t;
3171 +
3172 + err = rt2880_mdio_wait_ready(priv);
3173 + if (err)
3174 + return 0xffff;
3175 +
3176 + t = (phy_addr << 24) | (phy_reg << 16);
3177 + fe_w32(t, FE_MDIO_ACCESS);
3178 + t |= (1 << 31);
3179 + fe_w32(t, FE_MDIO_ACCESS);
3180 +
3181 + err = rt2880_mdio_wait_ready(priv);
3182 + if (err)
3183 + return 0xffff;
3184 +
3185 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3186 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3187 +
3188 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
3189 +}
3190 +
3191 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
3192 +{
3193 + struct fe_priv *priv = bus->priv;
3194 + int err;
3195 + u32 t;
3196 +
3197 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3198 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3199 +
3200 + err = rt2880_mdio_wait_ready(priv);
3201 + if (err)
3202 + return err;
3203 +
3204 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
3205 + fe_w32(t, FE_MDIO_ACCESS);
3206 + t |= (1 << 31);
3207 + fe_w32(t, FE_MDIO_ACCESS);
3208 +
3209 + return rt2880_mdio_wait_ready(priv);
3210 +}
3211 +
3212 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
3213 +{
3214 + const __be32 *id = of_get_property(np, "reg", NULL);
3215 + const __be32 *link;
3216 + int size;
3217 + int phy_mode;
3218 +
3219 + if (!id || (be32_to_cpu(*id) != 0)) {
3220 + pr_err("%s: invalid port id\n", np->name);
3221 + return;
3222 + }
3223 +
3224 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
3225 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
3226 + pr_err("%s: invalid fixed link property\n", np->name);
3227 + priv->phy->phy_fixed[0] = NULL;
3228 + return;
3229 + }
3230 +
3231 + phy_mode = of_get_phy_mode(np);
3232 + switch (phy_mode) {
3233 + case PHY_INTERFACE_MODE_RGMII:
3234 + break;
3235 + case PHY_INTERFACE_MODE_MII:
3236 + break;
3237 + case PHY_INTERFACE_MODE_RMII:
3238 + break;
3239 + default:
3240 + if (!priv->phy->phy_fixed[0])
3241 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
3242 + break;
3243 + }
3244 +
3245 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
3246 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
3247 + return;
3248 +
3249 + if (priv->phy->phy_fixed[0]) {
3250 + link = priv->phy->phy_fixed[0];
3251 + priv->phy->speed[0] = be32_to_cpup(link++);
3252 + priv->phy->duplex[0] = be32_to_cpup(link++);
3253 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
3254 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
3255 +
3256 + priv->link[0] = 1;
3257 + switch (priv->phy->speed[0]) {
3258 + case SPEED_10:
3259 + break;
3260 + case SPEED_100:
3261 + break;
3262 + case SPEED_1000:
3263 + break;
3264 + default:
3265 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
3266 + priv->phy->phy_fixed[0] = 0;
3267 + return;
3268 + }
3269 + dev_info(priv->device, "using fixed link parameters\n");
3270 + rt2880_mdio_link_adjust(priv, 0);
3271 + return;
3272 + }
3273 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
3274 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
3275 + }
3276 +
3277 + return;
3278 +}
3279 diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.h b/drivers/net/ethernet/ralink/mdio_rt2880.h
3280 new file mode 100644
3281 index 0000000..51e3633
3282 --- /dev/null
3283 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
3284 @@ -0,0 +1,26 @@
3285 +/*
3286 + * This program is free software; you can redistribute it and/or modify
3287 + * it under the terms of the GNU General Public License as published by
3288 + * the Free Software Foundation; version 2 of the License
3289 + *
3290 + * This program is distributed in the hope that it will be useful,
3291 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3292 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3293 + * GNU General Public License for more details.
3294 + *
3295 + * You should have received a copy of the GNU General Public License
3296 + * along with this program; if not, write to the Free Software
3297 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3298 + *
3299 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3300 + */
3301 +
3302 +#ifndef _RALINK_MDIO_RT2880_H__
3303 +#define _RALINK_MDIO_RT2880_H__
3304 +
3305 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
3306 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
3307 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3308 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
3309 +
3310 +#endif
3311 diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.c b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3312 new file mode 100644
3313 index 0000000..d75c669
3314 --- /dev/null
3315 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3316 @@ -0,0 +1,746 @@
3317 +/*
3318 + * This program is free software; you can redistribute it and/or modify
3319 + * it under the terms of the GNU General Public License as published by
3320 + * the Free Software Foundation; version 2 of the License
3321 + *
3322 + * This program is distributed in the hope that it will be useful,
3323 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3324 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3325 + * GNU General Public License for more details.
3326 + *
3327 + * You should have received a copy of the GNU General Public License
3328 + * along with this program; if not, write to the Free Software
3329 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3330 + *
3331 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3332 + */
3333 +
3334 +#include <linux/module.h>
3335 +#include <linux/kernel.h>
3336 +#include <linux/types.h>
3337 +#include <linux/dma-mapping.h>
3338 +#include <linux/init.h>
3339 +#include <linux/skbuff.h>
3340 +#include <linux/etherdevice.h>
3341 +#include <linux/ethtool.h>
3342 +#include <linux/platform_device.h>
3343 +#include <linux/of_device.h>
3344 +#include <linux/clk.h>
3345 +#include <linux/of_net.h>
3346 +#include <linux/of_mdio.h>
3347 +#include <linux/if_vlan.h>
3348 +
3349 +#include <asm/mach-ralink/ralink_regs.h>
3350 +
3351 +#include "ralink_soc_eth.h"
3352 +#include "esw_rt3052.h"
3353 +#include "mdio.h"
3354 +
3355 +#define TX_TIMEOUT (20 * HZ / 100)
3356 +#define MAX_RX_LENGTH 1536
3357 +
3358 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3359 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3360 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3361 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3362 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3363 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3364 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3365 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3366 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3367 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3368 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3369 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3370 + [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
3371 +};
3372 +
3373 +static const u32 *fe_reg_table = fe_reg_table_default;
3374 +
3375 +static void __iomem *fe_base = 0;
3376 +
3377 +void fe_w32(u32 val, unsigned reg)
3378 +{
3379 + __raw_writel(val, fe_base + reg);
3380 +}
3381 +
3382 +u32 fe_r32(unsigned reg)
3383 +{
3384 + return __raw_readl(fe_base + reg);
3385 +}
3386 +
3387 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3388 +{
3389 + fe_w32(val, fe_reg_table[reg]);
3390 +}
3391 +
3392 +static inline u32 fe_reg_r32(enum fe_reg reg)
3393 +{
3394 + return fe_r32(fe_reg_table[reg]);
3395 +}
3396 +
3397 +static inline void fe_int_disable(u32 mask)
3398 +{
3399 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3400 + FE_REG_FE_INT_ENABLE);
3401 + /* flush write */
3402 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3403 +}
3404 +
3405 +static inline void fe_int_enable(u32 mask)
3406 +{
3407 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3408 + FE_REG_FE_INT_ENABLE);
3409 + /* flush write */
3410 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3411 +}
3412 +
3413 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3414 +{
3415 + unsigned long flags;
3416 +
3417 + spin_lock_irqsave(&priv->page_lock, flags);
3418 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3419 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3420 + FE_GDMA1_MAC_ADRL);
3421 + spin_unlock_irqrestore(&priv->page_lock, flags);
3422 +}
3423 +
3424 +static int fe_set_mac_address(struct net_device *dev, void *p)
3425 +{
3426 + int ret = eth_mac_addr(dev, p);
3427 +
3428 + if (!ret) {
3429 + struct fe_priv *priv = netdev_priv(dev);
3430 +
3431 + if (priv->soc->set_mac)
3432 + priv->soc->set_mac(priv, dev->dev_addr);
3433 + else
3434 + fe_hw_set_macaddr(priv, p);
3435 + }
3436 +
3437 + return ret;
3438 +}
3439 +
3440 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3441 +{
3442 + struct sk_buff *skb;
3443 +
3444 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3445 + if (!skb)
3446 + return NULL;
3447 +
3448 + skb_reserve(skb, NET_IP_ALIGN);
3449 +
3450 + return skb;
3451 +}
3452 +
3453 +static int fe_alloc_rx(struct fe_priv *priv)
3454 +{
3455 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3456 + int i;
3457 +
3458 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3459 + &priv->rx_phys, GFP_ATOMIC);
3460 + if (!priv->rx_dma)
3461 + return -ENOMEM;
3462 +
3463 + memset(priv->rx_dma, 0, size);
3464 +
3465 + for (i = 0; i < NUM_DMA_DESC; i++) {
3466 + priv->rx_skb[i] = fe_alloc_skb(priv);
3467 + if (!priv->rx_skb[i])
3468 + return -ENOMEM;
3469 + }
3470 +
3471 + for (i = 0; i < NUM_DMA_DESC; i++) {
3472 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3473 + priv->rx_skb[i]->data,
3474 + MAX_RX_LENGTH,
3475 + DMA_FROM_DEVICE);
3476 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3477 +
3478 + if (priv->soc->rx_dma)
3479 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3480 + else
3481 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3482 + }
3483 + wmb();
3484 +
3485 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3486 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3487 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3488 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3489 +
3490 + return 0;
3491 +}
3492 +
3493 +static int fe_alloc_tx(struct fe_priv *priv)
3494 +{
3495 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3496 + int i;
3497 +
3498 + priv->tx_free_idx = 0;
3499 +
3500 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3501 + &priv->tx_phys, GFP_ATOMIC);
3502 + if (!priv->tx_dma)
3503 + return -ENOMEM;
3504 +
3505 + memset(priv->tx_dma, 0, size);
3506 +
3507 + for (i = 0; i < NUM_DMA_DESC; i++) {
3508 + if (priv->soc->tx_dma) {
3509 + priv->soc->tx_dma(priv, i, 0);
3510 + continue;
3511 + }
3512 +
3513 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3514 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3515 + }
3516 +
3517 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3518 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3519 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3520 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3521 +
3522 + return 0;
3523 +}
3524 +
3525 +static void fe_free_dma(struct fe_priv *priv)
3526 +{
3527 + int i;
3528 +
3529 + for (i = 0; i < NUM_DMA_DESC; i++) {
3530 + if (priv->rx_skb[i]) {
3531 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3532 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3533 + dev_kfree_skb_any(priv->rx_skb[i]);
3534 + priv->rx_skb[i] = NULL;
3535 + }
3536 +
3537 + if (priv->tx_skb[i]) {
3538 + dev_kfree_skb_any(priv->tx_skb[i]);
3539 + priv->tx_skb[i] = NULL;
3540 + }
3541 + }
3542 +
3543 + if (priv->rx_dma) {
3544 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3545 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3546 + priv->rx_phys);
3547 + }
3548 +
3549 + if (priv->tx_dma) {
3550 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3551 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3552 + priv->tx_phys);
3553 + }
3554 +
3555 + netdev_reset_queue(priv->netdev);
3556 +}
3557 +
3558 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3559 +{
3560 + struct fe_priv *priv = netdev_priv(dev);
3561 + dma_addr_t mapped_addr;
3562 + u32 tx_next;
3563 + u32 tx;
3564 +
3565 + if (priv->soc->min_pkt_len) {
3566 + if (skb->len < priv->soc->min_pkt_len) {
3567 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3568 + printk(KERN_ERR
3569 + "fe_eth: skb_padto failed\n");
3570 + kfree_skb(skb);
3571 + return 0;
3572 + }
3573 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3574 + }
3575 + }
3576 +
3577 + dev->trans_start = jiffies;
3578 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3579 + skb->len, DMA_TO_DEVICE);
3580 +
3581 + spin_lock(&priv->page_lock);
3582 +
3583 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3584 + tx_next = (tx + 1) % NUM_DMA_DESC;
3585 +
3586 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3587 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3588 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3589 + {
3590 + spin_unlock(&priv->page_lock);
3591 + dev->stats.tx_dropped++;
3592 + kfree_skb(skb);
3593 +
3594 + return NETDEV_TX_OK;
3595 + }
3596 +
3597 + priv->tx_skb[tx] = skb;
3598 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3599 + wmb();
3600 + if (priv->soc->tx_dma)
3601 + priv->soc->tx_dma(priv, tx, skb->len);
3602 + else
3603 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3604 +
3605 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3606 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3607 + else
3608 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3609 +
3610 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE] && vlan_tx_tag_present(skb))
3611 + priv->tx_dma[tx].txd4 |= 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
3612 + else
3613 + priv->tx_dma[tx].txd4 &= ~0x80;
3614 +
3615 + dev->stats.tx_packets++;
3616 + dev->stats.tx_bytes += skb->len;
3617 +
3618 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3619 + netdev_sent_queue(dev, skb->len);
3620 +
3621 + spin_unlock(&priv->page_lock);
3622 +
3623 + return NETDEV_TX_OK;
3624 +}
3625 +
3626 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3627 +{
3628 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3629 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3630 + int complete = 0;
3631 + int rx = 0;
3632 +
3633 + while ((rx < budget) && !complete) {
3634 + idx = (idx + 1) % NUM_DMA_DESC;
3635 +
3636 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3637 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3638 +
3639 + if (new_skb) {
3640 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3641 + dma_addr_t dma_addr;
3642 +
3643 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3644 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3645 +
3646 + skb_put(priv->rx_skb[idx], pktlen);
3647 + priv->rx_skb[idx]->dev = priv->netdev;
3648 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3649 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3650 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3651 + else
3652 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3653 + priv->netdev->stats.rx_packets++;
3654 + priv->netdev->stats.rx_bytes += pktlen;
3655 + netif_receive_skb(priv->rx_skb[idx]);
3656 +
3657 + priv->rx_skb[idx] = new_skb;
3658 +
3659 + dma_addr = dma_map_single(&priv->netdev->dev,
3660 + new_skb->data,
3661 + MAX_RX_LENGTH,
3662 + DMA_FROM_DEVICE);
3663 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3664 + wmb();
3665 + } else {
3666 + priv->netdev->stats.rx_dropped++;
3667 + }
3668 +
3669 + if (priv->soc->rx_dma)
3670 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3671 + else
3672 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3673 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3674 +
3675 + rx++;
3676 + } else {
3677 + complete = 1;
3678 + }
3679 + }
3680 +
3681 + if (complete) {
3682 + napi_complete(&priv->rx_napi);
3683 + fe_int_enable(priv->soc->rx_dly_int);
3684 + }
3685 +
3686 + return rx;
3687 +}
3688 +
3689 +static void fe_tx_housekeeping(unsigned long ptr)
3690 +{
3691 + struct net_device *dev = (struct net_device*)ptr;
3692 + struct fe_priv *priv = netdev_priv(dev);
3693 + unsigned int bytes_compl = 0;
3694 + unsigned int pkts_compl = 0;
3695 +
3696 + spin_lock(&priv->page_lock);
3697 + while (1) {
3698 + struct fe_tx_dma *txd;
3699 +
3700 + txd = &priv->tx_dma[priv->tx_free_idx];
3701 +
3702 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3703 + break;
3704 +
3705 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3706 + pkts_compl++;
3707 +
3708 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3709 + priv->tx_skb[priv->tx_free_idx] = NULL;
3710 + priv->tx_free_idx++;
3711 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3712 + priv->tx_free_idx = 0;
3713 + }
3714 +
3715 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3716 + spin_unlock(&priv->page_lock);
3717 +
3718 + fe_int_enable(priv->soc->tx_dly_int);
3719 +}
3720 +
3721 +static void fe_tx_timeout(struct net_device *dev)
3722 +{
3723 + struct fe_priv *priv = netdev_priv(dev);
3724 +
3725 + tasklet_schedule(&priv->tx_tasklet);
3726 + priv->netdev->stats.tx_errors++;
3727 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3728 + netif_wake_queue(dev);
3729 +}
3730 +
3731 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3732 +{
3733 + struct fe_priv *priv = netdev_priv(dev);
3734 + unsigned int status;
3735 + unsigned int mask;
3736 +
3737 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3738 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3739 +
3740 + if (!(status & mask))
3741 + return IRQ_NONE;
3742 +
3743 + if (status & priv->soc->rx_dly_int) {
3744 + fe_int_disable(priv->soc->rx_dly_int);
3745 + napi_schedule(&priv->rx_napi);
3746 + }
3747 +
3748 + if (status & priv->soc->tx_dly_int) {
3749 + fe_int_disable(priv->soc->tx_dly_int);
3750 + tasklet_schedule(&priv->tx_tasklet);
3751 + }
3752 +
3753 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3754 +
3755 + return IRQ_HANDLED;
3756 +}
3757 +
3758 +static int fe_hw_init(struct net_device *dev)
3759 +{
3760 + struct fe_priv *priv = netdev_priv(dev);
3761 + int err, i;
3762 +
3763 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3764 + dev_name(priv->device), dev);
3765 + if (err)
3766 + return err;
3767 +
3768 + err = fe_alloc_rx(priv);
3769 + if (!err)
3770 + err = fe_alloc_tx(priv);
3771 + if (err)
3772 + return err;
3773 +
3774 + if (priv->soc->set_mac)
3775 + priv->soc->set_mac(priv, dev->dev_addr);
3776 + else
3777 + fe_hw_set_macaddr(priv, dev->dev_addr);
3778 +
3779 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3780 +
3781 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3782 +
3783 +
3784 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3785 + for (i = 0; i < 16; i += 2)
3786 + fe_w32((i + 1) << 16 | i, fe_reg_table[FE_REG_FE_DMA_VID_BASE] + (i * 4));
3787 +
3788 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3789 +
3790 + if (priv->soc->fwd_config) {
3791 + priv->soc->fwd_config(priv);
3792 + } else {
3793 + unsigned long sysclk = priv->sysclk;
3794 +
3795 + if (!sysclk) {
3796 + netdev_err(dev, "unable to get clock\n");
3797 + return -EINVAL;
3798 + }
3799 +
3800 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3801 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3802 +
3803 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3804 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3805 + FE_FE_GLO_CFG);
3806 +
3807 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3808 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3809 + FE_GDMA1_FWD_CFG);
3810 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3811 + FE_CDMA_CSG_CFG);
3812 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3813 + }
3814 +
3815 + fe_w32(1, FE_FE_RST_GL);
3816 + fe_w32(0, FE_FE_RST_GL);
3817 +
3818 + return 0;
3819 +}
3820 +
3821 +static int fe_open(struct net_device *dev)
3822 +{
3823 + struct fe_priv *priv = netdev_priv(dev);
3824 + unsigned long flags;
3825 + u32 val;
3826 +
3827 + spin_lock_irqsave(&priv->page_lock, flags);
3828 + napi_enable(&priv->rx_napi);
3829 +
3830 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3831 + val |= priv->soc->pdma_glo_cfg;
3832 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3833 +
3834 + spin_unlock_irqrestore(&priv->page_lock, flags);
3835 +
3836 + if (priv->phy)
3837 + priv->phy->start(priv);
3838 +
3839 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3840 + netif_carrier_on(dev);
3841 +
3842 + netif_start_queue(dev);
3843 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3844 +
3845 + return 0;
3846 +}
3847 +
3848 +static int fe_stop(struct net_device *dev)
3849 +{
3850 + struct fe_priv *priv = netdev_priv(dev);
3851 + unsigned long flags;
3852 +
3853 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3854 +
3855 + netif_stop_queue(dev);
3856 +
3857 + if (priv->phy)
3858 + priv->phy->stop(priv);
3859 +
3860 + spin_lock_irqsave(&priv->page_lock, flags);
3861 + napi_disable(&priv->rx_napi);
3862 +
3863 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3864 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3865 + FE_REG_PDMA_GLO_CFG);
3866 + spin_unlock_irqrestore(&priv->page_lock, flags);
3867 +
3868 + return 0;
3869 +}
3870 +
3871 +static int __init fe_init(struct net_device *dev)
3872 +{
3873 + struct fe_priv *priv = netdev_priv(dev);
3874 + struct device_node *port;
3875 + int err;
3876 +
3877 + BUG_ON(!priv->soc->reset_fe);
3878 + priv->soc->reset_fe();
3879 +
3880 + if (priv->soc->switch_init)
3881 + priv->soc->switch_init(priv);
3882 +
3883 + net_srandom(jiffies);
3884 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3885 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3886 +
3887 + err = fe_mdio_init(priv);
3888 + if (err)
3889 + return err;
3890 +
3891 + if (priv->phy) {
3892 + err = priv->phy->connect(priv);
3893 + if (err)
3894 + goto err_mdio_cleanup;
3895 + }
3896 +
3897 + if (priv->soc->port_init)
3898 + for_each_child_of_node(priv->device->of_node, port)
3899 + if (of_device_is_compatible(port, "ralink,eth-port"))
3900 + priv->soc->port_init(priv, port);
3901 +
3902 + err = fe_hw_init(dev);
3903 + if (err)
3904 + goto err_phy_disconnect;
3905 +
3906 + return 0;
3907 +
3908 +err_phy_disconnect:
3909 + if (priv->phy)
3910 + priv->phy->disconnect(priv);
3911 +err_mdio_cleanup:
3912 + fe_mdio_cleanup(priv);
3913 +
3914 + return err;
3915 +}
3916 +
3917 +static void fe_uninit(struct net_device *dev)
3918 +{
3919 + struct fe_priv *priv = netdev_priv(dev);
3920 +
3921 + tasklet_kill(&priv->tx_tasklet);
3922 +
3923 + if (priv->phy)
3924 + priv->phy->disconnect(priv);
3925 + fe_mdio_cleanup(priv);
3926 +
3927 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3928 + free_irq(dev->irq, dev);
3929 +
3930 + fe_free_dma(priv);
3931 +}
3932 +
3933 +static const struct net_device_ops fe_netdev_ops = {
3934 + .ndo_init = fe_init,
3935 + .ndo_uninit = fe_uninit,
3936 + .ndo_open = fe_open,
3937 + .ndo_stop = fe_stop,
3938 + .ndo_start_xmit = fe_start_xmit,
3939 + .ndo_tx_timeout = fe_tx_timeout,
3940 + .ndo_set_mac_address = fe_set_mac_address,
3941 + .ndo_change_mtu = eth_change_mtu,
3942 + .ndo_validate_addr = eth_validate_addr,
3943 +};
3944 +
3945 +static int fe_probe(struct platform_device *pdev)
3946 +{
3947 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3948 + const struct of_device_id *match;
3949 + struct fe_soc_data *soc = NULL;
3950 + struct net_device *netdev;
3951 + struct fe_priv *priv;
3952 + struct clk *sysclk;
3953 + int err;
3954 +
3955 + match = of_match_device(of_fe_match, &pdev->dev);
3956 + soc = (struct fe_soc_data *) match->data;
3957 + if (soc->reg_table)
3958 + fe_reg_table = soc->reg_table;
3959 +
3960 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
3961 + if (!fe_base)
3962 + return -ENOMEM;
3963 +
3964 + netdev = alloc_etherdev(sizeof(struct fe_priv));
3965 + if (!netdev) {
3966 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
3967 + return -ENOMEM;
3968 + }
3969 +
3970 + strcpy(netdev->name, "eth%d");
3971 + netdev->netdev_ops = &fe_netdev_ops;
3972 + netdev->base_addr = (unsigned long) fe_base;
3973 + netdev->watchdog_timeo = TX_TIMEOUT;
3974 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3975 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3976 + netdev->features |= NETIF_F_HW_VLAN_TX;
3977 +
3978 + netdev->irq = platform_get_irq(pdev, 0);
3979 + if (netdev->irq < 0) {
3980 + dev_err(&pdev->dev, "no IRQ resource found\n");
3981 + kfree(netdev);
3982 + return -ENXIO;
3983 + }
3984 +
3985 + priv = netdev_priv(netdev);
3986 + memset(priv, 0, sizeof(struct fe_priv));
3987 + spin_lock_init(&priv->page_lock);
3988 +
3989 + sysclk = devm_clk_get(&pdev->dev, NULL);
3990 + if (!IS_ERR(sysclk))
3991 + priv->sysclk = clk_get_rate(sysclk);
3992 +
3993 + priv->netdev = netdev;
3994 + priv->device = &pdev->dev;
3995 + priv->soc = soc;
3996 +
3997 + err = register_netdev(netdev);
3998 + if (err) {
3999 + dev_err(&pdev->dev, "error bringing up device\n");
4000 + kfree(netdev);
4001 + return err;
4002 + }
4003 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
4004 +
4005 + platform_set_drvdata(pdev, netdev);
4006 +
4007 + netdev_info(netdev, "done loading\n");
4008 +
4009 + return 0;
4010 +}
4011 +
4012 +static int fe_remove(struct platform_device *pdev)
4013 +{
4014 + struct net_device *dev = platform_get_drvdata(pdev);
4015 + struct fe_priv *priv = netdev_priv(dev);
4016 +
4017 + netif_stop_queue(dev);
4018 + netif_napi_del(&priv->rx_napi);
4019 +
4020 + unregister_netdev(dev);
4021 + free_netdev(dev);
4022 +
4023 + return 0;
4024 +}
4025 +
4026 +static struct platform_driver fe_driver = {
4027 + .probe = fe_probe,
4028 + .remove = fe_remove,
4029 + .driver = {
4030 + .name = "ralink_soc_eth",
4031 + .owner = THIS_MODULE,
4032 + .of_match_table = of_fe_match,
4033 + },
4034 +};
4035 +
4036 +static int __init init_rtfe(void)
4037 +{
4038 + int ret;
4039 +
4040 + ret = rtesw_init();
4041 + if (ret)
4042 + return ret;
4043 +
4044 + ret = platform_driver_register(&fe_driver);
4045 + if (ret)
4046 + rtesw_exit();
4047 +
4048 + return ret;
4049 +}
4050 +
4051 +static void __exit exit_rtfe(void)
4052 +{
4053 + platform_driver_unregister(&fe_driver);
4054 + rtesw_exit();
4055 +}
4056 +
4057 +module_init(init_rtfe);
4058 +module_exit(exit_rtfe);
4059 +
4060 +MODULE_LICENSE("GPL");
4061 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4062 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4063 diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.h b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4064 new file mode 100644
4065 index 0000000..85bc881
4066 --- /dev/null
4067 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4068 @@ -0,0 +1,374 @@
4069 +/*
4070 + * This program is free software; you can redistribute it and/or modify
4071 + * it under the terms of the GNU General Public License as published by
4072 + * the Free Software Foundation; version 2 of the License
4073 + *
4074 + * This program is distributed in the hope that it will be useful,
4075 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4076 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4077 + * GNU General Public License for more details.
4078 + *
4079 + * You should have received a copy of the GNU General Public License
4080 + * along with this program; if not, write to the Free Software
4081 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4082 + *
4083 + * based on Ralink SDK3.3
4084 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4085 + */
4086 +
4087 +#ifndef FE_ETH_H
4088 +#define FE_ETH_H
4089 +
4090 +#include <linux/mii.h>
4091 +#include <linux/interrupt.h>
4092 +#include <linux/netdevice.h>
4093 +#include <linux/dma-mapping.h>
4094 +#include <linux/phy.h>
4095 +
4096 +
4097 +enum fe_reg {
4098 + FE_REG_PDMA_GLO_CFG = 0,
4099 + FE_REG_PDMA_RST_CFG,
4100 + FE_REG_DLY_INT_CFG,
4101 + FE_REG_TX_BASE_PTR0,
4102 + FE_REG_TX_MAX_CNT0,
4103 + FE_REG_TX_CTX_IDX0,
4104 + FE_REG_RX_BASE_PTR0,
4105 + FE_REG_RX_MAX_CNT0,
4106 + FE_REG_RX_CALC_IDX0,
4107 + FE_REG_FE_INT_ENABLE,
4108 + FE_REG_FE_INT_STATUS,
4109 + FE_REG_FE_DMA_VID_BASE,
4110 + FE_REG_COUNT
4111 +};
4112 +
4113 +#define NUM_DMA_DESC 0x100
4114 +
4115 +#define FE_DELAY_EN_INT 0x80
4116 +#define FE_DELAY_MAX_INT 0x04
4117 +#define FE_DELAY_MAX_TOUT 0x04
4118 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4119 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4120 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
4121 +
4122 +/* interrupt bits */
4123 +#define FE_CNT_PPE_AF BIT(31)
4124 +#define FE_CNT_GDM_AF BIT(29)
4125 +#define FE_PSE_P2_FC BIT(26)
4126 +#define FE_PSE_BUF_DROP BIT(24)
4127 +#define FE_GDM_OTHER_DROP BIT(23)
4128 +#define FE_PSE_P1_FC BIT(22)
4129 +#define FE_PSE_P0_FC BIT(21)
4130 +#define FE_PSE_FQ_EMPTY BIT(20)
4131 +#define FE_GE1_STA_CHG BIT(18)
4132 +#define FE_TX_COHERENT BIT(17)
4133 +#define FE_RX_COHERENT BIT(16)
4134 +#define FE_TX_DONE_INT3 BIT(11)
4135 +#define FE_TX_DONE_INT2 BIT(10)
4136 +#define FE_TX_DONE_INT1 BIT(9)
4137 +#define FE_TX_DONE_INT0 BIT(8)
4138 +#define FE_RX_DONE_INT0 BIT(2)
4139 +#define FE_TX_DLY_INT BIT(1)
4140 +#define FE_RX_DLY_INT BIT(0)
4141 +
4142 +#define RT5350_RX_DLY_INT BIT(30)
4143 +#define RT5350_TX_DLY_INT BIT(28)
4144 +
4145 +/* registers */
4146 +#define FE_FE_OFFSET 0x0000
4147 +#define FE_GDMA_OFFSET 0x0020
4148 +#define FE_PSE_OFFSET 0x0040
4149 +#define FE_GDMA2_OFFSET 0x0060
4150 +#define FE_CDMA_OFFSET 0x0080
4151 +#define FE_DMA_VID0 0x00a8
4152 +#define FE_PDMA_OFFSET 0x0100
4153 +#define FE_PPE_OFFSET 0x0200
4154 +#define FE_CMTABLE_OFFSET 0x0400
4155 +#define FE_POLICYTABLE_OFFSET 0x1000
4156 +
4157 +#define RT5350_PDMA_OFFSET 0x0800
4158 +#define RT5350_SDM_OFFSET 0x0c00
4159 +
4160 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
4161 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
4162 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
4163 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
4164 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
4165 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
4166 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
4167 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
4168 +
4169 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
4170 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
4171 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
4172 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
4173 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
4174 +
4175 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
4176 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
4177 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
4178 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
4179 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
4180 +
4181 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
4182 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
4183 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
4184 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
4185 +
4186 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
4187 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
4188 +
4189 +#define MT7620A_GDMA_OFFSET 0x0600
4190 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
4191 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
4192 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
4193 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
4194 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
4195 +
4196 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
4197 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
4198 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
4199 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
4200 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
4201 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
4202 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
4203 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
4204 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
4205 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
4206 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
4207 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
4208 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
4209 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
4210 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
4211 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
4212 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
4213 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
4214 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
4215 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
4216 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
4217 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
4218 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
4219 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
4220 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
4221 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
4222 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
4223 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
4224 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
4225 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
4226 +
4227 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
4228 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
4229 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
4230 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
4231 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
4232 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
4233 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
4234 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
4235 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
4236 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
4237 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
4238 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
4239 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
4240 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
4241 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
4242 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
4243 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
4244 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
4245 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
4246 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
4247 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
4248 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
4249 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
4250 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
4251 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
4252 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
4253 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
4254 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
4255 +
4256 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
4257 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
4258 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
4259 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
4260 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
4261 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4262 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4263 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4264 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4265 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4266 +
4267 +#define RT5350_SDM_ICS_EN BIT(16)
4268 +#define RT5350_SDM_TCS_EN BIT(17)
4269 +#define RT5350_SDM_UCS_EN BIT(18)
4270 +
4271 +
4272 +/* MDIO_CFG register bits */
4273 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
4274 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
4275 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
4276 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
4277 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
4278 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
4279 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
4280 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
4281 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
4282 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
4283 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
4284 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
4285 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
4286 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
4287 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
4288 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
4289 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
4290 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
4291 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
4292 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
4293 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
4294 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
4295 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
4296 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
4297 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
4298 +
4299 +/* uni-cast port */
4300 +#define FE_GDM1_ICS_EN BIT(22)
4301 +#define FE_GDM1_TCS_EN BIT(21)
4302 +#define FE_GDM1_UCS_EN BIT(20)
4303 +#define FE_GDM1_JMB_EN BIT(19)
4304 +#define FE_GDM1_STRPCRC BIT(16)
4305 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
4306 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
4307 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
4308 +
4309 +/* checksums */
4310 +#define FE_ICS_GEN_EN BIT(2)
4311 +#define FE_UCS_GEN_EN BIT(1)
4312 +#define FE_TCS_GEN_EN BIT(0)
4313 +
4314 +/* dma ring */
4315 +#define FE_PST_DRX_IDX0 BIT(16)
4316 +#define FE_PST_DTX_IDX3 BIT(3)
4317 +#define FE_PST_DTX_IDX2 BIT(2)
4318 +#define FE_PST_DTX_IDX1 BIT(1)
4319 +#define FE_PST_DTX_IDX0 BIT(0)
4320 +
4321 +#define FE_TX_WB_DDONE BIT(6)
4322 +#define FE_RX_DMA_BUSY BIT(3)
4323 +#define FE_TX_DMA_BUSY BIT(1)
4324 +#define FE_RX_DMA_EN BIT(2)
4325 +#define FE_TX_DMA_EN BIT(0)
4326 +
4327 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
4328 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
4329 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
4330 +
4331 +#define FE_US_CYC_CNT_MASK 0xff
4332 +#define FE_US_CYC_CNT_SHIFT 0x8
4333 +#define FE_US_CYC_CNT_DIVISOR 1000000
4334 +
4335 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
4336 +#define RX_DMA_LSO BIT(30)
4337 +#define RX_DMA_DONE BIT(31)
4338 +#define RX_DMA_L4VALID BIT(30)
4339 +
4340 +struct fe_rx_dma {
4341 + unsigned int rxd1;
4342 + unsigned int rxd2;
4343 + unsigned int rxd3;
4344 + unsigned int rxd4;
4345 +} __packed __aligned(4);
4346 +
4347 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
4348 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
4349 +#define TX_DMA_LSO BIT(30)
4350 +#define TX_DMA_DONE BIT(31)
4351 +#define TX_DMA_QN(_x) ((_x) << 16)
4352 +#define TX_DMA_PN(_x) ((_x) << 24)
4353 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
4354 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
4355 +#define TX_DMA_CHKSUM (0x7 << 29)
4356 +
4357 +struct fe_tx_dma {
4358 + unsigned int txd1;
4359 + unsigned int txd2;
4360 + unsigned int txd3;
4361 + unsigned int txd4;
4362 +} __packed __aligned(4);
4363 +
4364 +struct fe_priv;
4365 +
4366 +struct fe_phy {
4367 + struct phy_device *phy[8];
4368 + struct device_node *phy_node[8];
4369 + const __be32 *phy_fixed[8];
4370 + int duplex[8];
4371 + int speed[8];
4372 + int tx_fc[8];
4373 + int rx_fc[8];
4374 + spinlock_t lock;
4375 +
4376 + int (*connect)(struct fe_priv *priv);
4377 + void (*disconnect)(struct fe_priv *priv);
4378 + void (*start)(struct fe_priv *priv);
4379 + void (*stop)(struct fe_priv *priv);
4380 +};
4381 +
4382 +struct fe_soc_data
4383 +{
4384 + unsigned char mac[6];
4385 + const u32 *reg_table;
4386 +
4387 + void (*reset_fe)(void);
4388 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4389 + void (*fwd_config)(struct fe_priv *priv);
4390 + void (*tx_dma)(struct fe_priv *priv, int idx, int len);
4391 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4392 + int (*switch_init)(struct fe_priv *priv);
4393 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
4394 + int (*has_carrier)(struct fe_priv *priv);
4395 + int (*mdio_init)(struct fe_priv *priv);
4396 + void (*mdio_cleanup)(struct fe_priv *priv);
4397 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4398 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4399 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4400 +
4401 + void *swpriv;
4402 + u32 pdma_glo_cfg;
4403 + u32 rx_dly_int;
4404 + u32 tx_dly_int;
4405 + u32 checksum_bit;
4406 +
4407 + int min_pkt_len;
4408 +};
4409 +
4410 +struct fe_priv
4411 +{
4412 + spinlock_t page_lock;
4413 +
4414 + struct fe_soc_data *soc;
4415 + struct net_device *netdev;
4416 + struct device *device;
4417 + unsigned long sysclk;
4418 +
4419 + struct fe_rx_dma *rx_dma;
4420 + struct napi_struct rx_napi;
4421 + struct sk_buff *rx_skb[NUM_DMA_DESC];
4422 + dma_addr_t rx_phys;
4423 +
4424 + struct fe_tx_dma *tx_dma;
4425 + struct tasklet_struct tx_tasklet;
4426 + struct sk_buff *tx_skb[NUM_DMA_DESC];
4427 + dma_addr_t tx_phys;
4428 + unsigned int tx_free_idx;
4429 +
4430 + struct fe_phy *phy;
4431 + struct mii_bus *mii_bus;
4432 + int mii_irq[PHY_MAX_ADDR];
4433 +
4434 + int link[8];
4435 +};
4436 +
4437 +extern const struct of_device_id of_fe_match[];
4438 +
4439 +void fe_w32(u32 val, unsigned reg);
4440 +u32 fe_r32(unsigned reg);
4441 +
4442 +#endif /* FE_ETH_H */
4443 diff --git a/drivers/net/ethernet/ralink/soc_mt7620.c b/drivers/net/ethernet/ralink/soc_mt7620.c
4444 new file mode 100644
4445 index 0000000..55e303f
4446 --- /dev/null
4447 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4448 @@ -0,0 +1,111 @@
4449 +/*
4450 + * This program is free software; you can redistribute it and/or modify
4451 + * it under the terms of the GNU General Public License as published by
4452 + * the Free Software Foundation; version 2 of the License
4453 + *
4454 + * This program is distributed in the hope that it will be useful,
4455 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4456 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4457 + * GNU General Public License for more details.
4458 + *
4459 + * You should have received a copy of the GNU General Public License
4460 + * along with this program; if not, write to the Free Software
4461 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4462 + *
4463 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4464 + */
4465 +
4466 +#include <linux/module.h>
4467 +#include <linux/platform_device.h>
4468 +
4469 +#include <asm/mach-ralink/ralink_regs.h>
4470 +
4471 +#include "ralink_soc_eth.h"
4472 +#include "gsw_mt7620a.h"
4473 +
4474 +#define MT7620A_CDMA_CSG_CFG 0x400
4475 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
4476 +#define MT7620A_DMA_2B_OFFSET BIT(31)
4477 +#define MT7620A_RESET_FE BIT(21)
4478 +#define MT7620A_RESET_ESW BIT(23)
4479 +#define MT7620_L4_VALID BIT(23)
4480 +
4481 +#define SYSC_REG_RESET_CTRL 0x34
4482 +#define MAX_RX_LENGTH 1536
4483 +
4484 +#define CDMA_ICS_EN BIT(2)
4485 +#define CDMA_UCS_EN BIT(1)
4486 +#define CDMA_TCS_EN BIT(0)
4487 +
4488 +#define GDMA_ICS_EN BIT(22)
4489 +#define GDMA_TCS_EN BIT(21)
4490 +#define GDMA_UCS_EN BIT(20)
4491 +
4492 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4493 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4494 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4495 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4496 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4497 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4498 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4499 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4500 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4501 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4502 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4503 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4504 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4505 +};
4506 +
4507 +static void mt7620_fe_reset(void)
4508 +{
4509 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4510 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4511 +}
4512 +
4513 +static void mt7620_fwd_config(struct fe_priv *priv)
4514 +{
4515 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4516 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4517 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4518 +}
4519 +
4520 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
4521 +{
4522 + if (len)
4523 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4524 + else
4525 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4526 +}
4527 +
4528 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4529 +{
4530 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4531 +}
4532 +
4533 +static struct fe_soc_data mt7620_data = {
4534 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4535 + .reset_fe = mt7620_fe_reset,
4536 + .set_mac = mt7620_set_mac,
4537 + .fwd_config = mt7620_fwd_config,
4538 + .tx_dma = mt7620_tx_dma,
4539 + .rx_dma = mt7620_rx_dma,
4540 + .switch_init = mt7620_gsw_probe,
4541 + .port_init = mt7620_port_init,
4542 + .min_pkt_len = 0,
4543 + .reg_table = rt5350_reg_table,
4544 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4545 + .rx_dly_int = RT5350_RX_DLY_INT,
4546 + .tx_dly_int = RT5350_TX_DLY_INT,
4547 + .checksum_bit = MT7620_L4_VALID,
4548 + .has_carrier = mt7620a_has_carrier,
4549 + .mdio_read = mt7620_mdio_read,
4550 + .mdio_write = mt7620_mdio_write,
4551 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4552 +};
4553 +
4554 +const struct of_device_id of_fe_match[] = {
4555 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4556 + {},
4557 +};
4558 +
4559 +MODULE_DEVICE_TABLE(of, of_fe_match);
4560 diff --git a/drivers/net/ethernet/ralink/soc_rt2880.c b/drivers/net/ethernet/ralink/soc_rt2880.c
4561 new file mode 100644
4562 index 0000000..1110947
4563 --- /dev/null
4564 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4565 @@ -0,0 +1,51 @@
4566 +/*
4567 + * This program is free software; you can redistribute it and/or modify
4568 + * it under the terms of the GNU General Public License as published by
4569 + * the Free Software Foundation; version 2 of the License
4570 + *
4571 + * This program is distributed in the hope that it will be useful,
4572 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4573 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4574 + * GNU General Public License for more details.
4575 + *
4576 + * You should have received a copy of the GNU General Public License
4577 + * along with this program; if not, write to the Free Software
4578 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4579 + *
4580 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4581 + */
4582 +
4583 +#include <linux/module.h>
4584 +
4585 +#include <asm/mach-ralink/ralink_regs.h>
4586 +
4587 +#include "ralink_soc_eth.h"
4588 +#include "mdio_rt2880.h"
4589 +
4590 +#define SYSC_REG_RESET_CTRL 0x034
4591 +#define RT2880_RESET_FE BIT(18)
4592 +
4593 +void rt2880_fe_reset(void)
4594 +{
4595 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4596 +}
4597 +
4598 +struct fe_soc_data rt2880_data = {
4599 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4600 + .reset_fe = rt2880_fe_reset,
4601 + .min_pkt_len = 64,
4602 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4603 + .checksum_bit = RX_DMA_L4VALID,
4604 + .rx_dly_int = FE_RX_DLY_INT,
4605 + .tx_dly_int = FE_TX_DLY_INT,
4606 + .mdio_read = rt2880_mdio_read,
4607 + .mdio_write = rt2880_mdio_write,
4608 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4609 +};
4610 +
4611 +const struct of_device_id of_fe_match[] = {
4612 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4613 + {},
4614 +};
4615 +
4616 +MODULE_DEVICE_TABLE(of, of_fe_match);
4617 diff --git a/drivers/net/ethernet/ralink/soc_rt305x.c b/drivers/net/ethernet/ralink/soc_rt305x.c
4618 new file mode 100644
4619 index 0000000..482ca1f
4620 --- /dev/null
4621 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4622 @@ -0,0 +1,113 @@
4623 +/*
4624 + * This program is free software; you can redistribute it and/or modify
4625 + * it under the terms of the GNU General Public License as published by
4626 + * the Free Software Foundation; version 2 of the License
4627 + *
4628 + * This program is distributed in the hope that it will be useful,
4629 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4630 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4631 + * GNU General Public License for more details.
4632 + *
4633 + * You should have received a copy of the GNU General Public License
4634 + * along with this program; if not, write to the Free Software
4635 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4636 + *
4637 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4638 + */
4639 +
4640 +#include <linux/module.h>
4641 +
4642 +#include <asm/mach-ralink/ralink_regs.h>
4643 +
4644 +#include "ralink_soc_eth.h"
4645 +
4646 +#define RT305X_RESET_FE BIT(21)
4647 +#define RT305X_RESET_ESW BIT(23)
4648 +#define SYSC_REG_RESET_CTRL 0x034
4649 +
4650 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4651 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4652 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4653 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4654 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4655 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4656 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4657 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4658 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4659 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4660 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4661 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4662 + [FE_REG_FE_DMA_VID_BASE] = 0,
4663 +};
4664 +
4665 +static void rt305x_fe_reset(void)
4666 +{
4667 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4668 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4669 +}
4670 +
4671 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4672 +{
4673 + unsigned long flags;
4674 +
4675 + spin_lock_irqsave(&priv->page_lock, flags);
4676 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4677 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4678 + RT5350_SDM_MAC_ADRL);
4679 + spin_unlock_irqrestore(&priv->page_lock, flags);
4680 +}
4681 +
4682 +static void rt5350_fwd_config(struct fe_priv *priv)
4683 +{
4684 + unsigned long sysclk = priv->sysclk;
4685 +
4686 + if (sysclk) {
4687 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4688 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4689 +
4690 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4691 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4692 + FE_FE_GLO_CFG);
4693 + }
4694 +
4695 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4696 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4697 + RT5350_SDM_CFG);
4698 +}
4699 +
4700 +static void rt5350_fe_reset(void)
4701 +{
4702 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4703 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4704 +}
4705 +
4706 +static struct fe_soc_data rt3050_data = {
4707 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4708 + .reset_fe = rt305x_fe_reset,
4709 + .min_pkt_len = 64,
4710 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4711 + .checksum_bit = RX_DMA_L4VALID,
4712 + .rx_dly_int = FE_RX_DLY_INT,
4713 + .tx_dly_int = FE_TX_DLY_INT,
4714 +};
4715 +
4716 +static struct fe_soc_data rt5350_data = {
4717 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4718 + .reg_table = rt5350_reg_table,
4719 + .reset_fe = rt5350_fe_reset,
4720 + .set_mac = rt5350_set_mac,
4721 + .fwd_config = rt5350_fwd_config,
4722 + .min_pkt_len = 64,
4723 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4724 + .checksum_bit = RX_DMA_L4VALID,
4725 + .rx_dly_int = RT5350_RX_DLY_INT,
4726 + .tx_dly_int = RT5350_TX_DLY_INT,
4727 +};
4728 +
4729 +const struct of_device_id of_fe_match[] = {
4730 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4731 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4732 + {},
4733 +};
4734 +
4735 +MODULE_DEVICE_TABLE(of, of_fe_match);
4736 diff --git a/drivers/net/ethernet/ralink/soc_rt3883.c b/drivers/net/ethernet/ralink/soc_rt3883.c
4737 new file mode 100644
4738 index 0000000..c660529
4739 --- /dev/null
4740 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
4741 @@ -0,0 +1,60 @@
4742 +/*
4743 + * This program is free software; you can redistribute it and/or modify
4744 + * it under the terms of the GNU General Public License as published by
4745 + * the Free Software Foundation; version 2 of the License
4746 + *
4747 + * This program is distributed in the hope that it will be useful,
4748 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4749 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4750 + * GNU General Public License for more details.
4751 + *
4752 + * You should have received a copy of the GNU General Public License
4753 + * along with this program; if not, write to the Free Software
4754 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4755 + *
4756 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4757 + */
4758 +
4759 +#include <linux/module.h>
4760 +
4761 +#include <asm/mach-ralink/ralink_regs.h>
4762 +
4763 +#include "ralink_soc_eth.h"
4764 +#include "mdio_rt2880.h"
4765 +
4766 +#define RT3883_SYSC_REG_RSTCTRL 0x34
4767 +#define RT3883_RSTCTRL_FE BIT(21)
4768 +
4769 +static void rt3883_fe_reset(void)
4770 +{
4771 + u32 t;
4772 +
4773 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4774 + t |= RT3883_RSTCTRL_FE;
4775 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4776 +
4777 + t &= ~RT3883_RSTCTRL_FE;
4778 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4779 +}
4780 +
4781 +static struct fe_soc_data rt3883_data = {
4782 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4783 + .reset_fe = rt3883_fe_reset,
4784 + .min_pkt_len = 64,
4785 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4786 + .rx_dly_int = FE_RX_DLY_INT,
4787 + .tx_dly_int = FE_TX_DLY_INT,
4788 + .checksum_bit = RX_DMA_L4VALID,
4789 + .mdio_read = rt2880_mdio_read,
4790 + .mdio_write = rt2880_mdio_write,
4791 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4792 + .port_init = rt2880_port_init,
4793 +};
4794 +
4795 +const struct of_device_id of_fe_match[] = {
4796 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4797 + {},
4798 +};
4799 +
4800 +MODULE_DEVICE_TABLE(of, of_fe_match);
4801 +
4802 --
4803 1.7.10.4
4804
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