ralink: bump to the target to v4.3
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-4.3 / 0001-arch-mips-ralink-add-mt7621-support.patch
1 From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 7 Dec 2015 17:08:31 +0100
4 Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/mach-ralink/irq.h | 9 +
9 arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
10 arch/mips/kernel/mips-cm.c | 4 +-
11 arch/mips/kernel/vmlinux.lds.S | 1 +
12 arch/mips/ralink/Kconfig | 18 ++
13 arch/mips/ralink/Makefile | 7 +-
14 arch/mips/ralink/Platform | 5 +
15 arch/mips/ralink/irq-gic.c | 268 ++++++++++++++++++++++++++++
16 arch/mips/ralink/malta-amon.c | 81 +++++++++
17 arch/mips/ralink/mt7621.c | 209 ++++++++++++++++++++++
18 10 files changed, 638 insertions(+), 3 deletions(-)
19 create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
20 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
21 create mode 100644 arch/mips/ralink/irq-gic.c
22 create mode 100644 arch/mips/ralink/malta-amon.c
23 create mode 100644 arch/mips/ralink/mt7621.c
24
25 diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h
26 new file mode 100644
27 index 0000000..4321865
28 --- /dev/null
29 +++ b/arch/mips/include/asm/mach-ralink/irq.h
30 @@ -0,0 +1,9 @@
31 +#ifndef __ASM_MACH_RALINK_IRQ_H
32 +#define __ASM_MACH_RALINK_IRQ_H
33 +
34 +#define GIC_NUM_INTRS 64
35 +#define NR_IRQS 256
36 +
37 +#include_next <irq.h>
38 +
39 +#endif
40 diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
41 new file mode 100644
42 index 0000000..21c8dc2
43 --- /dev/null
44 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
45 @@ -0,0 +1,39 @@
46 +/*
47 + * This program is free software; you can redistribute it and/or modify it
48 + * under the terms of the GNU General Public License version 2 as published
49 + * by the Free Software Foundation.
50 + *
51 + * Parts of this file are based on Ralink's 2.6.21 BSP
52 + *
53 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
54 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
55 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
56 + */
57 +
58 +#ifndef _MT7621_REGS_H_
59 +#define _MT7621_REGS_H_
60 +
61 +#define MT7621_SYSC_BASE 0x1E000000
62 +
63 +#define SYSC_REG_CHIP_NAME0 0x00
64 +#define SYSC_REG_CHIP_NAME1 0x04
65 +#define SYSC_REG_CHIP_REV 0x0c
66 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
67 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
68 +
69 +#define CHIP_REV_PKG_MASK 0x1
70 +#define CHIP_REV_PKG_SHIFT 16
71 +#define CHIP_REV_VER_MASK 0xf
72 +#define CHIP_REV_VER_SHIFT 8
73 +#define CHIP_REV_ECO_MASK 0xf
74 +
75 +#define MT7621_DRAM_BASE 0x0
76 +#define MT7621_DDR2_SIZE_MIN 32
77 +#define MT7621_DDR2_SIZE_MAX 256
78 +
79 +#define MT7621_CHIP_NAME0 0x3637544D
80 +#define MT7621_CHIP_NAME1 0x20203132
81 +
82 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
83 +
84 +#endif
85 diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
86 index b8ceee5..b97de1d 100644
87 --- a/arch/mips/kernel/mips-cm.c
88 +++ b/arch/mips/kernel/mips-cm.c
89 @@ -232,7 +232,7 @@ int mips_cm_probe(void)
90 write_gcr_base(base_reg);
91
92 /* disable CM regions */
93 - write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
94 +/* write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
95 write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
96 write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
97 write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
98 @@ -240,7 +240,7 @@ int mips_cm_probe(void)
99 write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
100 write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
101 write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
102 -
103 +*/
104 /* probe for an L2-only sync region */
105 mips_cm_probe_l2sync();
106
107 diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
108 index 07d32a4..86c6284 100644
109 --- a/arch/mips/kernel/vmlinux.lds.S
110 +++ b/arch/mips/kernel/vmlinux.lds.S
111 @@ -51,6 +51,7 @@ SECTIONS
112 /* read-only */
113 _text = .; /* Text and read-only data */
114 .text : {
115 + /*. = . + 0x8000; */
116 TEXT_TEXT
117 SCHED_TEXT
118 LOCK_TEXT
119 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
120 index e9bc8c9..d078e61 100644
121 --- a/arch/mips/ralink/Kconfig
122 +++ b/arch/mips/ralink/Kconfig
123 @@ -12,6 +12,11 @@ config RALINK_ILL_ACC
124 depends on SOC_RT305X
125 default y
126
127 +config IRQ_INTC
128 + bool
129 + default y
130 + depends on !SOC_MT7621
131 +
132 choice
133 prompt "Ralink SoC selection"
134 default SOC_RT305X
135 @@ -34,6 +39,15 @@ choice
136 config SOC_MT7620
137 bool "MT7620/8"
138
139 + config SOC_MT7621
140 + bool "MT7621"
141 + select MIPS_CPU_SCACHE
142 + select SYS_SUPPORTS_MULTITHREADING
143 + select SYS_SUPPORTS_SMP
144 + select SYS_SUPPORTS_MIPS_CMP
145 + select IRQ_GIC
146 + select HW_HAS_PCI
147 +
148 endchoice
149
150 choice
151 @@ -65,6 +79,10 @@ choice
152 depends on SOC_MT7620
153 select BUILTIN_DTB
154
155 + config DTB_MT7621_EVAL
156 + bool "MT7621 eval kit"
157 + depends on SOC_MT7621
158 +
159 endchoice
160
161 endif
162 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
163 index a6c9d00..ca501db 100644
164 --- a/arch/mips/ralink/Makefile
165 +++ b/arch/mips/ralink/Makefile
166 @@ -6,16 +6,21 @@
167 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
168 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
169
170 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
171 +obj-y := prom.o of.o reset.o clk.o timer.o
172
173 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
174
175 obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
176
177 +obj-$(CONFIG_IRQ_INTC) += irq.o
178 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
179 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
180 +
181 obj-$(CONFIG_SOC_RT288X) += rt288x.o
182 obj-$(CONFIG_SOC_RT305X) += rt305x.o
183 obj-$(CONFIG_SOC_RT3883) += rt3883.o
184 obj-$(CONFIG_SOC_MT7620) += mt7620.o
185 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
186
187 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
188
189 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
190 index 6d9c8c4..6095fcc 100644
191 --- a/arch/mips/ralink/Platform
192 +++ b/arch/mips/ralink/Platform
193 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt
194 #
195 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
196 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
197 +
198 +# Ralink MT7621
199 +#
200 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
201 +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
202 diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c
203 new file mode 100644
204 index 0000000..f1c541b
205 --- /dev/null
206 +++ b/arch/mips/ralink/irq-gic.c
207 @@ -0,0 +1,268 @@
208 +#include <linux/init.h>
209 +#include <linux/sched.h>
210 +#include <linux/slab.h>
211 +#include <linux/interrupt.h>
212 +#include <linux/kernel_stat.h>
213 +#include <linux/hardirq.h>
214 +#include <linux/preempt.h>
215 +#include <linux/irqdomain.h>
216 +#include <linux/of_platform.h>
217 +#include <linux/of_address.h>
218 +#include <linux/of_irq.h>
219 +
220 +#include <asm/irq_cpu.h>
221 +#include <asm/mipsregs.h>
222 +
223 +#include <asm/irq.h>
224 +#include <asm/setup.h>
225 +
226 +#include <asm/gic.h>
227 +
228 +#include <asm/mach-ralink/mt7621.h>
229 +#define GIC_BASE_ADDR 0x1fbc0000
230 +
231 +unsigned long _gcmp_base;
232 +static int gic_resched_int_base = 56;
233 +static int gic_call_int_base = 60;
234 +static struct irq_chip *irq_gic;
235 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
236 +
237 +#if defined(CONFIG_MIPS_MT_SMP)
238 +static int gic_resched_int_base;
239 +static int gic_call_int_base;
240 +
241 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
242 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
243 +
244 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
245 +{
246 + scheduler_ipi();
247 +
248 + return IRQ_HANDLED;
249 +}
250 +
251 +static irqreturn_t
252 +ipi_call_interrupt(int irq, void *dev_id)
253 +{
254 + smp_call_function_interrupt();
255 +
256 + return IRQ_HANDLED;
257 +}
258 +
259 +static struct irqaction irq_resched = {
260 + .handler = ipi_resched_interrupt,
261 + .flags = IRQF_DISABLED|IRQF_PERCPU,
262 + .name = "ipi resched"
263 +};
264 +
265 +static struct irqaction irq_call = {
266 + .handler = ipi_call_interrupt,
267 + .flags = IRQF_DISABLED|IRQF_PERCPU,
268 + .name = "ipi call"
269 +};
270 +
271 +#endif
272 +
273 +static void __init
274 +gic_fill_map(void)
275 +{
276 + int i;
277 +
278 + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
279 + gic_intr_map[i].cpunum = 0;
280 + gic_intr_map[i].pin = GIC_CPU_INT0;
281 + gic_intr_map[i].polarity = GIC_POL_POS;
282 + gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
283 + gic_intr_map[i].flags = 0;
284 + }
285 +
286 +#if defined(CONFIG_MIPS_MT_SMP)
287 + {
288 + int cpu;
289 +
290 + gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
291 + gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
292 +
293 + i = gic_resched_int_base;
294 +
295 + for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
296 + gic_intr_map[i + cpu].cpunum = cpu;
297 + gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
298 + gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
299 +
300 + gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
301 + gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
302 + gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
303 + }
304 + }
305 +#endif
306 +}
307 +
308 +void
309 +gic_irq_ack(struct irq_data *d)
310 +{
311 + int irq = (d->irq - gic_irq_base);
312 +
313 + GIC_CLR_INTR_MASK(irq);
314 +
315 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
316 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
317 +}
318 +
319 +void
320 +gic_finish_irq(struct irq_data *d)
321 +{
322 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
323 +}
324 +
325 +void __init
326 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
327 +{
328 + irq_gic = irq_controller;
329 +}
330 +
331 +static void
332 +gic_irqdispatch(void)
333 +{
334 + unsigned int irq = gic_get_int();
335 +
336 + if (likely(irq < GIC_NUM_INTRS))
337 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
338 + else {
339 + pr_debug("Spurious GIC Interrupt!\n");
340 + spurious_interrupt();
341 + }
342 +
343 +}
344 +
345 +static void
346 +vi_timer_irqdispatch(void)
347 +{
348 + do_IRQ(cp0_compare_irq);
349 +}
350 +
351 +#if defined(CONFIG_MIPS_MT_SMP)
352 +unsigned int
353 +plat_ipi_call_int_xlate(unsigned int cpu)
354 +{
355 + return GIC_CALL_INT(cpu);
356 +}
357 +
358 +unsigned int
359 +plat_ipi_resched_int_xlate(unsigned int cpu)
360 +{
361 + return GIC_RESCHED_INT(cpu);
362 +}
363 +#endif
364 +
365 +asmlinkage void
366 +plat_irq_dispatch(void)
367 +{
368 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
369 +
370 + if (unlikely(!pending)) {
371 + pr_err("Spurious CP0 Interrupt!\n");
372 + spurious_interrupt();
373 + } else {
374 + if (pending & CAUSEF_IP7)
375 + do_IRQ(cp0_compare_irq);
376 +
377 + if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
378 + gic_irqdispatch();
379 + }
380 +}
381 +
382 +unsigned int __cpuinit
383 +get_c0_compare_int(void)
384 +{
385 + return CP0_LEGACY_COMPARE_IRQ;
386 +}
387 +
388 +static int
389 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
390 +{
391 + irq_set_chip_and_handler(irq, irq_gic,
392 +#if defined(CONFIG_MIPS_MT_SMP)
393 + (hw >= gic_resched_int_base) ?
394 + handle_percpu_irq :
395 +#endif
396 + handle_level_irq);
397 +
398 + return 0;
399 +}
400 +
401 +static const struct irq_domain_ops irq_domain_ops = {
402 + .xlate = irq_domain_xlate_onecell,
403 + .map = gic_map,
404 +};
405 +
406 +static int __init
407 +of_gic_init(struct device_node *node,
408 + struct device_node *parent)
409 +{
410 + struct irq_domain *domain;
411 + struct resource gcmp = { 0 }, gic = { 0 };
412 + unsigned int gic_rev;
413 + int i;
414 +
415 + if (of_address_to_resource(node, 0, &gic))
416 + panic("Failed to get gic memory range");
417 + if (request_mem_region(gic.start, resource_size(&gic),
418 + gic.name) < 0)
419 + panic("Failed to request gic memory");
420 + if (of_address_to_resource(node, 2, &gcmp))
421 + panic("Failed to get gic memory range");
422 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
423 + gcmp.name) < 0)
424 + panic("Failed to request gcmp memory");
425 +
426 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
427 + if (!_gcmp_base)
428 + panic("Failed to remap gcmp memory\n");
429 +
430 + /* tell the gcmp where to find the gic */
431 + write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
432 + gic_present = 1;
433 + if (cpu_has_vint) {
434 + set_vi_handler(2, gic_irqdispatch);
435 + set_vi_handler(3, gic_irqdispatch);
436 + set_vi_handler(4, gic_irqdispatch);
437 + set_vi_handler(7, vi_timer_irqdispatch);
438 + }
439 +
440 + gic_fill_map();
441 +
442 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
443 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
444 +
445 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
446 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
447 +
448 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
449 + 0, &irq_domain_ops, NULL);
450 + if (!domain)
451 + panic("Failed to add irqdomain");
452 +
453 +#if defined(CONFIG_MIPS_MT_SMP)
454 + for (i = 0; i < nr_cpu_ids; i++) {
455 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
456 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
457 + }
458 +#endif
459 +
460 + change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
461 + STATUSF_IP2);
462 + return 0;
463 +}
464 +
465 +static struct of_device_id __initdata of_irq_ids[] = {
466 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
467 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
468 + {},
469 +};
470 +
471 +void __init
472 +arch_init_irq(void)
473 +{
474 + of_irq_init(of_irq_ids);
475 +}
476 diff --git a/arch/mips/ralink/malta-amon.c b/arch/mips/ralink/malta-amon.c
477 new file mode 100644
478 index 0000000..1e47844
479 --- /dev/null
480 +++ b/arch/mips/ralink/malta-amon.c
481 @@ -0,0 +1,81 @@
482 +/*
483 + * Copyright (C) 2007 MIPS Technologies, Inc.
484 + * All rights reserved.
485 +
486 + * This program is free software; you can distribute it and/or modify it
487 + * under the terms of the GNU General Public License (Version 2) as
488 + * published by the Free Software Foundation.
489 + *
490 + * This program is distributed in the hope it will be useful, but WITHOUT
491 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
492 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
493 + * for more details.
494 + *
495 + * You should have received a copy of the GNU General Public License along
496 + * with this program; if not, write to the Free Software Foundation, Inc.,
497 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
498 + *
499 + * Arbitrary Monitor interface
500 + */
501 +
502 +#include <linux/kernel.h>
503 +#include <linux/init.h>
504 +#include <linux/smp.h>
505 +
506 +#include <asm/addrspace.h>
507 +#include <asm/mips-boards/launch.h>
508 +#include <asm/mipsmtregs.h>
509 +
510 +int amon_cpu_avail(int cpu)
511 +{
512 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
513 +
514 + if (cpu < 0 || cpu >= NCPULAUNCH) {
515 + pr_debug("avail: cpu%d is out of range\n", cpu);
516 + return 0;
517 + }
518 +
519 + launch += cpu;
520 + if (!(launch->flags & LAUNCH_FREADY)) {
521 + pr_debug("avail: cpu%d is not ready\n", cpu);
522 + return 0;
523 + }
524 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
525 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
526 + return 0;
527 + }
528 +
529 + return 1;
530 +}
531 +
532 +void amon_cpu_start(int cpu,
533 + unsigned long pc, unsigned long sp,
534 + unsigned long gp, unsigned long a0)
535 +{
536 + volatile struct cpulaunch *launch =
537 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
538 +
539 + if (!amon_cpu_avail(cpu))
540 + return;
541 + if (cpu == smp_processor_id()) {
542 + pr_debug("launch: I am cpu%d!\n", cpu);
543 + return;
544 + }
545 + launch += cpu;
546 +
547 + pr_debug("launch: starting cpu%d\n", cpu);
548 +
549 + launch->pc = pc;
550 + launch->gp = gp;
551 + launch->sp = sp;
552 + launch->a0 = a0;
553 +
554 + smp_wmb(); /* Target must see parameters before go */
555 + launch->flags |= LAUNCH_FGO;
556 + smp_wmb(); /* Target must see go before we poll */
557 +
558 + while ((launch->flags & LAUNCH_FGONE) == 0)
559 + ;
560 + smp_rmb(); /* Target will be updating flags soon */
561 + pr_debug("launch: cpu%d gone!\n", cpu);
562 +}
563 diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
564 new file mode 100644
565 index 0000000..c28743b
566 --- /dev/null
567 +++ b/arch/mips/ralink/mt7621.c
568 @@ -0,0 +1,209 @@
569 +/*
570 + * This program is free software; you can redistribute it and/or modify it
571 + * under the terms of the GNU General Public License version 2 as published
572 + * by the Free Software Foundation.
573 + *
574 + * Parts of this file are based on Ralink's 2.6.21 BSP
575 + *
576 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
577 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
578 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
579 + */
580 +
581 +#include <linux/kernel.h>
582 +#include <linux/init.h>
583 +#include <linux/module.h>
584 +
585 +#include <asm/mipsregs.h>
586 +#include <asm/smp-ops.h>
587 +#include <asm/mips-cm.h>
588 +#include <asm/mips-cpc.h>
589 +#include <asm/mach-ralink/ralink_regs.h>
590 +#include <asm/mach-ralink/mt7621.h>
591 +
592 +#include <pinmux.h>
593 +
594 +#include "common.h"
595 +
596 +#define SYSC_REG_SYSCFG 0x10
597 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
598 +#define SYSC_REG_CUR_CLK_STS 0x44
599 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
600 +
601 +#define MT7621_GPIO_MODE_UART1 1
602 +#define MT7621_GPIO_MODE_I2C 2
603 +#define MT7621_GPIO_MODE_UART3_MASK 0x3
604 +#define MT7621_GPIO_MODE_UART3_SHIFT 3
605 +#define MT7621_GPIO_MODE_UART3_GPIO 1
606 +#define MT7621_GPIO_MODE_UART2_MASK 0x3
607 +#define MT7621_GPIO_MODE_UART2_SHIFT 5
608 +#define MT7621_GPIO_MODE_UART2_GPIO 1
609 +#define MT7621_GPIO_MODE_JTAG 7
610 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
611 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
612 +#define MT7621_GPIO_MODE_WDT_GPIO 1
613 +#define MT7621_GPIO_MODE_PCIE_RST 0
614 +#define MT7621_GPIO_MODE_PCIE_REF 2
615 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
616 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
617 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
618 +#define MT7621_GPIO_MODE_MDIO_MASK 0x3
619 +#define MT7621_GPIO_MODE_MDIO_SHIFT 12
620 +#define MT7621_GPIO_MODE_MDIO_GPIO 1
621 +#define MT7621_GPIO_MODE_RGMII1 14
622 +#define MT7621_GPIO_MODE_RGMII2 15
623 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
624 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
625 +#define MT7621_GPIO_MODE_SPI_GPIO 1
626 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
627 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
628 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
629 +
630 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
631 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
632 +static struct rt2880_pmx_func uart3_grp[] = {
633 + FUNC("uart3", 0, 5, 4),
634 + FUNC("i2s", 2, 5, 4),
635 + FUNC("spdif3", 3, 5, 4),
636 +};
637 +static struct rt2880_pmx_func uart2_grp[] = {
638 + FUNC("uart2", 0, 9, 4),
639 + FUNC("pcm", 2, 9, 4),
640 + FUNC("spdif2", 3, 9, 4),
641 +};
642 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
643 +static struct rt2880_pmx_func wdt_grp[] = {
644 + FUNC("wdt rst", 0, 18, 1),
645 + FUNC("wdt refclk", 2, 18, 1),
646 +};
647 +static struct rt2880_pmx_func pcie_rst_grp[] = {
648 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
649 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
650 +};
651 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
652 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
653 +static struct rt2880_pmx_func spi_grp[] = {
654 + FUNC("spi", 0, 34, 7),
655 + FUNC("nand1", 2, 34, 7),
656 +};
657 +static struct rt2880_pmx_func sdhci_grp[] = {
658 + FUNC("sdhci", 0, 41, 8),
659 + FUNC("nand2", 2, 41, 8),
660 +};
661 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
662 +
663 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
664 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
665 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
666 + GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
667 + MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
668 + GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
669 + MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
670 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
671 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
672 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
673 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
674 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
675 + GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
676 + MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
677 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
678 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
679 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
680 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
681 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
682 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
683 + { 0 }
684 +};
685 +
686 +void __init ralink_clk_init(void)
687 +{
688 + int cpu_fdiv = 0;
689 + int cpu_ffrac = 0;
690 + int fbdiv = 0;
691 + u32 clk_sts, syscfg;
692 + u8 clk_sel = 0, xtal_mode;
693 + u32 cpu_clk;
694 +
695 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
696 + clk_sel = 1;
697 +
698 + switch (clk_sel) {
699 + case 0:
700 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
701 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
702 + cpu_ffrac = (clk_sts & 0x1F);
703 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
704 + break;
705 +
706 + case 1:
707 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
708 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
709 + xtal_mode = (syscfg >> 6) & 0x7;
710 + if(xtal_mode >= 6) { //25Mhz Xtal
711 + cpu_clk = 25 * fbdiv * 1000 * 1000;
712 + } else if(xtal_mode >=3) { //40Mhz Xtal
713 + cpu_clk = 40 * fbdiv * 1000 * 1000;
714 + } else { // 20Mhz Xtal
715 + cpu_clk = 20 * fbdiv * 1000 * 1000;
716 + }
717 + break;
718 + }
719 + cpu_clk = 880000000;
720 + ralink_clk_add("cpu", cpu_clk);
721 + ralink_clk_add("1e000b00.spi", 50000000);
722 + ralink_clk_add("1e000c00.uartlite", 50000000);
723 + ralink_clk_add("1e000d00.uart", 50000000);
724 +}
725 +
726 +void __init ralink_of_remap(void)
727 +{
728 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
729 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
730 +
731 + if (!rt_sysc_membase || !rt_memc_membase)
732 + panic("Failed to remap core resources");
733 +}
734 +
735 +void prom_soc_init(struct ralink_soc_info *soc_info)
736 +{
737 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
738 + unsigned char *name = NULL;
739 + u32 n0;
740 + u32 n1;
741 + u32 rev;
742 +
743 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
744 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
745 +
746 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
747 + name = "MT7621";
748 + soc_info->compatible = "mtk,mt7621-soc";
749 + } else {
750 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
751 + }
752 +
753 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
754 +
755 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
756 + "MediaTek %s ver:%u eco:%u",
757 + name,
758 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
759 + (rev & CHIP_REV_ECO_MASK));
760 +
761 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
762 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
763 + soc_info->mem_base = MT7621_DRAM_BASE;
764 +
765 + rt2880_pinmux_data = mt7621_pinmux_data;
766 +
767 + /* Early detection of CMP support */
768 + mips_cm_probe();
769 + mips_cpc_probe();
770 +
771 + if (!register_cps_smp_ops())
772 + return;
773 + if (!register_cmp_smp_ops())
774 + return;
775 + if (!register_vsmp_smp_ops())
776 + return;
777 +}
778 --
779 1.7.10.4
780