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ramips: fix subtarget kernel version assignment (only mt7621 is ready for now)
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-4.3 / 0039-mtd-add-mt7621-nand-support.patch
1 From 0e1c4e3c97b83b4e7da65b1c56f0a7d40736ac53 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:05:17 +0100
4 Subject: [PATCH 39/53] mtd: add mt7621 nand support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mtd/nand/Kconfig | 6 +
9 drivers/mtd/nand/Makefile | 1 +
10 drivers/mtd/nand/bmt.c | 750 ++++++++++++
11 drivers/mtd/nand/bmt.h | 80 ++
12 drivers/mtd/nand/dev-nand.c | 63 +
13 drivers/mtd/nand/mt6575_typedefs.h | 340 ++++++
14 drivers/mtd/nand/mtk_nand.c | 2304 +++++++++++++++++++++++++++++++++++
15 drivers/mtd/nand/mtk_nand.h | 452 +++++++
16 drivers/mtd/nand/nand_base.c | 6 +-
17 drivers/mtd/nand/nand_bbt.c | 19 +
18 drivers/mtd/nand/nand_def.h | 123 ++
19 drivers/mtd/nand/nand_device_list.h | 55 +
20 drivers/mtd/nand/partition.h | 115 ++
21 13 files changed, 4311 insertions(+), 3 deletions(-)
22 create mode 100644 drivers/mtd/nand/bmt.c
23 create mode 100644 drivers/mtd/nand/bmt.h
24 create mode 100644 drivers/mtd/nand/dev-nand.c
25 create mode 100644 drivers/mtd/nand/mt6575_typedefs.h
26 create mode 100644 drivers/mtd/nand/mtk_nand.c
27 create mode 100644 drivers/mtd/nand/mtk_nand.h
28 create mode 100644 drivers/mtd/nand/nand_def.h
29 create mode 100644 drivers/mtd/nand/nand_device_list.h
30 create mode 100644 drivers/mtd/nand/partition.h
31
32 --- a/drivers/mtd/nand/Kconfig
33 +++ b/drivers/mtd/nand/Kconfig
34 @@ -535,4 +535,10 @@ config MTD_NAND_HISI504
35 help
36 Enables support for NAND controller on Hisilicon SoC Hip04.
37
38 +config MTK_MTD_NAND
39 + tristate "Support for MTK SoC NAND controller"
40 + depends on SOC_MT7621
41 + select MTD_NAND_IDS
42 + select MTD_NAND_ECC
43 +
44 endif # MTD_NAND
45 --- a/drivers/mtd/nand/Makefile
46 +++ b/drivers/mtd/nand/Makefile
47 @@ -54,5 +54,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) +=
48 obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
49 obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
50 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
51 +obj-$(CONFIG_MTK_MTD_NAND) += mtk_nand.o bmt.o
52
53 nand-objs := nand_base.o nand_bbt.o nand_timings.o
54 --- /dev/null
55 +++ b/drivers/mtd/nand/bmt.c
56 @@ -0,0 +1,750 @@
57 +#include "bmt.h"
58 +
59 +typedef struct
60 +{
61 + char signature[3];
62 + u8 version;
63 + u8 bad_count; // bad block count in pool
64 + u8 mapped_count; // mapped block count in pool
65 + u8 checksum;
66 + u8 reseverd[13];
67 +} phys_bmt_header;
68 +
69 +typedef struct
70 +{
71 + phys_bmt_header header;
72 + bmt_entry table[MAX_BMT_SIZE];
73 +} phys_bmt_struct;
74 +
75 +typedef struct
76 +{
77 + char signature[3];
78 +} bmt_oob_data;
79 +
80 +static char MAIN_SIGNATURE[] = "BMT";
81 +static char OOB_SIGNATURE[] = "bmt";
82 +#define SIGNATURE_SIZE (3)
83 +
84 +#define MAX_DAT_SIZE 0x1000
85 +#define MAX_OOB_SIZE 0x80
86 +
87 +static struct mtd_info *mtd_bmt;
88 +static struct nand_chip *nand_chip_bmt;
89 +#define BLOCK_SIZE_BMT (1 << nand_chip_bmt->phys_erase_shift)
90 +#define PAGE_SIZE_BMT (1 << nand_chip_bmt->page_shift)
91 +
92 +#define OFFSET(block) ((block) * BLOCK_SIZE_BMT)
93 +#define PAGE_ADDR(block) ((block) * BLOCK_SIZE_BMT / PAGE_SIZE_BMT)
94 +
95 +/*********************************************************************
96 +* Flash is splited into 2 parts, system part is for normal system *
97 +* system usage, size is system_block_count, another is replace pool *
98 +* +-------------------------------------------------+ *
99 +* | system_block_count | bmt_block_count | *
100 +* +-------------------------------------------------+ *
101 +*********************************************************************/
102 +static u32 total_block_count; // block number in flash
103 +static u32 system_block_count;
104 +static int bmt_block_count; // bmt table size
105 +// static int bmt_count; // block used in bmt
106 +static int page_per_block; // page per count
107 +
108 +static u32 bmt_block_index; // bmt block index
109 +static bmt_struct bmt; // dynamic created global bmt table
110 +
111 +static u8 dat_buf[MAX_DAT_SIZE];
112 +static u8 oob_buf[MAX_OOB_SIZE];
113 +static bool pool_erased;
114 +
115 +/***************************************************************
116 +*
117 +* Interface adaptor for preloader/uboot/kernel
118 +* These interfaces operate on physical address, read/write
119 +* physical data.
120 +*
121 +***************************************************************/
122 +int nand_read_page_bmt(u32 page, u8 * dat, u8 * oob)
123 +{
124 + return mtk_nand_exec_read_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob);
125 +}
126 +
127 +bool nand_block_bad_bmt(u32 offset)
128 +{
129 + return mtk_nand_block_bad_hw(mtd_bmt, offset);
130 +}
131 +
132 +bool nand_erase_bmt(u32 offset)
133 +{
134 + int status;
135 + if (offset < 0x20000)
136 + {
137 + MSG(INIT, "erase offset: 0x%x\n", offset);
138 + }
139 +
140 + status = mtk_nand_erase_hw(mtd_bmt, offset / PAGE_SIZE_BMT); // as nand_chip structure doesn't have a erase function defined
141 + if (status & NAND_STATUS_FAIL)
142 + return false;
143 + else
144 + return true;
145 +}
146 +
147 +int mark_block_bad_bmt(u32 offset)
148 +{
149 + return mtk_nand_block_markbad_hw(mtd_bmt, offset); //mark_block_bad_hw(offset);
150 +}
151 +
152 +bool nand_write_page_bmt(u32 page, u8 * dat, u8 * oob)
153 +{
154 + if (mtk_nand_exec_write_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob))
155 + return false;
156 + else
157 + return true;
158 +}
159 +
160 +/***************************************************************
161 +* *
162 +* static internal function *
163 +* *
164 +***************************************************************/
165 +static void dump_bmt_info(bmt_struct * bmt)
166 +{
167 + int i;
168 +
169 + MSG(INIT, "BMT v%d. total %d mapping:\n", bmt->version, bmt->mapped_count);
170 + for (i = 0; i < bmt->mapped_count; i++)
171 + {
172 + MSG(INIT, "\t0x%x -> 0x%x\n", bmt->table[i].bad_index, bmt->table[i].mapped_index);
173 + }
174 +}
175 +
176 +static bool match_bmt_signature(u8 * dat, u8 * oob)
177 +{
178 +
179 + if (memcmp(dat + MAIN_SIGNATURE_OFFSET, MAIN_SIGNATURE, SIGNATURE_SIZE))
180 + {
181 + return false;
182 + }
183 +
184 + if (memcmp(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE))
185 + {
186 + MSG(INIT, "main signature match, oob signature doesn't match, but ignore\n");
187 + }
188 + return true;
189 +}
190 +
191 +static u8 cal_bmt_checksum(phys_bmt_struct * phys_table, int bmt_size)
192 +{
193 + int i;
194 + u8 checksum = 0;
195 + u8 *dat = (u8 *) phys_table;
196 +
197 + checksum += phys_table->header.version;
198 + checksum += phys_table->header.mapped_count;
199 +
200 + dat += sizeof(phys_bmt_header);
201 + for (i = 0; i < bmt_size * sizeof(bmt_entry); i++)
202 + {
203 + checksum += dat[i];
204 + }
205 +
206 + return checksum;
207 +}
208 +
209 +
210 +static int is_block_mapped(int index)
211 +{
212 + int i;
213 + for (i = 0; i < bmt.mapped_count; i++)
214 + {
215 + if (index == bmt.table[i].mapped_index)
216 + return i;
217 + }
218 + return -1;
219 +}
220 +
221 +static bool is_page_used(u8 * dat, u8 * oob)
222 +{
223 + return ((oob[OOB_INDEX_OFFSET] != 0xFF) || (oob[OOB_INDEX_OFFSET + 1] != 0xFF));
224 +}
225 +
226 +static bool valid_bmt_data(phys_bmt_struct * phys_table)
227 +{
228 + int i;
229 + u8 checksum = cal_bmt_checksum(phys_table, bmt_block_count);
230 +
231 + // checksum correct?
232 + if (phys_table->header.checksum != checksum)
233 + {
234 + MSG(INIT, "BMT Data checksum error: %x %x\n", phys_table->header.checksum, checksum);
235 + return false;
236 + }
237 +
238 + MSG(INIT, "BMT Checksum is: 0x%x\n", phys_table->header.checksum);
239 +
240 + // block index correct?
241 + for (i = 0; i < phys_table->header.mapped_count; i++)
242 + {
243 + if (phys_table->table[i].bad_index >= total_block_count || phys_table->table[i].mapped_index >= total_block_count || phys_table->table[i].mapped_index < system_block_count)
244 + {
245 + MSG(INIT, "index error: bad_index: %d, mapped_index: %d\n", phys_table->table[i].bad_index, phys_table->table[i].mapped_index);
246 + return false;
247 + }
248 + }
249 +
250 + // pass check, valid bmt.
251 + MSG(INIT, "Valid BMT, version v%d\n", phys_table->header.version);
252 + return true;
253 +}
254 +
255 +static void fill_nand_bmt_buffer(bmt_struct * bmt, u8 * dat, u8 * oob)
256 +{
257 + phys_bmt_struct phys_bmt;
258 +
259 + dump_bmt_info(bmt);
260 +
261 + // fill phys_bmt_struct structure with bmt_struct
262 + memset(&phys_bmt, 0xFF, sizeof(phys_bmt));
263 +
264 + memcpy(phys_bmt.header.signature, MAIN_SIGNATURE, SIGNATURE_SIZE);
265 + phys_bmt.header.version = BMT_VERSION;
266 + // phys_bmt.header.bad_count = bmt->bad_count;
267 + phys_bmt.header.mapped_count = bmt->mapped_count;
268 + memcpy(phys_bmt.table, bmt->table, sizeof(bmt_entry) * bmt_block_count);
269 +
270 + phys_bmt.header.checksum = cal_bmt_checksum(&phys_bmt, bmt_block_count);
271 +
272 + memcpy(dat + MAIN_SIGNATURE_OFFSET, &phys_bmt, sizeof(phys_bmt));
273 + memcpy(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE);
274 +}
275 +
276 +// return valid index if found BMT, else return 0
277 +static int load_bmt_data(int start, int pool_size)
278 +{
279 + int bmt_index = start + pool_size - 1; // find from the end
280 + phys_bmt_struct phys_table;
281 + int i;
282 +
283 + MSG(INIT, "[%s]: begin to search BMT from block 0x%x\n", __FUNCTION__, bmt_index);
284 +
285 + for (bmt_index = start + pool_size - 1; bmt_index >= start; bmt_index--)
286 + {
287 + if (nand_block_bad_bmt(OFFSET(bmt_index)))
288 + {
289 + MSG(INIT, "Skip bad block: %d\n", bmt_index);
290 + continue;
291 + }
292 +
293 + if (!nand_read_page_bmt(PAGE_ADDR(bmt_index), dat_buf, oob_buf))
294 + {
295 + MSG(INIT, "Error found when read block %d\n", bmt_index);
296 + continue;
297 + }
298 +
299 + if (!match_bmt_signature(dat_buf, oob_buf))
300 + {
301 + continue;
302 + }
303 +
304 + MSG(INIT, "Match bmt signature @ block: 0x%x\n", bmt_index);
305 +
306 + memcpy(&phys_table, dat_buf + MAIN_SIGNATURE_OFFSET, sizeof(phys_table));
307 +
308 + if (!valid_bmt_data(&phys_table))
309 + {
310 + MSG(INIT, "BMT data is not correct %d\n", bmt_index);
311 + continue;
312 + } else
313 + {
314 + bmt.mapped_count = phys_table.header.mapped_count;
315 + bmt.version = phys_table.header.version;
316 + // bmt.bad_count = phys_table.header.bad_count;
317 + memcpy(bmt.table, phys_table.table, bmt.mapped_count * sizeof(bmt_entry));
318 +
319 + MSG(INIT, "bmt found at block: %d, mapped block: %d\n", bmt_index, bmt.mapped_count);
320 +
321 + for (i = 0; i < bmt.mapped_count; i++)
322 + {
323 + if (!nand_block_bad_bmt(OFFSET(bmt.table[i].bad_index)))
324 + {
325 + MSG(INIT, "block 0x%x is not mark bad, should be power lost last time\n", bmt.table[i].bad_index);
326 + mark_block_bad_bmt(OFFSET(bmt.table[i].bad_index));
327 + }
328 + }
329 +
330 + return bmt_index;
331 + }
332 + }
333 +
334 + MSG(INIT, "bmt block not found!\n");
335 + return 0;
336 +}
337 +
338 +/*************************************************************************
339 +* Find an available block and erase. *
340 +* start_from_end: if true, find available block from end of flash. *
341 +* else, find from the beginning of the pool *
342 +* need_erase: if true, all unmapped blocks in the pool will be erased *
343 +*************************************************************************/
344 +static int find_available_block(bool start_from_end)
345 +{
346 + int i; // , j;
347 + int block = system_block_count;
348 + int direction;
349 + // int avail_index = 0;
350 + MSG(INIT, "Try to find_available_block, pool_erase: %d\n", pool_erased);
351 +
352 + // erase all un-mapped blocks in pool when finding avaliable block
353 + if (!pool_erased)
354 + {
355 + MSG(INIT, "Erase all un-mapped blocks in pool\n");
356 + for (i = 0; i < bmt_block_count; i++)
357 + {
358 + if (block == bmt_block_index)
359 + {
360 + MSG(INIT, "Skip bmt block 0x%x\n", block);
361 + continue;
362 + }
363 +
364 + if (nand_block_bad_bmt(OFFSET(block + i)))
365 + {
366 + MSG(INIT, "Skip bad block 0x%x\n", block + i);
367 + continue;
368 + }
369 +//if(block==4095)
370 +//{
371 +// continue;
372 +//}
373 +
374 + if (is_block_mapped(block + i) >= 0)
375 + {
376 + MSG(INIT, "Skip mapped block 0x%x\n", block + i);
377 + continue;
378 + }
379 +
380 + if (!nand_erase_bmt(OFFSET(block + i)))
381 + {
382 + MSG(INIT, "Erase block 0x%x failed\n", block + i);
383 + mark_block_bad_bmt(OFFSET(block + i));
384 + }
385 + }
386 +
387 + pool_erased = 1;
388 + }
389 +
390 + if (start_from_end)
391 + {
392 + block = total_block_count - 1;
393 + direction = -1;
394 + } else
395 + {
396 + block = system_block_count;
397 + direction = 1;
398 + }
399 +
400 + for (i = 0; i < bmt_block_count; i++, block += direction)
401 + {
402 + if (block == bmt_block_index)
403 + {
404 + MSG(INIT, "Skip bmt block 0x%x\n", block);
405 + continue;
406 + }
407 +
408 + if (nand_block_bad_bmt(OFFSET(block)))
409 + {
410 + MSG(INIT, "Skip bad block 0x%x\n", block);
411 + continue;
412 + }
413 +
414 + if (is_block_mapped(block) >= 0)
415 + {
416 + MSG(INIT, "Skip mapped block 0x%x\n", block);
417 + continue;
418 + }
419 +
420 + MSG(INIT, "Find block 0x%x available\n", block);
421 + return block;
422 + }
423 +
424 + return 0;
425 +}
426 +
427 +static unsigned short get_bad_index_from_oob(u8 * oob_buf)
428 +{
429 + unsigned short index;
430 + memcpy(&index, oob_buf + OOB_INDEX_OFFSET, OOB_INDEX_SIZE);
431 +
432 + return index;
433 +}
434 +
435 +void set_bad_index_to_oob(u8 * oob, u16 index)
436 +{
437 + memcpy(oob + OOB_INDEX_OFFSET, &index, sizeof(index));
438 +}
439 +
440 +static int migrate_from_bad(int offset, u8 * write_dat, u8 * write_oob)
441 +{
442 + int page;
443 + int error_block = offset / BLOCK_SIZE_BMT;
444 + int error_page = (offset / PAGE_SIZE_BMT) % page_per_block;
445 + int to_index;
446 +
447 + memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
448 +
449 + to_index = find_available_block(false);
450 +
451 + if (!to_index)
452 + {
453 + MSG(INIT, "Cannot find an available block for BMT\n");
454 + return 0;
455 + }
456 +
457 + { // migrate error page first
458 + MSG(INIT, "Write error page: 0x%x\n", error_page);
459 + if (!write_dat)
460 + {
461 + nand_read_page_bmt(PAGE_ADDR(error_block) + error_page, dat_buf, NULL);
462 + write_dat = dat_buf;
463 + }
464 + // memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
465 +
466 + if (error_block < system_block_count)
467 + set_bad_index_to_oob(oob_buf, error_block); // if error_block is already a mapped block, original mapping index is in OOB.
468 +
469 + if (!nand_write_page_bmt(PAGE_ADDR(to_index) + error_page, write_dat, oob_buf))
470 + {
471 + MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + error_page);
472 + mark_block_bad_bmt(to_index);
473 + return migrate_from_bad(offset, write_dat, write_oob);
474 + }
475 + }
476 +
477 + for (page = 0; page < page_per_block; page++)
478 + {
479 + if (page != error_page)
480 + {
481 + nand_read_page_bmt(PAGE_ADDR(error_block) + page, dat_buf, oob_buf);
482 + if (is_page_used(dat_buf, oob_buf))
483 + {
484 + if (error_block < system_block_count)
485 + {
486 + set_bad_index_to_oob(oob_buf, error_block);
487 + }
488 + MSG(INIT, "\tmigrate page 0x%x to page 0x%x\n", PAGE_ADDR(error_block) + page, PAGE_ADDR(to_index) + page);
489 + if (!nand_write_page_bmt(PAGE_ADDR(to_index) + page, dat_buf, oob_buf))
490 + {
491 + MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + page);
492 + mark_block_bad_bmt(to_index);
493 + return migrate_from_bad(offset, write_dat, write_oob);
494 + }
495 + }
496 + }
497 + }
498 +
499 + MSG(INIT, "Migrate from 0x%x to 0x%x done!\n", error_block, to_index);
500 +
501 + return to_index;
502 +}
503 +
504 +static bool write_bmt_to_flash(u8 * dat, u8 * oob)
505 +{
506 + bool need_erase = true;
507 + MSG(INIT, "Try to write BMT\n");
508 +
509 + if (bmt_block_index == 0)
510 + {
511 + // if we don't have index, we don't need to erase found block as it has been erased in find_available_block()
512 + need_erase = false;
513 + if (!(bmt_block_index = find_available_block(true)))
514 + {
515 + MSG(INIT, "Cannot find an available block for BMT\n");
516 + return false;
517 + }
518 + }
519 +
520 + MSG(INIT, "Find BMT block: 0x%x\n", bmt_block_index);
521 +
522 + // write bmt to flash
523 + if (need_erase)
524 + {
525 + if (!nand_erase_bmt(OFFSET(bmt_block_index)))
526 + {
527 + MSG(INIT, "BMT block erase fail, mark bad: 0x%x\n", bmt_block_index);
528 + mark_block_bad_bmt(OFFSET(bmt_block_index));
529 + // bmt.bad_count++;
530 +
531 + bmt_block_index = 0;
532 + return write_bmt_to_flash(dat, oob); // recursive call
533 + }
534 + }
535 +
536 + if (!nand_write_page_bmt(PAGE_ADDR(bmt_block_index), dat, oob))
537 + {
538 + MSG(INIT, "Write BMT data fail, need to write again\n");
539 + mark_block_bad_bmt(OFFSET(bmt_block_index));
540 + // bmt.bad_count++;
541 +
542 + bmt_block_index = 0;
543 + return write_bmt_to_flash(dat, oob); // recursive call
544 + }
545 +
546 + MSG(INIT, "Write BMT data to block 0x%x success\n", bmt_block_index);
547 + return true;
548 +}
549 +
550 +/*******************************************************************
551 +* Reconstruct bmt, called when found bmt info doesn't match bad
552 +* block info in flash.
553 +*
554 +* Return NULL for failure
555 +*******************************************************************/
556 +bmt_struct *reconstruct_bmt(bmt_struct * bmt)
557 +{
558 + int i;
559 + int index = system_block_count;
560 + unsigned short bad_index;
561 + int mapped;
562 +
563 + // init everything in BMT struct
564 + bmt->version = BMT_VERSION;
565 + bmt->bad_count = 0;
566 + bmt->mapped_count = 0;
567 +
568 + memset(bmt->table, 0, bmt_block_count * sizeof(bmt_entry));
569 +
570 + for (i = 0; i < bmt_block_count; i++, index++)
571 + {
572 + if (nand_block_bad_bmt(OFFSET(index)))
573 + {
574 + MSG(INIT, "Skip bad block: 0x%x\n", index);
575 + // bmt->bad_count++;
576 + continue;
577 + }
578 +
579 + MSG(INIT, "read page: 0x%x\n", PAGE_ADDR(index));
580 + nand_read_page_bmt(PAGE_ADDR(index), dat_buf, oob_buf);
581 + /* if (mtk_nand_read_page_hw(PAGE_ADDR(index), dat_buf))
582 + {
583 + MSG(INIT, "Error when read block %d\n", bmt_block_index);
584 + continue;
585 + } */
586 +
587 + if ((bad_index = get_bad_index_from_oob(oob_buf)) >= system_block_count)
588 + {
589 + MSG(INIT, "get bad index: 0x%x\n", bad_index);
590 + if (bad_index != 0xFFFF)
591 + MSG(INIT, "Invalid bad index found in block 0x%x, bad index 0x%x\n", index, bad_index);
592 + continue;
593 + }
594 +
595 + MSG(INIT, "Block 0x%x is mapped to bad block: 0x%x\n", index, bad_index);
596 +
597 + if (!nand_block_bad_bmt(OFFSET(bad_index)))
598 + {
599 + MSG(INIT, "\tbut block 0x%x is not marked as bad, invalid mapping\n", bad_index);
600 + continue; // no need to erase here, it will be erased later when trying to write BMT
601 + }
602 +
603 + if ((mapped = is_block_mapped(bad_index)) >= 0)
604 + {
605 + MSG(INIT, "bad block 0x%x is mapped to 0x%x, should be caused by power lost, replace with one\n", bmt->table[mapped].bad_index, bmt->table[mapped].mapped_index);
606 + bmt->table[mapped].mapped_index = index; // use new one instead.
607 + } else
608 + {
609 + // add mapping to BMT
610 + bmt->table[bmt->mapped_count].bad_index = bad_index;
611 + bmt->table[bmt->mapped_count].mapped_index = index;
612 + bmt->mapped_count++;
613 + }
614 +
615 + MSG(INIT, "Add mapping: 0x%x -> 0x%x to BMT\n", bad_index, index);
616 +
617 + }
618 +
619 + MSG(INIT, "Scan replace pool done, mapped block: %d\n", bmt->mapped_count);
620 + // dump_bmt_info(bmt);
621 +
622 + // fill NAND BMT buffer
623 + memset(oob_buf, 0xFF, sizeof(oob_buf));
624 + fill_nand_bmt_buffer(bmt, dat_buf, oob_buf);
625 +
626 + // write BMT back
627 + if (!write_bmt_to_flash(dat_buf, oob_buf))
628 + {
629 + MSG(INIT, "TRAGEDY: cannot find a place to write BMT!!!!\n");
630 + }
631 +
632 + return bmt;
633 +}
634 +
635 +/*******************************************************************
636 +* [BMT Interface]
637 +*
638 +* Description:
639 +* Init bmt from nand. Reconstruct if not found or data error
640 +*
641 +* Parameter:
642 +* size: size of bmt and replace pool
643 +*
644 +* Return:
645 +* NULL for failure, and a bmt struct for success
646 +*******************************************************************/
647 +bmt_struct *init_bmt(struct nand_chip * chip, int size)
648 +{
649 + struct mtk_nand_host *host;
650 +
651 + if (size > 0 && size < MAX_BMT_SIZE)
652 + {
653 + MSG(INIT, "Init bmt table, size: %d\n", size);
654 + bmt_block_count = size;
655 + } else
656 + {
657 + MSG(INIT, "Invalid bmt table size: %d\n", size);
658 + return NULL;
659 + }
660 + nand_chip_bmt = chip;
661 + system_block_count = chip->chipsize >> chip->phys_erase_shift;
662 + total_block_count = bmt_block_count + system_block_count;
663 + page_per_block = BLOCK_SIZE_BMT / PAGE_SIZE_BMT;
664 + host = (struct mtk_nand_host *)chip->priv;
665 + mtd_bmt = &host->mtd;
666 +
667 + MSG(INIT, "mtd_bmt: %p, nand_chip_bmt: %p\n", mtd_bmt, nand_chip_bmt);
668 + MSG(INIT, "bmt count: %d, system count: %d\n", bmt_block_count, system_block_count);
669 +
670 + // set this flag, and unmapped block in pool will be erased.
671 + pool_erased = 0;
672 + memset(bmt.table, 0, size * sizeof(bmt_entry));
673 + if ((bmt_block_index = load_bmt_data(system_block_count, size)))
674 + {
675 + MSG(INIT, "Load bmt data success @ block 0x%x\n", bmt_block_index);
676 + dump_bmt_info(&bmt);
677 + return &bmt;
678 + } else
679 + {
680 + MSG(INIT, "Load bmt data fail, need re-construct!\n");
681 +#ifndef __UBOOT_NAND__ // BMT is not re-constructed in UBOOT.
682 + if (reconstruct_bmt(&bmt))
683 + return &bmt;
684 + else
685 +#endif
686 + return NULL;
687 + }
688 +}
689 +
690 +/*******************************************************************
691 +* [BMT Interface]
692 +*
693 +* Description:
694 +* Update BMT.
695 +*
696 +* Parameter:
697 +* offset: update block/page offset.
698 +* reason: update reason, see update_reason_t for reason.
699 +* dat/oob: data and oob buffer for write fail.
700 +*
701 +* Return:
702 +* Return true for success, and false for failure.
703 +*******************************************************************/
704 +bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob)
705 +{
706 + int map_index;
707 + int orig_bad_block = -1;
708 + // int bmt_update_index;
709 + int i;
710 + int bad_index = offset / BLOCK_SIZE_BMT;
711 +
712 +#ifndef MTK_NAND_BMT
713 + return false;
714 +#endif
715 + if (reason == UPDATE_WRITE_FAIL)
716 + {
717 + MSG(INIT, "Write fail, need to migrate\n");
718 + if (!(map_index = migrate_from_bad(offset, dat, oob)))
719 + {
720 + MSG(INIT, "migrate fail\n");
721 + return false;
722 + }
723 + } else
724 + {
725 + if (!(map_index = find_available_block(false)))
726 + {
727 + MSG(INIT, "Cannot find block in pool\n");
728 + return false;
729 + }
730 + }
731 +
732 + // now let's update BMT
733 + if (bad_index >= system_block_count) // mapped block become bad, find original bad block
734 + {
735 + for (i = 0; i < bmt_block_count; i++)
736 + {
737 + if (bmt.table[i].mapped_index == bad_index)
738 + {
739 + orig_bad_block = bmt.table[i].bad_index;
740 + break;
741 + }
742 + }
743 + // bmt.bad_count++;
744 + MSG(INIT, "Mapped block becomes bad, orig bad block is 0x%x\n", orig_bad_block);
745 +
746 + bmt.table[i].mapped_index = map_index;
747 + } else
748 + {
749 + bmt.table[bmt.mapped_count].mapped_index = map_index;
750 + bmt.table[bmt.mapped_count].bad_index = bad_index;
751 + bmt.mapped_count++;
752 + }
753 +
754 + memset(oob_buf, 0xFF, sizeof(oob_buf));
755 + fill_nand_bmt_buffer(&bmt, dat_buf, oob_buf);
756 + if (!write_bmt_to_flash(dat_buf, oob_buf))
757 + return false;
758 +
759 + mark_block_bad_bmt(offset);
760 +
761 + return true;
762 +}
763 +
764 +/*******************************************************************
765 +* [BMT Interface]
766 +*
767 +* Description:
768 +* Given an block index, return mapped index if it's mapped, else
769 +* return given index.
770 +*
771 +* Parameter:
772 +* index: given an block index. This value cannot exceed
773 +* system_block_count.
774 +*
775 +* Return NULL for failure
776 +*******************************************************************/
777 +u16 get_mapping_block_index(int index)
778 +{
779 + int i;
780 +#ifndef MTK_NAND_BMT
781 + return index;
782 +#endif
783 + if (index > system_block_count)
784 + {
785 + return index;
786 + }
787 +
788 + for (i = 0; i < bmt.mapped_count; i++)
789 + {
790 + if (bmt.table[i].bad_index == index)
791 + {
792 + return bmt.table[i].mapped_index;
793 + }
794 + }
795 +
796 + return index;
797 +}
798 +#ifdef __KERNEL_NAND__
799 +EXPORT_SYMBOL_GPL(init_bmt);
800 +EXPORT_SYMBOL_GPL(update_bmt);
801 +EXPORT_SYMBOL_GPL(get_mapping_block_index);
802 +
803 +MODULE_LICENSE("GPL");
804 +MODULE_AUTHOR("MediaTek");
805 +MODULE_DESCRIPTION("Bad Block mapping management for MediaTek NAND Flash Driver");
806 +#endif
807 --- /dev/null
808 +++ b/drivers/mtd/nand/bmt.h
809 @@ -0,0 +1,80 @@
810 +#ifndef __BMT_H__
811 +#define __BMT_H__
812 +
813 +#include "nand_def.h"
814 +
815 +#if defined(__PRELOADER_NAND__)
816 +
817 +#include "nand.h"
818 +
819 +#elif defined(__UBOOT_NAND__)
820 +
821 +#include <linux/mtd/nand.h>
822 +#include "mtk_nand.h"
823 +
824 +#elif defined(__KERNEL_NAND__)
825 +
826 +#include <linux/mtd/mtd.h>
827 +#include <linux/mtd/nand.h>
828 +#include <linux/module.h>
829 +#include "mtk_nand.h"
830 +
831 +#endif
832 +
833 +
834 +#define MAX_BMT_SIZE (0x80)
835 +#define BMT_VERSION (1) // initial version
836 +
837 +#define MAIN_SIGNATURE_OFFSET (0)
838 +#define OOB_SIGNATURE_OFFSET (1)
839 +#define OOB_INDEX_OFFSET (29)
840 +#define OOB_INDEX_SIZE (2)
841 +#define FAKE_INDEX (0xAAAA)
842 +
843 +typedef struct _bmt_entry_
844 +{
845 + u16 bad_index; // bad block index
846 + u16 mapped_index; // mapping block index in the replace pool
847 +} bmt_entry;
848 +
849 +typedef enum
850 +{
851 + UPDATE_ERASE_FAIL,
852 + UPDATE_WRITE_FAIL,
853 + UPDATE_UNMAPPED_BLOCK,
854 + UPDATE_REASON_COUNT,
855 +} update_reason_t;
856 +
857 +typedef struct
858 +{
859 + bmt_entry table[MAX_BMT_SIZE];
860 + u8 version;
861 + u8 mapped_count; // mapped block count in pool
862 + u8 bad_count; // bad block count in pool. Not used in V1
863 +} bmt_struct;
864 +
865 +/***************************************************************
866 +* *
867 +* Interface BMT need to use *
868 +* *
869 +***************************************************************/
870 +extern bool mtk_nand_exec_read_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
871 +extern int mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs);
872 +extern int mtk_nand_erase_hw(struct mtd_info *mtd, int page);
873 +extern int mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t ofs);
874 +extern int mtk_nand_exec_write_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
875 +
876 +
877 +/***************************************************************
878 +* *
879 +* Different function interface for preloader/uboot/kernel *
880 +* *
881 +***************************************************************/
882 +void set_bad_index_to_oob(u8 * oob, u16 index);
883 +
884 +
885 +bmt_struct *init_bmt(struct nand_chip *nand, int size);
886 +bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob);
887 +unsigned short get_mapping_block_index(int index);
888 +
889 +#endif // #ifndef __BMT_H__
890 --- /dev/null
891 +++ b/drivers/mtd/nand/dev-nand.c
892 @@ -0,0 +1,63 @@
893 +#include <linux/init.h>
894 +#include <linux/kernel.h>
895 +#include <linux/platform_device.h>
896 +
897 +#include "mt6575_typedefs.h"
898 +
899 +#define RALINK_NAND_CTRL_BASE 0xBE003000
900 +#define NFI_base RALINK_NAND_CTRL_BASE
901 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
902 +#define NFIECC_base RALINK_NANDECC_CTRL_BASE
903 +#define MT7621_NFI_IRQ_ID SURFBOARDINT_NAND
904 +#define MT7621_NFIECC_IRQ_ID SURFBOARDINT_NAND_ECC
905 +
906 +#define SURFBOARDINT_NAND 22
907 +#define SURFBOARDINT_NAND_ECC 23
908 +
909 +static struct resource MT7621_resource_nand[] = {
910 + {
911 + .start = NFI_base,
912 + .end = NFI_base + 0x1A0,
913 + .flags = IORESOURCE_MEM,
914 + },
915 + {
916 + .start = NFIECC_base,
917 + .end = NFIECC_base + 0x150,
918 + .flags = IORESOURCE_MEM,
919 + },
920 + {
921 + .start = MT7621_NFI_IRQ_ID,
922 + .flags = IORESOURCE_IRQ,
923 + },
924 + {
925 + .start = MT7621_NFIECC_IRQ_ID,
926 + .flags = IORESOURCE_IRQ,
927 + },
928 +};
929 +
930 +static struct platform_device MT7621_nand_dev = {
931 + .name = "MT7621-NAND",
932 + .id = 0,
933 + .num_resources = ARRAY_SIZE(MT7621_resource_nand),
934 + .resource = MT7621_resource_nand,
935 + .dev = {
936 + .platform_data = &mt7621_nand_hw,
937 + },
938 +};
939 +
940 +
941 +int __init mtk_nand_register(void)
942 +{
943 +
944 + int retval = 0;
945 +
946 + retval = platform_device_register(&MT7621_nand_dev);
947 + if (retval != 0) {
948 + printk(KERN_ERR "register nand device fail\n");
949 + return retval;
950 + }
951 +
952 +
953 + return retval;
954 +}
955 +arch_initcall(mtk_nand_register);
956 --- /dev/null
957 +++ b/drivers/mtd/nand/mt6575_typedefs.h
958 @@ -0,0 +1,340 @@
959 +/* Copyright Statement:
960 + *
961 + * This software/firmware and related documentation ("MediaTek Software") are
962 + * protected under relevant copyright laws. The information contained herein
963 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
964 + * Without the prior written permission of MediaTek inc. and/or its licensors,
965 + * any reproduction, modification, use or disclosure of MediaTek Software,
966 + * and information contained herein, in whole or in part, shall be strictly prohibited.
967 + */
968 +/* MediaTek Inc. (C) 2010. All rights reserved.
969 + *
970 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
971 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
972 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
973 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
974 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
975 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
976 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
977 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
978 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
979 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
980 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
981 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
982 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
983 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
984 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
985 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
986 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
987 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
988 + *
989 + * The following software/firmware and/or related documentation ("MediaTek Software")
990 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
991 + * applicable license agreements with MediaTek Inc.
992 + */
993 +
994 +/*****************************************************************************
995 +* Copyright Statement:
996 +* --------------------
997 +* This software is protected by Copyright and the information contained
998 +* herein is confidential. The software may not be copied and the information
999 +* contained herein may not be used or disclosed except with the written
1000 +* permission of MediaTek Inc. (C) 2008
1001 +*
1002 +* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1003 +* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1004 +* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
1005 +* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1006 +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1007 +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1008 +* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1009 +* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1010 +* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
1011 +* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
1012 +* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
1013 +* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
1014 +*
1015 +* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
1016 +* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1017 +* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1018 +* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
1019 +* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1020 +*
1021 +* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
1022 +* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
1023 +* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
1024 +* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
1025 +* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
1026 +*
1027 +*****************************************************************************/
1028 +
1029 +#ifndef _MT6575_TYPEDEFS_H
1030 +#define _MT6575_TYPEDEFS_H
1031 +
1032 +#if defined (__KERNEL_NAND__)
1033 +#include <linux/bug.h>
1034 +#else
1035 +#define true 1
1036 +#define false 0
1037 +#define bool u8
1038 +#endif
1039 +
1040 +// ---------------------------------------------------------------------------
1041 +// Basic Type Definitions
1042 +// ---------------------------------------------------------------------------
1043 +
1044 +typedef volatile unsigned char *P_kal_uint8;
1045 +typedef volatile unsigned short *P_kal_uint16;
1046 +typedef volatile unsigned int *P_kal_uint32;
1047 +
1048 +typedef long LONG;
1049 +typedef unsigned char UBYTE;
1050 +typedef short SHORT;
1051 +
1052 +typedef signed char kal_int8;
1053 +typedef signed short kal_int16;
1054 +typedef signed int kal_int32;
1055 +typedef long long kal_int64;
1056 +typedef unsigned char kal_uint8;
1057 +typedef unsigned short kal_uint16;
1058 +typedef unsigned int kal_uint32;
1059 +typedef unsigned long long kal_uint64;
1060 +typedef char kal_char;
1061 +
1062 +typedef unsigned int *UINT32P;
1063 +typedef volatile unsigned short *UINT16P;
1064 +typedef volatile unsigned char *UINT8P;
1065 +typedef unsigned char *U8P;
1066 +
1067 +typedef volatile unsigned char *P_U8;
1068 +typedef volatile signed char *P_S8;
1069 +typedef volatile unsigned short *P_U16;
1070 +typedef volatile signed short *P_S16;
1071 +typedef volatile unsigned int *P_U32;
1072 +typedef volatile signed int *P_S32;
1073 +typedef unsigned long long *P_U64;
1074 +typedef signed long long *P_S64;
1075 +
1076 +typedef unsigned char U8;
1077 +typedef signed char S8;
1078 +typedef unsigned short U16;
1079 +typedef signed short S16;
1080 +typedef unsigned int U32;
1081 +typedef signed int S32;
1082 +typedef unsigned long long U64;
1083 +typedef signed long long S64;
1084 +//typedef unsigned char bool;
1085 +
1086 +typedef unsigned char UINT8;
1087 +typedef unsigned short UINT16;
1088 +typedef unsigned int UINT32;
1089 +typedef unsigned short USHORT;
1090 +typedef signed char INT8;
1091 +typedef signed short INT16;
1092 +typedef signed int INT32;
1093 +typedef unsigned int DWORD;
1094 +typedef void VOID;
1095 +typedef unsigned char BYTE;
1096 +typedef float FLOAT;
1097 +
1098 +typedef char *LPCSTR;
1099 +typedef short *LPWSTR;
1100 +
1101 +
1102 +// ---------------------------------------------------------------------------
1103 +// Constants
1104 +// ---------------------------------------------------------------------------
1105 +
1106 +#define IMPORT EXTERN
1107 +#ifndef __cplusplus
1108 + #define EXTERN extern
1109 +#else
1110 + #define EXTERN extern "C"
1111 +#endif
1112 +#define LOCAL static
1113 +#define GLOBAL
1114 +#define EXPORT GLOBAL
1115 +
1116 +#define EQ ==
1117 +#define NEQ !=
1118 +#define AND &&
1119 +#define OR ||
1120 +#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B)))
1121 +
1122 +#ifndef FALSE
1123 + #define FALSE (0)
1124 +#endif
1125 +
1126 +#ifndef TRUE
1127 + #define TRUE (1)
1128 +#endif
1129 +
1130 +#ifndef NULL
1131 + #define NULL (0)
1132 +#endif
1133 +
1134 +//enum boolean {false, true};
1135 +enum {RX, TX, NONE};
1136 +
1137 +#ifndef BOOL
1138 +typedef unsigned char BOOL;
1139 +#endif
1140 +
1141 +typedef enum {
1142 + KAL_FALSE = 0,
1143 + KAL_TRUE = 1,
1144 +} kal_bool;
1145 +
1146 +
1147 +// ---------------------------------------------------------------------------
1148 +// Type Casting
1149 +// ---------------------------------------------------------------------------
1150 +
1151 +#define AS_INT32(x) (*(INT32 *)((void*)x))
1152 +#define AS_INT16(x) (*(INT16 *)((void*)x))
1153 +#define AS_INT8(x) (*(INT8 *)((void*)x))
1154 +
1155 +#define AS_UINT32(x) (*(UINT32 *)((void*)x))
1156 +#define AS_UINT16(x) (*(UINT16 *)((void*)x))
1157 +#define AS_UINT8(x) (*(UINT8 *)((void*)x))
1158 +
1159 +
1160 +// ---------------------------------------------------------------------------
1161 +// Register Manipulations
1162 +// ---------------------------------------------------------------------------
1163 +
1164 +#define READ_REGISTER_UINT32(reg) \
1165 + (*(volatile UINT32 * const)(reg))
1166 +
1167 +#define WRITE_REGISTER_UINT32(reg, val) \
1168 + (*(volatile UINT32 * const)(reg)) = (val)
1169 +
1170 +#define READ_REGISTER_UINT16(reg) \
1171 + (*(volatile UINT16 * const)(reg))
1172 +
1173 +#define WRITE_REGISTER_UINT16(reg, val) \
1174 + (*(volatile UINT16 * const)(reg)) = (val)
1175 +
1176 +#define READ_REGISTER_UINT8(reg) \
1177 + (*(volatile UINT8 * const)(reg))
1178 +
1179 +#define WRITE_REGISTER_UINT8(reg, val) \
1180 + (*(volatile UINT8 * const)(reg)) = (val)
1181 +
1182 +#define INREG8(x) READ_REGISTER_UINT8((UINT8*)((void*)(x)))
1183 +#define OUTREG8(x, y) WRITE_REGISTER_UINT8((UINT8*)((void*)(x)), (UINT8)(y))
1184 +#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
1185 +#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
1186 +#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
1187 +
1188 +#define INREG16(x) READ_REGISTER_UINT16((UINT16*)((void*)(x)))
1189 +#define OUTREG16(x, y) WRITE_REGISTER_UINT16((UINT16*)((void*)(x)),(UINT16)(y))
1190 +#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
1191 +#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
1192 +#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
1193 +
1194 +#define INREG32(x) READ_REGISTER_UINT32((UINT32*)((void*)(x)))
1195 +#define OUTREG32(x, y) WRITE_REGISTER_UINT32((UINT32*)((void*)(x)), (UINT32)(y))
1196 +#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
1197 +#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
1198 +#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
1199 +
1200 +
1201 +#define DRV_Reg8(addr) INREG8(addr)
1202 +#define DRV_WriteReg8(addr, data) OUTREG8(addr, data)
1203 +#define DRV_SetReg8(addr, data) SETREG8(addr, data)
1204 +#define DRV_ClrReg8(addr, data) CLRREG8(addr, data)
1205 +
1206 +#define DRV_Reg16(addr) INREG16(addr)
1207 +#define DRV_WriteReg16(addr, data) OUTREG16(addr, data)
1208 +#define DRV_SetReg16(addr, data) SETREG16(addr, data)
1209 +#define DRV_ClrReg16(addr, data) CLRREG16(addr, data)
1210 +
1211 +#define DRV_Reg32(addr) INREG32(addr)
1212 +#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
1213 +#define DRV_SetReg32(addr, data) SETREG32(addr, data)
1214 +#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
1215 +
1216 +// !!! DEPRECATED, WILL BE REMOVED LATER !!!
1217 +#define DRV_Reg(addr) DRV_Reg16(addr)
1218 +#define DRV_WriteReg(addr, data) DRV_WriteReg16(addr, data)
1219 +#define DRV_SetReg(addr, data) DRV_SetReg16(addr, data)
1220 +#define DRV_ClrReg(addr, data) DRV_ClrReg16(addr, data)
1221 +
1222 +
1223 +// ---------------------------------------------------------------------------
1224 +// Compiler Time Deduction Macros
1225 +// ---------------------------------------------------------------------------
1226 +
1227 +#define _MASK_OFFSET_1(x, n) ((x) & 0x1) ? (n) :
1228 +#define _MASK_OFFSET_2(x, n) _MASK_OFFSET_1((x), (n)) _MASK_OFFSET_1((x) >> 1, (n) + 1)
1229 +#define _MASK_OFFSET_4(x, n) _MASK_OFFSET_2((x), (n)) _MASK_OFFSET_2((x) >> 2, (n) + 2)
1230 +#define _MASK_OFFSET_8(x, n) _MASK_OFFSET_4((x), (n)) _MASK_OFFSET_4((x) >> 4, (n) + 4)
1231 +#define _MASK_OFFSET_16(x, n) _MASK_OFFSET_8((x), (n)) _MASK_OFFSET_8((x) >> 8, (n) + 8)
1232 +#define _MASK_OFFSET_32(x, n) _MASK_OFFSET_16((x), (n)) _MASK_OFFSET_16((x) >> 16, (n) + 16)
1233 +
1234 +#define MASK_OFFSET_ERROR (0xFFFFFFFF)
1235 +
1236 +#define MASK_OFFSET(x) (_MASK_OFFSET_32(x, 0) MASK_OFFSET_ERROR)
1237 +
1238 +
1239 +// ---------------------------------------------------------------------------
1240 +// Assertions
1241 +// ---------------------------------------------------------------------------
1242 +
1243 +#ifndef ASSERT
1244 + #define ASSERT(expr) BUG_ON(!(expr))
1245 +#endif
1246 +
1247 +#ifndef NOT_IMPLEMENTED
1248 + #define NOT_IMPLEMENTED() BUG_ON(1)
1249 +#endif
1250 +
1251 +#define STATIC_ASSERT(pred) STATIC_ASSERT_X(pred, __LINE__)
1252 +#define STATIC_ASSERT_X(pred, line) STATIC_ASSERT_XX(pred, line)
1253 +#define STATIC_ASSERT_XX(pred, line) \
1254 + extern char assertion_failed_at_##line[(pred) ? 1 : -1]
1255 +
1256 +// ---------------------------------------------------------------------------
1257 +// Resolve Compiler Warnings
1258 +// ---------------------------------------------------------------------------
1259 +
1260 +#define NOT_REFERENCED(x) { (x) = (x); }
1261 +
1262 +
1263 +// ---------------------------------------------------------------------------
1264 +// Utilities
1265 +// ---------------------------------------------------------------------------
1266 +
1267 +#define MAXIMUM(A,B) (((A)>(B))?(A):(B))
1268 +#define MINIMUM(A,B) (((A)<(B))?(A):(B))
1269 +
1270 +#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
1271 +#define DVT_DELAYMACRO(u4Num) \
1272 +{ \
1273 + UINT32 u4Count = 0 ; \
1274 + for (u4Count = 0; u4Count < u4Num; u4Count++ ); \
1275 +} \
1276 +
1277 +#define A68351B 0
1278 +#define B68351B 1
1279 +#define B68351D 2
1280 +#define B68351E 3
1281 +#define UNKNOWN_IC_VERSION 0xFF
1282 +
1283 +/* NAND driver */
1284 +struct mtk_nand_host_hw {
1285 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
1286 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
1287 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
1288 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
1289 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
1290 + unsigned int nand_ecc_size;
1291 + unsigned int nand_ecc_bytes;
1292 + unsigned int nand_ecc_mode;
1293 +};
1294 +extern struct mtk_nand_host_hw mt7621_nand_hw;
1295 +extern unsigned int CFG_BLOCKSIZE;
1296 +
1297 +#endif // _MT6575_TYPEDEFS_H
1298 +
1299 --- /dev/null
1300 +++ b/drivers/mtd/nand/mtk_nand.c
1301 @@ -0,0 +1,2304 @@
1302 +/******************************************************************************
1303 +* mtk_nand.c - MTK NAND Flash Device Driver
1304 + *
1305 +* Copyright 2009-2012 MediaTek Co.,Ltd.
1306 + *
1307 +* DESCRIPTION:
1308 +* This file provid the other drivers nand relative functions
1309 + *
1310 +* modification history
1311 +* ----------------------------------------
1312 +* v3.0, 11 Feb 2010, mtk
1313 +* ----------------------------------------
1314 +******************************************************************************/
1315 +#include "nand_def.h"
1316 +#include <linux/slab.h>
1317 +#include <linux/init.h>
1318 +#include <linux/module.h>
1319 +#include <linux/delay.h>
1320 +#include <linux/errno.h>
1321 +#include <linux/sched.h>
1322 +#include <linux/types.h>
1323 +#include <linux/wait.h>
1324 +#include <linux/spinlock.h>
1325 +#include <linux/interrupt.h>
1326 +#include <linux/mtd/mtd.h>
1327 +#include <linux/mtd/nand.h>
1328 +#include <linux/mtd/partitions.h>
1329 +#include <linux/mtd/nand_ecc.h>
1330 +#include <linux/dma-mapping.h>
1331 +#include <linux/jiffies.h>
1332 +#include <linux/platform_device.h>
1333 +#include <linux/proc_fs.h>
1334 +#include <linux/time.h>
1335 +#include <linux/mm.h>
1336 +#include <asm/io.h>
1337 +#include <asm/cacheflush.h>
1338 +#include <asm/uaccess.h>
1339 +#include <linux/miscdevice.h>
1340 +#include "mtk_nand.h"
1341 +#include "nand_device_list.h"
1342 +
1343 +#include "bmt.h"
1344 +#include "partition.h"
1345 +
1346 +unsigned int CFG_BLOCKSIZE;
1347 +
1348 +static int shift_on_bbt = 0;
1349 +extern void nand_bbt_set(struct mtd_info *mtd, int page, int flag);
1350 +extern int nand_bbt_get(struct mtd_info *mtd, int page);
1351 +int mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page);
1352 +
1353 +static const char * const probe_types[] = { "cmdlinepart", "ofpart", NULL };
1354 +
1355 +#define NAND_CMD_STATUS_MULTI 0x71
1356 +
1357 +void show_stack(struct task_struct *tsk, unsigned long *sp);
1358 +extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
1359 +extern void mt_irq_set_polarity(unsigned int irq,unsigned int polarity);
1360 +
1361 +struct mtk_nand_host mtk_nand_host; /* include mtd_info and nand_chip structs */
1362 +struct mtk_nand_host_hw mt7621_nand_hw = {
1363 + .nfi_bus_width = 8,
1364 + .nfi_access_timing = NFI_DEFAULT_ACCESS_TIMING,
1365 + .nfi_cs_num = NFI_CS_NUM,
1366 + .nand_sec_size = 512,
1367 + .nand_sec_shift = 9,
1368 + .nand_ecc_size = 2048,
1369 + .nand_ecc_bytes = 32,
1370 + .nand_ecc_mode = NAND_ECC_HW,
1371 +};
1372 +
1373 +
1374 +/*******************************************************************************
1375 + * Gloable Varible Definition
1376 + *******************************************************************************/
1377 +
1378 +#define NFI_ISSUE_COMMAND(cmd, col_addr, row_addr, col_num, row_num) \
1379 + do { \
1380 + DRV_WriteReg(NFI_CMD_REG16,cmd);\
1381 + while (DRV_Reg32(NFI_STA_REG32) & STA_CMD_STATE);\
1382 + DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);\
1383 + DRV_WriteReg32(NFI_ROWADDR_REG32, row_addr);\
1384 + DRV_WriteReg(NFI_ADDRNOB_REG16, col_num | (row_num<<ADDR_ROW_NOB_SHIFT));\
1385 + while (DRV_Reg32(NFI_STA_REG32) & STA_ADDR_STATE);\
1386 + }while(0);
1387 +
1388 +//-------------------------------------------------------------------------------
1389 +static struct NAND_CMD g_kCMD;
1390 +static u32 g_u4ChipVer;
1391 +bool g_bInitDone;
1392 +static bool g_bcmdstatus;
1393 +static u32 g_value = 0;
1394 +static int g_page_size;
1395 +
1396 +BOOL g_bHwEcc = true;
1397 +
1398 +
1399 +static u8 *local_buffer_16_align; // 16 byte aligned buffer, for HW issue
1400 +static u8 local_buffer[4096 + 512];
1401 +
1402 +extern void nand_release_device(struct mtd_info *mtd);
1403 +extern int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state);
1404 +
1405 +#if defined(MTK_NAND_BMT)
1406 +static bmt_struct *g_bmt;
1407 +#endif
1408 +struct mtk_nand_host *host;
1409 +extern struct mtd_partition g_pasStatic_Partition[];
1410 +int part_num = NUM_PARTITIONS;
1411 +int manu_id;
1412 +int dev_id;
1413 +
1414 +static u8 local_oob_buf[NAND_MAX_OOBSIZE];
1415 +
1416 +static u8 nand_badblock_offset = 0;
1417 +
1418 +void nand_enable_clock(void)
1419 +{
1420 + //enable_clock(MT65XX_PDN_PERI_NFI, "NAND");
1421 +}
1422 +
1423 +void nand_disable_clock(void)
1424 +{
1425 + //disable_clock(MT65XX_PDN_PERI_NFI, "NAND");
1426 +}
1427 +
1428 +static struct nand_ecclayout nand_oob_16 = {
1429 + .eccbytes = 8,
1430 + .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
1431 + .oobfree = {{1, 6}, {0, 0}}
1432 +};
1433 +
1434 +struct nand_ecclayout nand_oob_64 = {
1435 + .eccbytes = 32,
1436 + .eccpos = {32, 33, 34, 35, 36, 37, 38, 39,
1437 + 40, 41, 42, 43, 44, 45, 46, 47,
1438 + 48, 49, 50, 51, 52, 53, 54, 55,
1439 + 56, 57, 58, 59, 60, 61, 62, 63},
1440 + .oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 6}, {0, 0}}
1441 +};
1442 +
1443 +struct nand_ecclayout nand_oob_128 = {
1444 + .eccbytes = 64,
1445 + .eccpos = {
1446 + 64, 65, 66, 67, 68, 69, 70, 71,
1447 + 72, 73, 74, 75, 76, 77, 78, 79,
1448 + 80, 81, 82, 83, 84, 85, 86, 86,
1449 + 88, 89, 90, 91, 92, 93, 94, 95,
1450 + 96, 97, 98, 99, 100, 101, 102, 103,
1451 + 104, 105, 106, 107, 108, 109, 110, 111,
1452 + 112, 113, 114, 115, 116, 117, 118, 119,
1453 + 120, 121, 122, 123, 124, 125, 126, 127},
1454 + .oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 7}, {33, 7}, {41, 7}, {49, 7}, {57, 6}}
1455 +};
1456 +
1457 +flashdev_info devinfo;
1458 +
1459 +void dump_nfi(void)
1460 +{
1461 +}
1462 +
1463 +void dump_ecc(void)
1464 +{
1465 +}
1466 +
1467 +u32
1468 +nand_virt_to_phys_add(u32 va)
1469 +{
1470 + u32 pageOffset = (va & (PAGE_SIZE - 1));
1471 + pgd_t *pgd;
1472 + pmd_t *pmd;
1473 + pte_t *pte;
1474 + u32 pa;
1475 +
1476 + if (virt_addr_valid(va))
1477 + return __virt_to_phys(va);
1478 +
1479 + if (NULL == current) {
1480 + printk(KERN_ERR "[nand_virt_to_phys_add] ERROR ,current is NULL! \n");
1481 + return 0;
1482 + }
1483 +
1484 + if (NULL == current->mm) {
1485 + printk(KERN_ERR "[nand_virt_to_phys_add] ERROR current->mm is NULL! tgid=0x%x, name=%s \n", current->tgid, current->comm);
1486 + return 0;
1487 + }
1488 +
1489 + pgd = pgd_offset(current->mm, va); /* what is tsk->mm */
1490 + if (pgd_none(*pgd) || pgd_bad(*pgd)) {
1491 + printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pgd invalid! \n", va);
1492 + return 0;
1493 + }
1494 +
1495 + pmd = pmd_offset((pud_t *)pgd, va);
1496 + if (pmd_none(*pmd) || pmd_bad(*pmd)) {
1497 + printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pmd invalid! \n", va);
1498 + return 0;
1499 + }
1500 +
1501 + pte = pte_offset_map(pmd, va);
1502 + if (pte_present(*pte)) {
1503 + pa = (pte_val(*pte) & (PAGE_MASK)) | pageOffset;
1504 + return pa;
1505 + }
1506 +
1507 + printk(KERN_ERR "[nand_virt_to_phys_add] ERROR va=0x%x, pte invalid! \n", va);
1508 + return 0;
1509 +}
1510 +EXPORT_SYMBOL(nand_virt_to_phys_add);
1511 +
1512 +bool
1513 +get_device_info(u16 id, u32 ext_id, flashdev_info * pdevinfo)
1514 +{
1515 + u32 index;
1516 + for (index = 0; gen_FlashTable[index].id != 0; index++) {
1517 + if (id == gen_FlashTable[index].id && ext_id == gen_FlashTable[index].ext_id) {
1518 + pdevinfo->id = gen_FlashTable[index].id;
1519 + pdevinfo->ext_id = gen_FlashTable[index].ext_id;
1520 + pdevinfo->blocksize = gen_FlashTable[index].blocksize;
1521 + pdevinfo->addr_cycle = gen_FlashTable[index].addr_cycle;
1522 + pdevinfo->iowidth = gen_FlashTable[index].iowidth;
1523 + pdevinfo->timmingsetting = gen_FlashTable[index].timmingsetting;
1524 + pdevinfo->advancedmode = gen_FlashTable[index].advancedmode;
1525 + pdevinfo->pagesize = gen_FlashTable[index].pagesize;
1526 + pdevinfo->sparesize = gen_FlashTable[index].sparesize;
1527 + pdevinfo->totalsize = gen_FlashTable[index].totalsize;
1528 + memcpy(pdevinfo->devciename, gen_FlashTable[index].devciename, sizeof(pdevinfo->devciename));
1529 + printk(KERN_INFO "Device found in MTK table, ID: %x, EXT_ID: %x\n", id, ext_id);
1530 +
1531 + goto find;
1532 + }
1533 + }
1534 +
1535 +find:
1536 + if (0 == pdevinfo->id) {
1537 + printk(KERN_INFO "Device not found, ID: %x\n", id);
1538 + return false;
1539 + } else {
1540 + return true;
1541 + }
1542 +}
1543 +
1544 +static void
1545 +ECC_Config(struct mtk_nand_host_hw *hw,u32 ecc_bit)
1546 +{
1547 + u32 u4ENCODESize;
1548 + u32 u4DECODESize;
1549 + u32 ecc_bit_cfg = ECC_CNFG_ECC4;
1550 +
1551 + switch(ecc_bit){
1552 + case 4:
1553 + ecc_bit_cfg = ECC_CNFG_ECC4;
1554 + break;
1555 + case 8:
1556 + ecc_bit_cfg = ECC_CNFG_ECC8;
1557 + break;
1558 + case 10:
1559 + ecc_bit_cfg = ECC_CNFG_ECC10;
1560 + break;
1561 + case 12:
1562 + ecc_bit_cfg = ECC_CNFG_ECC12;
1563 + break;
1564 + default:
1565 + break;
1566 + }
1567 + DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
1568 + do {
1569 + } while (!DRV_Reg16(ECC_DECIDLE_REG16));
1570 +
1571 + DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
1572 + do {
1573 + } while (!DRV_Reg32(ECC_ENCIDLE_REG32));
1574 +
1575 + /* setup FDM register base */
1576 + DRV_WriteReg32(ECC_FDMADDR_REG32, NFI_FDM0L_REG32);
1577 +
1578 + /* Sector + FDM */
1579 + u4ENCODESize = (hw->nand_sec_size + 8) << 3;
1580 + /* Sector + FDM + YAFFS2 meta data bits */
1581 + u4DECODESize = ((hw->nand_sec_size + 8) << 3) + ecc_bit * 13;
1582 +
1583 + /* configure ECC decoder && encoder */
1584 + DRV_WriteReg32(ECC_DECCNFG_REG32, ecc_bit_cfg | DEC_CNFG_NFI | DEC_CNFG_EMPTY_EN | (u4DECODESize << DEC_CNFG_CODE_SHIFT));
1585 +
1586 + DRV_WriteReg32(ECC_ENCCNFG_REG32, ecc_bit_cfg | ENC_CNFG_NFI | (u4ENCODESize << ENC_CNFG_MSG_SHIFT));
1587 + NFI_SET_REG32(ECC_DECCNFG_REG32, DEC_CNFG_EL);
1588 +}
1589 +
1590 +static void
1591 +ECC_Decode_Start(void)
1592 +{
1593 + while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
1594 + ;
1595 + DRV_WriteReg16(ECC_DECCON_REG16, DEC_EN);
1596 +}
1597 +
1598 +static void
1599 +ECC_Decode_End(void)
1600 +{
1601 + while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
1602 + ;
1603 + DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
1604 +}
1605 +
1606 +static void
1607 +ECC_Encode_Start(void)
1608 +{
1609 + while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE))
1610 + ;
1611 + mb();
1612 + DRV_WriteReg16(ECC_ENCCON_REG16, ENC_EN);
1613 +}
1614 +
1615 +static void
1616 +ECC_Encode_End(void)
1617 +{
1618 + /* wait for device returning idle */
1619 + while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE)) ;
1620 + mb();
1621 + DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
1622 +}
1623 +
1624 +static bool
1625 +mtk_nand_check_bch_error(struct mtd_info *mtd, u8 * pDataBuf, u32 u4SecIndex, u32 u4PageAddr)
1626 +{
1627 + bool bRet = true;
1628 + u16 u2SectorDoneMask = 1 << u4SecIndex;
1629 + u32 u4ErrorNumDebug, i, u4ErrNum;
1630 + u32 timeout = 0xFFFF;
1631 + // int el;
1632 + u32 au4ErrBitLoc[6];
1633 + u32 u4ErrByteLoc, u4BitOffset;
1634 + u32 u4ErrBitLoc1th, u4ErrBitLoc2nd;
1635 +
1636 + //4 // Wait for Decode Done
1637 + while (0 == (u2SectorDoneMask & DRV_Reg16(ECC_DECDONE_REG16))) {
1638 + timeout--;
1639 + if (0 == timeout)
1640 + return false;
1641 + }
1642 + /* We will manually correct the error bits in the last sector, not all the sectors of the page! */
1643 + memset(au4ErrBitLoc, 0x0, sizeof(au4ErrBitLoc));
1644 + u4ErrorNumDebug = DRV_Reg32(ECC_DECENUM_REG32);
1645 + u4ErrNum = DRV_Reg32(ECC_DECENUM_REG32) >> (u4SecIndex << 2);
1646 + u4ErrNum &= 0xF;
1647 +
1648 + if (u4ErrNum) {
1649 + if (0xF == u4ErrNum) {
1650 + mtd->ecc_stats.failed++;
1651 + bRet = false;
1652 + //printk(KERN_ERR"UnCorrectable at PageAddr=%d\n", u4PageAddr);
1653 + } else {
1654 + for (i = 0; i < ((u4ErrNum + 1) >> 1); ++i) {
1655 + au4ErrBitLoc[i] = DRV_Reg32(ECC_DECEL0_REG32 + i);
1656 + u4ErrBitLoc1th = au4ErrBitLoc[i] & 0x1FFF;
1657 + if (u4ErrBitLoc1th < 0x1000) {
1658 + u4ErrByteLoc = u4ErrBitLoc1th / 8;
1659 + u4BitOffset = u4ErrBitLoc1th % 8;
1660 + pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
1661 + mtd->ecc_stats.corrected++;
1662 + } else {
1663 + mtd->ecc_stats.failed++;
1664 + }
1665 + u4ErrBitLoc2nd = (au4ErrBitLoc[i] >> 16) & 0x1FFF;
1666 + if (0 != u4ErrBitLoc2nd) {
1667 + if (u4ErrBitLoc2nd < 0x1000) {
1668 + u4ErrByteLoc = u4ErrBitLoc2nd / 8;
1669 + u4BitOffset = u4ErrBitLoc2nd % 8;
1670 + pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
1671 + mtd->ecc_stats.corrected++;
1672 + } else {
1673 + mtd->ecc_stats.failed++;
1674 + //printk(KERN_ERR"UnCorrectable High ErrLoc=%d\n", au4ErrBitLoc[i]);
1675 + }
1676 + }
1677 + }
1678 + }
1679 + if (0 == (DRV_Reg16(ECC_DECFER_REG16) & (1 << u4SecIndex)))
1680 + bRet = false;
1681 + }
1682 + return bRet;
1683 +}
1684 +
1685 +static bool
1686 +mtk_nand_RFIFOValidSize(u16 u2Size)
1687 +{
1688 + u32 timeout = 0xFFFF;
1689 + while (FIFO_RD_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) < u2Size) {
1690 + timeout--;
1691 + if (0 == timeout)
1692 + return false;
1693 + }
1694 + return true;
1695 +}
1696 +
1697 +static bool
1698 +mtk_nand_WFIFOValidSize(u16 u2Size)
1699 +{
1700 + u32 timeout = 0xFFFF;
1701 +
1702 + while (FIFO_WR_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) > u2Size) {
1703 + timeout--;
1704 + if (0 == timeout)
1705 + return false;
1706 + }
1707 + return true;
1708 +}
1709 +
1710 +static bool
1711 +mtk_nand_status_ready(u32 u4Status)
1712 +{
1713 + u32 timeout = 0xFFFF;
1714 +
1715 + while ((DRV_Reg32(NFI_STA_REG32) & u4Status) != 0) {
1716 + timeout--;
1717 + if (0 == timeout)
1718 + return false;
1719 + }
1720 + return true;
1721 +}
1722 +
1723 +static bool
1724 +mtk_nand_reset(void)
1725 +{
1726 + int timeout = 0xFFFF;
1727 + if (DRV_Reg16(NFI_MASTERSTA_REG16)) {
1728 + mb();
1729 + DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
1730 + while (DRV_Reg16(NFI_MASTERSTA_REG16)) {
1731 + timeout--;
1732 + if (!timeout)
1733 + MSG(INIT, "Wait for NFI_MASTERSTA timeout\n");
1734 + }
1735 + }
1736 + /* issue reset operation */
1737 + mb();
1738 + DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
1739 +
1740 + return mtk_nand_status_ready(STA_NFI_FSM_MASK | STA_NAND_BUSY) && mtk_nand_RFIFOValidSize(0) && mtk_nand_WFIFOValidSize(0);
1741 +}
1742 +
1743 +static void
1744 +mtk_nand_set_mode(u16 u2OpMode)
1745 +{
1746 + u16 u2Mode = DRV_Reg16(NFI_CNFG_REG16);
1747 + u2Mode &= ~CNFG_OP_MODE_MASK;
1748 + u2Mode |= u2OpMode;
1749 + DRV_WriteReg16(NFI_CNFG_REG16, u2Mode);
1750 +}
1751 +
1752 +static void
1753 +mtk_nand_set_autoformat(bool bEnable)
1754 +{
1755 + if (bEnable)
1756 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
1757 + else
1758 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
1759 +}
1760 +
1761 +static void
1762 +mtk_nand_configure_fdm(u16 u2FDMSize)
1763 +{
1764 + NFI_CLN_REG16(NFI_PAGEFMT_REG16, PAGEFMT_FDM_MASK | PAGEFMT_FDM_ECC_MASK);
1765 + NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_SHIFT);
1766 + NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_ECC_SHIFT);
1767 +}
1768 +
1769 +static void
1770 +mtk_nand_configure_lock(void)
1771 +{
1772 + u32 u4WriteColNOB = 2;
1773 + u32 u4WriteRowNOB = 3;
1774 + u32 u4EraseColNOB = 0;
1775 + u32 u4EraseRowNOB = 3;
1776 + DRV_WriteReg16(NFI_LOCKANOB_REG16,
1777 + (u4WriteColNOB << PROG_CADD_NOB_SHIFT) | (u4WriteRowNOB << PROG_RADD_NOB_SHIFT) | (u4EraseColNOB << ERASE_CADD_NOB_SHIFT) | (u4EraseRowNOB << ERASE_RADD_NOB_SHIFT));
1778 +
1779 + if (CHIPVER_ECO_1 == g_u4ChipVer) {
1780 + int i;
1781 + for (i = 0; i < 16; ++i) {
1782 + DRV_WriteReg32(NFI_LOCK00ADD_REG32 + (i << 1), 0xFFFFFFFF);
1783 + DRV_WriteReg32(NFI_LOCK00FMT_REG32 + (i << 1), 0xFFFFFFFF);
1784 + }
1785 + //DRV_WriteReg16(NFI_LOCKANOB_REG16, 0x0);
1786 + DRV_WriteReg32(NFI_LOCKCON_REG32, 0xFFFFFFFF);
1787 + DRV_WriteReg16(NFI_LOCK_REG16, NFI_LOCK_ON);
1788 + }
1789 +}
1790 +
1791 +static bool
1792 +mtk_nand_pio_ready(void)
1793 +{
1794 + int count = 0;
1795 + while (!(DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1)) {
1796 + count++;
1797 + if (count > 0xffff) {
1798 + printk("PIO_DIRDY timeout\n");
1799 + return false;
1800 + }
1801 + }
1802 +
1803 + return true;
1804 +}
1805 +
1806 +static bool
1807 +mtk_nand_set_command(u16 command)
1808 +{
1809 + mb();
1810 + DRV_WriteReg16(NFI_CMD_REG16, command);
1811 + return mtk_nand_status_ready(STA_CMD_STATE);
1812 +}
1813 +
1814 +static bool
1815 +mtk_nand_set_address(u32 u4ColAddr, u32 u4RowAddr, u16 u2ColNOB, u16 u2RowNOB)
1816 +{
1817 + mb();
1818 + DRV_WriteReg32(NFI_COLADDR_REG32, u4ColAddr);
1819 + DRV_WriteReg32(NFI_ROWADDR_REG32, u4RowAddr);
1820 + DRV_WriteReg16(NFI_ADDRNOB_REG16, u2ColNOB | (u2RowNOB << ADDR_ROW_NOB_SHIFT));
1821 + return mtk_nand_status_ready(STA_ADDR_STATE);
1822 +}
1823 +
1824 +static bool
1825 +mtk_nand_check_RW_count(u16 u2WriteSize)
1826 +{
1827 + u32 timeout = 0xFFFF;
1828 + u16 u2SecNum = u2WriteSize >> 9;
1829 +
1830 + while (ADDRCNTR_CNTR(DRV_Reg16(NFI_ADDRCNTR_REG16)) < u2SecNum) {
1831 + timeout--;
1832 + if (0 == timeout) {
1833 + printk(KERN_INFO "[%s] timeout\n", __FUNCTION__);
1834 + return false;
1835 + }
1836 + }
1837 + return true;
1838 +}
1839 +
1840 +static bool
1841 +mtk_nand_ready_for_read(struct nand_chip *nand, u32 u4RowAddr, u32 u4ColAddr, bool full, u8 * buf)
1842 +{
1843 + /* Reset NFI HW internal state machine and flush NFI in/out FIFO */
1844 + bool bRet = false;
1845 + u16 sec_num = 1 << (nand->page_shift - 9);
1846 + u32 col_addr = u4ColAddr;
1847 + u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
1848 + if (nand->options & NAND_BUSWIDTH_16)
1849 + col_addr /= 2;
1850 +
1851 + if (!mtk_nand_reset())
1852 + goto cleanup;
1853 + if (g_bHwEcc) {
1854 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1855 + } else {
1856 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1857 + }
1858 +
1859 + mtk_nand_set_mode(CNFG_OP_READ);
1860 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
1861 + DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
1862 +
1863 + if (full) {
1864 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1865 +
1866 + if (g_bHwEcc)
1867 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1868 + else
1869 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1870 + } else {
1871 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1872 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1873 + }
1874 +
1875 + mtk_nand_set_autoformat(full);
1876 + if (full)
1877 + if (g_bHwEcc)
1878 + ECC_Decode_Start();
1879 + if (!mtk_nand_set_command(NAND_CMD_READ0))
1880 + goto cleanup;
1881 + if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
1882 + goto cleanup;
1883 + if (!mtk_nand_set_command(NAND_CMD_READSTART))
1884 + goto cleanup;
1885 + if (!mtk_nand_status_ready(STA_NAND_BUSY))
1886 + goto cleanup;
1887 +
1888 + bRet = true;
1889 +
1890 +cleanup:
1891 + return bRet;
1892 +}
1893 +
1894 +static bool
1895 +mtk_nand_ready_for_write(struct nand_chip *nand, u32 u4RowAddr, u32 col_addr, bool full, u8 * buf)
1896 +{
1897 + bool bRet = false;
1898 + u32 sec_num = 1 << (nand->page_shift - 9);
1899 + u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
1900 + if (nand->options & NAND_BUSWIDTH_16)
1901 + col_addr /= 2;
1902 +
1903 + /* Reset NFI HW internal state machine and flush NFI in/out FIFO */
1904 + if (!mtk_nand_reset())
1905 + return false;
1906 +
1907 + mtk_nand_set_mode(CNFG_OP_PRGM);
1908 +
1909 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
1910 +
1911 + DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
1912 +
1913 + if (full) {
1914 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1915 + if (g_bHwEcc)
1916 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1917 + else
1918 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1919 + } else {
1920 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1921 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1922 + }
1923 +
1924 + mtk_nand_set_autoformat(full);
1925 +
1926 + if (full)
1927 + if (g_bHwEcc)
1928 + ECC_Encode_Start();
1929 +
1930 + if (!mtk_nand_set_command(NAND_CMD_SEQIN))
1931 + goto cleanup;
1932 + //1 FIXED ME: For Any Kind of AddrCycle
1933 + if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
1934 + goto cleanup;
1935 +
1936 + if (!mtk_nand_status_ready(STA_NAND_BUSY))
1937 + goto cleanup;
1938 +
1939 + bRet = true;
1940 +
1941 +cleanup:
1942 + return bRet;
1943 +}
1944 +
1945 +static bool
1946 +mtk_nand_check_dececc_done(u32 u4SecNum)
1947 +{
1948 + u32 timeout, dec_mask;
1949 +
1950 + timeout = 0xffff;
1951 + dec_mask = (1 << u4SecNum) - 1;
1952 + while ((dec_mask != DRV_Reg(ECC_DECDONE_REG16)) && timeout > 0)
1953 + timeout--;
1954 + if (timeout == 0) {
1955 + MSG(VERIFY, "ECC_DECDONE: timeout\n");
1956 + return false;
1957 + }
1958 + return true;
1959 +}
1960 +
1961 +static bool
1962 +mtk_nand_mcu_read_data(u8 * buf, u32 length)
1963 +{
1964 + int timeout = 0xffff;
1965 + u32 i;
1966 + u32 *buf32 = (u32 *) buf;
1967 + if ((u32) buf % 4 || length % 4)
1968 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
1969 + else
1970 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
1971 +
1972 + //DRV_WriteReg32(NFI_STRADDR_REG32, 0);
1973 + mb();
1974 + NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BRD);
1975 +
1976 + if ((u32) buf % 4 || length % 4) {
1977 + for (i = 0; (i < (length)) && (timeout > 0);) {
1978 + if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
1979 + *buf++ = (u8) DRV_Reg32(NFI_DATAR_REG32);
1980 + i++;
1981 + } else {
1982 + timeout--;
1983 + }
1984 + if (0 == timeout) {
1985 + printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
1986 + dump_nfi();
1987 + return false;
1988 + }
1989 + }
1990 + } else {
1991 + for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
1992 + if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
1993 + *buf32++ = DRV_Reg32(NFI_DATAR_REG32);
1994 + i++;
1995 + } else {
1996 + timeout--;
1997 + }
1998 + if (0 == timeout) {
1999 + printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2000 + dump_nfi();
2001 + return false;
2002 + }
2003 + }
2004 + }
2005 + return true;
2006 +}
2007 +
2008 +static bool
2009 +mtk_nand_read_page_data(struct mtd_info *mtd, u8 * pDataBuf, u32 u4Size)
2010 +{
2011 + return mtk_nand_mcu_read_data(pDataBuf, u4Size);
2012 +}
2013 +
2014 +static bool
2015 +mtk_nand_mcu_write_data(struct mtd_info *mtd, const u8 * buf, u32 length)
2016 +{
2017 + u32 timeout = 0xFFFF;
2018 + u32 i;
2019 + u32 *pBuf32;
2020 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2021 + mb();
2022 + NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BWR);
2023 + pBuf32 = (u32 *) buf;
2024 +
2025 + if ((u32) buf % 4 || length % 4)
2026 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2027 + else
2028 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2029 +
2030 + if ((u32) buf % 4 || length % 4) {
2031 + for (i = 0; (i < (length)) && (timeout > 0);) {
2032 + if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
2033 + DRV_WriteReg32(NFI_DATAW_REG32, *buf++);
2034 + i++;
2035 + } else {
2036 + timeout--;
2037 + }
2038 + if (0 == timeout) {
2039 + printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2040 + dump_nfi();
2041 + return false;
2042 + }
2043 + }
2044 + } else {
2045 + for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
2046 + if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
2047 + DRV_WriteReg32(NFI_DATAW_REG32, *pBuf32++);
2048 + i++;
2049 + } else {
2050 + timeout--;
2051 + }
2052 + if (0 == timeout) {
2053 + printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2054 + dump_nfi();
2055 + return false;
2056 + }
2057 + }
2058 + }
2059 +
2060 + return true;
2061 +}
2062 +
2063 +static bool
2064 +mtk_nand_write_page_data(struct mtd_info *mtd, u8 * buf, u32 size)
2065 +{
2066 + return mtk_nand_mcu_write_data(mtd, buf, size);
2067 +}
2068 +
2069 +static void
2070 +mtk_nand_read_fdm_data(u8 * pDataBuf, u32 u4SecNum)
2071 +{
2072 + u32 i;
2073 + u32 *pBuf32 = (u32 *) pDataBuf;
2074 +
2075 + if (pBuf32) {
2076 + for (i = 0; i < u4SecNum; ++i) {
2077 + *pBuf32++ = DRV_Reg32(NFI_FDM0L_REG32 + (i << 1));
2078 + *pBuf32++ = DRV_Reg32(NFI_FDM0M_REG32 + (i << 1));
2079 + }
2080 + }
2081 +}
2082 +
2083 +static u8 fdm_buf[64];
2084 +static void
2085 +mtk_nand_write_fdm_data(struct nand_chip *chip, u8 * pDataBuf, u32 u4SecNum)
2086 +{
2087 + u32 i, j;
2088 + u8 checksum = 0;
2089 + bool empty = true;
2090 + struct nand_oobfree *free_entry;
2091 + u32 *pBuf32;
2092 +
2093 + memcpy(fdm_buf, pDataBuf, u4SecNum * 8);
2094 +
2095 + free_entry = chip->ecc.layout->oobfree;
2096 + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free_entry[i].length; i++) {
2097 + for (j = 0; j < free_entry[i].length; j++) {
2098 + if (pDataBuf[free_entry[i].offset + j] != 0xFF)
2099 + empty = false;
2100 + checksum ^= pDataBuf[free_entry[i].offset + j];
2101 + }
2102 + }
2103 +
2104 + if (!empty) {
2105 + fdm_buf[free_entry[i - 1].offset + free_entry[i - 1].length] = checksum;
2106 + }
2107 +
2108 + pBuf32 = (u32 *) fdm_buf;
2109 + for (i = 0; i < u4SecNum; ++i) {
2110 + DRV_WriteReg32(NFI_FDM0L_REG32 + (i << 1), *pBuf32++);
2111 + DRV_WriteReg32(NFI_FDM0M_REG32 + (i << 1), *pBuf32++);
2112 + }
2113 +}
2114 +
2115 +static void
2116 +mtk_nand_stop_read(void)
2117 +{
2118 + NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
2119 + mtk_nand_reset();
2120 + if (g_bHwEcc)
2121 + ECC_Decode_End();
2122 + DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
2123 +}
2124 +
2125 +static void
2126 +mtk_nand_stop_write(void)
2127 +{
2128 + NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
2129 + if (g_bHwEcc)
2130 + ECC_Encode_End();
2131 + DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
2132 +}
2133 +
2134 +bool
2135 +mtk_nand_exec_read_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
2136 +{
2137 + u8 *buf;
2138 + bool bRet = true;
2139 + struct nand_chip *nand = mtd->priv;
2140 + u32 u4SecNum = u4PageSize >> 9;
2141 +
2142 + if (((u32) pPageBuf % 16) && local_buffer_16_align)
2143 + buf = local_buffer_16_align;
2144 + else
2145 + buf = pPageBuf;
2146 + if (mtk_nand_ready_for_read(nand, u4RowAddr, 0, true, buf)) {
2147 + int j;
2148 + for (j = 0 ; j < u4SecNum; j++) {
2149 + if (!mtk_nand_read_page_data(mtd, buf+j*512, 512))
2150 + bRet = false;
2151 + if(g_bHwEcc && !mtk_nand_check_dececc_done(j+1))
2152 + bRet = false;
2153 + if(g_bHwEcc && !mtk_nand_check_bch_error(mtd, buf+j*512, j, u4RowAddr))
2154 + bRet = false;
2155 + }
2156 + if (!mtk_nand_status_ready(STA_NAND_BUSY))
2157 + bRet = false;
2158 +
2159 + mtk_nand_read_fdm_data(pFDMBuf, u4SecNum);
2160 + mtk_nand_stop_read();
2161 + }
2162 +
2163 + if (buf == local_buffer_16_align)
2164 + memcpy(pPageBuf, buf, u4PageSize);
2165 +
2166 + return bRet;
2167 +}
2168 +
2169 +int
2170 +mtk_nand_exec_write_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
2171 +{
2172 + struct nand_chip *chip = mtd->priv;
2173 + u32 u4SecNum = u4PageSize >> 9;
2174 + u8 *buf;
2175 + u8 status;
2176 +
2177 + MSG(WRITE, "mtk_nand_exec_write_page, page: 0x%x\n", u4RowAddr);
2178 +
2179 + if (((u32) pPageBuf % 16) && local_buffer_16_align) {
2180 + printk(KERN_INFO "Data buffer not 16 bytes aligned: %p\n", pPageBuf);
2181 + memcpy(local_buffer_16_align, pPageBuf, mtd->writesize);
2182 + buf = local_buffer_16_align;
2183 + } else
2184 + buf = pPageBuf;
2185 +
2186 + if (mtk_nand_ready_for_write(chip, u4RowAddr, 0, true, buf)) {
2187 + mtk_nand_write_fdm_data(chip, pFDMBuf, u4SecNum);
2188 + (void)mtk_nand_write_page_data(mtd, buf, u4PageSize);
2189 + (void)mtk_nand_check_RW_count(u4PageSize);
2190 + mtk_nand_stop_write();
2191 + (void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
2192 + while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY) ;
2193 + }
2194 +
2195 + status = chip->waitfunc(mtd, chip);
2196 + if (status & NAND_STATUS_FAIL)
2197 + return -EIO;
2198 + return 0;
2199 +}
2200 +
2201 +static int
2202 +get_start_end_block(struct mtd_info *mtd, int block, int *start_blk, int *end_blk)
2203 +{
2204 + struct nand_chip *chip = mtd->priv;
2205 + int i;
2206 +
2207 + *start_blk = 0;
2208 + for (i = 0; i <= part_num; i++)
2209 + {
2210 + if (i == part_num)
2211 + {
2212 + // try the last reset partition
2213 + *end_blk = (chip->chipsize >> chip->phys_erase_shift) - 1;
2214 + if (*start_blk <= *end_blk)
2215 + {
2216 + if ((block >= *start_blk) && (block <= *end_blk))
2217 + break;
2218 + }
2219 + }
2220 + // skip All partition entry
2221 + else if (g_pasStatic_Partition[i].size == MTDPART_SIZ_FULL)
2222 + {
2223 + continue;
2224 + }
2225 + *end_blk = *start_blk + (g_pasStatic_Partition[i].size >> chip->phys_erase_shift) - 1;
2226 + if ((block >= *start_blk) && (block <= *end_blk))
2227 + break;
2228 + *start_blk = *end_blk + 1;
2229 + }
2230 + if (*start_blk > *end_blk)
2231 + {
2232 + return -1;
2233 + }
2234 + return 0;
2235 +}
2236 +
2237 +static int
2238 +block_remap(struct mtd_info *mtd, int block)
2239 +{
2240 + struct nand_chip *chip = mtd->priv;
2241 + int start_blk, end_blk;
2242 + int j, block_offset;
2243 + int bad_block = 0;
2244 +
2245 + if (chip->bbt == NULL) {
2246 + printk("ERROR!! no bbt table for block_remap\n");
2247 + return -1;
2248 + }
2249 +
2250 + if (get_start_end_block(mtd, block, &start_blk, &end_blk) < 0) {
2251 + printk("ERROR!! can not find start_blk and end_blk\n");
2252 + return -1;
2253 + }
2254 +
2255 + block_offset = block - start_blk;
2256 + for (j = start_blk; j <= end_blk;j++) {
2257 + if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) == 0x0) {
2258 + if (!block_offset)
2259 + break;
2260 + block_offset--;
2261 + } else {
2262 + bad_block++;
2263 + }
2264 + }
2265 + if (j <= end_blk) {
2266 + return j;
2267 + } else {
2268 + // remap to the bad block
2269 + for (j = end_blk; bad_block > 0; j--)
2270 + {
2271 + if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) != 0x0)
2272 + {
2273 + bad_block--;
2274 + if (bad_block <= block_offset)
2275 + return j;
2276 + }
2277 + }
2278 + }
2279 +
2280 + printk("Error!! block_remap error\n");
2281 + return -1;
2282 +}
2283 +
2284 +int
2285 +check_block_remap(struct mtd_info *mtd, int block)
2286 +{
2287 + if (shift_on_bbt)
2288 + return block_remap(mtd, block);
2289 + else
2290 + return block;
2291 +}
2292 +EXPORT_SYMBOL(check_block_remap);
2293 +
2294 +
2295 +static int
2296 +write_next_on_fail(struct mtd_info *mtd, char *write_buf, int page, int * to_blk)
2297 +{
2298 + struct nand_chip *chip = mtd->priv;
2299 + int i, j, to_page = 0, first_page;
2300 + char *buf, *oob;
2301 + int start_blk = 0, end_blk;
2302 + int mapped_block;
2303 + int page_per_block_bit = chip->phys_erase_shift - chip->page_shift;
2304 + int block = page >> page_per_block_bit;
2305 +
2306 + // find next available block in the same MTD partition
2307 + mapped_block = block_remap(mtd, block);
2308 + if (mapped_block == -1)
2309 + return NAND_STATUS_FAIL;
2310 +
2311 + get_start_end_block(mtd, block, &start_blk, &end_blk);
2312 +
2313 + buf = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL | GFP_DMA);
2314 + if (buf == NULL)
2315 + return -1;
2316 +
2317 + oob = buf + mtd->writesize;
2318 + for ((*to_blk) = block + 1; (*to_blk) <= end_blk ; (*to_blk)++) {
2319 + if (nand_bbt_get(mtd, (*to_blk) << page_per_block_bit) == 0) {
2320 + int status;
2321 + status = mtk_nand_erase_hw(mtd, (*to_blk) << page_per_block_bit);
2322 + if (status & NAND_STATUS_FAIL) {
2323 + mtk_nand_block_markbad_hw(mtd, (*to_blk) << chip->phys_erase_shift);
2324 + nand_bbt_set(mtd, (*to_blk) << page_per_block_bit, 0x3);
2325 + } else {
2326 + /* good block */
2327 + to_page = (*to_blk) << page_per_block_bit;
2328 + break;
2329 + }
2330 + }
2331 + }
2332 +
2333 + if (!to_page) {
2334 + kfree(buf);
2335 + return -1;
2336 + }
2337 +
2338 + first_page = (page >> page_per_block_bit) << page_per_block_bit;
2339 + for (i = 0; i < (1 << page_per_block_bit); i++) {
2340 + if ((first_page + i) != page) {
2341 + mtk_nand_read_oob_hw(mtd, chip, (first_page+i));
2342 + for (j = 0; j < mtd->oobsize; j++)
2343 + if (chip->oob_poi[j] != (unsigned char)0xff)
2344 + break;
2345 + if (j < mtd->oobsize) {
2346 + mtk_nand_exec_read_page(mtd, (first_page+i), mtd->writesize, buf, oob);
2347 + memset(oob, 0xff, mtd->oobsize);
2348 + if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)buf, oob) != 0) {
2349 + int ret, new_blk = 0;
2350 + nand_bbt_set(mtd, to_page, 0x3);
2351 + ret = write_next_on_fail(mtd, buf, to_page + i, &new_blk);
2352 + if (ret) {
2353 + kfree(buf);
2354 + mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2355 + return ret;
2356 + }
2357 + mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2358 + *to_blk = new_blk;
2359 + to_page = ((*to_blk) << page_per_block_bit);
2360 + }
2361 + }
2362 + } else {
2363 + memset(chip->oob_poi, 0xff, mtd->oobsize);
2364 + if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)write_buf, chip->oob_poi) != 0) {
2365 + int ret, new_blk = 0;
2366 + nand_bbt_set(mtd, to_page, 0x3);
2367 + ret = write_next_on_fail(mtd, write_buf, to_page + i, &new_blk);
2368 + if (ret) {
2369 + kfree(buf);
2370 + mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2371 + return ret;
2372 + }
2373 + mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2374 + *to_blk = new_blk;
2375 + to_page = ((*to_blk) << page_per_block_bit);
2376 + }
2377 + }
2378 + }
2379 +
2380 + kfree(buf);
2381 +
2382 + return 0;
2383 +}
2384 +
2385 +static int
2386 +mtk_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset,
2387 + int data_len, const u8 * buf, int oob_required, int page, int cached, int raw)
2388 +{
2389 + int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2390 + int block = page / page_per_block;
2391 + u16 page_in_block = page % page_per_block;
2392 + int mapped_block = block;
2393 +
2394 +#if defined(MTK_NAND_BMT)
2395 + mapped_block = get_mapping_block_index(block);
2396 + // write bad index into oob
2397 + if (mapped_block != block)
2398 + set_bad_index_to_oob(chip->oob_poi, block);
2399 + else
2400 + set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
2401 +#else
2402 + if (shift_on_bbt) {
2403 + mapped_block = block_remap(mtd, block);
2404 + if (mapped_block == -1)
2405 + return NAND_STATUS_FAIL;
2406 + if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2407 + return NAND_STATUS_FAIL;
2408 + }
2409 +#endif
2410 + do {
2411 + if (mtk_nand_exec_write_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, (u8 *)buf, chip->oob_poi)) {
2412 + MSG(INIT, "write fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
2413 +#if defined(MTK_NAND_BMT)
2414 + if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift, UPDATE_WRITE_FAIL, (u8 *) buf, chip->oob_poi)) {
2415 + MSG(INIT, "Update BMT success\n");
2416 + return 0;
2417 + } else {
2418 + MSG(INIT, "Update BMT fail\n");
2419 + return -EIO;
2420 + }
2421 +#else
2422 + {
2423 + int new_blk;
2424 + nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
2425 + if (write_next_on_fail(mtd, (char *)buf, page_in_block + mapped_block * page_per_block, &new_blk) != 0)
2426 + {
2427 + mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2428 + return NAND_STATUS_FAIL;
2429 + }
2430 + mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2431 + break;
2432 + }
2433 +#endif
2434 + } else
2435 + break;
2436 + } while(1);
2437 +
2438 + return 0;
2439 +}
2440 +
2441 +static void
2442 +mtk_nand_command_bp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
2443 +{
2444 + struct nand_chip *nand = mtd->priv;
2445 +
2446 + switch (command) {
2447 + case NAND_CMD_SEQIN:
2448 + memset(g_kCMD.au1OOB, 0xFF, sizeof(g_kCMD.au1OOB));
2449 + g_kCMD.pDataBuf = NULL;
2450 + g_kCMD.u4RowAddr = page_addr;
2451 + g_kCMD.u4ColAddr = column;
2452 + break;
2453 +
2454 + case NAND_CMD_PAGEPROG:
2455 + if (g_kCMD.pDataBuf || (0xFF != g_kCMD.au1OOB[nand_badblock_offset])) {
2456 + u8 *pDataBuf = g_kCMD.pDataBuf ? g_kCMD.pDataBuf : nand->buffers->databuf;
2457 + mtk_nand_exec_write_page(mtd, g_kCMD.u4RowAddr, mtd->writesize, pDataBuf, g_kCMD.au1OOB);
2458 + g_kCMD.u4RowAddr = (u32) - 1;
2459 + g_kCMD.u4OOBRowAddr = (u32) - 1;
2460 + }
2461 + break;
2462 +
2463 + case NAND_CMD_READOOB:
2464 + g_kCMD.u4RowAddr = page_addr;
2465 + g_kCMD.u4ColAddr = column + mtd->writesize;
2466 + break;
2467 +
2468 + case NAND_CMD_READ0:
2469 + g_kCMD.u4RowAddr = page_addr;
2470 + g_kCMD.u4ColAddr = column;
2471 + break;
2472 +
2473 + case NAND_CMD_ERASE1:
2474 + nand->state=FL_ERASING;
2475 + (void)mtk_nand_reset();
2476 + mtk_nand_set_mode(CNFG_OP_ERASE);
2477 + (void)mtk_nand_set_command(NAND_CMD_ERASE1);
2478 + (void)mtk_nand_set_address(0, page_addr, 0, devinfo.addr_cycle - 2);
2479 + break;
2480 +
2481 + case NAND_CMD_ERASE2:
2482 + (void)mtk_nand_set_command(NAND_CMD_ERASE2);
2483 + while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
2484 + ;
2485 + break;
2486 +
2487 + case NAND_CMD_STATUS:
2488 + (void)mtk_nand_reset();
2489 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2490 + mtk_nand_set_mode(CNFG_OP_SRD);
2491 + mtk_nand_set_mode(CNFG_READ_EN);
2492 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
2493 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2494 + (void)mtk_nand_set_command(NAND_CMD_STATUS);
2495 + NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
2496 + mb();
2497 + DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD | (1 << CON_NFI_NOB_SHIFT));
2498 + g_bcmdstatus = true;
2499 + break;
2500 +
2501 + case NAND_CMD_RESET:
2502 + (void)mtk_nand_reset();
2503 + DRV_WriteReg16(NFI_INTR_EN_REG16, INTR_RST_DONE_EN);
2504 + (void)mtk_nand_set_command(NAND_CMD_RESET);
2505 + DRV_WriteReg16(NFI_BASE+0x44, 0xF1);
2506 + while(!(DRV_Reg16(NFI_INTR_REG16)&INTR_RST_DONE_EN))
2507 + ;
2508 + break;
2509 +
2510 + case NAND_CMD_READID:
2511 + mtk_nand_reset();
2512 + /* Disable HW ECC */
2513 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2514 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
2515 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN | CNFG_BYTE_RW);
2516 + (void)mtk_nand_reset();
2517 + mb();
2518 + mtk_nand_set_mode(CNFG_OP_SRD);
2519 + (void)mtk_nand_set_command(NAND_CMD_READID);
2520 + (void)mtk_nand_set_address(0, 0, 1, 0);
2521 + DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD);
2522 + while (DRV_Reg32(NFI_STA_REG32) & STA_DATAR_STATE)
2523 + ;
2524 + break;
2525 +
2526 + default:
2527 + BUG();
2528 + break;
2529 + }
2530 +}
2531 +
2532 +static void
2533 +mtk_nand_select_chip(struct mtd_info *mtd, int chip)
2534 +{
2535 + if ((chip == -1) && (false == g_bInitDone)) {
2536 + struct nand_chip *nand = mtd->priv;
2537 + struct mtk_nand_host *host = nand->priv;
2538 + struct mtk_nand_host_hw *hw = host->hw;
2539 + u32 spare_per_sector = mtd->oobsize / (mtd->writesize / 512);
2540 + u32 ecc_bit = 4;
2541 + u32 spare_bit = PAGEFMT_SPARE_16;
2542 +
2543 + if (spare_per_sector >= 28) {
2544 + spare_bit = PAGEFMT_SPARE_28;
2545 + ecc_bit = 12;
2546 + spare_per_sector = 28;
2547 + } else if (spare_per_sector >= 27) {
2548 + spare_bit = PAGEFMT_SPARE_27;
2549 + ecc_bit = 8;
2550 + spare_per_sector = 27;
2551 + } else if (spare_per_sector >= 26) {
2552 + spare_bit = PAGEFMT_SPARE_26;
2553 + ecc_bit = 8;
2554 + spare_per_sector = 26;
2555 + } else if (spare_per_sector >= 16) {
2556 + spare_bit = PAGEFMT_SPARE_16;
2557 + ecc_bit = 4;
2558 + spare_per_sector = 16;
2559 + } else {
2560 + MSG(INIT, "[NAND]: NFI not support oobsize: %x\n", spare_per_sector);
2561 + ASSERT(0);
2562 + }
2563 + mtd->oobsize = spare_per_sector*(mtd->writesize/512);
2564 + MSG(INIT, "[NAND]select ecc bit:%d, sparesize :%d spare_per_sector=%d\n",ecc_bit,mtd->oobsize,spare_per_sector);
2565 + /* Setup PageFormat */
2566 + if (4096 == mtd->writesize) {
2567 + NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_4K);
2568 + nand->cmdfunc = mtk_nand_command_bp;
2569 + } else if (2048 == mtd->writesize) {
2570 + NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_2K);
2571 + nand->cmdfunc = mtk_nand_command_bp;
2572 + }
2573 + ECC_Config(hw,ecc_bit);
2574 + g_bInitDone = true;
2575 + }
2576 + switch (chip) {
2577 + case -1:
2578 + break;
2579 + case 0:
2580 + case 1:
2581 + /* Jun Shen, 2011.04.13 */
2582 + /* Note: MT6577 EVB NAND is mounted on CS0, but FPGA is CS1 */
2583 + DRV_WriteReg16(NFI_CSEL_REG16, chip);
2584 + /* Jun Shen, 2011.04.13 */
2585 + break;
2586 + }
2587 +}
2588 +
2589 +static uint8_t
2590 +mtk_nand_read_byte(struct mtd_info *mtd)
2591 +{
2592 + uint8_t retval = 0;
2593 +
2594 + if (!mtk_nand_pio_ready()) {
2595 + printk("pio ready timeout\n");
2596 + retval = false;
2597 + }
2598 +
2599 + if (g_bcmdstatus) {
2600 + retval = DRV_Reg8(NFI_DATAR_REG32);
2601 + NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
2602 + mtk_nand_reset();
2603 + if (g_bHwEcc) {
2604 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2605 + } else {
2606 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2607 + }
2608 + g_bcmdstatus = false;
2609 + } else
2610 + retval = DRV_Reg8(NFI_DATAR_REG32);
2611 +
2612 + return retval;
2613 +}
2614 +
2615 +static void
2616 +mtk_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
2617 +{
2618 + struct nand_chip *nand = (struct nand_chip *)mtd->priv;
2619 + struct NAND_CMD *pkCMD = &g_kCMD;
2620 + u32 u4ColAddr = pkCMD->u4ColAddr;
2621 + u32 u4PageSize = mtd->writesize;
2622 +
2623 + if (u4ColAddr < u4PageSize) {
2624 + if ((u4ColAddr == 0) && (len >= u4PageSize)) {
2625 + mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, pkCMD->au1OOB);
2626 + if (len > u4PageSize) {
2627 + u32 u4Size = min(len - u4PageSize, sizeof(pkCMD->au1OOB));
2628 + memcpy(buf + u4PageSize, pkCMD->au1OOB, u4Size);
2629 + }
2630 + } else {
2631 + mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
2632 + memcpy(buf, nand->buffers->databuf + u4ColAddr, len);
2633 + }
2634 + pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
2635 + } else {
2636 + u32 u4Offset = u4ColAddr - u4PageSize;
2637 + u32 u4Size = min(len - u4Offset, sizeof(pkCMD->au1OOB));
2638 + if (pkCMD->u4OOBRowAddr != pkCMD->u4RowAddr) {
2639 + mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
2640 + pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
2641 + }
2642 + memcpy(buf, pkCMD->au1OOB + u4Offset, u4Size);
2643 + }
2644 + pkCMD->u4ColAddr += len;
2645 +}
2646 +
2647 +static void
2648 +mtk_nand_write_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
2649 +{
2650 + struct NAND_CMD *pkCMD = &g_kCMD;
2651 + u32 u4ColAddr = pkCMD->u4ColAddr;
2652 + u32 u4PageSize = mtd->writesize;
2653 + int i4Size, i;
2654 +
2655 + if (u4ColAddr >= u4PageSize) {
2656 + u32 u4Offset = u4ColAddr - u4PageSize;
2657 + u8 *pOOB = pkCMD->au1OOB + u4Offset;
2658 + i4Size = min(len, (int)(sizeof(pkCMD->au1OOB) - u4Offset));
2659 + for (i = 0; i < i4Size; i++) {
2660 + pOOB[i] &= buf[i];
2661 + }
2662 + } else {
2663 + pkCMD->pDataBuf = (u8 *) buf;
2664 + }
2665 +
2666 + pkCMD->u4ColAddr += len;
2667 +}
2668 +
2669 +static int
2670 +mtk_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, int oob_required)
2671 +{
2672 + mtk_nand_write_buf(mtd, buf, mtd->writesize);
2673 + mtk_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
2674 + return 0;
2675 +}
2676 +
2677 +static int
2678 +mtk_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, int oob_required, int page)
2679 +{
2680 + struct NAND_CMD *pkCMD = &g_kCMD;
2681 + u32 u4ColAddr = pkCMD->u4ColAddr;
2682 + u32 u4PageSize = mtd->writesize;
2683 +
2684 + if (u4ColAddr == 0) {
2685 + mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, chip->oob_poi);
2686 + pkCMD->u4ColAddr += u4PageSize + mtd->oobsize;
2687 + }
2688 +
2689 + return 0;
2690 +}
2691 +
2692 +static int
2693 +mtk_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, u8 * buf, int page)
2694 +{
2695 + int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2696 + int block = page / page_per_block;
2697 + u16 page_in_block = page % page_per_block;
2698 + int mapped_block = block;
2699 +
2700 +#if defined (MTK_NAND_BMT)
2701 + mapped_block = get_mapping_block_index(block);
2702 + if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block,
2703 + mtd->writesize, buf, chip->oob_poi))
2704 + return 0;
2705 +#else
2706 + if (shift_on_bbt) {
2707 + mapped_block = block_remap(mtd, block);
2708 + if (mapped_block == -1)
2709 + return NAND_STATUS_FAIL;
2710 + if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2711 + return NAND_STATUS_FAIL;
2712 + }
2713 +
2714 + if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, buf, chip->oob_poi))
2715 + return 0;
2716 + else
2717 + return -EIO;
2718 +#endif
2719 +}
2720 +
2721 +int
2722 +mtk_nand_erase_hw(struct mtd_info *mtd, int page)
2723 +{
2724 + struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2725 +
2726 + chip->erase_cmd(mtd, page);
2727 +
2728 + return chip->waitfunc(mtd, chip);
2729 +}
2730 +
2731 +static int
2732 +mtk_nand_erase(struct mtd_info *mtd, int page)
2733 +{
2734 + // get mapping
2735 + struct nand_chip *chip = mtd->priv;
2736 + int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2737 + int page_in_block = page % page_per_block;
2738 + int block = page / page_per_block;
2739 + int mapped_block = block;
2740 +
2741 +#if defined(MTK_NAND_BMT)
2742 + mapped_block = get_mapping_block_index(block);
2743 +#else
2744 + if (shift_on_bbt) {
2745 + mapped_block = block_remap(mtd, block);
2746 + if (mapped_block == -1)
2747 + return NAND_STATUS_FAIL;
2748 + if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2749 + return NAND_STATUS_FAIL;
2750 + }
2751 +#endif
2752 +
2753 + do {
2754 + int status = mtk_nand_erase_hw(mtd, page_in_block + page_per_block * mapped_block);
2755 +
2756 + if (status & NAND_STATUS_FAIL) {
2757 +#if defined (MTK_NAND_BMT)
2758 + if (update_bmt( (page_in_block + mapped_block * page_per_block) << chip->page_shift,
2759 + UPDATE_ERASE_FAIL, NULL, NULL))
2760 + {
2761 + MSG(INIT, "Erase fail at block: 0x%x, update BMT success\n", mapped_block);
2762 + return 0;
2763 + } else {
2764 + MSG(INIT, "Erase fail at block: 0x%x, update BMT fail\n", mapped_block);
2765 + return NAND_STATUS_FAIL;
2766 + }
2767 +#else
2768 + mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2769 + nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
2770 + if (shift_on_bbt) {
2771 + mapped_block = block_remap(mtd, block);
2772 + if (mapped_block == -1)
2773 + return NAND_STATUS_FAIL;
2774 + if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2775 + return NAND_STATUS_FAIL;
2776 + } else
2777 + return NAND_STATUS_FAIL;
2778 +#endif
2779 + } else
2780 + break;
2781 + } while(1);
2782 +
2783 + return 0;
2784 +}
2785 +
2786 +static int
2787 +mtk_nand_read_oob_raw(struct mtd_info *mtd, uint8_t * buf, int page_addr, int len)
2788 +{
2789 + struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2790 + u32 col_addr = 0;
2791 + u32 sector = 0;
2792 + int res = 0;
2793 + u32 colnob = 2, rawnob = devinfo.addr_cycle - 2;
2794 + int randomread = 0;
2795 + int read_len = 0;
2796 + int sec_num = 1<<(chip->page_shift-9);
2797 + int spare_per_sector = mtd->oobsize/sec_num;
2798 +
2799 + if (len > NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
2800 + printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
2801 + return -EINVAL;
2802 + }
2803 + if (len > spare_per_sector)
2804 + randomread = 1;
2805 + if (!randomread || !(devinfo.advancedmode & RAMDOM_READ)) {
2806 + while (len > 0) {
2807 + read_len = min(len, spare_per_sector);
2808 + col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector); // TODO: Fix this hard-code 16
2809 + if (!mtk_nand_ready_for_read(chip, page_addr, col_addr, false, NULL)) {
2810 + printk(KERN_WARNING "mtk_nand_ready_for_read return failed\n");
2811 + res = -EIO;
2812 + goto error;
2813 + }
2814 + if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
2815 + printk(KERN_WARNING "mtk_nand_mcu_read_data return failed\n");
2816 + res = -EIO;
2817 + goto error;
2818 + }
2819 + mtk_nand_check_RW_count(read_len);
2820 + mtk_nand_stop_read();
2821 + sector++;
2822 + len -= read_len;
2823 + }
2824 + } else {
2825 + col_addr = NAND_SECTOR_SIZE;
2826 + if (chip->options & NAND_BUSWIDTH_16)
2827 + col_addr /= 2;
2828 + if (!mtk_nand_reset())
2829 + goto error;
2830 + mtk_nand_set_mode(0x6000);
2831 + NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
2832 + DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
2833 +
2834 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
2835 + NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2836 +
2837 + mtk_nand_set_autoformat(false);
2838 +
2839 + if (!mtk_nand_set_command(NAND_CMD_READ0))
2840 + goto error;
2841 + //1 FIXED ME: For Any Kind of AddrCycle
2842 + if (!mtk_nand_set_address(col_addr, page_addr, colnob, rawnob))
2843 + goto error;
2844 + if (!mtk_nand_set_command(NAND_CMD_READSTART))
2845 + goto error;
2846 + if (!mtk_nand_status_ready(STA_NAND_BUSY))
2847 + goto error;
2848 + read_len = min(len, spare_per_sector);
2849 + if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
2850 + printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
2851 + res = -EIO;
2852 + goto error;
2853 + }
2854 + sector++;
2855 + len -= read_len;
2856 + mtk_nand_stop_read();
2857 + while (len > 0) {
2858 + read_len = min(len, spare_per_sector);
2859 + if (!mtk_nand_set_command(0x05))
2860 + goto error;
2861 + col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector);
2862 + if (chip->options & NAND_BUSWIDTH_16)
2863 + col_addr /= 2;
2864 + DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);
2865 + DRV_WriteReg16(NFI_ADDRNOB_REG16, 2);
2866 + DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
2867 + if (!mtk_nand_status_ready(STA_ADDR_STATE))
2868 + goto error;
2869 + if (!mtk_nand_set_command(0xE0))
2870 + goto error;
2871 + if (!mtk_nand_status_ready(STA_NAND_BUSY))
2872 + goto error;
2873 + if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
2874 + printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
2875 + res = -EIO;
2876 + goto error;
2877 + }
2878 + mtk_nand_stop_read();
2879 + sector++;
2880 + len -= read_len;
2881 + }
2882 + }
2883 +error:
2884 + NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
2885 + return res;
2886 +}
2887 +
2888 +static int
2889 +mtk_nand_write_oob_raw(struct mtd_info *mtd, const uint8_t * buf, int page_addr, int len)
2890 +{
2891 + struct nand_chip *chip = mtd->priv;
2892 + u32 col_addr = 0;
2893 + u32 sector = 0;
2894 + int write_len = 0;
2895 + int status;
2896 + int sec_num = 1<<(chip->page_shift-9);
2897 + int spare_per_sector = mtd->oobsize/sec_num;
2898 +
2899 + if (len > NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
2900 + printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
2901 + return -EINVAL;
2902 + }
2903 +
2904 + while (len > 0) {
2905 + write_len = min(len, spare_per_sector);
2906 + col_addr = sector * (NAND_SECTOR_SIZE + spare_per_sector) + NAND_SECTOR_SIZE;
2907 + if (!mtk_nand_ready_for_write(chip, page_addr, col_addr, false, NULL))
2908 + return -EIO;
2909 + if (!mtk_nand_mcu_write_data(mtd, buf + sector * spare_per_sector, write_len))
2910 + return -EIO;
2911 + (void)mtk_nand_check_RW_count(write_len);
2912 + NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
2913 + (void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
2914 + while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
2915 + ;
2916 + status = chip->waitfunc(mtd, chip);
2917 + if (status & NAND_STATUS_FAIL) {
2918 + printk(KERN_INFO "status: %d\n", status);
2919 + return -EIO;
2920 + }
2921 + len -= write_len;
2922 + sector++;
2923 + }
2924 +
2925 + return 0;
2926 +}
2927 +
2928 +static int
2929 +mtk_nand_write_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
2930 +{
2931 + int i, iter;
2932 + int sec_num = 1<<(chip->page_shift-9);
2933 + int spare_per_sector = mtd->oobsize/sec_num;
2934 +
2935 + memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
2936 +
2937 + // copy ecc data
2938 + for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
2939 + iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) * spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
2940 + local_oob_buf[iter] = chip->oob_poi[chip->ecc.layout->eccpos[i]];
2941 + }
2942 +
2943 + // copy FDM data
2944 + for (i = 0; i < sec_num; i++)
2945 + memcpy(&local_oob_buf[i * spare_per_sector], &chip->oob_poi[i * OOB_AVAI_PER_SECTOR], OOB_AVAI_PER_SECTOR);
2946 +
2947 + return mtk_nand_write_oob_raw(mtd, local_oob_buf, page, mtd->oobsize);
2948 +}
2949 +
2950 +static int mtk_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
2951 +{
2952 + int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2953 + int block = page / page_per_block;
2954 + u16 page_in_block = page % page_per_block;
2955 + int mapped_block = block;
2956 +
2957 +#if defined(MTK_NAND_BMT)
2958 + mapped_block = get_mapping_block_index(block);
2959 + // write bad index into oob
2960 + if (mapped_block != block)
2961 + set_bad_index_to_oob(chip->oob_poi, block);
2962 + else
2963 + set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
2964 +#else
2965 + if (shift_on_bbt)
2966 + {
2967 + mapped_block = block_remap(mtd, block);
2968 + if (mapped_block == -1)
2969 + return NAND_STATUS_FAIL;
2970 + if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2971 + return NAND_STATUS_FAIL;
2972 + }
2973 +#endif
2974 + do {
2975 + if (mtk_nand_write_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block /* page */)) {
2976 + MSG(INIT, "write oob fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
2977 +#if defined(MTK_NAND_BMT)
2978 + if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift,
2979 + UPDATE_WRITE_FAIL, NULL, chip->oob_poi))
2980 + {
2981 + MSG(INIT, "Update BMT success\n");
2982 + return 0;
2983 + } else {
2984 + MSG(INIT, "Update BMT fail\n");
2985 + return -EIO;
2986 + }
2987 +#else
2988 + mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2989 + nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
2990 + if (shift_on_bbt) {
2991 + mapped_block = block_remap(mtd, mapped_block);
2992 + if (mapped_block == -1)
2993 + return NAND_STATUS_FAIL;
2994 + if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2995 + return NAND_STATUS_FAIL;
2996 + } else {
2997 + return NAND_STATUS_FAIL;
2998 + }
2999 +#endif
3000 + } else
3001 + break;
3002 + } while (1);
3003 +
3004 + return 0;
3005 +}
3006 +
3007 +int
3008 +mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t offset)
3009 +{
3010 + struct nand_chip *chip = mtd->priv;
3011 + int block = (int)offset >> chip->phys_erase_shift;
3012 + int page = block * (1 << (chip->phys_erase_shift - chip->page_shift));
3013 + u8 buf[8];
3014 +
3015 + memset(buf, 0xFF, 8);
3016 + buf[0] = 0;
3017 + return mtk_nand_write_oob_raw(mtd, buf, page, 8);
3018 +}
3019 +
3020 +static int
3021 +mtk_nand_block_markbad(struct mtd_info *mtd, loff_t offset)
3022 +{
3023 + struct nand_chip *chip = mtd->priv;
3024 + int block = (int)offset >> chip->phys_erase_shift;
3025 + int ret;
3026 + int mapped_block = block;
3027 +
3028 + nand_get_device(chip, mtd, FL_WRITING);
3029 +
3030 +#if defined(MTK_NAND_BMT)
3031 + mapped_block = get_mapping_block_index(block);
3032 + ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
3033 +#else
3034 + if (shift_on_bbt) {
3035 + mapped_block = block_remap(mtd, block);
3036 + if (mapped_block == -1) {
3037 + printk("NAND mark bad failed\n");
3038 + nand_release_device(mtd);
3039 + return NAND_STATUS_FAIL;
3040 + }
3041 + }
3042 + ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
3043 +#endif
3044 + nand_release_device(mtd);
3045 +
3046 + return ret;
3047 +}
3048 +
3049 +int
3050 +mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
3051 +{
3052 + int i;
3053 + u8 iter = 0;
3054 +
3055 + int sec_num = 1<<(chip->page_shift-9);
3056 + int spare_per_sector = mtd->oobsize/sec_num;
3057 +
3058 + if (mtk_nand_read_oob_raw(mtd, chip->oob_poi, page, mtd->oobsize)) {
3059 + printk(KERN_ERR "[%s]mtk_nand_read_oob_raw return failed\n", __FUNCTION__);
3060 + return -EIO;
3061 + }
3062 +
3063 + // adjust to ecc physical layout to memory layout
3064 + /*********************************************************/
3065 + /* FDM0 | ECC0 | FDM1 | ECC1 | FDM2 | ECC2 | FDM3 | ECC3 */
3066 + /* 8B | 8B | 8B | 8B | 8B | 8B | 8B | 8B */
3067 + /*********************************************************/
3068 +
3069 + memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
3070 + // copy ecc data
3071 + for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
3072 + iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) * spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
3073 + chip->oob_poi[chip->ecc.layout->eccpos[i]] = local_oob_buf[iter];
3074 + }
3075 +
3076 + // copy FDM data
3077 + for (i = 0; i < sec_num; i++) {
3078 + memcpy(&chip->oob_poi[i * OOB_AVAI_PER_SECTOR], &local_oob_buf[i * spare_per_sector], OOB_AVAI_PER_SECTOR);
3079 + }
3080 +
3081 + return 0;
3082 +}
3083 +
3084 +static int
3085 +mtk_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
3086 +{
3087 + int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3088 + int block = page / page_per_block;
3089 + u16 page_in_block = page % page_per_block;
3090 + int mapped_block = block;
3091 +
3092 +#if defined (MTK_NAND_BMT)
3093 + mapped_block = get_mapping_block_index(block);
3094 + mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block);
3095 +#else
3096 + if (shift_on_bbt) {
3097 + mapped_block = block_remap(mtd, block);
3098 + if (mapped_block == -1)
3099 + return NAND_STATUS_FAIL;
3100 + // allow to read oob even if the block is bad
3101 + }
3102 + if (mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block)!=0)
3103 + return -1;
3104 +#endif
3105 + return 0;
3106 +}
3107 +
3108 +int
3109 +mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs)
3110 +{
3111 + struct nand_chip *chip = (struct nand_chip *)mtd->priv;
3112 + int page_addr = (int)(ofs >> chip->page_shift);
3113 + unsigned int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3114 + unsigned char oob_buf[8];
3115 +
3116 + page_addr &= ~(page_per_block - 1);
3117 + if (mtk_nand_read_oob_raw(mtd, oob_buf, page_addr, sizeof(oob_buf))) {
3118 + printk(KERN_WARNING "mtk_nand_read_oob_raw return error\n");
3119 + return 1;
3120 + }
3121 +
3122 + if (oob_buf[0] != 0xff) {
3123 + printk(KERN_WARNING "Bad block detected at 0x%x, oob_buf[0] is 0x%x\n", page_addr, oob_buf[0]);
3124 + // dump_nfi();
3125 + return 1;
3126 + }
3127 +
3128 + return 0;
3129 +}
3130 +
3131 +static int
3132 +mtk_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
3133 +{
3134 + int chipnr = 0;
3135 + struct nand_chip *chip = (struct nand_chip *)mtd->priv;
3136 + int block = (int)ofs >> chip->phys_erase_shift;
3137 + int mapped_block = block;
3138 + int ret;
3139 +
3140 + if (getchip) {
3141 + chipnr = (int)(ofs >> chip->chip_shift);
3142 + nand_get_device(chip, mtd, FL_READING);
3143 + /* Select the NAND device */
3144 + chip->select_chip(mtd, chipnr);
3145 + }
3146 +
3147 +#if defined(MTK_NAND_BMT)
3148 + mapped_block = get_mapping_block_index(block);
3149 +#else
3150 + if (shift_on_bbt) {
3151 + mapped_block = block_remap(mtd, block);
3152 + if (mapped_block == -1) {
3153 + if (getchip)
3154 + nand_release_device(mtd);
3155 + return NAND_STATUS_FAIL;
3156 + }
3157 + }
3158 +#endif
3159 +
3160 + ret = mtk_nand_block_bad_hw(mtd, mapped_block << chip->phys_erase_shift);
3161 +#if defined (MTK_NAND_BMT)
3162 + if (ret) {
3163 + MSG(INIT, "Unmapped bad block: 0x%x\n", mapped_block);
3164 + if (update_bmt(mapped_block << chip->phys_erase_shift, UPDATE_UNMAPPED_BLOCK, NULL, NULL)) {
3165 + MSG(INIT, "Update BMT success\n");
3166 + ret = 0;
3167 + } else {
3168 + MSG(INIT, "Update BMT fail\n");
3169 + ret = 1;
3170 + }
3171 + }
3172 +#endif
3173 +
3174 + if (getchip)
3175 + nand_release_device(mtd);
3176 +
3177 + return ret;
3178 +}
3179 +
3180 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
3181 +char gacBuf[4096 + 288];
3182 +
3183 +static int
3184 +mtk_nand_verify_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
3185 +{
3186 + struct nand_chip *chip = (struct nand_chip *)mtd->priv;
3187 + struct NAND_CMD *pkCMD = &g_kCMD;
3188 + u32 u4PageSize = mtd->writesize;
3189 + u32 *pSrc, *pDst;
3190 + int i;
3191 +
3192 + mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, gacBuf, gacBuf + u4PageSize);
3193 +
3194 + pSrc = (u32 *) buf;
3195 + pDst = (u32 *) gacBuf;
3196 + len = len / sizeof(u32);
3197 + for (i = 0; i < len; ++i) {
3198 + if (*pSrc != *pDst) {
3199 + MSG(VERIFY, "mtk_nand_verify_buf page fail at page %d\n", pkCMD->u4RowAddr);
3200 + return -1;
3201 + }
3202 + pSrc++;
3203 + pDst++;
3204 + }
3205 +
3206 + pSrc = (u32 *) chip->oob_poi;
3207 + pDst = (u32 *) (gacBuf + u4PageSize);
3208 +
3209 + if ((pSrc[0] != pDst[0]) || (pSrc[1] != pDst[1]) || (pSrc[2] != pDst[2]) || (pSrc[3] != pDst[3]) || (pSrc[4] != pDst[4]) || (pSrc[5] != pDst[5])) {
3210 + // TODO: Ask Designer Why?
3211 + //(pSrc[6] != pDst[6]) || (pSrc[7] != pDst[7]))
3212 + MSG(VERIFY, "mtk_nand_verify_buf oob fail at page %d\n", pkCMD->u4RowAddr);
3213 + MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pSrc[0], pSrc[1], pSrc[2], pSrc[3], pSrc[4], pSrc[5], pSrc[6], pSrc[7]);
3214 + MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pDst[0], pDst[1], pDst[2], pDst[3], pDst[4], pDst[5], pDst[6], pDst[7]);
3215 + return -1;
3216 + }
3217 + return 0;
3218 +}
3219 +#endif
3220 +
3221 +static void
3222 +mtk_nand_init_hw(struct mtk_nand_host *host) {
3223 + struct mtk_nand_host_hw *hw = host->hw;
3224 + u32 data;
3225 +
3226 + data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
3227 + data &= ~((0x3<<18)|(0x3<<16));
3228 + data |= ((0x2<<18) |(0x2<<16));
3229 + DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
3230 +
3231 + MSG(INIT, "Enable NFI Clock\n");
3232 + nand_enable_clock();
3233 +
3234 + g_bInitDone = false;
3235 + g_kCMD.u4OOBRowAddr = (u32) - 1;
3236 +
3237 + /* Set default NFI access timing control */
3238 + DRV_WriteReg32(NFI_ACCCON_REG32, hw->nfi_access_timing);
3239 + DRV_WriteReg16(NFI_CNFG_REG16, 0);
3240 + DRV_WriteReg16(NFI_PAGEFMT_REG16, 0);
3241 +
3242 + /* Reset the state machine and data FIFO, because flushing FIFO */
3243 + (void)mtk_nand_reset();
3244 +
3245 + /* Set the ECC engine */
3246 + if (hw->nand_ecc_mode == NAND_ECC_HW) {
3247 + MSG(INIT, "%s : Use HW ECC\n", MODULE_NAME);
3248 + if (g_bHwEcc)
3249 + NFI_SET_REG32(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
3250 + ECC_Config(host->hw,4);
3251 + mtk_nand_configure_fdm(8);
3252 + mtk_nand_configure_lock();
3253 + }
3254 +
3255 + NFI_SET_REG16(NFI_IOCON_REG16, 0x47);
3256 +}
3257 +
3258 +static int mtk_nand_dev_ready(struct mtd_info *mtd)
3259 +{
3260 + return !(DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY);
3261 +}
3262 +
3263 +#define FACT_BBT_BLOCK_NUM 32 // use the latest 32 BLOCK for factory bbt table
3264 +#define FACT_BBT_OOB_SIGNATURE 1
3265 +#define FACT_BBT_SIGNATURE_LEN 7
3266 +const u8 oob_signature[] = "mtknand";
3267 +static u8 *fact_bbt = 0;
3268 +static u32 bbt_size = 0;
3269 +
3270 +static int
3271 +read_fact_bbt(struct mtd_info *mtd, unsigned int page)
3272 +{
3273 + struct nand_chip *chip = mtd->priv;
3274 +
3275 + // read oob
3276 + if (mtk_nand_read_oob_hw(mtd, chip, page)==0)
3277 + {
3278 + if (chip->oob_poi[nand_badblock_offset] != 0xFF)
3279 + {
3280 + printk("Bad Block on Page %x\n", page);
3281 + return -1;
3282 + }
3283 + if (memcmp(&chip->oob_poi[FACT_BBT_OOB_SIGNATURE], oob_signature, FACT_BBT_SIGNATURE_LEN) != 0)
3284 + {
3285 + printk("compare signature failed %x\n", page);
3286 + return -1;
3287 + }
3288 + if (mtk_nand_exec_read_page(mtd, page, mtd->writesize, chip->buffers->databuf, chip->oob_poi))
3289 + {
3290 + printk("Signature matched and data read!\n");
3291 + memcpy(fact_bbt, chip->buffers->databuf, (bbt_size <= mtd->writesize)? bbt_size:mtd->writesize);
3292 + return 0;
3293 + }
3294 +
3295 + }
3296 + printk("failed at page %x\n", page);
3297 + return -1;
3298 +}
3299 +
3300 +static int
3301 +load_fact_bbt(struct mtd_info *mtd)
3302 +{
3303 + struct nand_chip *chip = mtd->priv;
3304 + int i;
3305 + u32 total_block;
3306 +
3307 + total_block = 1 << (chip->chip_shift - chip->phys_erase_shift);
3308 + bbt_size = total_block >> 2;
3309 +
3310 + if ((!fact_bbt) && (bbt_size))
3311 + fact_bbt = (u8 *)kmalloc(bbt_size, GFP_KERNEL);
3312 + if (!fact_bbt)
3313 + return -1;
3314 +
3315 + for (i = total_block - 1; i >= (total_block - FACT_BBT_BLOCK_NUM); i--)
3316 + {
3317 + if (read_fact_bbt(mtd, i << (chip->phys_erase_shift - chip->page_shift)) == 0)
3318 + {
3319 + printk("load_fact_bbt success %d\n", i);
3320 + return 0;
3321 + }
3322 +
3323 + }
3324 + printk("load_fact_bbt failed\n");
3325 + return -1;
3326 +}
3327 +
3328 +static int
3329 +mtk_nand_probe(struct platform_device *pdev)
3330 +{
3331 + struct mtd_part_parser_data ppdata;
3332 + struct mtk_nand_host_hw *hw;
3333 + struct mtd_info *mtd;
3334 + struct nand_chip *nand_chip;
3335 + u8 ext_id1, ext_id2, ext_id3;
3336 + int err = 0;
3337 + int id;
3338 + u32 ext_id;
3339 + int i;
3340 + u32 data;
3341 +
3342 + data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
3343 + data &= ~((0x3<<18)|(0x3<<16));
3344 + data |= ((0x2<<18) |(0x2<<16));
3345 + DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
3346 +
3347 + hw = &mt7621_nand_hw,
3348 + BUG_ON(!hw);
3349 + /* Allocate memory for the device structure (and zero it) */
3350 + host = kzalloc(sizeof(struct mtk_nand_host), GFP_KERNEL);
3351 + if (!host) {
3352 + MSG(INIT, "mtk_nand: failed to allocate device structure.\n");
3353 + return -ENOMEM;
3354 + }
3355 +
3356 + /* Allocate memory for 16 byte aligned buffer */
3357 + local_buffer_16_align = local_buffer + 16 - ((u32) local_buffer % 16);
3358 + printk(KERN_INFO "Allocate 16 byte aligned buffer: %p\n", local_buffer_16_align);
3359 + host->hw = hw;
3360 +
3361 + /* init mtd data structure */
3362 + nand_chip = &host->nand_chip;
3363 + nand_chip->priv = host; /* link the private data structures */
3364 +
3365 + mtd = &host->mtd;
3366 + mtd->priv = nand_chip;
3367 + mtd->owner = THIS_MODULE;
3368 + mtd->name = "MT7621-NAND";
3369 +
3370 + hw->nand_ecc_mode = NAND_ECC_HW;
3371 +
3372 + /* Set address of NAND IO lines */
3373 + nand_chip->IO_ADDR_R = (void __iomem *)NFI_DATAR_REG32;
3374 + nand_chip->IO_ADDR_W = (void __iomem *)NFI_DATAW_REG32;
3375 + nand_chip->chip_delay = 20; /* 20us command delay time */
3376 + nand_chip->ecc.mode = hw->nand_ecc_mode; /* enable ECC */
3377 + nand_chip->ecc.strength = 1;
3378 + nand_chip->read_byte = mtk_nand_read_byte;
3379 + nand_chip->read_buf = mtk_nand_read_buf;
3380 + nand_chip->write_buf = mtk_nand_write_buf;
3381 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
3382 + nand_chip->verify_buf = mtk_nand_verify_buf;
3383 +#endif
3384 + nand_chip->select_chip = mtk_nand_select_chip;
3385 + nand_chip->dev_ready = mtk_nand_dev_ready;
3386 + nand_chip->cmdfunc = mtk_nand_command_bp;
3387 + nand_chip->ecc.read_page = mtk_nand_read_page_hwecc;
3388 + nand_chip->ecc.write_page = mtk_nand_write_page_hwecc;
3389 +
3390 + nand_chip->ecc.layout = &nand_oob_64;
3391 + nand_chip->ecc.size = hw->nand_ecc_size; //2048
3392 + nand_chip->ecc.bytes = hw->nand_ecc_bytes; //32
3393 +
3394 + // For BMT, we need to revise driver architecture
3395 + nand_chip->write_page = mtk_nand_write_page;
3396 + nand_chip->ecc.write_oob = mtk_nand_write_oob;
3397 + nand_chip->block_markbad = mtk_nand_block_markbad; // need to add nand_get_device()/nand_release_device().
3398 + // nand_chip->erase = mtk_nand_erase;
3399 + // nand_chip->read_page = mtk_nand_read_page;
3400 + nand_chip->ecc.read_oob = mtk_nand_read_oob;
3401 + nand_chip->block_bad = mtk_nand_block_bad;
3402 +
3403 + //Qwert:Add for Uboot
3404 + mtk_nand_init_hw(host);
3405 + /* Select the device */
3406 + nand_chip->select_chip(mtd, NFI_DEFAULT_CS);
3407 +
3408 + /*
3409 + * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3410 + * after power-up
3411 + */
3412 + nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3413 +
3414 + memset(&devinfo, 0 , sizeof(flashdev_info));
3415 +
3416 + /* Send the command for reading device ID */
3417 +
3418 + nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3419 +
3420 + /* Read manufacturer and device IDs */
3421 + manu_id = nand_chip->read_byte(mtd);
3422 + dev_id = nand_chip->read_byte(mtd);
3423 + id = dev_id | (manu_id << 8);
3424 + ext_id1 = nand_chip->read_byte(mtd);
3425 + ext_id2 = nand_chip->read_byte(mtd);
3426 + ext_id3 = nand_chip->read_byte(mtd);
3427 + ext_id = ext_id1 << 16 | ext_id2 << 8 | ext_id3;
3428 + if (!get_device_info(id, ext_id, &devinfo)) {
3429 + u32 chip_mode = RALINK_REG(RALINK_SYSCTL_BASE+0x010)&0x0F;
3430 + MSG(INIT, "Not Support this Device! \r\n");
3431 + memset(&devinfo, 0 , sizeof(flashdev_info));
3432 + MSG(INIT, "chip_mode=%08X\n",chip_mode);
3433 +
3434 + /* apply bootstrap first */
3435 + devinfo.addr_cycle = 5;
3436 + devinfo.iowidth = 8;
3437 +
3438 + switch (chip_mode) {
3439 + case 10:
3440 + devinfo.pagesize = 2048;
3441 + devinfo.sparesize = 128;
3442 + devinfo.totalsize = 128;
3443 + devinfo.blocksize = 128;
3444 + break;
3445 + case 11:
3446 + devinfo.pagesize = 4096;
3447 + devinfo.sparesize = 128;
3448 + devinfo.totalsize = 1024;
3449 + devinfo.blocksize = 256;
3450 + break;
3451 + case 12:
3452 + devinfo.pagesize = 4096;
3453 + devinfo.sparesize = 224;
3454 + devinfo.totalsize = 2048;
3455 + devinfo.blocksize = 512;
3456 + break;
3457 + default:
3458 + case 1:
3459 + devinfo.pagesize = 2048;
3460 + devinfo.sparesize = 64;
3461 + devinfo.totalsize = 128;
3462 + devinfo.blocksize = 128;
3463 + break;
3464 + }
3465 +
3466 + devinfo.timmingsetting = NFI_DEFAULT_ACCESS_TIMING;
3467 + devinfo.devciename[0] = 'U';
3468 + devinfo.advancedmode = 0;
3469 + }
3470 + mtd->writesize = devinfo.pagesize;
3471 + mtd->erasesize = (devinfo.blocksize<<10);
3472 + mtd->oobsize = devinfo.sparesize;
3473 +
3474 + nand_chip->chipsize = (devinfo.totalsize<<20);
3475 + nand_chip->page_shift = ffs(mtd->writesize) - 1;
3476 + nand_chip->pagemask = (nand_chip->chipsize >> nand_chip->page_shift) - 1;
3477 + nand_chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
3478 + nand_chip->chip_shift = ffs(nand_chip->chipsize) - 1;//0x1C;//ffs(nand_chip->chipsize) - 1;
3479 + nand_chip->oob_poi = nand_chip->buffers->databuf + mtd->writesize;
3480 + nand_chip->badblockpos = 0;
3481 +
3482 + if (devinfo.pagesize == 4096)
3483 + nand_chip->ecc.layout = &nand_oob_128;
3484 + else if (devinfo.pagesize == 2048)
3485 + nand_chip->ecc.layout = &nand_oob_64;
3486 + else if (devinfo.pagesize == 512)
3487 + nand_chip->ecc.layout = &nand_oob_16;
3488 +
3489 + nand_chip->ecc.layout->eccbytes = devinfo.sparesize-OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE);
3490 + for (i = 0; i < nand_chip->ecc.layout->eccbytes; i++)
3491 + nand_chip->ecc.layout->eccpos[i]=OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE)+i;
3492 +
3493 + MSG(INIT, "Support this Device in MTK table! %x \r\n", id);
3494 + hw->nfi_bus_width = devinfo.iowidth;
3495 + DRV_WriteReg32(NFI_ACCCON_REG32, devinfo.timmingsetting);
3496 +
3497 + /* 16-bit bus width */
3498 + if (hw->nfi_bus_width == 16) {
3499 + MSG(INIT, "%s : Set the 16-bit I/O settings!\n", MODULE_NAME);
3500 + nand_chip->options |= NAND_BUSWIDTH_16;
3501 + }
3502 + mtd->oobsize = devinfo.sparesize;
3503 + hw->nfi_cs_num = 1;
3504 +
3505 + /* Scan to find existance of the device */
3506 + if (nand_scan(mtd, hw->nfi_cs_num)) {
3507 + MSG(INIT, "%s : nand_scan fail.\n", MODULE_NAME);
3508 + err = -ENXIO;
3509 + goto out;
3510 + }
3511 +
3512 + g_page_size = mtd->writesize;
3513 + platform_set_drvdata(pdev, host);
3514 + if (hw->nfi_bus_width == 16) {
3515 + NFI_SET_REG16(NFI_PAGEFMT_REG16, PAGEFMT_DBYTE_EN);
3516 + }
3517 +
3518 + nand_chip->select_chip(mtd, 0);
3519 +#if defined(MTK_NAND_BMT)
3520 + nand_chip->chipsize -= (BMT_POOL_SIZE) << nand_chip->phys_erase_shift;
3521 +#endif
3522 + mtd->size = nand_chip->chipsize;
3523 +
3524 + CFG_BLOCKSIZE = mtd->erasesize;
3525 +
3526 +#if defined(MTK_NAND_BMT)
3527 + if (!g_bmt) {
3528 + if (!(g_bmt = init_bmt(nand_chip, BMT_POOL_SIZE))) {
3529 + MSG(INIT, "Error: init bmt failed\n");
3530 + return 0;
3531 + }
3532 + }
3533 +#endif
3534 +
3535 + ppdata.of_node = pdev->dev.of_node;
3536 + err = mtd_device_parse_register(mtd, probe_types, &ppdata,
3537 + NULL, 0);
3538 + if (!err) {
3539 + MSG(INIT, "[mtk_nand] probe successfully!\n");
3540 + nand_disable_clock();
3541 + shift_on_bbt = 1;
3542 + if (load_fact_bbt(mtd) == 0) {
3543 + int i;
3544 + for (i = 0; i < 0x100; i++)
3545 + nand_chip->bbt[i] |= fact_bbt[i];
3546 + }
3547 +
3548 + return err;
3549 + }
3550 +
3551 +out:
3552 + MSG(INIT, "[NFI] mtk_nand_probe fail, err = %d!\n", err);
3553 + nand_release(mtd);
3554 + platform_set_drvdata(pdev, NULL);
3555 + kfree(host);
3556 + nand_disable_clock();
3557 + return err;
3558 +}
3559 +
3560 +static int
3561 +mtk_nand_remove(struct platform_device *pdev)
3562 +{
3563 + struct mtk_nand_host *host = platform_get_drvdata(pdev);
3564 + struct mtd_info *mtd = &host->mtd;
3565 +
3566 + nand_release(mtd);
3567 + kfree(host);
3568 + nand_disable_clock();
3569 +
3570 + return 0;
3571 +}
3572 +
3573 +static const struct of_device_id mt7621_nand_match[] = {
3574 + { .compatible = "mtk,mt7621-nand" },
3575 + {},
3576 +};
3577 +MODULE_DEVICE_TABLE(of, mt7621_nand_match);
3578 +
3579 +static struct platform_driver mtk_nand_driver = {
3580 + .probe = mtk_nand_probe,
3581 + .remove = mtk_nand_remove,
3582 + .driver = {
3583 + .name = "MT7621-NAND",
3584 + .owner = THIS_MODULE,
3585 + .of_match_table = mt7621_nand_match,
3586 + },
3587 +};
3588 +
3589 +static int __init
3590 +mtk_nand_init(void)
3591 +{
3592 + printk("MediaTek Nand driver init, version %s\n", VERSION);
3593 +
3594 + return platform_driver_register(&mtk_nand_driver);
3595 +}
3596 +
3597 +static void __exit
3598 +mtk_nand_exit(void)
3599 +{
3600 + platform_driver_unregister(&mtk_nand_driver);
3601 +}
3602 +
3603 +module_init(mtk_nand_init);
3604 +module_exit(mtk_nand_exit);
3605 +MODULE_LICENSE("GPL");
3606 --- /dev/null
3607 +++ b/drivers/mtd/nand/mtk_nand.h
3608 @@ -0,0 +1,452 @@
3609 +#ifndef __MTK_NAND_H
3610 +#define __MTK_NAND_H
3611 +
3612 +#define RALINK_NAND_CTRL_BASE 0xBE003000
3613 +#define RALINK_SYSCTL_BASE 0xBE000000
3614 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
3615 +/*******************************************************************************
3616 + * NFI Register Definition
3617 + *******************************************************************************/
3618 +
3619 +#define NFI_CNFG_REG16 ((volatile P_U16)(NFI_BASE+0x0000))
3620 +#define NFI_PAGEFMT_REG16 ((volatile P_U16)(NFI_BASE+0x0004))
3621 +#define NFI_CON_REG16 ((volatile P_U16)(NFI_BASE+0x0008))
3622 +#define NFI_ACCCON_REG32 ((volatile P_U32)(NFI_BASE+0x000C))
3623 +#define NFI_INTR_EN_REG16 ((volatile P_U16)(NFI_BASE+0x0010))
3624 +#define NFI_INTR_REG16 ((volatile P_U16)(NFI_BASE+0x0014))
3625 +
3626 +#define NFI_CMD_REG16 ((volatile P_U16)(NFI_BASE+0x0020))
3627 +
3628 +#define NFI_ADDRNOB_REG16 ((volatile P_U16)(NFI_BASE+0x0030))
3629 +#define NFI_COLADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0034))
3630 +#define NFI_ROWADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0038))
3631 +
3632 +#define NFI_STRDATA_REG16 ((volatile P_U16)(NFI_BASE+0x0040))
3633 +
3634 +#define NFI_DATAW_REG32 ((volatile P_U32)(NFI_BASE+0x0050))
3635 +#define NFI_DATAR_REG32 ((volatile P_U32)(NFI_BASE+0x0054))
3636 +#define NFI_PIO_DIRDY_REG16 ((volatile P_U16)(NFI_BASE+0x0058))
3637 +
3638 +#define NFI_STA_REG32 ((volatile P_U32)(NFI_BASE+0x0060))
3639 +#define NFI_FIFOSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0064))
3640 +#define NFI_LOCKSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0068))
3641 +
3642 +#define NFI_ADDRCNTR_REG16 ((volatile P_U16)(NFI_BASE+0x0070))
3643 +
3644 +#define NFI_STRADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0080))
3645 +#define NFI_BYTELEN_REG16 ((volatile P_U16)(NFI_BASE+0x0084))
3646 +
3647 +#define NFI_CSEL_REG16 ((volatile P_U16)(NFI_BASE+0x0090))
3648 +#define NFI_IOCON_REG16 ((volatile P_U16)(NFI_BASE+0x0094))
3649 +
3650 +#define NFI_FDM0L_REG32 ((volatile P_U32)(NFI_BASE+0x00A0))
3651 +#define NFI_FDM0M_REG32 ((volatile P_U32)(NFI_BASE+0x00A4))
3652 +
3653 +#define NFI_LOCK_REG16 ((volatile P_U16)(NFI_BASE+0x0100))
3654 +#define NFI_LOCKCON_REG32 ((volatile P_U32)(NFI_BASE+0x0104))
3655 +#define NFI_LOCKANOB_REG16 ((volatile P_U16)(NFI_BASE+0x0108))
3656 +#define NFI_LOCK00ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0110))
3657 +#define NFI_LOCK00FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0114))
3658 +#define NFI_LOCK01ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0118))
3659 +#define NFI_LOCK01FMT_REG32 ((volatile P_U32)(NFI_BASE+0x011C))
3660 +#define NFI_LOCK02ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0120))
3661 +#define NFI_LOCK02FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0124))
3662 +#define NFI_LOCK03ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0128))
3663 +#define NFI_LOCK03FMT_REG32 ((volatile P_U32)(NFI_BASE+0x012C))
3664 +#define NFI_LOCK04ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0130))
3665 +#define NFI_LOCK04FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0134))
3666 +#define NFI_LOCK05ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0138))
3667 +#define NFI_LOCK05FMT_REG32 ((volatile P_U32)(NFI_BASE+0x013C))
3668 +#define NFI_LOCK06ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0140))
3669 +#define NFI_LOCK06FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0144))
3670 +#define NFI_LOCK07ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0148))
3671 +#define NFI_LOCK07FMT_REG32 ((volatile P_U32)(NFI_BASE+0x014C))
3672 +#define NFI_LOCK08ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0150))
3673 +#define NFI_LOCK08FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0154))
3674 +#define NFI_LOCK09ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0158))
3675 +#define NFI_LOCK09FMT_REG32 ((volatile P_U32)(NFI_BASE+0x015C))
3676 +#define NFI_LOCK10ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0160))
3677 +#define NFI_LOCK10FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0164))
3678 +#define NFI_LOCK11ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0168))
3679 +#define NFI_LOCK11FMT_REG32 ((volatile P_U32)(NFI_BASE+0x016C))
3680 +#define NFI_LOCK12ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0170))
3681 +#define NFI_LOCK12FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0174))
3682 +#define NFI_LOCK13ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0178))
3683 +#define NFI_LOCK13FMT_REG32 ((volatile P_U32)(NFI_BASE+0x017C))
3684 +#define NFI_LOCK14ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0180))
3685 +#define NFI_LOCK14FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0184))
3686 +#define NFI_LOCK15ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0188))
3687 +#define NFI_LOCK15FMT_REG32 ((volatile P_U32)(NFI_BASE+0x018C))
3688 +
3689 +#define NFI_FIFODATA0_REG32 ((volatile P_U32)(NFI_BASE+0x0190))
3690 +#define NFI_FIFODATA1_REG32 ((volatile P_U32)(NFI_BASE+0x0194))
3691 +#define NFI_FIFODATA2_REG32 ((volatile P_U32)(NFI_BASE+0x0198))
3692 +#define NFI_FIFODATA3_REG32 ((volatile P_U32)(NFI_BASE+0x019C))
3693 +#define NFI_MASTERSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0210))
3694 +
3695 +
3696 +/*******************************************************************************
3697 + * NFI Register Field Definition
3698 + *******************************************************************************/
3699 +
3700 +/* NFI_CNFG */
3701 +#define CNFG_AHB (0x0001)
3702 +#define CNFG_READ_EN (0x0002)
3703 +#define CNFG_DMA_BURST_EN (0x0004)
3704 +#define CNFG_BYTE_RW (0x0040)
3705 +#define CNFG_HW_ECC_EN (0x0100)
3706 +#define CNFG_AUTO_FMT_EN (0x0200)
3707 +#define CNFG_OP_IDLE (0x0000)
3708 +#define CNFG_OP_READ (0x1000)
3709 +#define CNFG_OP_SRD (0x2000)
3710 +#define CNFG_OP_PRGM (0x3000)
3711 +#define CNFG_OP_ERASE (0x4000)
3712 +#define CNFG_OP_RESET (0x5000)
3713 +#define CNFG_OP_CUST (0x6000)
3714 +#define CNFG_OP_MODE_MASK (0x7000)
3715 +#define CNFG_OP_MODE_SHIFT (12)
3716 +
3717 +/* NFI_PAGEFMT */
3718 +#define PAGEFMT_512 (0x0000)
3719 +#define PAGEFMT_2K (0x0001)
3720 +#define PAGEFMT_4K (0x0002)
3721 +
3722 +#define PAGEFMT_PAGE_MASK (0x0003)
3723 +
3724 +#define PAGEFMT_DBYTE_EN (0x0008)
3725 +
3726 +#define PAGEFMT_SPARE_16 (0x0000)
3727 +#define PAGEFMT_SPARE_26 (0x0001)
3728 +#define PAGEFMT_SPARE_27 (0x0002)
3729 +#define PAGEFMT_SPARE_28 (0x0003)
3730 +#define PAGEFMT_SPARE_MASK (0x0030)
3731 +#define PAGEFMT_SPARE_SHIFT (4)
3732 +
3733 +#define PAGEFMT_FDM_MASK (0x0F00)
3734 +#define PAGEFMT_FDM_SHIFT (8)
3735 +
3736 +#define PAGEFMT_FDM_ECC_MASK (0xF000)
3737 +#define PAGEFMT_FDM_ECC_SHIFT (12)
3738 +
3739 +/* NFI_CON */
3740 +#define CON_FIFO_FLUSH (0x0001)
3741 +#define CON_NFI_RST (0x0002)
3742 +#define CON_NFI_SRD (0x0010)
3743 +
3744 +#define CON_NFI_NOB_MASK (0x0060)
3745 +#define CON_NFI_NOB_SHIFT (5)
3746 +
3747 +#define CON_NFI_BRD (0x0100)
3748 +#define CON_NFI_BWR (0x0200)
3749 +
3750 +#define CON_NFI_SEC_MASK (0xF000)
3751 +#define CON_NFI_SEC_SHIFT (12)
3752 +
3753 +/* NFI_ACCCON */
3754 +#define ACCCON_SETTING ()
3755 +
3756 +/* NFI_INTR_EN */
3757 +#define INTR_RD_DONE_EN (0x0001)
3758 +#define INTR_WR_DONE_EN (0x0002)
3759 +#define INTR_RST_DONE_EN (0x0004)
3760 +#define INTR_ERASE_DONE_EN (0x0008)
3761 +#define INTR_BSY_RTN_EN (0x0010)
3762 +#define INTR_ACC_LOCK_EN (0x0020)
3763 +#define INTR_AHB_DONE_EN (0x0040)
3764 +#define INTR_ALL_INTR_DE (0x0000)
3765 +#define INTR_ALL_INTR_EN (0x007F)
3766 +
3767 +/* NFI_INTR */
3768 +#define INTR_RD_DONE (0x0001)
3769 +#define INTR_WR_DONE (0x0002)
3770 +#define INTR_RST_DONE (0x0004)
3771 +#define INTR_ERASE_DONE (0x0008)
3772 +#define INTR_BSY_RTN (0x0010)
3773 +#define INTR_ACC_LOCK (0x0020)
3774 +#define INTR_AHB_DONE (0x0040)
3775 +
3776 +/* NFI_ADDRNOB */
3777 +#define ADDR_COL_NOB_MASK (0x0003)
3778 +#define ADDR_COL_NOB_SHIFT (0)
3779 +#define ADDR_ROW_NOB_MASK (0x0030)
3780 +#define ADDR_ROW_NOB_SHIFT (4)
3781 +
3782 +/* NFI_STA */
3783 +#define STA_READ_EMPTY (0x00001000)
3784 +#define STA_ACC_LOCK (0x00000010)
3785 +#define STA_CMD_STATE (0x00000001)
3786 +#define STA_ADDR_STATE (0x00000002)
3787 +#define STA_DATAR_STATE (0x00000004)
3788 +#define STA_DATAW_STATE (0x00000008)
3789 +
3790 +#define STA_NAND_FSM_MASK (0x1F000000)
3791 +#define STA_NAND_BUSY (0x00000100)
3792 +#define STA_NAND_BUSY_RETURN (0x00000200)
3793 +#define STA_NFI_FSM_MASK (0x000F0000)
3794 +#define STA_NFI_OP_MASK (0x0000000F)
3795 +
3796 +/* NFI_FIFOSTA */
3797 +#define FIFO_RD_EMPTY (0x0040)
3798 +#define FIFO_RD_FULL (0x0080)
3799 +#define FIFO_WR_FULL (0x8000)
3800 +#define FIFO_WR_EMPTY (0x4000)
3801 +#define FIFO_RD_REMAIN(x) (0x1F&(x))
3802 +#define FIFO_WR_REMAIN(x) ((0x1F00&(x))>>8)
3803 +
3804 +/* NFI_ADDRCNTR */
3805 +#define ADDRCNTR_CNTR(x) ((0xF000&(x))>>12)
3806 +#define ADDRCNTR_OFFSET(x) (0x03FF&(x))
3807 +
3808 +/* NFI_LOCK */
3809 +#define NFI_LOCK_ON (0x0001)
3810 +
3811 +/* NFI_LOCKANOB */
3812 +#define PROG_RADD_NOB_MASK (0x7000)
3813 +#define PROG_RADD_NOB_SHIFT (12)
3814 +#define PROG_CADD_NOB_MASK (0x0300)
3815 +#define PROG_CADD_NOB_SHIFT (8)
3816 +#define ERASE_RADD_NOB_MASK (0x0070)
3817 +#define ERASE_RADD_NOB_SHIFT (4)
3818 +#define ERASE_CADD_NOB_MASK (0x0007)
3819 +#define ERASE_CADD_NOB_SHIFT (0)
3820 +
3821 +/*******************************************************************************
3822 + * ECC Register Definition
3823 + *******************************************************************************/
3824 +
3825 +#define ECC_ENCCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0000))
3826 +#define ECC_ENCCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0004))
3827 +#define ECC_ENCDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0008))
3828 +#define ECC_ENCIDLE_REG32 ((volatile P_U32)(NFIECC_BASE+0x000C))
3829 +#define ECC_ENCPAR0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0010))
3830 +#define ECC_ENCPAR1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0014))
3831 +#define ECC_ENCPAR2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0018))
3832 +#define ECC_ENCPAR3_REG32 ((volatile P_U32)(NFIECC_BASE+0x001C))
3833 +#define ECC_ENCPAR4_REG32 ((volatile P_U32)(NFIECC_BASE+0x0020))
3834 +#define ECC_ENCSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0024))
3835 +#define ECC_ENCIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0028))
3836 +#define ECC_ENCIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x002C))
3837 +
3838 +#define ECC_DECCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0100))
3839 +#define ECC_DECCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0104))
3840 +#define ECC_DECDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0108))
3841 +#define ECC_DECIDLE_REG16 ((volatile P_U16)(NFIECC_BASE+0x010C))
3842 +#define ECC_DECFER_REG16 ((volatile P_U16)(NFIECC_BASE+0x0110))
3843 +#define ECC_DECENUM_REG32 ((volatile P_U32)(NFIECC_BASE+0x0114))
3844 +#define ECC_DECDONE_REG16 ((volatile P_U16)(NFIECC_BASE+0x0118))
3845 +#define ECC_DECEL0_REG32 ((volatile P_U32)(NFIECC_BASE+0x011C))
3846 +#define ECC_DECEL1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0120))
3847 +#define ECC_DECEL2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0124))
3848 +#define ECC_DECEL3_REG32 ((volatile P_U32)(NFIECC_BASE+0x0128))
3849 +#define ECC_DECEL4_REG32 ((volatile P_U32)(NFIECC_BASE+0x012C))
3850 +#define ECC_DECEL5_REG32 ((volatile P_U32)(NFIECC_BASE+0x0130))
3851 +#define ECC_DECIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0134))
3852 +#define ECC_DECIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0138))
3853 +#define ECC_FDMADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x013C))
3854 +#define ECC_DECFSM_REG32 ((volatile P_U32)(NFIECC_BASE+0x0140))
3855 +#define ECC_SYNSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0144))
3856 +#define ECC_DECNFIDI_REG32 ((volatile P_U32)(NFIECC_BASE+0x0148))
3857 +#define ECC_SYN0_REG32 ((volatile P_U32)(NFIECC_BASE+0x014C))
3858 +
3859 +/*******************************************************************************
3860 + * ECC register definition
3861 + *******************************************************************************/
3862 +/* ECC_ENCON */
3863 +#define ENC_EN (0x0001)
3864 +#define ENC_DE (0x0000)
3865 +
3866 +/* ECC_ENCCNFG */
3867 +#define ECC_CNFG_ECC4 (0x0000)
3868 +#define ECC_CNFG_ECC6 (0x0001)
3869 +#define ECC_CNFG_ECC8 (0x0002)
3870 +#define ECC_CNFG_ECC10 (0x0003)
3871 +#define ECC_CNFG_ECC12 (0x0004)
3872 +#define ECC_CNFG_ECC_MASK (0x00000007)
3873 +
3874 +#define ENC_CNFG_NFI (0x0010)
3875 +#define ENC_CNFG_MODE_MASK (0x0010)
3876 +
3877 +#define ENC_CNFG_META6 (0x10300000)
3878 +#define ENC_CNFG_META8 (0x10400000)
3879 +
3880 +#define ENC_CNFG_MSG_MASK (0x1FFF0000)
3881 +#define ENC_CNFG_MSG_SHIFT (0x10)
3882 +
3883 +/* ECC_ENCIDLE */
3884 +#define ENC_IDLE (0x0001)
3885 +
3886 +/* ECC_ENCSTA */
3887 +#define STA_FSM (0x001F)
3888 +#define STA_COUNT_PS (0xFF10)
3889 +#define STA_COUNT_MS (0x3FFF0000)
3890 +
3891 +/* ECC_ENCIRQEN */
3892 +#define ENC_IRQEN (0x0001)
3893 +
3894 +/* ECC_ENCIRQSTA */
3895 +#define ENC_IRQSTA (0x0001)
3896 +
3897 +/* ECC_DECCON */
3898 +#define DEC_EN (0x0001)
3899 +#define DEC_DE (0x0000)
3900 +
3901 +/* ECC_ENCCNFG */
3902 +#define DEC_CNFG_ECC4 (0x0000)
3903 +//#define DEC_CNFG_ECC6 (0x0001)
3904 +//#define DEC_CNFG_ECC12 (0x0002)
3905 +#define DEC_CNFG_NFI (0x0010)
3906 +//#define DEC_CNFG_META6 (0x10300000)
3907 +//#define DEC_CNFG_META8 (0x10400000)
3908 +
3909 +#define DEC_CNFG_FER (0x01000)
3910 +#define DEC_CNFG_EL (0x02000)
3911 +#define DEC_CNFG_CORRECT (0x03000)
3912 +#define DEC_CNFG_TYPE_MASK (0x03000)
3913 +
3914 +#define DEC_CNFG_EMPTY_EN (0x80000000)
3915 +
3916 +#define DEC_CNFG_CODE_MASK (0x1FFF0000)
3917 +#define DEC_CNFG_CODE_SHIFT (0x10)
3918 +
3919 +/* ECC_DECIDLE */
3920 +#define DEC_IDLE (0x0001)
3921 +
3922 +/* ECC_DECFER */
3923 +#define DEC_FER0 (0x0001)
3924 +#define DEC_FER1 (0x0002)
3925 +#define DEC_FER2 (0x0004)
3926 +#define DEC_FER3 (0x0008)
3927 +#define DEC_FER4 (0x0010)
3928 +#define DEC_FER5 (0x0020)
3929 +#define DEC_FER6 (0x0040)
3930 +#define DEC_FER7 (0x0080)
3931 +
3932 +/* ECC_DECENUM */
3933 +#define ERR_NUM0 (0x0000000F)
3934 +#define ERR_NUM1 (0x000000F0)
3935 +#define ERR_NUM2 (0x00000F00)
3936 +#define ERR_NUM3 (0x0000F000)
3937 +#define ERR_NUM4 (0x000F0000)
3938 +#define ERR_NUM5 (0x00F00000)
3939 +#define ERR_NUM6 (0x0F000000)
3940 +#define ERR_NUM7 (0xF0000000)
3941 +
3942 +/* ECC_DECDONE */
3943 +#define DEC_DONE0 (0x0001)
3944 +#define DEC_DONE1 (0x0002)
3945 +#define DEC_DONE2 (0x0004)
3946 +#define DEC_DONE3 (0x0008)
3947 +#define DEC_DONE4 (0x0010)
3948 +#define DEC_DONE5 (0x0020)
3949 +#define DEC_DONE6 (0x0040)
3950 +#define DEC_DONE7 (0x0080)
3951 +
3952 +/* ECC_DECIRQEN */
3953 +#define DEC_IRQEN (0x0001)
3954 +
3955 +/* ECC_DECIRQSTA */
3956 +#define DEC_IRQSTA (0x0001)
3957 +
3958 +#define CHIPVER_ECO_1 (0x8a00)
3959 +#define CHIPVER_ECO_2 (0x8a01)
3960 +
3961 +//#define NAND_PFM
3962 +
3963 +/*******************************************************************************
3964 + * Data Structure Definition
3965 + *******************************************************************************/
3966 +struct mtk_nand_host
3967 +{
3968 + struct nand_chip nand_chip;
3969 + struct mtd_info mtd;
3970 + struct mtk_nand_host_hw *hw;
3971 +};
3972 +
3973 +struct NAND_CMD
3974 +{
3975 + u32 u4ColAddr;
3976 + u32 u4RowAddr;
3977 + u32 u4OOBRowAddr;
3978 + u8 au1OOB[288];
3979 + u8* pDataBuf;
3980 +#ifdef NAND_PFM
3981 + u32 pureReadOOB;
3982 + u32 pureReadOOBNum;
3983 +#endif
3984 +};
3985 +
3986 +/*
3987 + * ECC layout control structure. Exported to userspace for
3988 + * diagnosis and to allow creation of raw images
3989 +struct nand_ecclayout {
3990 + uint32_t eccbytes;
3991 + uint32_t eccpos[64];
3992 + uint32_t oobavail;
3993 + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
3994 +};
3995 +*/
3996 +#define __DEBUG_NAND 1 /* Debug information on/off */
3997 +
3998 +/* Debug message event */
3999 +#define DBG_EVT_NONE 0x00000000 /* No event */
4000 +#define DBG_EVT_INIT 0x00000001 /* Initial related event */
4001 +#define DBG_EVT_VERIFY 0x00000002 /* Verify buffer related event */
4002 +#define DBG_EVT_PERFORMANCE 0x00000004 /* Performance related event */
4003 +#define DBG_EVT_READ 0x00000008 /* Read related event */
4004 +#define DBG_EVT_WRITE 0x00000010 /* Write related event */
4005 +#define DBG_EVT_ERASE 0x00000020 /* Erase related event */
4006 +#define DBG_EVT_BADBLOCK 0x00000040 /* Badblock related event */
4007 +#define DBG_EVT_POWERCTL 0x00000080 /* Suspend/Resume related event */
4008 +
4009 +#define DBG_EVT_ALL 0xffffffff
4010 +
4011 +#define DBG_EVT_MASK (DBG_EVT_INIT)
4012 +
4013 +#if __DEBUG_NAND
4014 +#define MSG(evt, fmt, args...) \
4015 +do { \
4016 + if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
4017 + printk(fmt, ##args); \
4018 + } \
4019 +} while(0)
4020 +
4021 +#define MSG_FUNC_ENTRY(f) MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
4022 +#else
4023 +#define MSG(evt, fmt, args...) do{}while(0)
4024 +#define MSG_FUNC_ENTRY(f) do{}while(0)
4025 +#endif
4026 +
4027 +#define RAMDOM_READ 1<<0
4028 +#define CACHE_READ 1<<1
4029 +
4030 +typedef struct
4031 +{
4032 + u16 id; //deviceid+menuid
4033 + u32 ext_id;
4034 + u8 addr_cycle;
4035 + u8 iowidth;
4036 + u16 totalsize;
4037 + u16 blocksize;
4038 + u16 pagesize;
4039 + u16 sparesize;
4040 + u32 timmingsetting;
4041 + char devciename[14];
4042 + u32 advancedmode; //
4043 +}flashdev_info,*pflashdev_info;
4044 +
4045 +/* NAND driver */
4046 +#if 0
4047 +struct mtk_nand_host_hw {
4048 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
4049 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
4050 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
4051 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
4052 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
4053 + unsigned int nand_ecc_size;
4054 + unsigned int nand_ecc_bytes;
4055 + unsigned int nand_ecc_mode;
4056 +};
4057 +extern struct mtk_nand_host_hw mt7621_nand_hw;
4058 +extern u32 CFG_BLOCKSIZE;
4059 +#endif
4060 +#endif
4061 --- a/drivers/mtd/nand/nand_base.c
4062 +++ b/drivers/mtd/nand/nand_base.c
4063 @@ -92,7 +92,7 @@ static struct nand_ecclayout nand_oob_12
4064 .length = 78} }
4065 };
4066
4067 -static int nand_get_device(struct mtd_info *mtd, int new_state);
4068 +int nand_get_device(struct mtd_info *mtd, int new_state);
4069
4070 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
4071 struct mtd_oob_ops *ops);
4072 @@ -130,7 +130,7 @@ static int check_offs_len(struct mtd_inf
4073 *
4074 * Release chip lock and wake up anyone waiting on the device.
4075 */
4076 -static void nand_release_device(struct mtd_info *mtd)
4077 +void nand_release_device(struct mtd_info *mtd)
4078 {
4079 struct nand_chip *chip = mtd->priv;
4080
4081 @@ -820,7 +820,7 @@ static void panic_nand_get_device(struct
4082 *
4083 * Get the device and lock it for exclusive access
4084 */
4085 -static int
4086 +int
4087 nand_get_device(struct mtd_info *mtd, int new_state)
4088 {
4089 struct nand_chip *chip = mtd->priv;
4090 --- a/drivers/mtd/nand/nand_bbt.c
4091 +++ b/drivers/mtd/nand/nand_bbt.c
4092 @@ -1374,4 +1374,23 @@ int nand_markbad_bbt(struct mtd_info *mt
4093 return ret;
4094 }
4095
4096 +void nand_bbt_set(struct mtd_info *mtd, int page, int flag)
4097 +{
4098 + struct nand_chip *this = mtd->priv;
4099 + int block;
4100 +
4101 + block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
4102 + this->bbt[block >> 3] &= ~(0x03 << (block & 0x6));
4103 + this->bbt[block >> 3] |= (flag & 0x3) << (block & 0x6);
4104 +}
4105 +
4106 +int nand_bbt_get(struct mtd_info *mtd, int page)
4107 +{
4108 + struct nand_chip *this = mtd->priv;
4109 + int block;
4110 +
4111 + block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
4112 + return (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
4113 +}
4114 +
4115 EXPORT_SYMBOL(nand_scan_bbt);
4116 --- /dev/null
4117 +++ b/drivers/mtd/nand/nand_def.h
4118 @@ -0,0 +1,123 @@
4119 +#ifndef __NAND_DEF_H__
4120 +#define __NAND_DEF_H__
4121 +
4122 +#define VERSION "v2.1 Fix AHB virt2phys error"
4123 +#define MODULE_NAME "# MTK NAND #"
4124 +#define PROCNAME "driver/nand"
4125 +
4126 +#undef TESTTIME
4127 +//#define __UBOOT_NAND__ 1
4128 +#define __KERNEL_NAND__ 1
4129 +//#define __PRELOADER_NAND__ 1
4130 +//#define PMT 1
4131 +//#define _MTK_NAND_DUMMY_DRIVER
4132 +//#define CONFIG_BADBLOCK_CHECK 1
4133 +//#ifdef CONFIG_BADBLOCK_CHECK
4134 +//#define MTK_NAND_BMT 1
4135 +//#endif
4136 +#define ECC_ENABLE 1
4137 +#define MANUAL_CORRECT 1
4138 +//#define __INTERNAL_USE_AHB_MODE__ (0)
4139 +#define SKIP_BAD_BLOCK
4140 +#define FACT_BBT
4141 +
4142 +#ifndef NAND_OTP_SUPPORT
4143 +#define NAND_OTP_SUPPORT 0
4144 +#endif
4145 +
4146 +/*******************************************************************************
4147 + * Macro definition
4148 + *******************************************************************************/
4149 +//#define NFI_SET_REG32(reg, value) (DRV_WriteReg32(reg, DRV_Reg32(reg) | (value)))
4150 +//#define NFI_SET_REG16(reg, value) (DRV_WriteReg16(reg, DRV_Reg16(reg) | (value)))
4151 +//#define NFI_CLN_REG32(reg, value) (DRV_WriteReg32(reg, DRV_Reg32(reg) & (~(value))))
4152 +//#define NFI_CLN_REG16(reg, value) (DRV_WriteReg16(reg, DRV_Reg16(reg) & (~(value))))
4153 +
4154 +#if defined (__KERNEL_NAND__)
4155 +#define NFI_SET_REG32(reg, value) \
4156 +do { \
4157 + g_value = (DRV_Reg32(reg) | (value));\
4158 + DRV_WriteReg32(reg, g_value); \
4159 +} while(0)
4160 +
4161 +#define NFI_SET_REG16(reg, value) \
4162 +do { \
4163 + g_value = (DRV_Reg16(reg) | (value));\
4164 + DRV_WriteReg16(reg, g_value); \
4165 +} while(0)
4166 +
4167 +#define NFI_CLN_REG32(reg, value) \
4168 +do { \
4169 + g_value = (DRV_Reg32(reg) & (~(value)));\
4170 + DRV_WriteReg32(reg, g_value); \
4171 +} while(0)
4172 +
4173 +#define NFI_CLN_REG16(reg, value) \
4174 +do { \
4175 + g_value = (DRV_Reg16(reg) & (~(value)));\
4176 + DRV_WriteReg16(reg, g_value); \
4177 +} while(0)
4178 +#endif
4179 +
4180 +#define NFI_WAIT_STATE_DONE(state) do{;}while (__raw_readl(NFI_STA_REG32) & state)
4181 +#define NFI_WAIT_TO_READY() do{;}while (!(__raw_readl(NFI_STA_REG32) & STA_BUSY2READY))
4182 +
4183 +
4184 +#define NAND_SECTOR_SIZE (512)
4185 +#define OOB_PER_SECTOR (16)
4186 +#define OOB_AVAI_PER_SECTOR (8)
4187 +
4188 +#ifndef PART_SIZE_BMTPOOL
4189 +#define BMT_POOL_SIZE (80)
4190 +#else
4191 +#define BMT_POOL_SIZE (PART_SIZE_BMTPOOL)
4192 +#endif
4193 +
4194 +#define PMT_POOL_SIZE (2)
4195 +
4196 +#define TIMEOUT_1 0x1fff
4197 +#define TIMEOUT_2 0x8ff
4198 +#define TIMEOUT_3 0xffff
4199 +#define TIMEOUT_4 0xffff//5000 //PIO
4200 +
4201 +
4202 +/* temporarity definiation */
4203 +#if !defined (__KERNEL_NAND__)
4204 +#define KERN_INFO
4205 +#define KERN_WARNING
4206 +#define KERN_ERR
4207 +#define PAGE_SIZE (4096)
4208 +#endif
4209 +#define AddStorageTrace //AddStorageTrace
4210 +#define STORAGE_LOGGER_MSG_NAND 0
4211 +#define NFI_BASE RALINK_NAND_CTRL_BASE
4212 +#define NFIECC_BASE RALINK_NANDECC_CTRL_BASE
4213 +
4214 +#ifdef __INTERNAL_USE_AHB_MODE__
4215 +#define MT65xx_POLARITY_LOW 0
4216 +#define MT65XX_PDN_PERI_NFI 0
4217 +#define MT65xx_EDGE_SENSITIVE 0
4218 +#define MT6575_NFI_IRQ_ID (58)
4219 +#endif
4220 +
4221 +#if defined (__KERNEL_NAND__)
4222 +#define RALINK_REG(x) (*((volatile u32 *)(x)))
4223 +#define __virt_to_phys(x) virt_to_phys((volatile void*)x)
4224 +#else
4225 +#define CONFIG_MTD_NAND_VERIFY_WRITE (1)
4226 +#define printk printf
4227 +#define ra_dbg printf
4228 +#define BUG() //BUG()
4229 +#define BUG_ON(x) //BUG_ON()
4230 +#define NUM_PARTITIONS 1
4231 +#endif
4232 +
4233 +#define NFI_DEFAULT_ACCESS_TIMING (0x30C77fff) //(0x44333)
4234 +
4235 +//uboot only support 1 cs
4236 +#define NFI_CS_NUM (1)
4237 +#define NFI_DEFAULT_CS (0)
4238 +
4239 +#include "mt6575_typedefs.h"
4240 +
4241 +#endif /* __NAND_DEF_H__ */
4242 --- /dev/null
4243 +++ b/drivers/mtd/nand/nand_device_list.h
4244 @@ -0,0 +1,55 @@
4245 +/* Copyright Statement:
4246 + *
4247 + * This software/firmware and related documentation ("MediaTek Software") are
4248 + * protected under relevant copyright laws. The information contained herein
4249 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
4250 + * Without the prior written permission of MediaTek inc. and/or its licensors,
4251 + * any reproduction, modification, use or disclosure of MediaTek Software,
4252 + * and information contained herein, in whole or in part, shall be strictly prohibited.
4253 + */
4254 +/* MediaTek Inc. (C) 2010. All rights reserved.
4255 + *
4256 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
4257 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
4258 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
4259 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
4260 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
4261 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
4262 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
4263 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
4264 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
4265 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
4266 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
4267 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
4268 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
4269 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
4270 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
4271 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
4272 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
4273 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
4274 + *
4275 + * The following software/firmware and/or related documentation ("MediaTek Software")
4276 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
4277 + * applicable license agreements with MediaTek Inc.
4278 + */
4279 +
4280 +#ifndef __NAND_DEVICE_LIST_H__
4281 +#define __NAND_DEVICE_LIST_H__
4282 +
4283 +static const flashdev_info gen_FlashTable[]={
4284 + {0x20BC, 0x105554, 5, 16, 512, 128, 2048, 64, 0x1123, "EHD013151MA_5", 0},
4285 + {0xECBC, 0x005554, 5, 16, 512, 128, 2048, 64, 0x1123, "K524G2GACB_A0", 0},
4286 + {0x2CBC, 0x905556, 5, 16, 512, 128, 2048, 64, 0x21044333, "MT29C4G96MAZA", 0},
4287 + {0xADBC, 0x905554, 5, 16, 512, 128, 2048, 64, 0x10801011, "H9DA4GH4JJAMC", 0},
4288 + {0x01F1, 0x801D01, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "S34ML01G100TF", 0},
4289 + {0x92F1, 0x8095FF, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "F59L1G81A", 0},
4290 + {0xECD3, 0x519558, 5, 8, 1024, 128, 2048, 64, 0x44333, "K9K8G8000", 0},
4291 + {0xC2F1, 0x801DC2, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "MX30LF1G08AA", 0},
4292 + {0x98D3, 0x902676, 5, 8, 1024, 256, 4096, 224, 0x00C25332, "TC58NVG3S0F", 0},
4293 + {0x01DA, 0x909546, 5, 8, 256, 128, 2048, 128, 0x30C77fff, "S34ML02G200TF", 0},
4294 + {0x01DC, 0x909556, 5, 8, 512, 128, 2048, 128, 0x30C77fff, "S34ML04G200TF", 0},
4295 + {0x0000, 0x000000, 0, 0, 0, 0, 0, 0, 0, "xxxxxxxxxx", 0},
4296 +};
4297 +
4298 +
4299 +#endif
4300 --- /dev/null
4301 +++ b/drivers/mtd/nand/partition.h
4302 @@ -0,0 +1,115 @@
4303 +/* Copyright Statement:
4304 + *
4305 + * This software/firmware and related documentation ("MediaTek Software") are
4306 + * protected under relevant copyright laws. The information contained herein
4307 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
4308 + * Without the prior written permission of MediaTek inc. and/or its licensors,
4309 + * any reproduction, modification, use or disclosure of MediaTek Software,
4310 + * and information contained herein, in whole or in part, shall be strictly prohibited.
4311 + */
4312 +/* MediaTek Inc. (C) 2010. All rights reserved.
4313 + *
4314 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
4315 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
4316 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
4317 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
4318 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
4319 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
4320 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
4321 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
4322 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
4323 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
4324 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
4325 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
4326 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
4327 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
4328 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
4329 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
4330 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
4331 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
4332 + *
4333 + * The following software/firmware and/or related documentation ("MediaTek Software")
4334 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
4335 + * applicable license agreements with MediaTek Inc.
4336 + */
4337 +
4338 +#include <linux/mtd/mtd.h>
4339 +#include <linux/mtd/nand.h>
4340 +#include <linux/mtd/partitions.h>
4341 +
4342 +#define RECONFIG_PARTITION_SIZE 1
4343 +
4344 +#define MTD_BOOT_PART_SIZE 0x80000
4345 +#define MTD_CONFIG_PART_SIZE 0x20000
4346 +#define MTD_FACTORY_PART_SIZE 0x20000
4347 +
4348 +extern unsigned int CFG_BLOCKSIZE;
4349 +#define LARGE_MTD_BOOT_PART_SIZE (CFG_BLOCKSIZE<<2)
4350 +#define LARGE_MTD_CONFIG_PART_SIZE (CFG_BLOCKSIZE<<2)
4351 +#define LARGE_MTD_FACTORY_PART_SIZE (CFG_BLOCKSIZE<<1)
4352 +
4353 +/*=======================================================================*/
4354 +/* NAND PARTITION Mapping */
4355 +/*=======================================================================*/
4356 +//#ifdef CONFIG_MTD_PARTITIONS
4357 +static struct mtd_partition g_pasStatic_Partition[] = {
4358 + {
4359 + name: "ALL",
4360 + size: MTDPART_SIZ_FULL,
4361 + offset: 0,
4362 + },
4363 + /* Put your own partition definitions here */
4364 + {
4365 + name: "Bootloader",
4366 + size: MTD_BOOT_PART_SIZE,
4367 + offset: 0,
4368 + }, {
4369 + name: "Config",
4370 + size: MTD_CONFIG_PART_SIZE,
4371 + offset: MTDPART_OFS_APPEND
4372 + }, {
4373 + name: "Factory",
4374 + size: MTD_FACTORY_PART_SIZE,
4375 + offset: MTDPART_OFS_APPEND
4376 +#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
4377 + }, {
4378 + name: "Kernel",
4379 + size: MTD_KERN_PART_SIZE,
4380 + offset: MTDPART_OFS_APPEND,
4381 + }, {
4382 + name: "RootFS",
4383 + size: MTD_ROOTFS_PART_SIZE,
4384 + offset: MTDPART_OFS_APPEND,
4385 +#ifdef CONFIG_ROOTFS_IN_FLASH_NO_PADDING
4386 + }, {
4387 + name: "Kernel_RootFS",
4388 + size: MTD_KERN_PART_SIZE + MTD_ROOTFS_PART_SIZE,
4389 + offset: MTD_BOOT_PART_SIZE + MTD_CONFIG_PART_SIZE + MTD_FACTORY_PART_SIZE,
4390 +#endif
4391 +#else //CONFIG_RT2880_ROOTFS_IN_RAM
4392 + }, {
4393 + name: "Kernel",
4394 + size: 0x10000,
4395 + offset: MTDPART_OFS_APPEND,
4396 +#endif
4397 +#ifdef CONFIG_DUAL_IMAGE
4398 + }, {
4399 + name: "Kernel2",
4400 + size: MTD_KERN2_PART_SIZE,
4401 + offset: MTD_KERN2_PART_OFFSET,
4402 +#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
4403 + }, {
4404 + name: "RootFS2",
4405 + size: MTD_ROOTFS2_PART_SIZE,
4406 + offset: MTD_ROOTFS2_PART_OFFSET,
4407 +#endif
4408 +#endif
4409 + }
4410 +
4411 +};
4412 +
4413 +#define NUM_PARTITIONS ARRAY_SIZE(g_pasStatic_Partition)
4414 +extern int part_num; // = NUM_PARTITIONS;
4415 +//#endif
4416 +#undef RECONFIG_PARTITION_SIZE
4417 +
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