target/linux/ramips/patches-4.3/0053-gic.patch

   1 From 7b042645c1bd6407b1f7d9aa5785868e7e14b860 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 18:40:16 +0100
   4 Subject: [PATCH 53/53] gic
   5
   6 ---
   7  arch/mips/ralink/Kconfig   |    1 +
   8  arch/mips/ralink/Makefile  |    2 +-
   9  arch/mips/ralink/irq-gic.c |  212 ++------------------------------------------
  10  3 files changed, 11 insertions(+), 204 deletions(-)
  11
  12 --- a/arch/mips/ralink/Kconfig
  13 +++ b/arch/mips/ralink/Kconfig
  14 @@ -51,9 +51,9 @@
  15                 select SYS_SUPPORTS_MULTITHREADING
  16                 select SYS_SUPPORTS_SMP
  17                 select SYS_SUPPORTS_MIPS_CMP
  18 +               select MIPS_GIC
  19                 select IRQ_GIC
  20                 select HW_HAS_PCI
  21 -
  22  endchoice
  23
  24  choice
  25 --- a/arch/mips/ralink/Makefile
  26 +++ b/arch/mips/ralink/Makefile
  27 @@ -13,7 +13,7 @@
  28  obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
  29
  30  obj-$(CONFIG_IRQ_INTC) += irq.o
  31 -obj-$(CONFIG_IRQ_GIC) += irq-gic.o
  32 +obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o
  33  obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
  34
  35  obj-$(CONFIG_SOC_RT288X) += rt288x.o
  36 --- a/arch/mips/ralink/irq-gic.c
  37 +++ b/arch/mips/ralink/irq-gic.c
  38 @@ -16,248 +16,22 @@
  39  #include <asm/irq.h>
  40  #include <asm/setup.h>
  41
  42 -#include <asm/gic.h>
  43 +#include <asm/mips-cm.h>
  44 +#include <linux/irqchip/mips-gic.h>
  45
  46  #include <asm/mach-ralink/mt7621.h>
  47 -#define GIC_BASE_ADDR                  0x1fbc0000
  48
  49 -unsigned long _gcmp_base;
  50 -static int gic_resched_int_base = 56;
  51 -static int gic_call_int_base = 60;
  52 -static struct irq_chip *irq_gic;
  53 -static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
  54 -
  55 -#if defined(CONFIG_MIPS_MT_SMP)
  56 -static int gic_resched_int_base;
  57 -static int gic_call_int_base;
  58 +extern int __init gic_of_init(struct device_node *node,
  59 +                             struct device_node *parent);
  60
  61 -#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
  62 -#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
  63 -
  64 -static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
  65 -{
  66 -       scheduler_ipi();
  67 -
  68 -       return IRQ_HANDLED;
  69 -}
  70 -
  71 -static irqreturn_t
  72 -ipi_call_interrupt(int irq, void *dev_id)
  73 -{
  74 -       smp_call_function_interrupt();
  75 -
  76 -       return IRQ_HANDLED;
  77 -}
  78 -
  79 -static struct irqaction irq_resched = {
  80 -        .handler        = ipi_resched_interrupt,
  81 -        .flags          = IRQF_DISABLED|IRQF_PERCPU,
  82 -        .name           = "ipi resched"
  83 -};
  84 -
  85 -static struct irqaction irq_call = {
  86 -        .handler        = ipi_call_interrupt,
  87 -        .flags          = IRQF_DISABLED|IRQF_PERCPU,
  88 -        .name           = "ipi call"
  89 -};
  90 -
  91 -#endif
  92 -
  93 -static void __init
  94 -gic_fill_map(void)
  95 -{
  96 -       int i;
  97 -
  98 -       for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
  99 -               gic_intr_map[i].cpunum = 0;
 100 -               gic_intr_map[i].pin = GIC_CPU_INT0;
 101 -               gic_intr_map[i].polarity = GIC_POL_POS;
 102 -               gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
 103 -               gic_intr_map[i].flags = 0;
 104 -       }
 105 -
 106 -#if defined(CONFIG_MIPS_MT_SMP)
 107 -       {
 108 -               int cpu;
 109 -
 110 -               gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
 111 -               gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
 112 -
 113 -               i = gic_resched_int_base;
 114 -
 115 -               for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
 116 -                       gic_intr_map[i + cpu].cpunum = cpu;
 117 -                       gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
 118 -                       gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
 119 -
 120 -                       gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
 121 -                       gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
 122 -                       gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
 123 -               }
 124 -       }
 125 -#endif
 126 -}
 127 -
 128 -void
 129 -gic_irq_ack(struct irq_data *d)
 130 -{
 131 -       int irq = (d->irq - gic_irq_base);
 132 -
 133 -       GIC_CLR_INTR_MASK(irq);
 134 -
 135 -       if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
 136 -               GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
 137 -}
 138 -
 139 -void
 140 -gic_finish_irq(struct irq_data *d)
 141 -{
 142 -       GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 143 -}
 144 -
 145 -void __init
 146 -gic_platform_init(int irqs, struct irq_chip *irq_controller)
 147 -{
 148 -       irq_gic = irq_controller;
 149 -}
 150 -
 151 -static void
 152 -gic_irqdispatch(void)
 153 -{
 154 -       unsigned int irq = gic_get_int();
 155 -
 156 -       if (likely(irq < GIC_NUM_INTRS))
 157 -               do_IRQ(MIPS_GIC_IRQ_BASE + irq);
 158 -       else {
 159 -               pr_debug("Spurious GIC Interrupt!\n");
 160 -               spurious_interrupt();
 161 -       }
 162 -
 163 -}
 164 -
 165 -static void
 166 -vi_timer_irqdispatch(void)
 167 -{
 168 -       do_IRQ(cp0_compare_irq);
 169 -}
 170 -
 171 -#if defined(CONFIG_MIPS_MT_SMP)
 172 -unsigned int
 173 -plat_ipi_call_int_xlate(unsigned int cpu)
 174 -{
 175 -       return GIC_CALL_INT(cpu);
 176 -}
 177 -
 178 -unsigned int
 179 -plat_ipi_resched_int_xlate(unsigned int cpu)
 180 -{
 181 -       return GIC_RESCHED_INT(cpu);
 182 -}
 183 -#endif
 184 -
 185 -asmlinkage void
 186 -plat_irq_dispatch(void)
 187 -{
 188 -       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 189 -
 190 -       if (unlikely(!pending)) {
 191 -               pr_err("Spurious CP0 Interrupt!\n");
 192 -               spurious_interrupt();
 193 -       } else {
 194 -               if (pending & CAUSEF_IP7)
 195 -                       do_IRQ(cp0_compare_irq);
 196 -
 197 -               if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
 198 -                       gic_irqdispatch();
 199 -       }
 200 -}
 201 -
 202 -unsigned int __cpuinit
 203 -get_c0_compare_int(void)
 204 -{
 205 -       return CP0_LEGACY_COMPARE_IRQ;
 206 -}
 207 -
 208 -static int
 209 -gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 210 -{
 211 -       irq_set_chip_and_handler(irq, irq_gic,
 212 -#if defined(CONFIG_MIPS_MT_SMP)
 213 -               (hw >= gic_resched_int_base) ?
 214 -                       handle_percpu_irq :
 215 -#endif
 216 -                       handle_level_irq);
 217 -
 218 -       return 0;
 219 -}
 220 -
 221 -static const struct irq_domain_ops irq_domain_ops = {
 222 -       .xlate = irq_domain_xlate_onecell,
 223 -       .map = gic_map,
 224 -};
 225 -
 226 -static int __init
 227 -of_gic_init(struct device_node *node,
 228 -                               struct device_node *parent)
 229 +unsigned int get_c0_compare_int(void)
 230  {
 231 -       struct irq_domain *domain;
 232 -       struct resource gcmp = { 0 }, gic = { 0 };
 233 -       unsigned int gic_rev;
 234 -       int i;
 235 -
 236 -       if (of_address_to_resource(node, 0, &gic))
 237 -               panic("Failed to get gic memory range");
 238 -       if (request_mem_region(gic.start, resource_size(&gic),
 239 -                               gic.name) < 0)
 240 -               panic("Failed to request gic memory");
 241 -       if (of_address_to_resource(node, 2, &gcmp))
 242 -               panic("Failed to get gic memory range");
 243 -       if (request_mem_region(gcmp.start, resource_size(&gcmp),
 244 -                               gcmp.name) < 0)
 245 -               panic("Failed to request gcmp memory");
 246 -
 247 -       _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
 248 -       if (!_gcmp_base)
 249 -               panic("Failed to remap gcmp memory\n");
 250 -
 251 -       /* tell the gcmp where to find the gic */
 252 -       write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
 253 -       gic_present = 1;
 254 -       if (cpu_has_vint) {
 255 -               set_vi_handler(2, gic_irqdispatch);
 256 -               set_vi_handler(3, gic_irqdispatch);
 257 -               set_vi_handler(4, gic_irqdispatch);
 258 -               set_vi_handler(7, vi_timer_irqdispatch);
 259 -       }
 260 -
 261 -       gic_fill_map();
 262 -
 263 -       gic_init(gic.start, resource_size(&gic), gic_intr_map,
 264 -               ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
 265 -
 266 -       GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
 267 -       pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
 268 -
 269 -       domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
 270 -                       0, &irq_domain_ops, NULL);
 271 -       if (!domain)
 272 -               panic("Failed to add irqdomain");
 273 -
 274 -#if defined(CONFIG_MIPS_MT_SMP)
 275 -       for (i = 0; i < nr_cpu_ids; i++) {
 276 -               setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
 277 -               setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
 278 -       }
 279 -#endif
 280 -
 281 -       change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
 282 -                               STATUSF_IP2);
 283 -       return 0;
 284 +       return gic_get_c0_compare_int();
 285  }
 286
 287  static struct of_device_id __initdata of_irq_ids[] = {
 288 -       { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
 289 -       { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
 290 +       { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
 291 +       { .compatible = "mti,gic", .data = gic_of_init },
 292         {},
 293  };
 294
 295 --- a/drivers/irqchip/irq-mips-gic.c
 296 +++ b/drivers/irqchip/irq-mips-gic.c
 297 @@ -864,7 +864,7 @@
 298         __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
 299  }
 300
 301 -static int __init gic_of_init(struct device_node *node,
 302 +int __init gic_of_init(struct device_node *node,
 303                               struct device_node *parent)
 304  {
 305         struct resource res;