target/linux/ramips/patches-4.4/0019-arch-mips-ralink-add-mt7621-cpu-feature-overrides.patch

   1 From 43372c2be9fcf68bc40c322039c75893ce4e982c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:20:47 +0100
   4 Subject: [PATCH 19/53] arch: mips: ralink: add mt7621 cpu-feature-overrides
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../asm/mach-ralink/mt7621/cpu-feature-overrides.h |   65 ++++++++++++++++++++
   9  1 file changed, 65 insertions(+)
  10  create mode 100644 arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
  11
  12 --- /dev/null
  13 +++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
  14 @@ -0,0 +1,65 @@
  15 +/*
  16 + * Ralink MT7621 specific CPU feature overrides
  17 + *
  18 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  19 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  20 + * Copyright (C) 2015 Felix Fietkau <nbd@nbd.name>
  21 + *
  22 + * This file was derived from: include/asm-mips/cpu-features.h
  23 + *     Copyright (C) 2003, 2004 Ralf Baechle
  24 + *     Copyright (C) 2004 Maciej W. Rozycki
  25 + *
  26 + * This program is free software; you can redistribute it and/or modify it
  27 + * under the terms of the GNU General Public License version 2 as published
  28 + * by the Free Software Foundation.
  29 + *
  30 + */
  31 +#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
  32 +#define _MT7621_CPU_FEATURE_OVERRIDES_H
  33 +
  34 +#define cpu_has_tlb            1
  35 +#define cpu_has_4kex           1
  36 +#define cpu_has_3k_cache       0
  37 +#define cpu_has_4k_cache       1
  38 +#define cpu_has_tx39_cache     0
  39 +#define cpu_has_sb1_cache      0
  40 +#define cpu_has_fpu            0
  41 +#define cpu_has_32fpr          0
  42 +#define cpu_has_counter                1
  43 +#define cpu_has_watch          1
  44 +#define cpu_has_divec          1
  45 +
  46 +#define cpu_has_prefetch       1
  47 +#define cpu_has_ejtag          1
  48 +#define cpu_has_llsc           1
  49 +
  50 +#define cpu_has_mips16         1
  51 +#define cpu_has_mdmx           0
  52 +#define cpu_has_mips3d         0
  53 +#define cpu_has_smartmips      0
  54 +
  55 +#define cpu_has_mips32r1       1
  56 +#define cpu_has_mips32r2       1
  57 +#define cpu_has_mips64r1       0
  58 +#define cpu_has_mips64r2       0
  59 +
  60 +#define cpu_has_dsp            1
  61 +#define cpu_has_dsp2           0
  62 +#define cpu_has_mipsmt         1
  63 +
  64 +#define cpu_has_64bits         0
  65 +#define cpu_has_64bit_zero_reg 0
  66 +#define cpu_has_64bit_gp_regs  0
  67 +#define cpu_has_64bit_addresses        0
  68 +
  69 +#define cpu_dcache_line_size() 32
  70 +#define cpu_icache_line_size() 32
  71 +
  72 +#define cpu_has_dc_aliases     0
  73 +#define cpu_has_vtag_icache    0
  74 +
  75 +#define cpu_has_rixi           0
  76 +#define cpu_has_tlbinv         0
  77 +#define cpu_has_userlocal      1
  78 +
  79 +#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */