Move NAND driver from rb1xx to adm5120, rbmipsnand fixed by David Goodenough, thanks !
[openwrt/svn-archive/archive.git] / target / linux / rb1xx-2.6 / files / arch / mips / adm5120 / irq.c
1 /*
2 * Copyright (C) ADMtek Incorporated.
3 * Creator : daniell@admtek.com.tw
4 * Carsten Langgaard, carstenl@mips.com
5 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
6 * Copyright (C) 2001 Ralf Baechle
7 * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
8 */
9
10 #include <linux/autoconf.h>
11 #include <linux/init.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/pm.h>
19
20 #include <asm/irq.h>
21 #include <asm/time.h>
22 #include <asm/mipsregs.h>
23 #include <asm/gdb-stub.h>
24 #include <asm/irq_cpu.h>
25
26 #define MIPS_CPU_TIMER_IRQ 7
27
28 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
29 extern irq_desc_t irq_desc[];
30 extern asmlinkage void mipsIRQ(void);
31
32 int mips_int_lock(void);
33 void mips_int_unlock(int);
34
35 unsigned int mips_counter_frequency;
36
37 #define ADM5120_INTC_REG(reg) (*(volatile u32 *)(KSEG1ADDR(0x12200000+(reg))))
38 #define ADM5120_INTC_STATUS ADM5120_INTC_REG(0x00)
39 #define ADM5120_INTC_ENABLE ADM5120_INTC_REG(0x08)
40 #define ADM5120_INTC_DISABLE ADM5120_INTC_REG(0x0c)
41 #define ADM5120_IRQ_MAX 9
42 #define ADM5120_IRQ_MASK 0x3ff
43
44 void adm5120_hw0_irqdispatch(struct pt_regs *regs)
45 {
46 unsigned long intsrc;
47 int i;
48
49 intsrc = ADM5120_INTC_STATUS & ADM5120_IRQ_MASK;
50
51 for (i = 0; intsrc; intsrc >>= 1, i++)
52 if (intsrc & 0x1)
53 do_IRQ(i);
54 else
55 spurious_interrupt();
56 }
57
58 void mips_timer_interrupt(struct pt_regs *regs)
59 {
60 write_c0_compare(read_c0_count()+ mips_counter_frequency/HZ);
61 ll_timer_interrupt(MIPS_CPU_TIMER_IRQ);
62 }
63
64 /* Main interrupt dispatcher */
65 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
66 {
67 unsigned int cp0_cause = read_c0_cause() & read_c0_status();
68
69 if (cp0_cause & CAUSEF_IP7) {
70 mips_timer_interrupt( regs);
71 } else if (cp0_cause & CAUSEF_IP2) {
72 adm5120_hw0_irqdispatch( regs);
73 }
74 }
75
76 void enable_adm5120_irq(unsigned int irq)
77 {
78 int s;
79
80 /* Disable all interrupts (FIQ/IRQ) */
81 s = mips_int_lock();
82
83 if ((irq < 0) || (irq > ADM5120_IRQ_MAX))
84 goto err_exit;
85
86 ADM5120_INTC_ENABLE = (1<<irq);
87
88 err_exit:
89
90 /* Restore the interrupts states */
91 mips_int_unlock(s);
92 }
93
94
95 void disable_adm5120_irq(unsigned int irq)
96 {
97 int s;
98
99 /* Disable all interrupts (FIQ/IRQ) */
100 s = mips_int_lock();
101
102 if ((irq < 0) || (irq > ADM5120_IRQ_MAX))
103 goto err_exit;
104
105 ADM5120_INTC_DISABLE = (1<<irq);
106
107 err_exit:
108 /* Restore the interrupts states */
109 mips_int_unlock(s);
110 }
111
112 unsigned int startup_adm5120_irq(unsigned int irq)
113 {
114 enable_adm5120_irq(irq);
115 return 0;
116 }
117
118 void shutdown_adm5120_irq(unsigned int irq)
119 {
120 disable_adm5120_irq(irq);
121 }
122
123 static inline void ack_adm5120_irq(unsigned int irq_nr)
124 {
125 ADM5120_INTC_DISABLE = (1 << irq_nr);
126 }
127
128
129 static void end_adm5120_irq(unsigned int irq_nr)
130 {
131 ADM5120_INTC_ENABLE = (1 << irq_nr);
132 }
133
134 static hw_irq_controller adm5120_irq_type = {
135 .typename = "MIPS",
136 .startup = startup_adm5120_irq,
137 .shutdown = shutdown_adm5120_irq,
138 .enable = enable_adm5120_irq,
139 .disable = disable_adm5120_irq,
140 .ack = ack_adm5120_irq,
141 .end = end_adm5120_irq,
142 .set_affinity = NULL,
143 };
144
145
146 void __init arch_init_irq(void)
147 {
148 int i;
149
150 for (i = 0; i <= ADM5120_IRQ_MAX; i++) {
151 irq_desc[i].status = IRQ_DISABLED;
152 irq_desc[i].action = 0;
153 irq_desc[i].depth = 1;
154 irq_desc[i].chip = &adm5120_irq_type;
155 }
156 }