convert rb532 to the new structure
[openwrt/svn-archive/archive.git] / target / linux / rb532-2.6 / files / arch / mips / pci / pci-rc32434.c
1 /**************************************************************************
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI initialization for IDT EB434 board
5 *
6 * Copyright 2004 IDT Inc. (rischelp@idt.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 **************************************************************************
30 * May 2004 rkt, neb
31 *
32 * Initial Release
33 *
34 *
35 *
36 **************************************************************************
37 */
38
39 #include <linux/autoconf.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/kernel.h>
43 #include <linux/init.h>
44
45 #include <asm/rc32434/rc32434.h>
46 #include <asm/rc32434/pci.h>
47
48 #define PCI_ACCESS_READ 0
49 #define PCI_ACCESS_WRITE 1
50
51 /* define an unsigned array for the PCI registers */
52 unsigned int korinaCnfgRegs[25] = {
53 KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
54 KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
55 KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
56 KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
57 KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
58 KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
59 };
60 static struct resource rc32434_res_pci_mem1;
61 static struct resource rc32434_res_pci_mem2;
62
63 static struct resource rc32434_res_pci_mem1 = {
64 .name = "PCI MEM1",
65 .start = 0x50000000,
66 .end = 0x5FFFFFFF,
67 .flags = IORESOURCE_MEM,
68 .parent = &rc32434_res_pci_mem1,
69 .sibling = NULL,
70 .child = &rc32434_res_pci_mem2
71 };
72
73 static struct resource rc32434_res_pci_mem2 = {
74 .name = "PCI Mem2",
75 .start = 0x60000000,
76 .end = 0x6FFFFFFF,
77 .flags = IORESOURCE_MEM,
78 .parent = &rc32434_res_pci_mem1,
79 .sibling = NULL,
80 .child = NULL
81 };
82
83 static struct resource rc32434_res_pci_io1 = {
84 .name = "PCI I/O1",
85 .start = 0x18800000,
86 .end = 0x188FFFFF,
87 .flags = IORESOURCE_IO,
88 };
89
90 extern struct pci_ops rc32434_pci_ops;
91
92 #define PCI_MEM1_START PCI_ADDR_START
93 #define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
94 #define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
95 #define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
96 #define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
97 #define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
98 #define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
99 #define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
100
101
102 struct pci_controller rc32434_controller2;
103
104 struct pci_controller rc32434_controller = {
105 .pci_ops = &rc32434_pci_ops,
106 .mem_resource = &rc32434_res_pci_mem1,
107 .io_resource = &rc32434_res_pci_io1,
108 .mem_offset = 0,
109 .io_offset = 0,
110
111 };
112
113 #ifdef __MIPSEB__
114 #define PCI_ENDIAN_FLAG PCILBAC_sb_m
115 #else
116 #define PCI_ENDIAN_FLAG 0
117 #endif
118
119 static int __init rc32434_pcibridge_init(void)
120 {
121 unsigned int pcicValue, pcicData = 0;
122 unsigned int dummyRead, pciCntlVal;
123 int loopCount;
124 unsigned int pciConfigAddr;
125
126 pcicValue = rc32434_pci->pcic;
127 pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
128 if (!((pcicValue == PCIM_H_EA) ||
129 (pcicValue == PCIM_H_IA_FIX) ||
130 (pcicValue == PCIM_H_IA_RR))) {
131 printk("PCI init error!!!\n");
132 /* Not in Host Mode, return ERROR */
133 return -1;
134 }
135 /* Enables the Idle Grant mode, Arbiter Parking */
136 pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
137 rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
138 /* Zero out the PCI status & PCI Status Mask */
139 for(;;)
140 {
141 pcicData = rc32434_pci->pcis;
142 if (!(pcicData & PCIS_rip_m))
143 break;
144 }
145
146 rc32434_pci->pcis = 0;
147 rc32434_pci->pcism = 0xFFFFFFFF;
148 /* Zero out the PCI decoupled registers */
149 rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
150 rc32434_pci->pcidas=0; /* clear the status */
151 rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
152 /* Mask PCI Messaging Interrupts */
153 rc32434_pci_msg->pciiic = 0;
154 rc32434_pci_msg->pciiim = 0xFFFFFFFF;
155 rc32434_pci_msg->pciioic = 0;
156 rc32434_pci_msg->pciioim = 0;
157
158
159 /* Setup PCILB0 as Memory Window */
160 rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
161
162 /* setup the PCI map address as same as the local address */
163
164 rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
165
166
167 /* Setup PCILBA1 as MEM */
168 rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
169 dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
170 rc32434_pci->pcilba[1].a = 0x60000000;
171 rc32434_pci->pcilba[1].m = 0x60000000;
172
173 /* setup PCILBA2 as IO Window*/
174 rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
175 dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
176 rc32434_pci->pcilba[2].a = 0x18C00000;
177 rc32434_pci->pcilba[2].m = 0x18FFFFFF;
178
179 /* setup PCILBA2 as IO Window*/
180 rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
181 dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
182
183 /* Setup PCILBA3 as IO Window */
184 rc32434_pci->pcilba[3].a = 0x18800000;
185 rc32434_pci->pcilba[3].m = 0x18800000;
186 rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
187 dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
188
189 pciConfigAddr=(unsigned int)(0x80000004);
190 for(loopCount=0;loopCount<24;loopCount++){
191 rc32434_pci->pcicfga=pciConfigAddr;
192 dummyRead=rc32434_pci->pcicfga;
193 rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
194 dummyRead=rc32434_pci->pcicfgd;
195 pciConfigAddr += 4;
196 }
197 rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
198 | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
199
200 pciCntlVal=rc32434_pci->pcic;
201 pciCntlVal &=~(PCIC_tnr_m);
202 rc32434_pci->pcic = pciCntlVal;
203 pciCntlVal=rc32434_pci->pcic;
204 return 0;
205 }
206
207 /* Do platform specific device initialization at pci_enable_device() time */
208 int pcibios_plat_dev_init(struct pci_dev *dev)
209 {
210 if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
211 /* disable prefetched memory range */
212 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
213 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
214
215 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
216 }
217 return 0;
218 }
219
220 static int __init rc32434_pci_init(void)
221 {
222 printk("PCI: Initializing PCI\n");
223
224 ioport_resource.start = rc32434_res_pci_io1.start;
225 ioport_resource.end = rc32434_res_pci_io1.end;
226
227 rc32434_pcibridge_init();
228
229 register_pci_controller(&rc32434_controller);
230 rc32434_sync();
231 }
232
233 arch_initcall(rc32434_pci_init);
234