convert rb532 to the new structure
[openwrt/svn-archive/archive.git] / target / linux / rb532-2.6 / files / include / asm-mips / rc32434 / dma.h
1 #ifndef __IDT_DMA_H__
2 #define __IDT_DMA_H__
3
4 /*******************************************************************************
5 *
6 * Copyright 2002 Integrated Device Technology, Inc.
7 * All rights reserved.
8 *
9 * DMA register definition.
10 *
11 * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
12 *
13 * Author : ryan.holmQVist@idt.com
14 * Date : 20011005
15 * Update :
16 * $Log: dma.h,v $
17 * Revision 1.3 2002/06/06 18:34:03 astichte
18 * Added XXX_PhysicalAddress and XXX_VirtualAddress
19 *
20 * Revision 1.2 2002/06/05 18:30:46 astichte
21 * Removed IDTField
22 *
23 * Revision 1.1 2002/05/29 17:33:21 sysarch
24 * jba File moved from vcode/include/idt/acacia
25 *
26 *
27 ******************************************************************************/
28
29 enum
30 {
31 DMA0_PhysicalAddress = 0x18040000,
32 DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
33
34 DMA0_VirtualAddress = 0xb8040000,
35 DMA_VirtualAddress = DMA0_VirtualAddress, // Default
36 } ;
37
38 /*
39 * DMA descriptor (in physical memory).
40 */
41
42 typedef struct DMAD_s
43 {
44 u32 control ; // Control. use DMAD_*
45 u32 ca ; // Current Address.
46 u32 devcs ; // Device control and status.
47 u32 link ; // Next descriptor in chain.
48 } volatile *DMAD_t ;
49
50 enum
51 {
52 DMAD_size = sizeof (struct DMAD_s),
53 DMAD_count_b = 0, // in DMAD_t -> control
54 DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
55 DMAD_ds_b = 20, // in DMAD_t -> control
56 DMAD_ds_m = 0x00300000, // in DMAD_t -> control
57 DMAD_ds_ethRcv_v = 0,
58 DMAD_ds_ethXmt_v = 0,
59 DMAD_ds_memToFifo_v = 0,
60 DMAD_ds_fifoToMem_v = 0,
61 DMAD_ds_pciToMem_v = 0,
62 DMAD_ds_memToPci_v = 0,
63
64 DMAD_devcmd_b = 22, // in DMAD_t -> control
65 DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
66 DMAD_devcmd_byte_v = 0, //memory-to-memory
67 DMAD_devcmd_halfword_v = 1, //memory-to-memory
68 DMAD_devcmd_word_v = 2, //memory-to-memory
69 DMAD_devcmd_2words_v = 3, //memory-to-memory
70 DMAD_devcmd_4words_v = 4, //memory-to-memory
71 DMAD_devcmd_6words_v = 5, //memory-to-memory
72 DMAD_devcmd_8words_v = 6, //memory-to-memory
73 DMAD_devcmd_16words_v = 7, //memory-to-memory
74 DMAD_cof_b = 25, // chain on finished
75 DMAD_cof_m = 0x02000000, //
76 DMAD_cod_b = 26, // chain on done
77 DMAD_cod_m = 0x04000000, //
78 DMAD_iof_b = 27, // interrupt on finished
79 DMAD_iof_m = 0x08000000, //
80 DMAD_iod_b = 28, // interrupt on done
81 DMAD_iod_m = 0x10000000, //
82 DMAD_t_b = 29, // terminated
83 DMAD_t_m = 0x20000000, //
84 DMAD_d_b = 30, // done
85 DMAD_d_m = 0x40000000, //
86 DMAD_f_b = 31, // finished
87 DMAD_f_m = 0x80000000, //
88 } ;
89
90 /*
91 * DMA register (within Internal Register Map).
92 */
93
94 struct DMA_Chan_s
95 {
96 u32 dmac ; // Control.
97 u32 dmas ; // Status.
98 u32 dmasm ; // Mask.
99 u32 dmadptr ; // Descriptor pointer.
100 u32 dmandptr ; // Next descriptor pointer.
101 };
102
103 typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
104
105 //DMA_Channels use DMACH_count instead
106
107 enum
108 {
109 DMAC_run_b = 0, //
110 DMAC_run_m = 0x00000001, //
111 DMAC_dm_b = 1, // done mask
112 DMAC_dm_m = 0x00000002, //
113 DMAC_mode_b = 2, //
114 DMAC_mode_m = 0x0000000c, //
115 DMAC_mode_auto_v = 0,
116 DMAC_mode_burst_v = 1,
117 DMAC_mode_transfer_v = 2, //usually used
118 DMAC_mode_reserved_v = 3,
119 DMAC_a_b = 4, //
120 DMAC_a_m = 0x00000010, //
121
122 DMAS_f_b = 0, // finished (sticky)
123 DMAS_f_m = 0x00000001, //
124 DMAS_d_b = 1, // done (sticky)
125 DMAS_d_m = 0x00000002, //
126 DMAS_c_b = 2, // chain (sticky)
127 DMAS_c_m = 0x00000004, //
128 DMAS_e_b = 3, // error (sticky)
129 DMAS_e_m = 0x00000008, //
130 DMAS_h_b = 4, // halt (sticky)
131 DMAS_h_m = 0x00000010, //
132
133 DMASM_f_b = 0, // finished (1=mask)
134 DMASM_f_m = 0x00000001, //
135 DMASM_d_b = 1, // done (1=mask)
136 DMASM_d_m = 0x00000002, //
137 DMASM_c_b = 2, // chain (1=mask)
138 DMASM_c_m = 0x00000004, //
139 DMASM_e_b = 3, // error (1=mask)
140 DMASM_e_m = 0x00000008, //
141 DMASM_h_b = 4, // halt (1=mask)
142 DMASM_h_m = 0x00000010, //
143 } ;
144
145 /*
146 * DMA channel definitions
147 */
148
149 enum
150 {
151 DMACH_ethRcv = 0,
152 DMACH_ethXmt = 1,
153 DMACH_memToFifo = 2,
154 DMACH_fifoToMem = 3,
155 DMACH_pciToMem = 4,
156 DMACH_memToPci = 5,
157
158 DMACH_count //must be last
159 };
160
161
162 typedef struct DMAC_s
163 {
164 struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
165 } volatile *DMA_t ;
166
167 #endif // __IDT_DMA_H__
168