convert rb532 to the new structure
[openwrt/svn-archive/archive.git] / target / linux / rb532-2.6 / files / include / asm-mips / rc32434 / gpio.h
1 #ifndef __IDT_GPIO_H__
2 #define __IDT_GPIO_H__
3
4 /*******************************************************************************
5 *
6 * Copyright 2002 Integrated Device Technology, Inc.
7 * All rights reserved.
8 *
9 * GPIO register definition.
10 *
11 * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
12 *
13 * Author : ryan.holmQVist@idt.com
14 * Date : 20011005
15 * Update :
16 * $Log: gpio.h,v $
17 * Revision 1.2 2002/06/06 18:34:04 astichte
18 * Added XXX_PhysicalAddress and XXX_VirtualAddress
19 *
20 * Revision 1.1 2002/05/29 17:33:22 sysarch
21 * jba File moved from vcode/include/idt/acacia
22 *
23 *
24 ******************************************************************************/
25
26 enum
27 {
28 GPIO0_PhysicalAddress = 0x18050000,
29 GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
30
31 GPIO0_VirtualAddress = 0xb8050000,
32 GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
33 } ;
34
35 typedef struct
36 {
37 u32 gpiofunc; /* GPIO Function Register
38 * gpiofunc[x]==0 bit = gpio
39 * func[x]==1 bit = altfunc
40 */
41 u32 gpiocfg; /* GPIO Configuration Register
42 * gpiocfg[x]==0 bit = input
43 * gpiocfg[x]==1 bit = output
44 */
45 u32 gpiod; /* GPIO Data Register
46 * gpiod[x] read/write gpio pinX status
47 */
48 u32 gpioilevel; /* GPIO Interrupt Status Register
49 * interrupt level (see gpioistat)
50 */
51 u32 gpioistat; /* Gpio Interrupt Status Register
52 * istat[x] = (gpiod[x] == level[x])
53 * cleared in ISR (STICKY bits)
54 */
55 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
56 } volatile * GPIO_t ;
57
58 typedef enum
59 {
60 GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
61 GPIO_alt_v = 1, // gpiofunc use pin as alt.
62 GPIO_input_v = 0, // gpiocfg use pin as input.
63 GPIO_output_v = 1, // gpiocfg use pin as output.
64 GPIO_pin0_b = 0,
65 GPIO_pin0_m = 0x00000001,
66 GPIO_pin1_b = 1,
67 GPIO_pin1_m = 0x00000002,
68 GPIO_pin2_b = 2,
69 GPIO_pin2_m = 0x00000004,
70 GPIO_pin3_b = 3,
71 GPIO_pin3_m = 0x00000008,
72 GPIO_pin4_b = 4,
73 GPIO_pin4_m = 0x00000010,
74 GPIO_pin5_b = 5,
75 GPIO_pin5_m = 0x00000020,
76 GPIO_pin6_b = 6,
77 GPIO_pin6_m = 0x00000040,
78 GPIO_pin7_b = 7,
79 GPIO_pin7_m = 0x00000080,
80 GPIO_pin8_b = 8,
81 GPIO_pin8_m = 0x00000100,
82 GPIO_pin9_b = 9,
83 GPIO_pin9_m = 0x00000200,
84 GPIO_pin10_b = 10,
85 GPIO_pin10_m = 0x00000400,
86 GPIO_pin11_b = 11,
87 GPIO_pin11_m = 0x00000800,
88 GPIO_pin12_b = 12,
89 GPIO_pin12_m = 0x00001000,
90 GPIO_pin13_b = 13,
91 GPIO_pin13_m = 0x00002000,
92 GPIO_pin14_b = 14,
93 GPIO_pin14_m = 0x00004000,
94 GPIO_pin15_b = 15,
95 GPIO_pin15_m = 0x00008000,
96 GPIO_pin16_b = 16,
97 GPIO_pin16_m = 0x00010000,
98 GPIO_pin17_b = 17,
99 GPIO_pin17_m = 0x00020000,
100 GPIO_pin18_b = 18,
101 GPIO_pin18_m = 0x00040000,
102 GPIO_pin19_b = 19,
103 GPIO_pin19_m = 0x00080000,
104 GPIO_pin20_b = 20,
105 GPIO_pin20_m = 0x00100000,
106 GPIO_pin21_b = 21,
107 GPIO_pin21_m = 0x00200000,
108 GPIO_pin22_b = 22,
109 GPIO_pin22_m = 0x00400000,
110 GPIO_pin23_b = 23,
111 GPIO_pin23_m = 0x00800000,
112 GPIO_pin24_b = 24,
113 GPIO_pin24_m = 0x01000000,
114 GPIO_pin25_b = 25,
115 GPIO_pin25_m = 0x02000000,
116 GPIO_pin26_b = 26,
117 GPIO_pin26_m = 0x04000000,
118 GPIO_pin27_b = 27,
119 GPIO_pin27_m = 0x08000000,
120 GPIO_pin28_b = 28,
121 GPIO_pin28_m = 0x10000000,
122 GPIO_pin29_b = 29,
123 GPIO_pin29_m = 0x20000000,
124 GPIO_pin30_b = 30,
125 GPIO_pin30_m = 0x40000000,
126 GPIO_pin31_b = 31,
127 GPIO_pin31_m = 0x80000000,
128
129 // Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
130
131 GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
132 GPIO_u0sout_m = GPIO_pin0_m,
133 GPIO_u0sout_cfg_v = GPIO_output_v,
134 GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
135 GPIO_u0sinp_m = GPIO_pin1_m,
136 GPIO_u0sinp_cfg_v = GPIO_input_v,
137 GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
138 GPIO_u0rtsn_m = GPIO_pin2_m,
139 GPIO_u0rtsn_cfg_v = GPIO_output_v,
140 GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
141 GPIO_u0ctsn_m = GPIO_pin3_m,
142 GPIO_u0ctsn_cfg_v = GPIO_input_v,
143 GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
144 GPIO_maddr22_m = GPIO_pin4_m,
145 GPIO_maddr22_cfg_v = GPIO_output_v,
146
147 GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
148 GPIO_maddr23_m = GPIO_pin5_m,
149 GPIO_maddr23_cfg_v = GPIO_output_v,
150
151 GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
152 GPIO_maddr24_m = GPIO_pin6_m,
153 GPIO_maddr24_cfg_v = GPIO_output_v,
154
155 GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
156 GPIO_maddr25_m = GPIO_pin7_m,
157 GPIO_maddr25_cfg_v = GPIO_output_v,
158
159 GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
160 GPIO_cpu_m = GPIO_pin8_m,
161 GPIO_cpu_cfg_v = GPIO_output_v,
162 GPIO_afspare6_b = GPIO_pin9_b, // reserved.
163 GPIO_afspare6_m = GPIO_pin9_m,
164 GPIO_afspare6_cfg_v = GPIO_input_v,
165 GPIO_afspare4_b = GPIO_pin10_b, // reserved.
166 GPIO_afspare4_m = GPIO_pin10_m,
167 GPIO_afspare4_cfg_v = GPIO_input_v,
168 GPIO_afspare3_b = GPIO_pin11_b, // reserved.
169 GPIO_afspare3_m = GPIO_pin11_m,
170 GPIO_afspare3_cfg_v = GPIO_input_v,
171 GPIO_afspare2_b = GPIO_pin12_b, // reserved.
172 GPIO_afspare2_m = GPIO_pin12_m,
173 GPIO_afspare2_cfg_v = GPIO_input_v,
174 GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
175 GPIO_pcimuintn_m = GPIO_pin13_m,
176 GPIO_pcimuintn_cfg_v = GPIO_output_v,
177
178 } GPIO_DEFS_t;
179
180 #endif // __IDT_GPIO_H__
181