convert rb532 to the new structure
[openwrt/svn-archive/archive.git] / target / linux / rb532-2.6 / files / include / asm-mips / rc32434 / rc32434.h
1 /*
2 ***************************************************************************
3 * Definitions for IDT RC323434 CPU.
4 *
5 ****************************************************************************
6 * Kiran Rao
7 *
8 * Original form
9 ****************************************************************************
10 * P. Sadik Oct 08, 2003
11 *
12 * Started revision history
13 * Made IDT_BUS_FREQ a kernel configuration parameter
14 ****************************************************************************
15 * P. Sadik Oct 10, 2003
16 *
17 * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
18 * idt_cpu_freq is used everywhere
19 ****************************************************************************
20 * P. Sadik Oct 20, 2003
21 *
22 * Removed RC32434_BASE_BAUD
23 ****************************************************************************
24 */
25 #ifndef _RC32434_H_
26 #define _RC32434_H_
27
28 #include <linux/autoconf.h>
29 #include <linux/delay.h>
30 #include <asm/io.h>
31
32 #define RC32434_REG_BASE 0x18000000
33
34 #define interrupt ((volatile INT_t ) INT0_VirtualAddress)
35 #define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
36
37
38 #define IDT_CLOCK_MULT 2
39 #define MIPS_CPU_TIMER_IRQ 7
40 /* Interrupt Controller */
41 #define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
42 #define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
43 #define IC_GROUP_OFFSET 0x0C
44
45 #define NUM_INTR_GROUPS 5
46 /* 16550 UARTs */
47
48 #define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
49 #define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
50 #define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
51 #define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
52 #define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
53
54
55 #ifdef __MIPSEB__
56 #define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
57 #else
58 #define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
59 #endif
60
61 #define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
62 // #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
63
64 #define local_readl(addr) __raw_readl(addr)
65 #define local_writel(l,addr) __raw_writel(l,addr)
66
67 /* cpu pipeline flush */
68 static inline void rc32434_sync(void)
69 {
70 __asm__ volatile ("sync");
71 }
72
73 static inline void rc32434_sync_udelay(int us)
74 {
75 __asm__ volatile ("sync");
76 udelay(us);
77 }
78
79 static inline void rc32434_sync_delay(int ms)
80 {
81 __asm__ volatile ("sync");
82 mdelay(ms);
83 }
84
85 /*
86 * C access to CLZ and CLO instructions
87 * (count leading zeroes/ones).
88 */
89 static inline int rc32434_clz(unsigned long val)
90 {
91 int ret;
92 __asm__ volatile (
93 ".set\tnoreorder\n\t"
94 ".set\tnoat\n\t"
95 ".set\tmips32\n\t"
96 "clz\t%0,%1\n\t"
97 ".set\tmips0\n\t"
98 ".set\tat\n\t"
99 ".set\treorder"
100 : "=r" (ret)
101 : "r" (val));
102
103 return ret;
104 }
105 static inline int rc32434_clo(unsigned long val)
106 {
107 int ret;
108 __asm__ volatile (
109 ".set\tnoreorder\n\t"
110 ".set\tnoat\n\t"
111 ".set\tmips32\n\t"
112 "clo\t%0,%1\n\t"
113 ".set\tmips0\n\t"
114 ".set\tat\n\t"
115 ".set\treorder"
116 : "=r" (ret)
117 : "r" (val));
118
119 return ret;
120 }
121
122 #endif /* _RC32434_H_ */