Add NAND flash/YAFFS2 patches for RB532 by David Goodenough
[openwrt/svn-archive/archive.git] / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
3 +++ linux.dev/arch/mips/Kconfig 2006-10-11 21:56:38.000000000 +0200
4 @@ -742,6 +742,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1028,7 +1041,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-10-11 21:55:59.000000000 +0200
35 +++ linux.dev/arch/mips/Makefile 2006-10-11 21:56:38.000000000 +0200
36 @@ -580,6 +580,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-10-11 21:56:38.000000000 +0200
53 @@ -876,7 +876,6 @@
54 case CPU_R10000:
55 case CPU_R12000:
56 case CPU_R14000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -904,6 +903,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-10-11 21:56:38.000000000 +0200
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/config.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-06-18 03:49:35.000000000 +0200
124 +++ linux.dev/arch/mips/pci/Makefile 2006-10-11 21:56:38.000000000 +0200
125 @@ -57,3 +57,4 @@
126 obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
127 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
128 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-10-11 21:56:38.000000000 +0200
133 @@ -0,0 +1,195 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + *
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License as published by the
143 + * Free Software Foundation; either version 2 of the License, or (at your
144 + * option) any later version.
145 + *
146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
156 + *
157 + * You should have received a copy of the GNU General Public License along
158 + * with this program; if not, write to the Free Software Foundation, Inc.,
159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
160 + *
161 + *
162 + **************************************************************************
163 + * May 2004 rkt, neb
164 + *
165 + * Initial Release
166 + *
167 + *
168 + *
169 + **************************************************************************
170 + */
171 +
172 +#include <linux/config.h>
173 +#include <linux/init.h>
174 +#include <linux/pci.h>
175 +#include <linux/types.h>
176 +#include <linux/delay.h>
177 +
178 +#include <asm/cpu.h>
179 +#include <asm/io.h>
180 +
181 +#include <asm/rc32434/rc32434.h>
182 +#include <asm/rc32434/pci.h>
183 +
184 +#define PCI_ACCESS_READ 0
185 +#define PCI_ACCESS_WRITE 1
186 +
187 +
188 +#define PCI_CFG_SET(bus,slot,func,off) \
189 + (rc32434_pci->pcicfga = (0x80000000 | \
190 + ((bus) << 16) | ((slot)<<11) | \
191 + ((func)<<8) | (off)))
192 +
193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
194 + unsigned int devfn, unsigned char where,
195 + u32 * data)
196 +{
197 + unsigned int slot = PCI_SLOT(devfn);
198 + u8 func = PCI_FUNC(devfn);
199 +
200 + /* Setup address */
201 + PCI_CFG_SET(bus->number, slot, func, where);
202 + rc32434_sync();
203 +
204 + if (access_type == PCI_ACCESS_WRITE)
205 + rc32434_pci->pcicfgd = *data;
206 + else
207 + *data = rc32434_pci->pcicfgd;
208 +
209 + rc32434_sync();
210 +
211 + return 0;
212 +}
213 +
214 +
215 +/*
216 + * We can't address 8 and 16 bit words directly. Instead we have to
217 + * read/write a 32bit word and mask/modify the data we actually want.
218 + */
219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
220 + int where, u8 * val)
221 +{
222 + u32 data;
223 + int ret;
224 +
225 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
226 + *val = (data >> ((where & 3) << 3)) & 0xff;
227 + return ret;
228 +}
229 +
230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
231 + int where, u16 * val)
232 +{
233 + u32 data;
234 + int ret;
235 +
236 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
237 + *val = (data >> ((where & 3) << 3)) & 0xffff;
238 + return ret;
239 +}
240 +
241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
242 + int where, u32 * val)
243 +{
244 + int ret;
245 +
246 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
247 + return ret;
248 +}
249 +
250 +static int
251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
252 + u8 val)
253 +{
254 + u32 data = 0;
255 +
256 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
257 + return -1;
258 +
259 + data = (data & ~(0xff << ((where & 3) << 3))) |
260 + (val << ((where & 3) << 3));
261 +
262 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 + return -1;
264 +
265 + return PCIBIOS_SUCCESSFUL;
266 +}
267 +
268 +
269 +static int
270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
271 + u16 val)
272 +{
273 + u32 data = 0;
274 +
275 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
276 + return -1;
277 +
278 + data = (data & ~(0xffff << ((where & 3) << 3))) |
279 + (val << ((where & 3) << 3));
280 +
281 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
282 + return -1;
283 +
284 +
285 + return PCIBIOS_SUCCESSFUL;
286 +}
287 +
288 +
289 +static int
290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
291 + u32 val)
292 +{
293 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
294 + return -1;
295 +
296 + return PCIBIOS_SUCCESSFUL;
297 +}
298 +
299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
300 + int where, int size, u32 * val)
301 +{
302 + switch (size) {
303 + case 1:
304 + return read_config_byte(bus, devfn, where, (u8 *) val);
305 + case 2:
306 + return read_config_word(bus, devfn, where, (u16 *) val);
307 + default:
308 + return read_config_dword(bus, devfn, where, val);
309 + }
310 +}
311 +
312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
313 + int where, int size, u32 val)
314 +{
315 + switch (size) {
316 + case 1:
317 + return write_config_byte(bus, devfn, where, (u8) val);
318 + case 2:
319 + return write_config_word(bus, devfn, where, (u16) val);
320 + default:
321 + return write_config_dword(bus, devfn, where, val);
322 + }
323 +}
324 +
325 +struct pci_ops rc32434_pci_ops = {
326 + .read = pci_config_read,
327 + .write = pci_config_write,
328 +};
329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
330 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
331 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-10-11 21:56:38.000000000 +0200
332 @@ -0,0 +1,234 @@
333 +/**************************************************************************
334 + *
335 + * BRIEF MODULE DESCRIPTION
336 + * PCI initialization for IDT EB434 board
337 + *
338 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
346 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
347 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
348 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
349 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
350 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
351 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
352 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
353 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
354 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
355 + *
356 + * You should have received a copy of the GNU General Public License along
357 + * with this program; if not, write to the Free Software Foundation, Inc.,
358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
359 + *
360 + *
361 + **************************************************************************
362 + * May 2004 rkt, neb
363 + *
364 + * Initial Release
365 + *
366 + *
367 + *
368 + **************************************************************************
369 + */
370 +
371 +#include <linux/config.h>
372 +#include <linux/types.h>
373 +#include <linux/pci.h>
374 +#include <linux/kernel.h>
375 +#include <linux/init.h>
376 +
377 +#include <asm/rc32434/rc32434.h>
378 +#include <asm/rc32434/pci.h>
379 +
380 +#define PCI_ACCESS_READ 0
381 +#define PCI_ACCESS_WRITE 1
382 +
383 +/* define an unsigned array for the PCI registers */
384 +unsigned int korinaCnfgRegs[25] = {
385 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
386 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
387 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
388 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
389 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
390 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
391 +};
392 +static struct resource rc32434_res_pci_mem1;
393 +static struct resource rc32434_res_pci_mem2;
394 +
395 +static struct resource rc32434_res_pci_mem1 = {
396 + .name = "PCI MEM1",
397 + .start = 0x50000000,
398 + .end = 0x5FFFFFFF,
399 + .flags = IORESOURCE_MEM,
400 + .parent = &rc32434_res_pci_mem1,
401 + .sibling = NULL,
402 + .child = &rc32434_res_pci_mem2
403 +};
404 +
405 +static struct resource rc32434_res_pci_mem2 = {
406 + .name = "PCI Mem2",
407 + .start = 0x60000000,
408 + .end = 0x6FFFFFFF,
409 + .flags = IORESOURCE_MEM,
410 + .parent = &rc32434_res_pci_mem1,
411 + .sibling = NULL,
412 + .child = NULL
413 +};
414 +
415 +static struct resource rc32434_res_pci_io1 = {
416 + .name = "PCI I/O1",
417 + .start = 0x18800000,
418 + .end = 0x188FFFFF,
419 + .flags = IORESOURCE_IO,
420 +};
421 +
422 +extern struct pci_ops rc32434_pci_ops;
423 +
424 +#define PCI_MEM1_START PCI_ADDR_START
425 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
427 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
428 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
429 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
430 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
431 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
432 +
433 +
434 +struct pci_controller rc32434_controller2;
435 +
436 +struct pci_controller rc32434_controller = {
437 + .pci_ops = &rc32434_pci_ops,
438 + .mem_resource = &rc32434_res_pci_mem1,
439 + .io_resource = &rc32434_res_pci_io1,
440 + .mem_offset = 0,
441 + .io_offset = 0,
442 +
443 +};
444 +
445 +#ifdef __MIPSEB__
446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
447 +#else
448 +#define PCI_ENDIAN_FLAG 0
449 +#endif
450 +
451 +static int __init rc32434_pcibridge_init(void)
452 +{
453 + unsigned int pcicValue, pcicData = 0;
454 + unsigned int dummyRead, pciCntlVal;
455 + int loopCount;
456 + unsigned int pciConfigAddr;
457 +
458 + pcicValue = rc32434_pci->pcic;
459 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
460 + if (!((pcicValue == PCIM_H_EA) ||
461 + (pcicValue == PCIM_H_IA_FIX) ||
462 + (pcicValue == PCIM_H_IA_RR))) {
463 + printk("PCI init error!!!\n");
464 + /* Not in Host Mode, return ERROR */
465 + return -1;
466 + }
467 + /* Enables the Idle Grant mode, Arbiter Parking */
468 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
469 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
470 + /* Zero out the PCI status & PCI Status Mask */
471 + for(;;)
472 + {
473 + pcicData = rc32434_pci->pcis;
474 + if (!(pcicData & PCIS_rip_m))
475 + break;
476 + }
477 +
478 + rc32434_pci->pcis = 0;
479 + rc32434_pci->pcism = 0xFFFFFFFF;
480 + /* Zero out the PCI decoupled registers */
481 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
482 + rc32434_pci->pcidas=0; /* clear the status */
483 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
484 + /* Mask PCI Messaging Interrupts */
485 + rc32434_pci_msg->pciiic = 0;
486 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
487 + rc32434_pci_msg->pciioic = 0;
488 + rc32434_pci_msg->pciioim = 0;
489 +
490 +
491 + /* Setup PCILB0 as Memory Window */
492 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
493 +
494 + /* setup the PCI map address as same as the local address */
495 +
496 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
497 +
498 +
499 + /* Setup PCILBA1 as MEM */
500 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
501 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
502 + rc32434_pci->pcilba[1].a = 0x60000000;
503 + rc32434_pci->pcilba[1].m = 0x60000000;
504 +
505 + /* setup PCILBA2 as IO Window*/
506 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
507 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
508 + rc32434_pci->pcilba[2].a = 0x18C00000;
509 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
510 +
511 + /* setup PCILBA2 as IO Window*/
512 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
513 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
514 +
515 + /* Setup PCILBA3 as IO Window */
516 + rc32434_pci->pcilba[3].a = 0x18800000;
517 + rc32434_pci->pcilba[3].m = 0x18800000;
518 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
519 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
520 +
521 + pciConfigAddr=(unsigned int)(0x80000004);
522 + for(loopCount=0;loopCount<24;loopCount++){
523 + rc32434_pci->pcicfga=pciConfigAddr;
524 + dummyRead=rc32434_pci->pcicfga;
525 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
526 + dummyRead=rc32434_pci->pcicfgd;
527 + pciConfigAddr += 4;
528 + }
529 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
530 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
531 +
532 + pciCntlVal=rc32434_pci->pcic;
533 + pciCntlVal &=~(PCIC_tnr_m);
534 + rc32434_pci->pcic = pciCntlVal;
535 + pciCntlVal=rc32434_pci->pcic;
536 + return 0;
537 +}
538 +
539 +/* Do platform specific device initialization at pci_enable_device() time */
540 +int pcibios_plat_dev_init(struct pci_dev *dev)
541 +{
542 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
543 + /* disable prefetched memory range */
544 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
545 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
546 +
547 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
548 + }
549 + return 0;
550 +}
551 +
552 +static int __init rc32434_pci_init(void)
553 +{
554 + printk("PCI: Initializing PCI\n");
555 +
556 + ioport_resource.start = rc32434_res_pci_io1.start;
557 + ioport_resource.end = rc32434_res_pci_io1.end;
558 +
559 + rc32434_pcibridge_init();
560 +
561 + register_pci_controller(&rc32434_controller);
562 + rc32434_sync();
563 +}
564 +
565 +arch_initcall(rc32434_pci_init);
566 +
567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
569 +++ linux.dev/arch/mips/rb500/devices.c 2006-10-11 21:56:38.000000000 +0200
570 @@ -0,0 +1,198 @@
571 +#include <linux/kernel.h>
572 +#include <linux/init.h>
573 +#include <linux/module.h>
574 +#include <linux/ctype.h>
575 +#include <linux/string.h>
576 +#include <linux/platform_device.h>
577 +#include <asm/unaligned.h>
578 +#include <asm/io.h>
579 +
580 +#include <asm/rc32434/rc32434.h>
581 +#include <asm/rc32434/dma.h>
582 +#include <asm/rc32434/dma_v.h>
583 +#include <asm/rc32434/eth.h>
584 +#include <asm/rc32434/rb.h>
585 +
586 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
587 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
588 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
589 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
590 +
591 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
592 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
593 +
594 +static struct resource korina_dev0_res[] = {
595 + {
596 + .name = "korina_regs",
597 + .start = ETH0_PhysicalAddress,
598 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
599 + .flags = IORESOURCE_MEM,
600 + },
601 + {
602 + .name = "korina_rx",
603 + .start = ETH0_DMA_RX_IRQ,
604 + .end = ETH0_DMA_RX_IRQ,
605 + .flags = IORESOURCE_IRQ
606 + },
607 + {
608 + .name = "korina_tx",
609 + .start = ETH0_DMA_TX_IRQ,
610 + .end = ETH0_DMA_TX_IRQ,
611 + .flags = IORESOURCE_IRQ
612 + },
613 + {
614 + .name = "korina_ovr",
615 + .start = ETH0_RX_OVR_IRQ,
616 + .end = ETH0_RX_OVR_IRQ,
617 + .flags = IORESOURCE_IRQ
618 + },
619 + {
620 + .name = "korina_und",
621 + .start = ETH0_TX_UND_IRQ,
622 + .end = ETH0_TX_UND_IRQ,
623 + .flags = IORESOURCE_IRQ
624 + },
625 + {
626 + .name = "korina_dma_rx",
627 + .start = ETH0_RX_DMA_ADDR,
628 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
629 + .flags = IORESOURCE_MEM,
630 + },
631 + {
632 + .name = "korina_dma_tx",
633 + .start = ETH0_TX_DMA_ADDR,
634 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
635 + .flags = IORESOURCE_MEM,
636 + }
637 +};
638 +
639 +static struct korina_device korina_dev0_data = {
640 + .name = "korina0",
641 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
642 +};
643 +
644 +static struct platform_device korina_dev0 = {
645 + .id = 0,
646 + .name = "korina",
647 + .dev.platform_data = &korina_dev0_data,
648 + .resource = korina_dev0_res,
649 + .num_resources = ARRAY_SIZE(korina_dev0_res),
650 +};
651 +
652 +
653 +#define CF_GPIO_NUM 13
654 +
655 +static struct resource cf_slot0_res[] = {
656 + {
657 + .name = "cf_membase",
658 + .flags = IORESOURCE_MEM
659 + },
660 + {
661 + .name = "cf_irq",
662 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
663 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
664 + .flags = IORESOURCE_IRQ
665 + }
666 +};
667 +
668 +static struct cf_device cf_slot0_data = {
669 + .gpio_pin = 13
670 +};
671 +
672 +static struct platform_device cf_slot0 = {
673 + .id = 0,
674 + .name = "rb500-cf",
675 + .dev.platform_data = &cf_slot0_data,
676 + .resource = cf_slot0_res,
677 + .num_resources = ARRAY_SIZE(cf_slot0_res),
678 +};
679 +
680 +/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
681 +static struct resource nand_slot0_res[] = {
682 + {
683 + .name = "nand_membase",
684 + .flags = IORESOURCE_MEM
685 + }
686 +};
687 +
688 +static struct platform_device nand_slot0 = {
689 + .id = 0,
690 + .name = "rb500-nand",
691 + .resource = nand_slot0_res,
692 + .num_resources = ARRAY_SIZE(nand_slot0_res),
693 +};
694 +
695 +
696 +static struct platform_device *rb500_devs[] = {
697 + &korina_dev0,
698 + &nand_slot0,
699 + &cf_slot0
700 +};
701 +
702 +static void __init parse_mac_addr(char* macstr)
703 +{
704 + int i, j;
705 + unsigned char result, value;
706 +
707 + for (i=0; i<6; i++) {
708 + result = 0;
709 + if (i != 5 && *(macstr+2) != ':') {
710 + return;
711 + }
712 + for (j=0; j<2; j++) {
713 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
714 + toupper(*macstr)-'A'+10) < 16) {
715 + result = result*16 + value;
716 + macstr++;
717 + }
718 + else return;
719 + }
720 +
721 + macstr++;
722 + korina_dev0_data.mac[i] = result;
723 + }
724 +}
725 +
726 +
727 +/* DEVICE CONTROLLER 1 */
728 +#define CFG_DC_DEV1 (void*)0xb8010010
729 +#define CFG_DC_DEV2 (void*)0xb8010020
730 +#define CFG_DC_DEVBASE 0x0
731 +#define CFG_DC_DEVMASK 0x4
732 +#define CFG_DC_DEVC 0x8
733 +#define CFG_DC_DEVTC 0xC
734 +
735 +
736 +static int __init plat_setup_devices(void)
737 +{
738 + /* Look for the CF card reader */
739 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
740 + rb500_devs[1] = NULL;
741 + else {
742 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
743 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
744 + }
745 +
746 + /* There is always a NAND device */
747 + nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
748 + nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
749 +
750 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
751 +}
752 +
753 +static int __init setup_kmac(char *s)
754 +{
755 + printk("korina mac = %s\n",s);
756 + parse_mac_addr(s);
757 + return 0;
758 +}
759 +
760 +__setup("kmac=", setup_kmac);
761 +arch_initcall(plat_setup_devices);
762 +
763 +
764 +#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
765 +extern void block2mtd_setup(char *initstr);
766 +extern void mount_devfs_fs(void);
767 +
768 +#endif
769 diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
770 --- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100
771 +++ linux.dev/arch/mips/rb500/early_serial.c 2006-10-11 21:56:38.000000000 +0200
772 @@ -0,0 +1,199 @@
773 +/**************************************************************************
774 + *
775 + * BRIEF MODULE DESCRIPTION
776 + * EB434 specific polling driver for 16550 UART.
777 + *
778 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
779 + *
780 + * This program is free software; you can redistribute it and/or modify it
781 + * under the terms of the GNU General Public License as published by the
782 + * Free Software Foundation; either version 2 of the License, or (at your
783 + * option) any later version.
784 + *
785 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
786 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
787 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
788 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
789 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
790 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
791 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
792 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
793 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
794 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
795 + *
796 + * You should have received a copy of the GNU General Public License along
797 + * with this program; if not, write to the Free Software Foundation, Inc.,
798 + * 675 Mass Ave, Cambridge, MA 02139, USA.
799 + *
800 + *
801 + **************************************************************************
802 + * Copyright (C) 2000 by Lineo, Inc.
803 + * Written by Quinn Jensen (jensenq@lineo.com)
804 + **************************************************************************
805 + * P. Sadik Oct 20, 2003
806 + *
807 + * DIVISOR is made a function of idt_cpu_freq
808 + **************************************************************************
809 + * P. Sadik Oct 30, 2003
810 + *
811 + * added reset_cons_port
812 + **************************************************************************
813 + */
814 +
815 +#include <linux/serial_reg.h>
816 +
817 +/* turn this on to watch the debug protocol echoed on the console port */
818 +#define DEBUG_REMOTE_DEBUG
819 +
820 +#define CONS_BAUD 115200
821 +
822 +extern unsigned int idt_cpu_freq;
823 +
824 +#define EXT_FREQ 24000000
825 +#define INT_FREQ idt_cpu_freq
826 +
827 +#define EXT_PORT 0xb9800000u
828 +#define EXT_SHIFT 0
829 +
830 +#ifdef __MIPSEB__
831 +#define INT_PORT 0xb8058003u
832 +#else
833 +#define INT_PORT 0xb8058000u
834 +#endif
835 +#define INT_SHIFT 2
836 +
837 +#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
838 +#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
839 +
840 +typedef struct
841 +{
842 + volatile unsigned char *base;
843 + unsigned int shift;
844 + unsigned int freq;
845 + unsigned int fcr;
846 +} ser_port;
847 +
848 +ser_port ports[2] =
849 +{
850 + { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
851 + { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
852 +};
853 +
854 +#define CONS_PORT 0
855 +
856 +void cons_putc(char c);
857 +int port_getc(int port);
858 +void port_putc(int port, char c);
859 +
860 +int cons_getc(void)
861 +{
862 + return port_getc(CONS_PORT);
863 +}
864 +
865 +void cons_putc(char c)
866 +{
867 + port_putc(CONS_PORT, c);
868 +}
869 +
870 +void cons_puts(char *s)
871 +{
872 + while(*s) {
873 + if(*s == '\n') cons_putc('\r');
874 + cons_putc(*s);
875 + s++;
876 + }
877 +}
878 +
879 +void cons_do_putn(int n)
880 +{
881 + if(n) {
882 + cons_do_putn(n / 10);
883 + cons_putc(n % 10 + '0');
884 + }
885 +}
886 +
887 +void cons_putn(int n)
888 +{
889 + if(n < 0) {
890 + cons_putc('-');
891 + n = -n;
892 + }
893 +
894 + if (n == 0) {
895 + cons_putc('0');
896 + } else {
897 + cons_do_putn(n);
898 + }
899 +}
900 +
901 +int port_getc(int p)
902 +{
903 + volatile unsigned char *port = ports[p].base;
904 + int s = ports[p].shift;
905 + int c;
906 +
907 + while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
908 + continue;
909 + }
910 +
911 + c = *(port + (UART_RX << s));
912 +
913 + return c;
914 +}
915 +
916 +int port_getc_ready(int p)
917 +{
918 + volatile unsigned char *port = ports[p].base;
919 + int s = ports[p].shift;
920 +
921 + return *(port + (UART_LSR << s)) & UART_LSR_DR;
922 +}
923 +
924 +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
925 +
926 +void port_putc(int p, char c)
927 +{
928 + volatile unsigned char *port = ports[p].base;
929 + int s = ports[p].shift;
930 + volatile unsigned char *lsr = port + (UART_LSR << s);
931 +
932 + while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
933 + continue;
934 + }
935 +
936 + *(port + (UART_TX << s)) = c;
937 +}
938 +
939 +void reset_cons_port(void)
940 +{
941 + volatile unsigned char *port = ports[CONS_PORT].base;
942 + unsigned int s = ports[CONS_PORT].shift;
943 + unsigned int DIVISOR;
944 +
945 + if (ports[CONS_PORT].freq)
946 + DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
947 + else
948 + DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
949 +
950 + /* reset the port */
951 + *(port + (UART_CSR << s)) = 0;
952 +
953 + /* clear and enable the FIFOs */
954 + *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
955 +
956 + /* set the baud rate */
957 + *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */
958 +
959 + *(port + (UART_DLL << s)) = DIVISOR;
960 + *(port + (UART_DLM << s)) = DIVISOR >> 8;
961 + /* set the line control stuff and disable DLL, DLM regs */
962 +
963 + *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */
964 + UART_LCR_WLEN8; /* 8 bit word length */
965 +
966 + /* leave interrupts off */
967 + *(port + (UART_IER << s)) = 0;
968 +
969 + /* the modem controls don't leave the chip on this port, so leave them alone */
970 + *(port + (UART_MCR << s)) = 0;
971 +}
972 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
973 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
974 +++ linux.dev/arch/mips/rb500/irq.c 2006-10-11 21:56:38.000000000 +0200
975 @@ -0,0 +1,264 @@
976 +/*
977 + * BRIEF MODULE DESCRIPTION
978 + * RC32434 interrupt routines.
979 + *
980 + * Copyright 2002 MontaVista Software Inc.
981 + * Author: MontaVista Software, Inc.
982 + * stevel@mvista.com or source@mvista.com
983 + *
984 + * This program is free software; you can redistribute it and/or modify it
985 + * under the terms of the GNU General Public License as published by the
986 + * Free Software Foundation; either version 2 of the License, or (at your
987 + * option) any later version.
988 + *
989 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
990 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
991 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
992 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
993 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
994 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
995 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
996 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
997 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
998 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
999 + *
1000 + * You should have received a copy of the GNU General Public License along
1001 + * with this program; if not, write to the Free Software Foundation, Inc.,
1002 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1003 + */
1004 +
1005 +#include <linux/errno.h>
1006 +#include <linux/init.h>
1007 +#include <linux/kernel_stat.h>
1008 +#include <linux/module.h>
1009 +#include <linux/signal.h>
1010 +#include <linux/sched.h>
1011 +#include <linux/types.h>
1012 +#include <linux/interrupt.h>
1013 +#include <linux/ioport.h>
1014 +#include <linux/timex.h>
1015 +#include <linux/slab.h>
1016 +#include <linux/random.h>
1017 +#include <linux/delay.h>
1018 +
1019 +#include <asm/bitops.h>
1020 +#include <asm/bootinfo.h>
1021 +#include <asm/io.h>
1022 +#include <asm/irq.h>
1023 +#include <asm/time.h>
1024 +#include <asm/mipsregs.h>
1025 +#include <asm/system.h>
1026 +#include <asm/rc32434/rc32434.h>
1027 +#include <asm/rc32434/gpio.h>
1028 +
1029 +extern void set_debug_traps(void);
1030 +extern irq_cpustat_t irq_stat [NR_CPUS];
1031 +unsigned int local_bh_count[NR_CPUS];
1032 +unsigned int local_irq_count[NR_CPUS];
1033 +
1034 +static unsigned int startup_irq(unsigned int irq);
1035 +static void rb500_end_irq(unsigned int irq_nr);
1036 +static void mask_and_ack_irq(unsigned int irq_nr);
1037 +static void rb500_enable_irq(unsigned int irq_nr);
1038 +static void rb500_disable_irq(unsigned int irq_nr);
1039 +
1040 +extern void __init init_generic_irq(void);
1041 +
1042 +typedef struct {
1043 + u32 mask; /* mask of valid bits in pending/mask registers */
1044 + volatile u32 *base_addr;
1045 +} intr_group_t;
1046 +
1047 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
1048 +
1049 +#if (NR_IRQS < RC32434_NR_IRQS)
1050 +#error Too little irqs defined. Did you override <asm/irq.h> ?
1051 +#endif
1052 +
1053 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
1054 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
1055 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
1056 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
1057 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
1058 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
1059 +};
1060 +
1061 +#define READ_PEND(base) (*(base))
1062 +#define READ_MASK(base) (*(base + 2))
1063 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
1064 +
1065 +static inline int irq_to_group(unsigned int irq_nr)
1066 +{
1067 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
1068 +}
1069 +
1070 +static inline int group_to_ip(unsigned int group)
1071 +{
1072 + return group + 2;
1073 +}
1074 +
1075 +static inline void enable_local_irq(unsigned int ip)
1076 +{
1077 + int ipnum = 0x100 << ip;
1078 + clear_c0_cause(ipnum);
1079 + set_c0_status(ipnum);
1080 +}
1081 +
1082 +static inline void disable_local_irq(unsigned int ip)
1083 +{
1084 + int ipnum = 0x100 << ip;
1085 + clear_c0_status(ipnum);
1086 +}
1087 +
1088 +static inline void ack_local_irq(unsigned int ip)
1089 +{
1090 + int ipnum = 0x100 << ip;
1091 + clear_c0_cause(ipnum);
1092 +}
1093 +
1094 +static void rb500_enable_irq(unsigned int irq_nr)
1095 +{
1096 + int ip = irq_nr - GROUP0_IRQ_BASE;
1097 + unsigned int group, intr_bit;
1098 + volatile unsigned int *addr;
1099 +
1100 +
1101 + if (ip < 0)
1102 + enable_local_irq(irq_nr);
1103 + else {
1104 + group = ip >> 5;
1105 +
1106 + ip &= (1<<5)-1;
1107 + intr_bit = 1 << ip;
1108 +
1109 + enable_local_irq(group_to_ip(group));
1110 +
1111 + addr = intr_group[group].base_addr;
1112 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1113 + }
1114 +}
1115 +
1116 +static void rb500_disable_irq(unsigned int irq_nr)
1117 +{
1118 + int ip = irq_nr - GROUP0_IRQ_BASE;
1119 + unsigned int group, intr_bit, mask;
1120 + volatile unsigned int *addr;
1121 +
1122 + if (ip < 0) {
1123 + disable_local_irq(irq_nr);
1124 + }else{
1125 + group = ip >> 5;
1126 +
1127 + ip &= (1<<5) -1;
1128 + intr_bit = 1 << ip;
1129 + addr = intr_group[group].base_addr;
1130 + mask = READ_MASK(addr);
1131 + mask |= intr_bit;
1132 + WRITE_MASK(addr,mask);
1133 +
1134 + /*
1135 + * if there are no more interrupts enabled in this
1136 + * group, disable corresponding IP
1137 + */
1138 + if (mask == intr_group[group].mask)
1139 + disable_local_irq(group_to_ip(group));
1140 + }
1141 +}
1142 +
1143 +static unsigned int startup_irq(unsigned int irq_nr)
1144 +{
1145 + rb500_enable_irq(irq_nr);
1146 + return 0;
1147 +}
1148 +
1149 +static void shutdown_irq(unsigned int irq_nr)
1150 +{
1151 + rb500_disable_irq(irq_nr);
1152 + return;
1153 +}
1154 +
1155 +static void mask_and_ack_irq(unsigned int irq_nr)
1156 +{
1157 + rb500_disable_irq(irq_nr);
1158 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
1159 +}
1160 +
1161 +static void rb500_end_irq(unsigned int irq_nr)
1162 +{
1163 +
1164 + int ip = irq_nr - GROUP0_IRQ_BASE;
1165 + unsigned int intr_bit, group;
1166 + volatile unsigned int *addr;
1167 +
1168 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1169 + printk("warning: end_irq %d did not enable (%x)\n",
1170 + irq_nr, irq_desc[irq_nr].status);
1171 + return;
1172 + }
1173 +
1174 + if (ip < 0) {
1175 + enable_local_irq(irq_nr);
1176 + } else {
1177 + group = ip >> 5;
1178 +
1179 + ip &= (1 << 5) - 1;
1180 + intr_bit = 1 << ip;
1181 +
1182 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1183 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1184 + }
1185 +
1186 + enable_local_irq(group_to_ip(group));
1187 +
1188 + addr = intr_group[group].base_addr;
1189 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1190 + }
1191 +}
1192 +
1193 +static struct hw_interrupt_type rc32434_irq_type = {
1194 + .typename = "RB500",
1195 + .startup = startup_irq,
1196 + .shutdown = shutdown_irq,
1197 + .enable = rb500_enable_irq,
1198 + .disable = rb500_disable_irq,
1199 + .ack = mask_and_ack_irq,
1200 + .end = rb500_end_irq,
1201 +};
1202 +
1203 +
1204 +void __init arch_init_irq(void)
1205 +{
1206 + int i;
1207 +
1208 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1209 + memset(irq_desc, 0, sizeof(irq_desc));
1210 +
1211 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1212 + irq_desc[i].status = IRQ_DISABLED;
1213 + irq_desc[i].action = NULL;
1214 + irq_desc[i].depth = 1;
1215 + irq_desc[i].handler = &rc32434_irq_type;
1216 + spin_lock_init(&irq_desc[i].lock);
1217 + }
1218 +}
1219 +
1220 +/* Main Interrupt dispatcher */
1221 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1222 +{
1223 + unsigned int ip, pend, group;
1224 + volatile unsigned int *addr;
1225 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1226 +
1227 + if (cp0_cause & CAUSEF_IP7) {
1228 + ll_timer_interrupt(7, regs);
1229 + } else if ((ip = (cp0_cause & 0x7c00))) {
1230 + group = 21 - rc32434_clz(ip);
1231 +
1232 + addr = intr_group[group].base_addr;
1233 +
1234 + pend = READ_PEND(addr);
1235 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1236 + pend = 39 - rc32434_clz(pend);
1237 + do_IRQ((group << 5) + pend, regs);
1238 + }
1239 +}
1240 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1241 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1242 +++ linux.dev/arch/mips/rb500/Makefile 2006-10-11 21:56:38.000000000 +0200
1243 @@ -0,0 +1,5 @@
1244 +#
1245 +# Makefile for the RB500 board specific parts of the kernel
1246 +#
1247 +
1248 +obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o
1249 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1250 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1251 +++ linux.dev/arch/mips/rb500/misc.c 2006-10-11 21:56:38.000000000 +0200
1252 @@ -0,0 +1,56 @@
1253 +#include <linux/module.h>
1254 +#include <linux/kernel.h> /* printk() */
1255 +#include <linux/types.h> /* size_t */
1256 +#include <linux/pci.h>
1257 +#include <linux/spinlock.h>
1258 +#include <asm/rc32434/rb.h>
1259 +
1260 +#define GPIO_BADDR 0xb8050000
1261 +
1262 +
1263 +static volatile unsigned char *devCtl3Base = 0;
1264 +static unsigned char latchU5State = 0;
1265 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1266 +
1267 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1268 + unsigned flags, data;
1269 + unsigned i = 0;
1270 + spin_lock_irqsave(&clu5Lock, flags);
1271 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1272 + for (i = 0; i != len; ++i) {
1273 + if (val & (1 << i)) data |= (1 << (i + bit));
1274 + else data &= ~(1 << (i + bit));
1275 + }
1276 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1277 + spin_unlock_irqrestore(&clu5Lock, flags);
1278 +}
1279 +
1280 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1281 + unsigned flags;
1282 + spin_lock_irqsave(&clu5Lock, flags);
1283 + latchU5State = (latchU5State | orMask) & ~nandMask;
1284 + if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
1285 + KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
1286 + *devCtl3Base = latchU5State;
1287 + spin_unlock_irqrestore(&clu5Lock, flags);
1288 +}
1289 +
1290 +u32 gpio_get(gpio_func func)
1291 +{
1292 + return readl((void *) GPIO_BADDR + func);
1293 +}
1294 +
1295 +void gpio_set(gpio_func func, u32 mask, u32 value)
1296 +{
1297 + u32 val = readl((void *) GPIO_BADDR + func);
1298 +
1299 + val &= ~mask;
1300 + val |= value & mask;
1301 +
1302 + writel(val, (void *) GPIO_BADDR + func);
1303 +}
1304 +
1305 +EXPORT_SYMBOL(gpio_set);
1306 +EXPORT_SYMBOL(gpio_get);
1307 +EXPORT_SYMBOL(set434Reg);
1308 +EXPORT_SYMBOL(changeLatchU5);
1309 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1310 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1311 +++ linux.dev/arch/mips/rb500/prom.c 2006-10-11 21:56:38.000000000 +0200
1312 @@ -0,0 +1,181 @@
1313 +/*
1314 +* prom.c
1315 +**********************************************************************
1316 +* P . Sadik Oct 10, 2003
1317 +*
1318 +* Started change log
1319 +* idt_cpu_freq is make a kernel configuration parameter
1320 +* idt_cpu_freq is exported so that other modules can use it.
1321 +* Code cleanup
1322 +**********************************************************************
1323 +* P. Sadik Oct 20, 2003
1324 +*
1325 +* Removed NVRAM code from here, since they are already available under
1326 +* nvram directory.
1327 +* Added serial port initialisation.
1328 +**********************************************************************
1329 +**********************************************************************
1330 +* P. Sadik Oct 30, 2003
1331 +*
1332 +* Added reset_cons_port
1333 +**********************************************************************
1334 +
1335 + P.Christeas, 2005-2006
1336 + Port to 2.6, add 2.6 cmdline parsing
1337 +
1338 +*/
1339 +
1340 +#include <linux/config.h>
1341 +#include <linux/init.h>
1342 +#include <linux/mm.h>
1343 +#include <linux/module.h>
1344 +#include <linux/string.h>
1345 +#include <linux/console.h>
1346 +#include <asm/bootinfo.h>
1347 +#include <linux/bootmem.h>
1348 +#include <linux/ioport.h>
1349 +#include <linux/blkdev.h>
1350 +#include <asm/rc32434/ddr.h>
1351 +
1352 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1353 +extern void __init setup_serial_port(void);
1354 +extern void cons_putc(char c);
1355 +extern void cons_puts(char *s);
1356 +
1357 +unsigned int idt_cpu_freq = 132000000;
1358 +EXPORT_SYMBOL(idt_cpu_freq);
1359 +unsigned int board_type = 500;
1360 +EXPORT_SYMBOL(board_type);
1361 +unsigned int gpio_bootup_state = 0;
1362 +EXPORT_SYMBOL(gpio_bootup_state);
1363 +
1364 +
1365 +char mips_mac_address[18] = "08:00:06:05:40:01";
1366 +EXPORT_SYMBOL(mips_mac_address);
1367 +
1368 +/* what to append to cmdline when button is [not] pressed */
1369 +#define GPIO_INIT_NOBUTTON ""
1370 +#define GPIO_INIT_BUTTON " 2"
1371 +
1372 +#ifdef CONFIG_MIKROTIK_RB500
1373 +unsigned soft_reboot = 0;
1374 +EXPORT_SYMBOL(soft_reboot);
1375 +#endif
1376 +
1377 +#define SR_NMI 0x00180000 /* NMI */
1378 +#define SERIAL_SPEED_ENTRY 0x00000001
1379 +
1380 +#ifdef CONFIG_REMOTE_DEBUG
1381 +extern int remote_debug;
1382 +#endif
1383 +
1384 +extern unsigned long mips_machgroup;
1385 +extern unsigned long mips_machtype;
1386 +
1387 +#define FREQ_TAG "HZ="
1388 +#define GPIO_TAG "gpio="
1389 +#define KMAC_TAG "kmac="
1390 +#define MEM_TAG "mem="
1391 +#define BOARD_TAG "board="
1392 +#define IGNORE_CMDLINE_MEM 1
1393 +#define DEBUG_DDR
1394 +
1395 +void parse_soft_settings(unsigned *ptr, unsigned size);
1396 +void parse_hard_settings(unsigned *ptr, unsigned size);
1397 +
1398 +void __init prom_setup_cmdline(void);
1399 +
1400 +#ifdef DEBUG_DDR
1401 +void cons_puthex4(u32 h){
1402 + h&=0x0f;
1403 + if (h>=10)
1404 + cons_putc((h-10)+'a');
1405 + else
1406 + cons_putc(h+'0');
1407 +}
1408 +
1409 +void cons_putreg32(u32 reg){
1410 + char c;
1411 + cons_putc('0');
1412 + cons_putc('x');
1413 + for (c=28;c>=0;c-=4)
1414 + cons_puthex4(reg>>c);
1415 +}
1416 +#endif
1417 +
1418 +void __init prom_init(void)
1419 +{
1420 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1421 + phys_t memsize = 0-ddr->ddrmask;
1422 +
1423 + /* this should be the very first message, even before serial is properly initialized */
1424 + prom_setup_cmdline();
1425 + setup_serial_port();
1426 +
1427 + mips_machgroup = MACH_GROUP_MIKROTIK;
1428 + soft_reboot = read_c0_status() & SR_NMI;
1429 + pm_power_off = NULL;
1430 +
1431 + /*
1432 + * give all RAM to boot allocator,
1433 + * except for the first 0x400 and the last 0x200 bytes
1434 + */
1435 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1436 +}
1437 +
1438 +void prom_free_prom_memory(void)
1439 +{
1440 + /* FIXME: STUB */
1441 +}
1442 +
1443 +void __init prom_setup_cmdline(void){
1444 + char cmd_line[CL_SIZE];
1445 + char *cp;
1446 + int prom_argc;
1447 + char **prom_argv, **prom_envp;
1448 + int i;
1449 +
1450 + prom_argc = fw_arg0;
1451 + prom_argv = (char **) fw_arg1;
1452 + prom_envp = (char **) fw_arg2;
1453 +
1454 + cp=cmd_line;
1455 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1456 + however, our elf loader starts at [0] */
1457 + for(i=0;i<prom_argc;i++){
1458 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1459 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1460 + continue;
1461 + }
1462 +#ifdef IGNORE_CMDLINE_MEM
1463 + /* parses out the "mem=xx" arg */
1464 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1465 + continue;
1466 + }
1467 +#endif
1468 + if (i>0) *(cp++) = ' ';
1469 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1470 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1471 + }
1472 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1473 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1474 + }
1475 + strcpy(cp,prom_argv[i]);
1476 + cp+=strlen(prom_argv[i]);
1477 + }
1478 +
1479 + i=strlen(arcs_cmdline);
1480 + if (i>0){
1481 + *(cp++) = ' ';
1482 + strcpy(cp,arcs_cmdline);
1483 + cp+=strlen(arcs_cmdline);
1484 + }
1485 + if (gpio_bootup_state&0x02)
1486 + strcpy(cp,GPIO_INIT_NOBUTTON);
1487 + else
1488 + strcpy(cp,GPIO_INIT_BUTTON);
1489 + cmd_line[CL_SIZE-1] = '\0';
1490 +
1491 + strcpy(arcs_cmdline,cmd_line);
1492 +}
1493 +
1494 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1495 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1496 +++ linux.dev/arch/mips/rb500/serial.c 2006-10-11 21:56:38.000000000 +0200
1497 @@ -0,0 +1,79 @@
1498 +/**************************************************************************
1499 + *
1500 + * BRIEF MODULE DESCRIPTION
1501 + * Serial port initialisation.
1502 + *
1503 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1504 + *
1505 + * This program is free software; you can redistribute it and/or modify it
1506 + * under the terms of the GNU General Public License as published by the
1507 + * Free Software Foundation; either version 2 of the License, or (at your
1508 + * option) any later version.
1509 + *
1510 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1511 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1512 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1513 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1514 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1515 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1516 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1517 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1518 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1519 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1520 + *
1521 + * You should have received a copy of the GNU General Public License along
1522 + * with this program; if not, write to the Free Software Foundation, Inc.,
1523 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1524 + *
1525 + *
1526 + **************************************************************************
1527 + * May 2004 rkt, neb
1528 + *
1529 + * Initial Release
1530 + *
1531 + *
1532 + *
1533 + **************************************************************************
1534 + */
1535 +
1536 +
1537 +#include <linux/config.h>
1538 +#include <linux/init.h>
1539 +#include <linux/sched.h>
1540 +#include <linux/pci.h>
1541 +#include <linux/interrupt.h>
1542 +#include <linux/tty.h>
1543 +#include <linux/serial.h>
1544 +#include <linux/serial_core.h>
1545 +
1546 +#include <asm/time.h>
1547 +#include <asm/cpu.h>
1548 +#include <asm/bootinfo.h>
1549 +#include <asm/irq.h>
1550 +#include <asm/serial.h>
1551 +#include <asm/rc32434/rc32434.h>
1552 +
1553 +extern unsigned int idt_cpu_freq;
1554 +
1555 +static struct uart_port serial_req = {
1556 + .type = PORT_16550A,
1557 + .line = 0,
1558 + .irq = RC32434_UART0_IRQ,
1559 + .flags = STD_COM_FLAGS,
1560 + .iotype = UPIO_MEM,
1561 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1562 +// .fifosize = 14
1563 + .regshift = 2
1564 +};
1565 +
1566 +int __init setup_serial_port(void)
1567 +{
1568 + serial_req.uartclk = idt_cpu_freq;
1569 +
1570 + if (early_serial_setup(&serial_req)){
1571 + cons_puts("Serial setup failed!\n");
1572 + return -ENODEV;
1573 + }
1574 +
1575 + return(0);
1576 +}
1577 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1578 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1579 +++ linux.dev/arch/mips/rb500/setup.c 2006-10-11 21:56:38.000000000 +0200
1580 @@ -0,0 +1,84 @@
1581 +/*
1582 + * setup.c - boot time setup code
1583 + */
1584 +
1585 +#include <linux/init.h>
1586 +#include <linux/mm.h>
1587 +#include <linux/sched.h>
1588 +#include <linux/irq.h>
1589 +#include <asm/bootinfo.h>
1590 +#include <asm/io.h>
1591 +#include <linux/ioport.h>
1592 +#include <asm/mipsregs.h>
1593 +#include <asm/pgtable.h>
1594 +#include <asm/reboot.h>
1595 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1596 +#include <asm/rc32434/rc32434.h>
1597 +#include <linux/pm.h>
1598 +#include <asm/rc32434/pci.h>
1599 +
1600 +extern void (*board_time_init)(void);
1601 +extern void (*board_timer_setup)(struct irqaction *irq);
1602 +extern void rc32434_time_init(void);
1603 +extern void rc32434_timer_setup(struct irqaction *irq);
1604 +#ifdef CONFIG_PCI
1605 +extern int __init rc32434_pcibridge_init(void);
1606 +#endif
1607 +
1608 +#define epldMask ((volatile unsigned char *)0xB900000d)
1609 +
1610 +static void rb_machine_restart(char *command)
1611 +{
1612 + /* just jump to the reset vector */
1613 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1614 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1615 +}
1616 +
1617 +static void rb_machine_halt(void)
1618 +{
1619 + for(;;) continue;
1620 +}
1621 +
1622 +#ifdef CONFIG_CPU_HAS_WB
1623 +void (*__wbflush) (void);
1624 +
1625 +static void rb_write_buffer_flush(void)
1626 +{
1627 + __asm__ __volatile__
1628 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1629 +}
1630 +#endif
1631 +
1632 +void __init plat_setup(void)
1633 +{
1634 + unsigned int pciCntlVal;
1635 +
1636 + board_time_init = rc32434_time_init;
1637 + board_timer_setup = rc32434_timer_setup;
1638 +
1639 +#ifdef CONFIG_CPU_HAS_WB
1640 + __wbflush = rb_write_buffer_flush;
1641 +#endif
1642 + _machine_restart = rb_machine_restart;
1643 + _machine_halt = rb_machine_halt;
1644 + /*_machine_power_off = rb_machine_power_halt;*/
1645 + pm_power_off = rb_machine_halt;
1646 +
1647 + set_io_port_base(KSEG1);
1648 +
1649 + pciCntlVal=rc32434_pci->pcic;
1650 + pciCntlVal &= 0xFFFFFF7;
1651 + rc32434_pci->pcic = pciCntlVal;
1652 +
1653 +#ifdef CONFIG_PCI
1654 + /* Enable PCI interrupts in EPLD Mask register */
1655 + *epldMask = 0x0;
1656 + *(epldMask + 1) = 0x0;
1657 +#endif
1658 + write_c0_wired(0);
1659 +}
1660 +
1661 +const char *get_system_type(void)
1662 +{
1663 + return "MIPS RB500";
1664 +}
1665 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1666 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1667 +++ linux.dev/arch/mips/rb500/time.c 2006-10-11 21:56:38.000000000 +0200
1668 @@ -0,0 +1,94 @@
1669 +/*
1670 +****************************************************************************
1671 +* Carsten Langgaard, carstenl@mips.com
1672 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1673 +*
1674 +***************************************************************************
1675 +*
1676 +* This program is free software; you can distribute it and/or modify it
1677 +* under the terms of the GNU General Public License (Version 2) as
1678 +* published by the Free Software Foundation.
1679 +*
1680 +* This program is distributed in the hope it will be useful, but WITHOUT
1681 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1682 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1683 +* for more details.
1684 +*
1685 +* You should have received a copy of the GNU General Public License along
1686 +* with this program; if not, write to the Free Software Foundation, Inc.,
1687 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1688 +*
1689 +****************************************************************************
1690 +*
1691 +* Setting up the clock on the MIPS boards.
1692 +*
1693 +****************************************************************************
1694 +* P. Sadik Oct 10, 2003
1695 +*
1696 +* Started change log.
1697 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1698 +* Code cleanup
1699 +****************************************************************************
1700 +*/
1701 +
1702 +#include <linux/config.h>
1703 +#include <linux/init.h>
1704 +#include <linux/kernel_stat.h>
1705 +#include <linux/sched.h>
1706 +#include <linux/spinlock.h>
1707 +#include <linux/mc146818rtc.h>
1708 +#include <linux/irq.h>
1709 +#include <linux/timex.h>
1710 +
1711 +#include <asm/mipsregs.h>
1712 +#include <asm/ptrace.h>
1713 +#include <asm/debug.h>
1714 +#include <asm/rc32434/rc32434.h>
1715 +
1716 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1717 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1718 +extern void ll_timer_interrupt(int irq, struct pt_regs *regs);
1719 +extern unsigned int mips_hpt_frequency;
1720 +extern unsigned int idt_cpu_freq;
1721 +
1722 +/*
1723 + * Figure out the r4k offset, the amount to increment the compare
1724 + * register for each time tick. There is no RTC available.
1725 + *
1726 + * The RC32434 counts at half the CPU *core* speed.
1727 + */
1728 +static unsigned long __init cal_r4koff(void)
1729 +{
1730 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1731 + return (mips_hpt_frequency / HZ);
1732 +}
1733 +
1734 +
1735 +void __init rc32434_time_init(void)
1736 +{
1737 + unsigned int est_freq, flags;
1738 +
1739 + local_irq_save(flags);
1740 +
1741 + printk("calculating r4koff... ");
1742 + r4k_offset = cal_r4koff();
1743 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1744 +
1745 + est_freq = 2*r4k_offset*HZ;
1746 + est_freq += 5000; /* round */
1747 + est_freq -= est_freq%10000;
1748 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1749 + (est_freq%1000000)*100/1000000);
1750 + local_irq_restore(flags);
1751 +}
1752 +
1753 +void __init rc32434_timer_setup(struct irqaction *irq)
1754 +{
1755 + /* we are using the cpu counter for timer interrupts */
1756 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1757 +
1758 + /* to generate the first timer interrupt */
1759 + r4k_cur = (read_c0_count() + r4k_offset);
1760 + write_c0_compare(r4k_cur);
1761 +}
1762 +
1763 diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
1764 --- linux.old/drivers/mtd/devices/block2mtd.c 2006-10-11 21:55:59.000000000 +0200
1765 +++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-10-11 22:24:51.000000000 +0200
1766 @@ -26,7 +26,6 @@
1767 #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
1768 #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
1769
1770 -
1771 /* Info for the block device */
1772 struct block2mtd_dev {
1773 struct list_head list;
1774 @@ -104,7 +103,7 @@
1775
1776 while (pages) {
1777 page = page_readahead(mapping, index);
1778 - if (!page)
1779 + if (!page || !page_address(page))
1780 return -ENOMEM;
1781 if (IS_ERR(page))
1782 return PTR_ERR(page);
1783 @@ -285,7 +284,7 @@
1784
1785
1786 /* FIXME: ensure that mtd->size % erase_size == 0 */
1787 -static struct block2mtd_dev *add_device(char *devname, int erase_size)
1788 +static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
1789 {
1790 struct block_device *bdev;
1791 struct block2mtd_dev *dev;
1792 @@ -328,14 +327,15 @@
1793
1794 /* Setup the MTD structure */
1795 /* make the name contain the block device in */
1796 - dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
1797 + dev->mtd.name = kmalloc(strlen((alias ?: devname)),
1798 GFP_KERNEL);
1799 if (!dev->mtd.name)
1800 goto devinit_err;
1801
1802 - sprintf(dev->mtd.name, "block2mtd: %s", devname);
1803 + strcpy(dev->mtd.name, (alias ?: devname));
1804
1805 dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
1806 + dev->mtd.size -= dev->mtd.size % erase_size;
1807 dev->mtd.erasesize = erase_size;
1808 dev->mtd.type = MTD_RAM;
1809 dev->mtd.flags = MTD_CAP_RAM;
1810 @@ -353,7 +353,7 @@
1811 }
1812 list_add(&dev->list, &blkmtd_device_list);
1813 INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
1814 - dev->mtd.name + strlen("blkmtd: "),
1815 + dev->mtd.name,
1816 dev->mtd.erasesize >> 10, dev->mtd.erasesize);
1817 return dev;
1818
1819 @@ -429,7 +429,7 @@
1820 {
1821 char buf[80 + 12]; /* 80 for device, 12 for erase size */
1822 char *str = buf;
1823 - char *token[2];
1824 + char *token[3];
1825 char *name;
1826 size_t erase_size = PAGE_SIZE;
1827 int i, ret;
1828 @@ -440,7 +440,7 @@
1829 strcpy(str, val);
1830 kill_final_newline(str);
1831
1832 - for (i = 0; i < 2; i++)
1833 + for (i = 0; i < 3; i++)
1834 token[i] = strsep(&str, ",");
1835
1836 if (str)
1837 @@ -461,13 +461,13 @@
1838 }
1839 }
1840
1841 - add_device(name, erase_size);
1842 + add_device(name, erase_size, token[2]);
1843
1844 return 0;
1845 }
1846
1847
1848 -static int block2mtd_setup(const char *val, struct kernel_param *kp)
1849 +int block2mtd_setup(const char *val, struct kernel_param *kp)
1850 {
1851 #ifdef MODULE
1852 return block2mtd_setup2(val);
1853 @@ -496,6 +496,7 @@
1854
1855 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
1856 MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
1857 +EXPORT_SYMBOL(block2mtd_setup);
1858
1859 static int __init block2mtd_init(void)
1860 {
1861 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1862 --- linux.old/drivers/pci/Makefile 2006-06-18 03:49:35.000000000 +0200
1863 +++ linux.dev/drivers/pci/Makefile 2006-10-11 21:56:38.000000000 +0200
1864 @@ -27,6 +27,7 @@
1865 obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
1866 obj-$(CONFIG_X86_VISWS) += setup-irq.o
1867 obj-$(CONFIG_PCI_MSI) += msi.o
1868 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1869
1870 #
1871 # ACPI Related PCI FW Functions
1872 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1873 --- linux.old/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
1874 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-11 21:56:38.000000000 +0200
1875 @@ -218,6 +218,8 @@
1876 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
1877 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
1878
1879 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1880 +
1881 #define CL_SIZE COMMAND_LINE_SIZE
1882
1883 const char *get_system_type(void);
1884 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1885 --- linux.old/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
1886 +++ linux.dev/include/asm-mips/cpu.h 2006-10-11 21:56:38.000000000 +0200
1887 @@ -200,7 +200,8 @@
1888 #define CPU_SB1A 62
1889 #define CPU_74K 63
1890 #define CPU_R14000 64
1891 -#define CPU_LAST 64
1892 +#define CPU_RC32300 65
1893 +#define CPU_LAST 65
1894
1895 /*
1896 * ISA Level encodings
1897 diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
1898 --- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100
1899 +++ linux.dev/include/asm-mips/rc32434/crom.h 2006-10-11 21:56:38.000000000 +0200
1900 @@ -0,0 +1,98 @@
1901 +#ifndef __IDT_CROM_H__
1902 +#define __IDT_CROM_H__
1903 +
1904 +/*******************************************************************************
1905 + *
1906 + * Copyright 2002 Integrated Device Technology, Inc.
1907 + * All rights reserved.
1908 + *
1909 + * Configuration ROM register definitions.
1910 + *
1911 + * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1912 + *
1913 + * Author : Allen.Stichter@idt.com
1914 + * Date : 20020118
1915 + * Update :
1916 + * $Log: crom.h,v $
1917 + * Revision 1.2 2002/06/06 18:34:03 astichte
1918 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1919 + *
1920 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1921 + * jba File moved from vcode/include/idt/acacia
1922 + *
1923 + *
1924 + ******************************************************************************/
1925 +
1926 +#include <asm/rc32434/types.h>
1927 +
1928 +enum
1929 +{
1930 + CROM0_PhysicalAddress = 0x100b8000,
1931 + CROM_PhysicalAddress = CROM0_PhysicalAddress,
1932 +
1933 + CROM0_VirtualAddress = 0xb00b8000,
1934 + CROM_VirtualAddress = CROM0_VirtualAddress,
1935 +} ;
1936 +
1937 +typedef struct CROM_s
1938 +{
1939 + U32 cromw0 ; // use CROMW0_
1940 + U32 cromw1 ; // use CROMW1_
1941 + U32 cromw2 ; // use CROMW2_
1942 +} volatile * CROM_t ;
1943 +
1944 +enum
1945 +{
1946 + CROMW0_xloc_b = 0,
1947 + CROMW0_xloc_m = 0x0000003f,
1948 + CROMW0_yloc_b = 8,
1949 + CROMW0_yloc_m = 0x00003f00,
1950 + CROMW0_speed_b = 16,
1951 + CROMW0_speed_m = 0x01ff0000,
1952 + CROMW1_wafer_b = 0,
1953 + CROMW1_wafer_m = 0x0000001f,
1954 + CROMW1_lot_b = 8,
1955 + CROMW1_lot_m = 0x0fffff00,
1956 + CROMW1_fab_b = 28,
1957 + CROMW1_fab_m = 0xf0000000,
1958 + CROMW2_pci_b = 0,
1959 + CROMW2_pci_m = 0x00000001,
1960 + CROMW2_eth0_b = 1,
1961 + CROMW2_eth0_m = 0x00000002,
1962 + CROMW2_eth1_b = 2,
1963 + CROMW2_eth1_m = 0x00000004
1964 + CROMW2_i2c_b = 3,
1965 + CROMW2_i2c_m = 0x00000008,
1966 + CROMW2_rng_b = 4,
1967 + CROMW2_rng_m = 0x00000010,
1968 + CROMW2_se_b = 5,
1969 + CROMW2_se_m = 0x00000020,
1970 + CROMW2_des_b = 6,
1971 + CROMW2_des_m = 0x00000040,
1972 + CROMW2_tdes_b = 7,
1973 + CROMW2_tdes_m = 0x00000080,
1974 + CROMW2_a128_b = 8,
1975 + CROMW2_a128_m = 0x00000100,
1976 + CROMW2_a192_b = 9,
1977 + CROMW2_a192_m = 0x00000200,
1978 + CROMW2_a256_b = 10,
1979 + CROMW2_a256_m = 0x00000400,
1980 + CROMW2_md5_b = 11,
1981 + CROMW2_md5_m = 0x00000800,
1982 + CROMW2_s1_b = 12,
1983 + CROMW2_s1_m = 0x00001000,
1984 + CROMW2_s256_b = 13,
1985 + CROMW2_s256_m = 0x00002000,
1986 + CROMW2_pka_b = 14,
1987 + CROMW2_pka_m = 0x00004000,
1988 + CROMW2_exp_b = 15,
1989 + CROMW2_exp_m = 0x00018000,
1990 + CROMW2_exp_8192_v = 0,
1991 + CROMW2_exp_1536_v = 1,
1992 + CROMW2_exp_1024_v = 2,
1993 + CROMW2_exp_512_v = 3,
1994 + CROMW2_rocfg_b = 17,
1995 + CROMW2_rocfg_m = 0x000e0000,
1996 +} ;
1997 +
1998 +#endif // __IDT_CROM_H__
1999 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
2000 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
2001 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-10-11 21:56:38.000000000 +0200
2002 @@ -0,0 +1,175 @@
2003 +#ifndef __IDT_DDR_H__
2004 +#define __IDT_DDR_H__
2005 +
2006 +/*******************************************************************************
2007 + *
2008 + * Copyright 2002 Integrated Device Technology, Inc.
2009 + * All rights reserved.
2010 + *
2011 + * DDR register definition.
2012 + *
2013 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2014 + *
2015 + * Author : ryan.holmQVist@idt.com
2016 + * Date : 20011005
2017 + * Update :
2018 + * $Log: ddr.h,v $
2019 + * Revision 1.2 2002/06/06 18:34:03 astichte
2020 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2021 + *
2022 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2023 + * jba File moved from vcode/include/idt/acacia
2024 + *
2025 + *
2026 + ******************************************************************************/
2027 +
2028 +#include <asm/rc32434/types.h>
2029 +
2030 +enum
2031 +{
2032 + DDR0_PhysicalAddress = 0x18018000,
2033 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
2034 +
2035 + DDR0_VirtualAddress = 0xb8018000,
2036 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
2037 +} ;
2038 +
2039 +typedef struct DDR_s
2040 +{
2041 + U32 ddrbase ;
2042 + U32 ddrmask ;
2043 + U32 res1;
2044 + U32 res2;
2045 + U32 ddrc ;
2046 + U32 ddrabase ;
2047 + U32 ddramask ;
2048 + U32 ddramap ;
2049 + U32 ddrcust;
2050 + U32 ddrrdc;
2051 + U32 ddrspare;
2052 +} volatile *DDR_t ;
2053 +
2054 +enum
2055 +{
2056 + DDR0BASE_baseaddr_b = 16,
2057 + DDR0BASE_baseaddr_m = 0xffff0000,
2058 +
2059 + DDR0MASK_mask_b = 16,
2060 + DDR0MASK_mask_m = 0xffff0000,
2061 +
2062 + DDR1BASE_baseaddr_b = 16,
2063 + DDR1BASE_baseaddr_m = 0xffff0000,
2064 +
2065 + DDR1MASK_mask_b = 16,
2066 + DDR1MASK_mask_m = 0xffff0000,
2067 +
2068 + DDRC_ata_b = 5,
2069 + DDRC_ata_m = 0x000000E0,
2070 + DDRC_dbw_b = 8,
2071 + DDRC_dbw_m = 0x00000100,
2072 + DDRC_wr_b = 9,
2073 + DDRC_wr_m = 0x00000600,
2074 + DDRC_ps_b = 11,
2075 + DDRC_ps_m = 0x00001800,
2076 + DDRC_dtype_b = 13,
2077 + DDRC_dtype_m = 0x0000e000,
2078 + DDRC_rfc_b = 16,
2079 + DDRC_rfc_m = 0x000f0000,
2080 + DDRC_rp_b = 20,
2081 + DDRC_rp_m = 0x00300000,
2082 + DDRC_ap_b = 22,
2083 + DDRC_ap_m = 0x00400000,
2084 + DDRC_rcd_b = 23,
2085 + DDRC_rcd_m = 0x01800000,
2086 + DDRC_cl_b = 25,
2087 + DDRC_cl_m = 0x06000000,
2088 + DDRC_dbm_b = 27,
2089 + DDRC_dbm_m = 0x08000000,
2090 + DDRC_sds_b = 28,
2091 + DDRC_sds_m = 0x10000000,
2092 + DDRC_atp_b = 29,
2093 + DDRC_atp_m = 0x60000000,
2094 + DDRC_re_b = 31,
2095 + DDRC_re_m = 0x80000000,
2096 +
2097 + DDRRDC_ces_b = 0,
2098 + DDRRDC_ces_m = 0x00000001,
2099 + DDRRDC_ace_b = 1,
2100 + DDRRDC_ace_m = 0x00000002,
2101 +
2102 + DDRABASE_baseaddr_b = 16,
2103 + DDRABASE_baseaddr_m = 0xffff0000,
2104 +
2105 + DDRAMASK_mask_b = 16,
2106 + DDRAMASK_mask_m = 0xffff0000,
2107 +
2108 + DDRAMAP_map_b = 16,
2109 + DDRAMAP_map_m = 0xffff0000,
2110 +
2111 + DDRCUST_cs_b = 0,
2112 + DDRCUST_cs_m = 0x00000003,
2113 + DDRCUST_we_b = 2,
2114 + DDRCUST_we_m = 0x00000004,
2115 + DDRCUST_ras_b = 3,
2116 + DDRCUST_ras_m = 0x00000008,
2117 + DDRCUST_cas_b = 4,
2118 + DDRCUST_cas_m = 0x00000010,
2119 + DDRCUST_cke_b = 5,
2120 + DDRCUST_cke_m = 0x00000020,
2121 + DDRCUST_ba_b = 6,
2122 + DDRCUST_ba_m = 0x000000c0,
2123 +
2124 + RCOUNT_rcount_b = 0,
2125 + RCOUNT_rcount_m = 0x0000ffff,
2126 +
2127 + RCOMPARE_rcompare_b = 0,
2128 + RCOMPARE_rcompare_m = 0x0000ffff,
2129 +
2130 + RTC_ce_b = 0,
2131 + RTC_ce_m = 0x00000001,
2132 + RTC_to_b = 1,
2133 + RTC_to_m = 0x00000002,
2134 + RTC_rqe_b = 2,
2135 + RTC_rqe_m = 0x00000004,
2136 +
2137 + DDRDQSC_dm_b = 0,
2138 + DDRDQSC_dm_m = 0x00000003,
2139 + DDRDQSC_dqsbs_b = 2,
2140 + DDRDQSC_dqsbs_m = 0x000000fc,
2141 + DDRDQSC_db_b = 8,
2142 + DDRDQSC_db_m = 0x00000100,
2143 + DDRDQSC_dbsp_b = 9,
2144 + DDRDQSC_dbsp_m = 0x01fffe00,
2145 + DDRDQSC_bdp_b = 25,
2146 + DDRDQSC_bdp_m = 0x7e000000,
2147 +
2148 + DDRDLLC_eao_b = 0,
2149 + DDRDLLC_eao_m = 0x00000001,
2150 + DDRDLLC_eo_b = 1,
2151 + DDRDLLC_eo_m = 0x0000003e,
2152 + DDRDLLC_fs_b = 6,
2153 + DDRDLLC_fs_m = 0x000000c0,
2154 + DDRDLLC_as_b = 8,
2155 + DDRDLLC_as_m = 0x00000700,
2156 + DDRDLLC_sp_b = 11,
2157 + DDRDLLC_sp_m = 0x001ff800,
2158 +
2159 + DDRDLLFC_men_b = 0,
2160 + DDRDLLFC_men_m = 0x00000001,
2161 + DDRDLLFC_aen_b = 1,
2162 + DDRDLLFC_aen_m = 0x00000002,
2163 + DDRDLLFC_ff_b = 2,
2164 + DDRDLLFC_ff_m = 0x00000004,
2165 +
2166 + DDRDLLTA_addr_b = 2,
2167 + DDRDLLTA_addr_m = 0xfffffffc,
2168 +
2169 + DDRDLLED_dbe_b = 0,
2170 + DDRDLLED_dbe_m = 0x00000001,
2171 + DDRDLLED_dte_b = 1,
2172 + DDRDLLED_dte_m = 0x00000002,
2173 +
2174 +
2175 +} ;
2176 +
2177 +#endif // __IDT_DDR_H__
2178 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
2179 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
2180 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-10-11 21:56:38.000000000 +0200
2181 @@ -0,0 +1,134 @@
2182 +#ifndef __IDT_DEV_H__
2183 +#define __IDT_DEV_H__
2184 +
2185 +/*******************************************************************************
2186 + *
2187 + * Copyright 2002 Integrated Device Technology, Inc.
2188 + * All rights reserved.
2189 + *
2190 + * Device Controller register definition.
2191 + *
2192 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2193 + *
2194 + * Author : John.Ahrens@idt.com
2195 + * Date : 200112013
2196 + * Update :
2197 + * $Log: dev.h,v $
2198 + * Revision 1.2 2002/06/06 18:34:03 astichte
2199 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2200 + *
2201 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2202 + * jba File moved from vcode/include/idt/acacia
2203 + *
2204 + *
2205 + ******************************************************************************/
2206 +
2207 +#include <asm/rc32434/types.h>
2208 +
2209 +enum
2210 +{
2211 + DEV0_PhysicalAddress = 0x18010000,
2212 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
2213 +
2214 + DEV0_VirtualAddress = 0xb8010000,
2215 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
2216 +} ;
2217 +
2218 +typedef struct DEVICE_s
2219 +{
2220 + U32 devbase ; // Device Base
2221 + U32 devmask ; // Device Mask
2222 + U32 devc ; // Device Control
2223 + U32 devtc ; // Device Timing Control
2224 +} volatile *DEVICE_t ;
2225 +
2226 +enum
2227 +{
2228 + DEV_Count = 3,
2229 +} ;
2230 +
2231 +typedef struct DEV_s
2232 +{
2233 + struct DEVICE_s dev [DEV_Count] ;
2234 + U32 btcs ; // Bus timeout control / status
2235 + U32 btcompare ; // Compare
2236 + U32 btaddr ; // Timeout address.
2237 + U32 devdacs ; // Decoupled access control.
2238 + U32 devdaa ; // Decoupled access address.
2239 + U32 devdad ; // Decoupled access address.
2240 + U32 devspare ; // spare.
2241 +} volatile *DEV_t ;
2242 +
2243 +enum
2244 +{
2245 + DEVBASE_baseaddr_b = 16,
2246 + DEVBASE_baseaddr_m = 0xffff0000,
2247 + DEVMASK_mask_b = 16,
2248 + DEVMASK_mask_m = 0xffff0000,
2249 +
2250 + DEVC_ds_b = 0,
2251 + DEVC_ds_m = 0x00000003,
2252 + DEVC_ds_8_v = 0, // 8-bit device.
2253 + DEVC_ds_16_v = 1, // reserved
2254 + DEVC_ds_res_v = 2, // reserved.
2255 + DEVC_ds_res2_v = 3, // reserved.
2256 + DEVC_be_b = 2,
2257 + DEVC_be_m = 0x00000004,
2258 + DEVC_wp_b = 3,
2259 + DEVC_wp_m = 0x00000008,
2260 + DEVC_csd_b = 4,
2261 + DEVC_csd_m = 0x000000f0,
2262 + DEVC_oed_b = 8,
2263 + DEVC_oed_m = 0x00000f00,
2264 + DEVC_bwd_b = 12,
2265 + DEVC_bwd_m = 0x0000f000,
2266 + DEVC_rws_b = 16,
2267 + DEVC_rws_m = 0x003f0000,
2268 + DEVC_wws_b = 22,
2269 + DEVC_wws_m = 0x0fc00000,
2270 + DEVC_bre_b = 28,
2271 + DEVC_bre_m = 0x10000000,
2272 + DEVC_bwe_b = 29,
2273 + DEVC_bwe_m = 0x20000000,
2274 + DEVC_wam_b = 30,
2275 + DEVC_wam_m = 0x40000000,
2276 +
2277 + DEVTC_prd_b = 0,
2278 + DEVTC_prd_m = 0x0000000f,
2279 + DEVTC_pwd_b = 4,
2280 + DEVTC_pwd_m = 0x000000f0,
2281 + DEVTC_wdh_b = 8,
2282 + DEVTC_wdh_m = 0x00000700,
2283 + DEVTC_csh_b = 11,
2284 + DEVTC_csh_m = 0x00001800,
2285 +
2286 + BTCS_tt_b = 0,
2287 + BTCS_tt_m = 0x00000001,
2288 + BTCS_tt_write = 0,
2289 + BTCS_tt_read = 1,
2290 + BTCS_bto_b = 1, // In btcs
2291 + BTCS_bto_m = 0x00000002, // In btcs
2292 + BTCS_bte_b = 2, // In btcs
2293 + BTCS_bte_m = 0x00000004, // In btcs
2294 +
2295 + BTCOMPARE_compare_b = 0, // In btcompare
2296 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
2297 +
2298 + DEVDACS_op_b = 0, // In devdacs
2299 + DEVDACS_op_m = 0x00000001, // In devdacs
2300 + DEVDACS_op_write_v = 0,
2301 + DEVDACS_op_read_v = 1,
2302 + DEVDACS_size_b = 1, // In devdacs
2303 + DEVDACS_size_m = 0x00000006, // In devdacs
2304 + DEVDACS_size_byte_v = 0,
2305 + DEVDACS_size_halfword = 1,
2306 + DEVDACS_size_triplebyte = 2,
2307 + DEVDACS_size_word = 3,
2308 + DEVDACS_err_b = 3, // In devdacs
2309 + DEVDACS_err_m = 0x00000008, // In devdacs
2310 + DEVDACS_f_b = 4, // In devdacs
2311 + DEVDACS_f_m = 0x00000010, // In devdacs
2312 +} ;
2313 +
2314 +#endif //__IDT_DEV_H__
2315 +
2316 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
2317 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
2318 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-10-11 21:56:38.000000000 +0200
2319 @@ -0,0 +1,202 @@
2320 +#ifndef __IDT_DMA_H__
2321 +#define __IDT_DMA_H__
2322 +
2323 +/*******************************************************************************
2324 + *
2325 + * Copyright 2002 Integrated Device Technology, Inc.
2326 + * All rights reserved.
2327 + *
2328 + * DMA register definition.
2329 + *
2330 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2331 + *
2332 + * Author : ryan.holmQVist@idt.com
2333 + * Date : 20011005
2334 + * Update :
2335 + * $Log: dma.h,v $
2336 + * Revision 1.3 2002/06/06 18:34:03 astichte
2337 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2338 + *
2339 + * Revision 1.2 2002/06/05 18:30:46 astichte
2340 + * Removed IDTField
2341 + *
2342 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2343 + * jba File moved from vcode/include/idt/acacia
2344 + *
2345 + *
2346 + ******************************************************************************/
2347 +
2348 +#include <asm/rc32434/types.h>
2349 +enum
2350 +{
2351 + DMA0_PhysicalAddress = 0x18040000,
2352 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
2353 +
2354 + DMA0_VirtualAddress = 0xb8040000,
2355 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
2356 +} ;
2357 +
2358 +/*
2359 + * DMA descriptor (in physical memory).
2360 + */
2361 +
2362 +typedef struct DMAD_s
2363 +{
2364 + U32 control ; // Control. use DMAD_*
2365 + U32 ca ; // Current Address.
2366 + U32 devcs ; // Device control and status.
2367 + U32 link ; // Next descriptor in chain.
2368 +} volatile *DMAD_t ;
2369 +
2370 +enum
2371 +{
2372 + DMAD_size = sizeof (struct DMAD_s),
2373 + DMAD_count_b = 0, // in DMAD_t -> control
2374 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
2375 + DMAD_ds_b = 20, // in DMAD_t -> control
2376 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
2377 + DMAD_ds_ethRcv_v = 0,
2378 + DMAD_ds_ethXmt_v = 0,
2379 + DMAD_ds_memToFifo_v = 0,
2380 + DMAD_ds_fifoToMem_v = 0,
2381 + DMAD_ds_pciToMem_v = 0,
2382 + DMAD_ds_memToPci_v = 0,
2383 +
2384 + DMAD_devcmd_b = 22, // in DMAD_t -> control
2385 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
2386 + DMAD_devcmd_byte_v = 0, //memory-to-memory
2387 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
2388 + DMAD_devcmd_word_v = 2, //memory-to-memory
2389 + DMAD_devcmd_2words_v = 3, //memory-to-memory
2390 + DMAD_devcmd_4words_v = 4, //memory-to-memory
2391 + DMAD_devcmd_6words_v = 5, //memory-to-memory
2392 + DMAD_devcmd_8words_v = 6, //memory-to-memory
2393 + DMAD_devcmd_16words_v = 7, //memory-to-memory
2394 + DMAD_cof_b = 25, // chain on finished
2395 + DMAD_cof_m = 0x02000000, //
2396 + DMAD_cod_b = 26, // chain on done
2397 + DMAD_cod_m = 0x04000000, //
2398 + DMAD_iof_b = 27, // interrupt on finished
2399 + DMAD_iof_m = 0x08000000, //
2400 + DMAD_iod_b = 28, // interrupt on done
2401 + DMAD_iod_m = 0x10000000, //
2402 + DMAD_t_b = 29, // terminated
2403 + DMAD_t_m = 0x20000000, //
2404 + DMAD_d_b = 30, // done
2405 + DMAD_d_m = 0x40000000, //
2406 + DMAD_f_b = 31, // finished
2407 + DMAD_f_m = 0x80000000, //
2408 +} ;
2409 +
2410 +/*
2411 + * DMA register (within Internal Register Map).
2412 + */
2413 +
2414 +struct DMA_Chan_s
2415 +{
2416 + U32 dmac ; // Control.
2417 + U32 dmas ; // Status.
2418 + U32 dmasm ; // Mask.
2419 + U32 dmadptr ; // Descriptor pointer.
2420 + U32 dmandptr ; // Next descriptor pointer.
2421 +};
2422 +
2423 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2424 +
2425 +//DMA_Channels use DMACH_count instead
2426 +
2427 +enum
2428 +{
2429 + DMAC_run_b = 0, //
2430 + DMAC_run_m = 0x00000001, //
2431 + DMAC_dm_b = 1, // done mask
2432 + DMAC_dm_m = 0x00000002, //
2433 + DMAC_mode_b = 2, //
2434 + DMAC_mode_m = 0x0000000c, //
2435 + DMAC_mode_auto_v = 0,
2436 + DMAC_mode_burst_v = 1,
2437 + DMAC_mode_transfer_v = 2, //usually used
2438 + DMAC_mode_reserved_v = 3,
2439 + DMAC_a_b = 4, //
2440 + DMAC_a_m = 0x00000010, //
2441 +
2442 + DMAS_f_b = 0, // finished (sticky)
2443 + DMAS_f_m = 0x00000001, //
2444 + DMAS_d_b = 1, // done (sticky)
2445 + DMAS_d_m = 0x00000002, //
2446 + DMAS_c_b = 2, // chain (sticky)
2447 + DMAS_c_m = 0x00000004, //
2448 + DMAS_e_b = 3, // error (sticky)
2449 + DMAS_e_m = 0x00000008, //
2450 + DMAS_h_b = 4, // halt (sticky)
2451 + DMAS_h_m = 0x00000010, //
2452 +
2453 + DMASM_f_b = 0, // finished (1=mask)
2454 + DMASM_f_m = 0x00000001, //
2455 + DMASM_d_b = 1, // done (1=mask)
2456 + DMASM_d_m = 0x00000002, //
2457 + DMASM_c_b = 2, // chain (1=mask)
2458 + DMASM_c_m = 0x00000004, //
2459 + DMASM_e_b = 3, // error (1=mask)
2460 + DMASM_e_m = 0x00000008, //
2461 + DMASM_h_b = 4, // halt (1=mask)
2462 + DMASM_h_m = 0x00000010, //
2463 +} ;
2464 +
2465 +/*
2466 + * DMA channel definitions
2467 + */
2468 +
2469 +enum
2470 +{
2471 + DMACH_ethRcv = 0,
2472 + DMACH_ethXmt = 1,
2473 + DMACH_memToFifo = 2,
2474 + DMACH_fifoToMem = 3,
2475 + DMACH_pciToMem = 4,
2476 + DMACH_memToPci = 5,
2477 +
2478 + DMACH_count //must be last
2479 +};
2480 +
2481 +
2482 +typedef struct DMAC_s
2483 +{
2484 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2485 +} volatile *DMA_t ;
2486 +
2487 +
2488 +/*
2489 + * External DMA parameters
2490 +*/
2491 +#if 0
2492 +enum
2493 +{
2494 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2495 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2496 + DMADEVCMD_ts_byte_v = 0,
2497 + DMADEVCMD_ts_halfword_v = 1,
2498 + DMADEVCMD_ts_word_v = 2,
2499 + DMADEVCMD_ts_2word_v = 3,
2500 + DMADEVCMD_ts_4word_v = 4,
2501 + DMADEVCMD_ts_6word_v = 5,
2502 + DMADEVCMD_ts_8word_v = 6,
2503 + DMADEVCMD_ts_16word_v = 7
2504 +};
2505 +#endif
2506 +
2507 +#if 1 // aws - Compatibility.
2508 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2509 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2510 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2511 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2512 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2513 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2514 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2515 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2516 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2517 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2518 +#endif // aws - Compatibility.
2519 +
2520 +#endif // __IDT_DMA_H__
2521 +
2522 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2523 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2524 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-10-11 21:56:38.000000000 +0200
2525 @@ -0,0 +1,73 @@
2526 +#ifndef __IDT_DMA_V_H__
2527 +#define __IDT_DMA_V_H__
2528 +
2529 +/*******************************************************************************
2530 + *
2531 + * Copyright 2002 Integrated Device Technology, Inc.
2532 + * All rights reserved.
2533 + *
2534 + * DMA register definition.
2535 + *
2536 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2537 + *
2538 + * Author : ryan.holmQVist@idt.com
2539 + * Date : 20011005
2540 + * Update :
2541 + * $Log: dma.h,v $
2542 + * Revision 1.3 2002/06/06 18:34:03 astichte
2543 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2544 + *
2545 + * Revision 1.2 2002/06/05 18:30:46 astichte
2546 + * Removed IDTField
2547 + *
2548 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2549 + * jba File moved from vcode/include/idt/acacia
2550 + *
2551 + *
2552 + ******************************************************************************/
2553 +#include <asm/rc32434/types.h>
2554 +#include <asm/rc32434/dma.h>
2555 +#include <asm/rc32434/rc32434.h>
2556 +#define DMA_CHAN_OFFSET 0x14
2557 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2558 +#define DMA_COUNT(count) \
2559 + ((count) & DMAD_count_m)
2560 +
2561 +#define DMA_HALT_TIMEOUT 500
2562 +
2563 +
2564 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2565 +{
2566 + int timeout=1;
2567 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2568 + local_writel(0, &ch->dmac);
2569 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2570 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2571 + local_writel(0, &ch->dmas);
2572 + break;
2573 + }
2574 + }
2575 + }
2576 +
2577 + return timeout ? 0 : 1;
2578 +}
2579 +
2580 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2581 +{
2582 + local_writel(0, &ch->dmandptr);
2583 + local_writel(dma_addr, &ch->dmadptr);
2584 +}
2585 +
2586 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2587 +{
2588 + local_writel(dma_addr, &ch->dmandptr);
2589 +}
2590 +
2591 +#endif // __IDT_DMA_V_H__
2592 +
2593 +
2594 +
2595 +
2596 +
2597 +
2598 +
2599 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2600 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2601 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-10-11 21:56:38.000000000 +0200
2602 @@ -0,0 +1,322 @@
2603 +#ifndef __IDT_ETH_H__
2604 +#define __IDT_ETH_H__
2605 +
2606 +/*******************************************************************************
2607 + *
2608 + * Copyright 2002 Integrated Device Technology, Inc.
2609 + * All rights reserved.
2610 + *
2611 + * Ethernet register definition.
2612 + *
2613 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2614 + *
2615 + * Author : Allen.Stichter@idt.com
2616 + * Date : 20020605
2617 + * Update :
2618 + * $Log: eth.h,v $
2619 + * Revision 1.3 2002/06/06 18:34:04 astichte
2620 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2621 + *
2622 + * Revision 1.2 2002/06/05 18:19:46 astichte
2623 + * Added
2624 + *
2625 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2626 + * jba File moved from vcode/include/idt/acacia
2627 + *
2628 + ******************************************************************************/
2629 +
2630 +#include <asm/rc32434/types.h>
2631 +
2632 +enum
2633 +{
2634 + ETH0_PhysicalAddress = 0x18060000,
2635 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2636 +
2637 + ETH0_VirtualAddress = 0xb8060000,
2638 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2639 +} ;
2640 +
2641 +typedef struct
2642 +{
2643 + U32 ethintfc ;
2644 + U32 ethfifott ;
2645 + U32 etharc ;
2646 + U32 ethhash0 ;
2647 + U32 ethhash1 ;
2648 + U32 ethu0 [4] ; // Reserved.
2649 + U32 ethpfs ;
2650 + U32 ethmcp ;
2651 + U32 eth_u1 [10] ; // Reserved.
2652 + U32 ethspare ;
2653 + U32 eth_u2 [42] ; // Reserved.
2654 + U32 ethsal0 ;
2655 + U32 ethsah0 ;
2656 + U32 ethsal1 ;
2657 + U32 ethsah1 ;
2658 + U32 ethsal2 ;
2659 + U32 ethsah2 ;
2660 + U32 ethsal3 ;
2661 + U32 ethsah3 ;
2662 + U32 ethrbc ;
2663 + U32 ethrpc ;
2664 + U32 ethrupc ;
2665 + U32 ethrfc ;
2666 + U32 ethtbc ;
2667 + U32 ethgpf ;
2668 + U32 eth_u9 [50] ; // Reserved.
2669 + U32 ethmac1 ;
2670 + U32 ethmac2 ;
2671 + U32 ethipgt ;
2672 + U32 ethipgr ;
2673 + U32 ethclrt ;
2674 + U32 ethmaxf ;
2675 + U32 eth_u10 ; // Reserved.
2676 + U32 ethmtest ;
2677 + U32 miimcfg ;
2678 + U32 miimcmd ;
2679 + U32 miimaddr ;
2680 + U32 miimwtd ;
2681 + U32 miimrdd ;
2682 + U32 miimind ;
2683 + U32 eth_u11 ; // Reserved.
2684 + U32 eth_u12 ; // Reserved.
2685 + U32 ethcfsa0 ;
2686 + U32 ethcfsa1 ;
2687 + U32 ethcfsa2 ;
2688 +} volatile *ETH_t;
2689 +
2690 +enum
2691 +{
2692 + ETHINTFC_en_b = 0,
2693 + ETHINTFC_en_m = 0x00000001,
2694 + ETHINTFC_its_b = 1,
2695 + ETHINTFC_its_m = 0x00000002,
2696 + ETHINTFC_rip_b = 2,
2697 + ETHINTFC_rip_m = 0x00000004,
2698 + ETHINTFC_jam_b = 3,
2699 + ETHINTFC_jam_m = 0x00000008,
2700 + ETHINTFC_ovr_b = 4,
2701 + ETHINTFC_ovr_m = 0x00000010,
2702 + ETHINTFC_und_b = 5,
2703 + ETHINTFC_und_m = 0x00000020,
2704 + ETHINTFC_iom_b = 6,
2705 + ETHINTFC_iom_m = 0x000000c0,
2706 +
2707 + ETHFIFOTT_tth_b = 0,
2708 + ETHFIFOTT_tth_m = 0x0000007f,
2709 +
2710 + ETHARC_pro_b = 0,
2711 + ETHARC_pro_m = 0x00000001,
2712 + ETHARC_am_b = 1,
2713 + ETHARC_am_m = 0x00000002,
2714 + ETHARC_afm_b = 2,
2715 + ETHARC_afm_m = 0x00000004,
2716 + ETHARC_ab_b = 3,
2717 + ETHARC_ab_m = 0x00000008,
2718 +
2719 + ETHSAL_byte5_b = 0,
2720 + ETHSAL_byte5_m = 0x000000ff,
2721 + ETHSAL_byte4_b = 8,
2722 + ETHSAL_byte4_m = 0x0000ff00,
2723 + ETHSAL_byte3_b = 16,
2724 + ETHSAL_byte3_m = 0x00ff0000,
2725 + ETHSAL_byte2_b = 24,
2726 + ETHSAL_byte2_m = 0xff000000,
2727 +
2728 + ETHSAH_byte1_b = 0,
2729 + ETHSAH_byte1_m = 0x000000ff,
2730 + ETHSAH_byte0_b = 8,
2731 + ETHSAH_byte0_m = 0x0000ff00,
2732 +
2733 + ETHGPF_ptv_b = 0,
2734 + ETHGPF_ptv_m = 0x0000ffff,
2735 +
2736 + ETHPFS_pfd_b = 0,
2737 + ETHPFS_pfd_m = 0x00000001,
2738 +
2739 + ETHCFSA0_cfsa4_b = 0,
2740 + ETHCFSA0_cfsa4_m = 0x000000ff,
2741 + ETHCFSA0_cfsa5_b = 8,
2742 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2743 +
2744 + ETHCFSA1_cfsa2_b = 0,
2745 + ETHCFSA1_cfsa2_m = 0x000000ff,
2746 + ETHCFSA1_cfsa3_b = 8,
2747 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2748 +
2749 + ETHCFSA2_cfsa0_b = 0,
2750 + ETHCFSA2_cfsa0_m = 0x000000ff,
2751 + ETHCFSA2_cfsa1_b = 8,
2752 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2753 +
2754 + ETHMAC1_re_b = 0,
2755 + ETHMAC1_re_m = 0x00000001,
2756 + ETHMAC1_paf_b = 1,
2757 + ETHMAC1_paf_m = 0x00000002,
2758 + ETHMAC1_rfc_b = 2,
2759 + ETHMAC1_rfc_m = 0x00000004,
2760 + ETHMAC1_tfc_b = 3,
2761 + ETHMAC1_tfc_m = 0x00000008,
2762 + ETHMAC1_lb_b = 4,
2763 + ETHMAC1_lb_m = 0x00000010,
2764 + ETHMAC1_mr_b = 31,
2765 + ETHMAC1_mr_m = 0x80000000,
2766 +
2767 + ETHMAC2_fd_b = 0,
2768 + ETHMAC2_fd_m = 0x00000001,
2769 + ETHMAC2_flc_b = 1,
2770 + ETHMAC2_flc_m = 0x00000002,
2771 + ETHMAC2_hfe_b = 2,
2772 + ETHMAC2_hfe_m = 0x00000004,
2773 + ETHMAC2_dc_b = 3,
2774 + ETHMAC2_dc_m = 0x00000008,
2775 + ETHMAC2_cen_b = 4,
2776 + ETHMAC2_cen_m = 0x00000010,
2777 + ETHMAC2_pe_b = 5,
2778 + ETHMAC2_pe_m = 0x00000020,
2779 + ETHMAC2_vpe_b = 6,
2780 + ETHMAC2_vpe_m = 0x00000040,
2781 + ETHMAC2_ape_b = 7,
2782 + ETHMAC2_ape_m = 0x00000080,
2783 + ETHMAC2_ppe_b = 8,
2784 + ETHMAC2_ppe_m = 0x00000100,
2785 + ETHMAC2_lpe_b = 9,
2786 + ETHMAC2_lpe_m = 0x00000200,
2787 + ETHMAC2_nb_b = 12,
2788 + ETHMAC2_nb_m = 0x00001000,
2789 + ETHMAC2_bp_b = 13,
2790 + ETHMAC2_bp_m = 0x00002000,
2791 + ETHMAC2_ed_b = 14,
2792 + ETHMAC2_ed_m = 0x00004000,
2793 +
2794 + ETHIPGT_ipgt_b = 0,
2795 + ETHIPGT_ipgt_m = 0x0000007f,
2796 +
2797 + ETHIPGR_ipgr2_b = 0,
2798 + ETHIPGR_ipgr2_m = 0x0000007f,
2799 + ETHIPGR_ipgr1_b = 8,
2800 + ETHIPGR_ipgr1_m = 0x00007f00,
2801 +
2802 + ETHCLRT_maxret_b = 0,
2803 + ETHCLRT_maxret_m = 0x0000000f,
2804 + ETHCLRT_colwin_b = 8,
2805 + ETHCLRT_colwin_m = 0x00003f00,
2806 +
2807 + ETHMAXF_maxf_b = 0,
2808 + ETHMAXF_maxf_m = 0x0000ffff,
2809 +
2810 + ETHMTEST_tb_b = 2,
2811 + ETHMTEST_tb_m = 0x00000004,
2812 +
2813 + ETHMCP_div_b = 0,
2814 + ETHMCP_div_m = 0x000000ff,
2815 +
2816 + MIIMCFG_rsv_b = 0,
2817 + MIIMCFG_rsv_m = 0x0000000c,
2818 +
2819 + MIIMCMD_rd_b = 0,
2820 + MIIMCMD_rd_m = 0x00000001,
2821 + MIIMCMD_scn_b = 1,
2822 + MIIMCMD_scn_m = 0x00000002,
2823 +
2824 + MIIMADDR_regaddr_b = 0,
2825 + MIIMADDR_regaddr_m = 0x0000001f,
2826 + MIIMADDR_phyaddr_b = 8,
2827 + MIIMADDR_phyaddr_m = 0x00001f00,
2828 +
2829 + MIIMWTD_wdata_b = 0,
2830 + MIIMWTD_wdata_m = 0x0000ffff,
2831 +
2832 + MIIMRDD_rdata_b = 0,
2833 + MIIMRDD_rdata_m = 0x0000ffff,
2834 +
2835 + MIIMIND_bsy_b = 0,
2836 + MIIMIND_bsy_m = 0x00000001,
2837 + MIIMIND_scn_b = 1,
2838 + MIIMIND_scn_m = 0x00000002,
2839 + MIIMIND_nv_b = 2,
2840 + MIIMIND_nv_m = 0x00000004,
2841 +
2842 +} ;
2843 +
2844 +/*
2845 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2846 + */
2847 +enum
2848 +{
2849 + ETHRX_fd_b = 0,
2850 + ETHRX_fd_m = 0x00000001,
2851 + ETHRX_ld_b = 1,
2852 + ETHRX_ld_m = 0x00000002,
2853 + ETHRX_rok_b = 2,
2854 + ETHRX_rok_m = 0x00000004,
2855 + ETHRX_fm_b = 3,
2856 + ETHRX_fm_m = 0x00000008,
2857 + ETHRX_mp_b = 4,
2858 + ETHRX_mp_m = 0x00000010,
2859 + ETHRX_bp_b = 5,
2860 + ETHRX_bp_m = 0x00000020,
2861 + ETHRX_vlt_b = 6,
2862 + ETHRX_vlt_m = 0x00000040,
2863 + ETHRX_cf_b = 7,
2864 + ETHRX_cf_m = 0x00000080,
2865 + ETHRX_ovr_b = 8,
2866 + ETHRX_ovr_m = 0x00000100,
2867 + ETHRX_crc_b = 9,
2868 + ETHRX_crc_m = 0x00000200,
2869 + ETHRX_cv_b = 10,
2870 + ETHRX_cv_m = 0x00000400,
2871 + ETHRX_db_b = 11,
2872 + ETHRX_db_m = 0x00000800,
2873 + ETHRX_le_b = 12,
2874 + ETHRX_le_m = 0x00001000,
2875 + ETHRX_lor_b = 13,
2876 + ETHRX_lor_m = 0x00002000,
2877 + ETHRX_ces_b = 14,
2878 + ETHRX_ces_m = 0x00004000,
2879 + ETHRX_length_b = 16,
2880 + ETHRX_length_m = 0xffff0000,
2881 +
2882 + ETHTX_fd_b = 0,
2883 + ETHTX_fd_m = 0x00000001,
2884 + ETHTX_ld_b = 1,
2885 + ETHTX_ld_m = 0x00000002,
2886 + ETHTX_oen_b = 2,
2887 + ETHTX_oen_m = 0x00000004,
2888 + ETHTX_pen_b = 3,
2889 + ETHTX_pen_m = 0x00000008,
2890 + ETHTX_cen_b = 4,
2891 + ETHTX_cen_m = 0x00000010,
2892 + ETHTX_hen_b = 5,
2893 + ETHTX_hen_m = 0x00000020,
2894 + ETHTX_tok_b = 6,
2895 + ETHTX_tok_m = 0x00000040,
2896 + ETHTX_mp_b = 7,
2897 + ETHTX_mp_m = 0x00000080,
2898 + ETHTX_bp_b = 8,
2899 + ETHTX_bp_m = 0x00000100,
2900 + ETHTX_und_b = 9,
2901 + ETHTX_und_m = 0x00000200,
2902 + ETHTX_of_b = 10,
2903 + ETHTX_of_m = 0x00000400,
2904 + ETHTX_ed_b = 11,
2905 + ETHTX_ed_m = 0x00000800,
2906 + ETHTX_ec_b = 12,
2907 + ETHTX_ec_m = 0x00001000,
2908 + ETHTX_lc_b = 13,
2909 + ETHTX_lc_m = 0x00002000,
2910 + ETHTX_td_b = 14,
2911 + ETHTX_td_m = 0x00004000,
2912 + ETHTX_crc_b = 15,
2913 + ETHTX_crc_m = 0x00008000,
2914 + ETHTX_le_b = 16,
2915 + ETHTX_le_m = 0x00010000,
2916 + ETHTX_cc_b = 17,
2917 + ETHTX_cc_m = 0x001E0000,
2918 +} ;
2919 +
2920 +#endif // __IDT_ETH_H__
2921 +
2922 +
2923 +
2924 +
2925 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2926 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
2927 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-10-11 21:56:38.000000000 +0200
2928 @@ -0,0 +1,64 @@
2929 +#ifndef __IDT_ETH_V_H__
2930 +#define __IDT_ETH_V_H__
2931 +
2932 +/*******************************************************************************
2933 + *
2934 + * Copyright 2002 Integrated Device Technology, Inc.
2935 + * All rights reserved.
2936 + *
2937 + * Ethernet register definition.
2938 + *
2939 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2940 + *
2941 + * Author : Allen.Stichter@idt.com
2942 + * Date : 20020605
2943 + * Update :
2944 + * $Log: eth.h,v $
2945 + * Revision 1.3 2002/06/06 18:34:04 astichte
2946 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2947 + *
2948 + * Revision 1.2 2002/06/05 18:19:46 astichte
2949 + * Added
2950 + *
2951 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2952 + * jba File moved from vcode/include/idt/acacia
2953 + *
2954 + ******************************************************************************/
2955 +
2956 +#include <asm/rc32434/types.h>
2957 +#include <asm/rc32434/eth.h>
2958 +
2959 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
2960 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
2961 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
2962 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
2963 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
2964 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
2965 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
2966 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
2967 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
2968 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
2969 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
2970 +
2971 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
2972 +
2973 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
2974 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
2975 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
2976 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
2977 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
2978 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
2979 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
2980 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
2981 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
2982 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
2983 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
2984 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
2985 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
2986 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
2987 +#endif // __IDT_ETH_V_H__
2988 +
2989 +
2990 +
2991 +
2992 +
2993 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
2994 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
2995 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-10-11 21:56:38.000000000 +0200
2996 @@ -0,0 +1,182 @@
2997 +#ifndef __IDT_GPIO_H__
2998 +#define __IDT_GPIO_H__
2999 +
3000 +/*******************************************************************************
3001 + *
3002 + * Copyright 2002 Integrated Device Technology, Inc.
3003 + * All rights reserved.
3004 + *
3005 + * GPIO register definition.
3006 + *
3007 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3008 + *
3009 + * Author : ryan.holmQVist@idt.com
3010 + * Date : 20011005
3011 + * Update :
3012 + * $Log: gpio.h,v $
3013 + * Revision 1.2 2002/06/06 18:34:04 astichte
3014 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3015 + *
3016 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3017 + * jba File moved from vcode/include/idt/acacia
3018 + *
3019 + *
3020 + ******************************************************************************/
3021 +
3022 +#include <asm/rc32434/types.h>
3023 +enum
3024 +{
3025 + GPIO0_PhysicalAddress = 0x18050000,
3026 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
3027 +
3028 + GPIO0_VirtualAddress = 0xb8050000,
3029 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
3030 +} ;
3031 +
3032 +typedef struct
3033 +{
3034 + U32 gpiofunc; /* GPIO Function Register
3035 + * gpiofunc[x]==0 bit = gpio
3036 + * func[x]==1 bit = altfunc
3037 + */
3038 + U32 gpiocfg; /* GPIO Configuration Register
3039 + * gpiocfg[x]==0 bit = input
3040 + * gpiocfg[x]==1 bit = output
3041 + */
3042 + U32 gpiod; /* GPIO Data Register
3043 + * gpiod[x] read/write gpio pinX status
3044 + */
3045 + U32 gpioilevel; /* GPIO Interrupt Status Register
3046 + * interrupt level (see gpioistat)
3047 + */
3048 + U32 gpioistat; /* Gpio Interrupt Status Register
3049 + * istat[x] = (gpiod[x] == level[x])
3050 + * cleared in ISR (STICKY bits)
3051 + */
3052 + U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
3053 +} volatile * GPIO_t ;
3054 +
3055 +typedef enum
3056 +{
3057 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
3058 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
3059 + GPIO_input_v = 0, // gpiocfg use pin as input.
3060 + GPIO_output_v = 1, // gpiocfg use pin as output.
3061 + GPIO_pin0_b = 0,
3062 + GPIO_pin0_m = 0x00000001,
3063 + GPIO_pin1_b = 1,
3064 + GPIO_pin1_m = 0x00000002,
3065 + GPIO_pin2_b = 2,
3066 + GPIO_pin2_m = 0x00000004,
3067 + GPIO_pin3_b = 3,
3068 + GPIO_pin3_m = 0x00000008,
3069 + GPIO_pin4_b = 4,
3070 + GPIO_pin4_m = 0x00000010,
3071 + GPIO_pin5_b = 5,
3072 + GPIO_pin5_m = 0x00000020,
3073 + GPIO_pin6_b = 6,
3074 + GPIO_pin6_m = 0x00000040,
3075 + GPIO_pin7_b = 7,
3076 + GPIO_pin7_m = 0x00000080,
3077 + GPIO_pin8_b = 8,
3078 + GPIO_pin8_m = 0x00000100,
3079 + GPIO_pin9_b = 9,
3080 + GPIO_pin9_m = 0x00000200,
3081 + GPIO_pin10_b = 10,
3082 + GPIO_pin10_m = 0x00000400,
3083 + GPIO_pin11_b = 11,
3084 + GPIO_pin11_m = 0x00000800,
3085 + GPIO_pin12_b = 12,
3086 + GPIO_pin12_m = 0x00001000,
3087 + GPIO_pin13_b = 13,
3088 + GPIO_pin13_m = 0x00002000,
3089 + GPIO_pin14_b = 14,
3090 + GPIO_pin14_m = 0x00004000,
3091 + GPIO_pin15_b = 15,
3092 + GPIO_pin15_m = 0x00008000,
3093 + GPIO_pin16_b = 16,
3094 + GPIO_pin16_m = 0x00010000,
3095 + GPIO_pin17_b = 17,
3096 + GPIO_pin17_m = 0x00020000,
3097 + GPIO_pin18_b = 18,
3098 + GPIO_pin18_m = 0x00040000,
3099 + GPIO_pin19_b = 19,
3100 + GPIO_pin19_m = 0x00080000,
3101 + GPIO_pin20_b = 20,
3102 + GPIO_pin20_m = 0x00100000,
3103 + GPIO_pin21_b = 21,
3104 + GPIO_pin21_m = 0x00200000,
3105 + GPIO_pin22_b = 22,
3106 + GPIO_pin22_m = 0x00400000,
3107 + GPIO_pin23_b = 23,
3108 + GPIO_pin23_m = 0x00800000,
3109 + GPIO_pin24_b = 24,
3110 + GPIO_pin24_m = 0x01000000,
3111 + GPIO_pin25_b = 25,
3112 + GPIO_pin25_m = 0x02000000,
3113 + GPIO_pin26_b = 26,
3114 + GPIO_pin26_m = 0x04000000,
3115 + GPIO_pin27_b = 27,
3116 + GPIO_pin27_m = 0x08000000,
3117 + GPIO_pin28_b = 28,
3118 + GPIO_pin28_m = 0x10000000,
3119 + GPIO_pin29_b = 29,
3120 + GPIO_pin29_m = 0x20000000,
3121 + GPIO_pin30_b = 30,
3122 + GPIO_pin30_m = 0x40000000,
3123 + GPIO_pin31_b = 31,
3124 + GPIO_pin31_m = 0x80000000,
3125 +
3126 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
3127 +
3128 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
3129 + GPIO_u0sout_m = GPIO_pin0_m,
3130 + GPIO_u0sout_cfg_v = GPIO_output_v,
3131 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
3132 + GPIO_u0sinp_m = GPIO_pin1_m,
3133 + GPIO_u0sinp_cfg_v = GPIO_input_v,
3134 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
3135 + GPIO_u0rtsn_m = GPIO_pin2_m,
3136 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
3137 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
3138 + GPIO_u0ctsn_m = GPIO_pin3_m,
3139 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
3140 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
3141 + GPIO_maddr22_m = GPIO_pin4_m,
3142 + GPIO_maddr22_cfg_v = GPIO_output_v,
3143 +
3144 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
3145 + GPIO_maddr23_m = GPIO_pin5_m,
3146 + GPIO_maddr23_cfg_v = GPIO_output_v,
3147 +
3148 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
3149 + GPIO_maddr24_m = GPIO_pin6_m,
3150 + GPIO_maddr24_cfg_v = GPIO_output_v,
3151 +
3152 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
3153 + GPIO_maddr25_m = GPIO_pin7_m,
3154 + GPIO_maddr25_cfg_v = GPIO_output_v,
3155 +
3156 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
3157 + GPIO_cpu_m = GPIO_pin8_m,
3158 + GPIO_cpu_cfg_v = GPIO_output_v,
3159 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
3160 + GPIO_afspare6_m = GPIO_pin9_m,
3161 + GPIO_afspare6_cfg_v = GPIO_input_v,
3162 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
3163 + GPIO_afspare4_m = GPIO_pin10_m,
3164 + GPIO_afspare4_cfg_v = GPIO_input_v,
3165 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
3166 + GPIO_afspare3_m = GPIO_pin11_m,
3167 + GPIO_afspare3_cfg_v = GPIO_input_v,
3168 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
3169 + GPIO_afspare2_m = GPIO_pin12_m,
3170 + GPIO_afspare2_cfg_v = GPIO_input_v,
3171 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
3172 + GPIO_pcimuintn_m = GPIO_pin13_m,
3173 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
3174 +
3175 +} GPIO_DEFS_t;
3176 +
3177 +#endif // __IDT_GPIO_H__
3178 +
3179 diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
3180 --- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100
3181 +++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-10-11 21:56:38.000000000 +0200
3182 @@ -0,0 +1,147 @@
3183 +#ifndef __IDT_I2C_H__
3184 +#define __IDT_I2C_H__
3185 +
3186 +/*******************************************************************************
3187 + *
3188 + * Copyright 2002 Integrated Device Technology, Inc.
3189 + * All rights reserved.
3190 + *
3191 + * I2C register definitions.
3192 + *
3193 + * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3194 + *
3195 + * Author : Allen.Stichter@idt.com
3196 + * Date : 20020120
3197 + * Update :
3198 + * $Log: i2c.h,v $
3199 + * Revision 1.2 2002/06/06 18:34:04 astichte
3200 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3201 + *
3202 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3203 + * jba File moved from vcode/include/idt/acacia
3204 + *
3205 + *
3206 + ******************************************************************************/
3207 +
3208 +#include <asm/rc32434/types.h>
3209 +
3210 +enum
3211 +{
3212 + I2C0_PhysicalAddress = 0x18068000,
3213 + I2C_PhysicalAddress = I2C0_PhysicalAddress,
3214 +
3215 + I2C0_VirtualAddress = 0xb8068000,
3216 + I2C_VirtualAddress = I2C0_VirtualAddress,
3217 +} ;
3218 +
3219 +typedef struct
3220 +{
3221 + U32 i2cc ;
3222 + U32 i2cdi ;
3223 + U32 i2cdo ;
3224 + U32 i2ccp ; // I2C clk = ICLK / div / 8
3225 + U32 i2cmcmd ;
3226 + U32 i2cms ;
3227 + U32 i2cmsm ;
3228 + U32 i2css ;
3229 + U32 i2cssm ;
3230 + U32 i2csaddr ;
3231 + U32 i2csack ;
3232 +} volatile * I2C_t ;
3233 +enum
3234 +{
3235 + I2CC_men_b = 0, // In I2C-> i2cc
3236 + I2CC_men_m = 0x00000001,
3237 + I2CC_sen_b = 1, // In I2C-> i2cc
3238 + I2CC_sen_m = 0x00000002,
3239 + I2CC_iom_b = 2, // In I2C-> i2cc
3240 + I2CC_iom_m = 0x00000004,
3241 +
3242 + I2CDI_data_b = 0, // In I2C-> i2cdi
3243 + I2CDI_data_m = 0x000000ff,
3244 +
3245 + I2CDO_data_b = 0, // In I2C-> i2cdo
3246 + I2CDO_data_m = 0x000000ff,
3247 +
3248 + I2CCP_div_b = 0, // In I2C-> i2ccp
3249 + I2CCP_div_m = 0x0000ffff,
3250 +
3251 + I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd
3252 + I2CMCMD_cmd_m = 0x0000000f,
3253 + I2CMCMD_cmd_nop_v = 0,
3254 + I2CMCMD_cmd_start_v = 1,
3255 + I2CMCMD_cmd_stop_v = 2,
3256 + I2CMCMD_cmd_res3_v = 3,
3257 + I2CMCMD_cmd_rd_v = 4,
3258 + I2CMCMD_cmd_rdack_v = 5,
3259 + I2CMCMD_cmd_wd_v = 6,
3260 + I2CMCMD_cmd_wdack_v = 7,
3261 + I2CMCMD_cmd_res8_v = 8,
3262 + I2CMCMD_cmd_res9_v = 9,
3263 + I2CMCMD_cmd_res10_v = 10,
3264 + I2CMCMD_cmd_res11_v = 11,
3265 + I2CMCMD_cmd_res12_v = 12,
3266 + I2CMCMD_cmd_res13_v = 13,
3267 + I2CMCMD_cmd_res14_v = 14,
3268 + I2CMCMD_cmd_res15_v = 15,
3269 +
3270 + I2CMS_d_b = 0, // In I2C-> i2cms
3271 + I2CMS_d_m = 0x00000001,
3272 + I2CMS_na_b = 1, // In I2C-> i2cms
3273 + I2CMS_na_m = 0x00000002,
3274 + I2CMS_la_b = 2, // In I2C-> i2cms
3275 + I2CMS_la_m = 0x00000004,
3276 + I2CMS_err_b = 3, // In I2C-> i2cms
3277 + I2CMS_err_m = 0x00000008,
3278 +
3279 + I2CMSM_d_b = 0, // In I2C-> i2cmsm
3280 + I2CMSM_d_m = 0x00000001,
3281 + I2CMSM_na_b = 1, // In I2C-> i2cmsm
3282 + I2CMSM_na_m = 0x00000002,
3283 + I2CMSM_la_b = 2, // In I2C-> i2cmsm
3284 + I2CMSM_la_m = 0x00000004,
3285 + I2CMSM_err_b = 3, // In I2C-> i2cmsm
3286 + I2CMSM_err_m = 0x00000008,
3287 +
3288 + I2CSS_rr_b = 0, // In I2C-> i2css
3289 + I2CSS_rr_m = 0x00000001,
3290 + I2CSS_wr_b = 1, // In I2C-> i2css
3291 + I2CSS_wr_m = 0x00000002,
3292 + I2CSS_sa_b = 2, // In I2C-> i2css
3293 + I2CSS_sa_m = 0x00000004,
3294 + I2CSS_tf_b = 3, // In I2C-> i2css
3295 + I2CSS_tf_m = 0x00000008,
3296 + I2CSS_gc_b = 4, // In I2C-> i2css
3297 + I2CSS_gc_m = 0x00000010,
3298 + I2CSS_na_b = 5, // In I2C-> i2css
3299 + I2CSS_na_m = 0x00000020,
3300 + I2CSS_err_b = 6, // In I2C-> i2css
3301 + I2CSS_err_m = 0x00000040,
3302 +
3303 + I2CSSM_rr_b = 0, // In I2C-> i2cssm
3304 + I2CSSM_rr_m = 0x00000001,
3305 + I2CSSM_wr_b = 1, // In I2C-> i2cssm
3306 + I2CSSM_wr_m = 0x00000002,
3307 + I2CSSM_sa_b = 2, // In I2C-> i2cssm
3308 + I2CSSM_sa_m = 0x00000004,
3309 + I2CSSM_tf_b = 3, // In I2C-> i2cssm
3310 + I2CSSM_tf_m = 0x00000008,
3311 + I2CSSM_gc_b = 4, // In I2C-> i2cssm
3312 + I2CSSM_gc_m = 0x00000010,
3313 + I2CSSM_na_b = 5, // In I2C-> i2cssm
3314 + I2CSSM_na_m = 0x00000020,
3315 + I2CSSM_err_b = 6, // In I2C-> i2cssm
3316 + I2CSSM_err_m = 0x00000040,
3317 +
3318 + I2CSADDR_addr_b = 0, // In I2C-> i2csaddr
3319 + I2CSADDR_addr_m = 0x000003ff,
3320 + I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr
3321 + I2CSADDR_a_gc_m = 0x00000400,
3322 + I2CSADDR_a10_b = 11, // In I2C-> i2csaddr
3323 + I2CSADDR_a10_m = 0x00000800,
3324 +
3325 + I2CSACK_ack_b = 0, // In I2C-> i2csack
3326 + I2CSACK_ack_m = 0x00000001,
3327 +
3328 +} ;
3329 +#endif // __IDT_I2C_H__
3330 diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
3331 --- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100
3332 +++ linux.dev/include/asm-mips/rc32434/integ.h 2006-10-11 21:56:38.000000000 +0200
3333 @@ -0,0 +1,78 @@
3334 +#ifndef __IDT_INTEG_H__
3335 +#define __IDT_INTEG_H__
3336 +
3337 +/*******************************************************************************
3338 + *
3339 + * Copyright 2002 Integrated Device Technology, Inc.
3340 + * All rights reserved.
3341 + *
3342 + * System Integrity register definition.
3343 + *
3344 + * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3345 + *
3346 + * Author : ryan.holmQVist@idt.com
3347 + * Date : 20011005
3348 + * Update :
3349 + * $Log: integ.h,v $
3350 + * Revision 1.3 2002/06/06 18:34:04 astichte
3351 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3352 + *
3353 + * Revision 1.2 2002/06/05 18:32:33 astichte
3354 + * Removed IDTField
3355 + *
3356 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3357 + * jba File moved from vcode/include/idt/acacia
3358 + *
3359 + ******************************************************************************/
3360 +
3361 +#include <asm/rc32434/types.h>
3362 +
3363 +enum
3364 +{
3365 + INTEG0_PhysicalAddress = 0x18030000,
3366 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
3367 +
3368 + INTEG0_VirtualAddress = 0xb8030000,
3369 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
3370 +} ;
3371 +
3372 +// if you are looing for CEA, try rst.h
3373 +typedef struct
3374 +{
3375 + U32 filler [0xc] ; // 0x30 bytes unused.
3376 + U32 errcs ; // sticky use ERRCS_
3377 + U32 wtcount ; // Watchdog timer count reg.
3378 + U32 wtcompare ; // Watchdog timer timeout value.
3379 + U32 wtc ; // Watchdog timer control. use WTC_
3380 +} volatile *INTEG_t ;
3381 +
3382 +enum
3383 +{
3384 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
3385 + ERRCS_wto_m = 0x00000001,
3386 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
3387 + ERRCS_wne_m = 0x00000002,
3388 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
3389 + ERRCS_ucw_m = 0x00000004,
3390 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
3391 + ERRCS_ucr_m = 0x00000008,
3392 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
3393 + ERRCS_upw_m = 0x00000010,
3394 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
3395 + ERRCS_upr_m = 0x00000020,
3396 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
3397 + ERRCS_udw_m = 0x00000040,
3398 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
3399 + ERRCS_udr_m = 0x00000080,
3400 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
3401 + ERRCS_sae_m = 0x00000100,
3402 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
3403 + ERRCS_wre_m = 0x00000200,
3404 +
3405 + WTC_en_b = 0, // In INTEG_t -> wtc
3406 + WTC_en_m = 0x00000001,
3407 + WTC_to_b = 1, // In INTEG_t -> wtc
3408 + WTC_to_m = 0x00000002,
3409 +} ;
3410 +
3411 +#endif // __IDT_INTEG_H__
3412 diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
3413 --- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
3414 +++ linux.dev/include/asm-mips/rc32434/int.h 2006-10-11 21:56:38.000000000 +0200
3415 @@ -0,0 +1,167 @@
3416 +#ifndef __IDT_INT_H__
3417 +#define __IDT_INT_H__
3418 +
3419 +/*******************************************************************************
3420 + *
3421 + * Copyright 2002 Integrated Device Technology, Inc.
3422 + * All rights reserved.
3423 + *
3424 + * Interrupt Controller register definition.
3425 + *
3426 + * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3427 + *
3428 + * Author : ryan.holmqvist@idt.com
3429 + * Date : 20011005
3430 + * Update :
3431 + * $Log: int.h,v $
3432 + * Revision 1.3 2002/06/06 18:34:04 astichte
3433 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3434 + *
3435 + * Revision 1.2 2002/06/05 18:47:33 astichte
3436 + * Removed IDTField
3437 + *
3438 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3439 + * jba File moved from vcode/include/idt/acacia
3440 + *
3441 + *
3442 + ******************************************************************************/
3443 +
3444 +#include <asm/rc32434/types.h>
3445 +
3446 +enum
3447 +{
3448 + INT0_PhysicalAddress = 0x18038000,
3449 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
3450 +
3451 + INT0_VirtualAddress = 0xb8038000,
3452 + INT_VirtualAddress = INT0_VirtualAddress, // Default
3453 +} ;
3454 +
3455 +struct INT_s
3456 +{
3457 + U32 ipend ; //Pending interrupts. use INT?_
3458 + U32 itest ; //Test bits. use INT?_
3459 + U32 imask ; //Interrupt disabled when set. use INT?_
3460 +} ;
3461 +
3462 +enum
3463 +{
3464 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
3465 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
3466 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
3467 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
3468 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
3469 +
3470 + IPEND_count, // must be last (used in loops)
3471 + IPEND_min = IPEND2 // min IPEND (used in loops)
3472 +};
3473 +
3474 +typedef struct INTC_s
3475 +{
3476 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
3477 + U32 nmips ; // use NMIPS_
3478 +} volatile *INT_t ;
3479 +
3480 +enum
3481 +{
3482 + INT2_timer0_b = 0,
3483 + INT2_timer0_m = 0x00000001,
3484 + INT2_timer1_b = 1,
3485 + INT2_timer1_m = 0x00000002,
3486 + INT2_timer2_b = 2,
3487 + INT2_timer2_m = 0x00000004,
3488 + INT2_refresh_b = 3,
3489 + INT2_refresh_m = 0x00000008,
3490 + INT2_watchdogTimeout_b = 4,
3491 + INT2_watchdogTimeout_m = 0x00000010,
3492 + INT2_undecodedCpuWrite_b = 5,
3493 + INT2_undecodedCpuWrite_m = 0x00000020,
3494 + INT2_undecodedCpuRead_b = 6,
3495 + INT2_undecodedCpuRead_m = 0x00000040,
3496 + INT2_undecodedPciWrite_b = 7,
3497 + INT2_undecodedPciWrite_m = 0x00000080,
3498 + INT2_undecodedPciRead_b = 8,
3499 + INT2_undecodedPciRead_m = 0x00000100,
3500 + INT2_undecodedDmaWrite_b = 9,
3501 + INT2_undecodedDmaWrite_m = 0x00000200,
3502 + INT2_undecodedDmaRead_b = 10,
3503 + INT2_undecodedDmaRead_m = 0x00000400,
3504 + INT2_ipBusSlaveAckError_b = 11,
3505 + INT2_ipBusSlaveAckError_m = 0x00000800,
3506 +
3507 + INT3_dmaChannel0_b = 0,
3508 + INT3_dmaChannel0_m = 0x00000001,
3509 + INT3_dmaChannel1_b = 1,
3510 + INT3_dmaChannel1_m = 0x00000002,
3511 + INT3_dmaChannel2_b = 2,
3512 + INT3_dmaChannel2_m = 0x00000004,
3513 + INT3_dmaChannel3_b = 3,
3514 + INT3_dmaChannel3_m = 0x00000008,
3515 + INT3_dmaChannel4_b = 4,
3516 + INT3_dmaChannel4_m = 0x00000010,
3517 + INT3_dmaChannel5_b = 5,
3518 + INT3_dmaChannel5_m = 0x00000020,
3519 +
3520 + INT5_uartGeneral0_b = 0,
3521 + INT5_uartGeneral0_m = 0x00000001,
3522 + INT5_uartTxrdy0_b = 1,
3523 + INT5_uartTxrdy0_m = 0x00000002,
3524 + INT5_uartRxrdy0_b = 2,
3525 + INT5_uartRxrdy0_m = 0x00000004,
3526 + INT5_pci_b = 3,
3527 + INT5_pci_m = 0x00000008,
3528 + INT5_pciDecoupled_b = 4,
3529 + INT5_pciDecoupled_m = 0x00000010,
3530 + INT5_spi_b = 5,