eb4e46d13c1bbe8b1802f42a96fce54ed8927025
[openwrt/svn-archive/archive.git] / target / linux / s3c24xx / files-2.6.30 / drivers / video / display / jbt6k74.c
1 /* Linux kernel driver for the tpo JBT6K74-AS LCM ASIC
2 *
3 * Copyright (C) 2006-2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>,
5 * Stefan Schmidt <stefan@openmoko.org>
6 * Copyright (C) 2008 by Harald Welte <laforge@openmoko.org>
7 * All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/jbt6k74.h>
33 #include <linux/fb.h>
34 #include <linux/time.h>
35
36 enum jbt_register {
37 JBT_REG_SLEEP_IN = 0x10,
38 JBT_REG_SLEEP_OUT = 0x11,
39
40 JBT_REG_DISPLAY_OFF = 0x28,
41 JBT_REG_DISPLAY_ON = 0x29,
42
43 JBT_REG_RGB_FORMAT = 0x3a,
44 JBT_REG_QUAD_RATE = 0x3b,
45
46 JBT_REG_POWER_ON_OFF = 0xb0,
47 JBT_REG_BOOSTER_OP = 0xb1,
48 JBT_REG_BOOSTER_MODE = 0xb2,
49 JBT_REG_BOOSTER_FREQ = 0xb3,
50 JBT_REG_OPAMP_SYSCLK = 0xb4,
51 JBT_REG_VSC_VOLTAGE = 0xb5,
52 JBT_REG_VCOM_VOLTAGE = 0xb6,
53 JBT_REG_EXT_DISPL = 0xb7,
54 JBT_REG_OUTPUT_CONTROL = 0xb8,
55 JBT_REG_DCCLK_DCEV = 0xb9,
56 JBT_REG_DISPLAY_MODE1 = 0xba,
57 JBT_REG_DISPLAY_MODE2 = 0xbb,
58 JBT_REG_DISPLAY_MODE = 0xbc,
59 JBT_REG_ASW_SLEW = 0xbd,
60 JBT_REG_DUMMY_DISPLAY = 0xbe,
61 JBT_REG_DRIVE_SYSTEM = 0xbf,
62
63 JBT_REG_SLEEP_OUT_FR_A = 0xc0,
64 JBT_REG_SLEEP_OUT_FR_B = 0xc1,
65 JBT_REG_SLEEP_OUT_FR_C = 0xc2,
66 JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
67 JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
68 JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
69 JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
70
71 JBT_REG_GAMMA1_FINE_1 = 0xc7,
72 JBT_REG_GAMMA1_FINE_2 = 0xc8,
73 JBT_REG_GAMMA1_INCLINATION = 0xc9,
74 JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
75
76 /* VGA */
77 JBT_REG_BLANK_CONTROL = 0xcf,
78 JBT_REG_BLANK_TH_TV = 0xd0,
79 JBT_REG_CKV_ON_OFF = 0xd1,
80 JBT_REG_CKV_1_2 = 0xd2,
81 JBT_REG_OEV_TIMING = 0xd3,
82 JBT_REG_ASW_TIMING_1 = 0xd4,
83 JBT_REG_ASW_TIMING_2 = 0xd5,
84
85 /* QVGA */
86 JBT_REG_BLANK_CONTROL_QVGA = 0xd6,
87 JBT_REG_BLANK_TH_TV_QVGA = 0xd7,
88 JBT_REG_CKV_ON_OFF_QVGA = 0xd8,
89 JBT_REG_CKV_1_2_QVGA = 0xd9,
90 JBT_REG_OEV_TIMING_QVGA = 0xde,
91 JBT_REG_ASW_TIMING_1_QVGA = 0xdf,
92 JBT_REG_ASW_TIMING_2_QVGA = 0xe0,
93
94
95 JBT_REG_HCLOCK_VGA = 0xec,
96 JBT_REG_HCLOCK_QVGA = 0xed,
97
98 };
99
100 enum jbt_state {
101 JBT_STATE_DEEP_STANDBY,
102 JBT_STATE_SLEEP,
103 JBT_STATE_NORMAL,
104 JBT_STATE_QVGA_NORMAL,
105 };
106
107 static const char *jbt_state_names[] = {
108 [JBT_STATE_DEEP_STANDBY] = "deep-standby",
109 [JBT_STATE_SLEEP] = "sleep",
110 [JBT_STATE_NORMAL] = "normal",
111 [JBT_STATE_QVGA_NORMAL] = "qvga-normal",
112 };
113
114 struct jbt_info {
115 enum jbt_state state, normal_state;
116 struct spi_device *spi_dev;
117 struct mutex lock; /* protects tx_buf and reg_cache */
118 struct notifier_block fb_notif;
119 u16 tx_buf[8];
120 u16 reg_cache[0xEE];
121 struct timespec last_sleep;
122 };
123
124 #define JBT_COMMAND 0x000
125 #define JBT_DATA 0x100
126
127 static inline unsigned int timespec_sub_ms(struct timespec lhs,
128 struct timespec rhs)
129 {
130 struct timespec ts = timespec_sub(lhs, rhs);
131 return (ts.tv_sec * MSEC_PER_SEC) + (ts.tv_nsec / NSEC_PER_MSEC);
132 }
133
134 static int jbt_reg_write_nodata(struct jbt_info *jbt, u8 reg)
135 {
136 int rc;
137
138 jbt->tx_buf[0] = JBT_COMMAND | reg;
139 rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
140 1*sizeof(u16));
141 if (rc == 0)
142 jbt->reg_cache[reg] = 0;
143 else
144 printk(KERN_ERR"jbt_reg_write_nodata spi_write ret %d\n",
145 rc);
146
147 return rc;
148 }
149
150
151 static int jbt_reg_write(struct jbt_info *jbt, u8 reg, u8 data)
152 {
153 int rc;
154
155 jbt->tx_buf[0] = JBT_COMMAND | reg;
156 jbt->tx_buf[1] = JBT_DATA | data;
157 rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
158 2*sizeof(u16));
159 if (rc == 0)
160 jbt->reg_cache[reg] = data;
161 else
162 printk(KERN_ERR"jbt_reg_write spi_write ret %d\n", rc);
163
164 return rc;
165 }
166
167 static int jbt_reg_write16(struct jbt_info *jbt, u8 reg, u16 data)
168 {
169 int rc;
170
171 jbt->tx_buf[0] = JBT_COMMAND | reg;
172 jbt->tx_buf[1] = JBT_DATA | (data >> 8);
173 jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
174
175 rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
176 3*sizeof(u16));
177 if (rc == 0)
178 jbt->reg_cache[reg] = data;
179 else
180 printk(KERN_ERR"jbt_reg_write16 spi_write ret %d\n", rc);
181
182 return rc;
183 }
184
185 static int jbt_init_regs(struct jbt_info *jbt)
186 {
187 int rc;
188
189 dev_dbg(&jbt->spi_dev->dev, "entering %cVGA mode\n",
190 jbt->normal_state == JBT_STATE_QVGA_NORMAL ? 'Q' : ' ');
191
192 rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
193 rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
194 rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
195 rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
196 rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
197 rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
198 rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
199 rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
200 rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
201 rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
202 rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
203 rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
204 /*
205 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
206 * to avoid red / blue flicker
207 */
208 rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
209 rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
210
211 rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
212 rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
213 rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
214 rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
215 rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
216 rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
217 rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
218
219 rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
220 rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
221 rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
222 rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
223
224 if (jbt->normal_state != JBT_STATE_QVGA_NORMAL) {
225 rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
226 rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
227 rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
228
229 rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
230 rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
231
232 rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
233 rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
234 rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
235 } else {
236 rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
237 rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL_QVGA, 0x02);
238 rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV_QVGA, 0x0804);
239
240 rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF_QVGA, 0x01);
241 rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2_QVGA, 0x0008);
242
243 rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING_QVGA, 0x050a);
244 rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1_QVGA, 0x0a19);
245 rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2_QVGA, 0x0a);
246 }
247
248 return rc ? -EIO : 0;
249 }
250
251 static int standby_to_sleep(struct jbt_info *jbt)
252 {
253 int rc;
254
255 /* three times command zero */
256 rc = jbt_reg_write_nodata(jbt, 0x00);
257 mdelay(1);
258 rc |= jbt_reg_write_nodata(jbt, 0x00);
259 mdelay(1);
260 rc |= jbt_reg_write_nodata(jbt, 0x00);
261 mdelay(1);
262
263 /* deep standby out */
264 rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x11);
265 mdelay(1);
266 rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x28);
267
268 /* (re)initialize register set */
269 rc |= jbt_init_regs(jbt);
270
271 return rc ? -EIO : 0;
272 }
273
274 static int sleep_to_normal(struct jbt_info *jbt)
275 {
276 int rc;
277
278 /* Make sure we are 120 ms after SLEEP_OUT */
279 unsigned int sleep_time = timespec_sub_ms(current_kernel_time(),
280 jbt->last_sleep);
281 if (sleep_time < 120)
282 mdelay(120 - sleep_time);
283
284 if (jbt->normal_state == JBT_STATE_NORMAL) {
285 /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
286 rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
287
288 /* Quad mode off */
289 rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
290 } else {
291 /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
292 rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x81);
293
294 /* Quad mode on */
295 rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x22);
296 }
297
298 /* AVDD on, XVDD on */
299 rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
300
301 /* Output control */
302 rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
303
304 /* Turn on display */
305 rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
306
307 /* Sleep mode off */
308 rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
309 jbt->last_sleep = current_kernel_time();
310
311 /* Allow the booster and display controller to restart stably */
312 mdelay(5);
313
314 return rc ? -EIO : 0;
315 }
316
317 static int normal_to_sleep(struct jbt_info *jbt)
318 {
319 int rc;
320
321 /* Make sure we are 120 ms after SLEEP_OUT */
322 unsigned int sleep_time = timespec_sub_ms(current_kernel_time(),
323 jbt->last_sleep);
324 if (sleep_time < 120)
325 mdelay(120 - sleep_time);
326
327 rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
328 rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
329 rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
330 jbt->last_sleep = current_kernel_time();
331
332 /* Allow the internal circuits to stop automatically */
333 mdelay(5);
334
335 return rc ? -EIO : 0;
336 }
337
338 static int sleep_to_standby(struct jbt_info *jbt)
339 {
340 return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
341 }
342
343 /* frontend function */
344 int jbt6k74_enter_state(struct jbt_info *jbt, enum jbt_state new_state)
345 {
346 int rc = -EINVAL;
347
348 /* dev_dbg(&jbt->spi_dev->dev, "entering (old_state=%s, new_state=%s)\n",
349 jbt_state_names[jbt->state],
350 jbt_state_names[new_state]);*/
351
352 /* printk("entering (old_state=%s, new_state=%s)\n",
353 jbt_state_names[jbt->state],
354 jbt_state_names[new_state]);*/
355
356 mutex_lock(&jbt->lock);
357
358 if (new_state == JBT_STATE_NORMAL ||
359 new_state == JBT_STATE_QVGA_NORMAL)
360 jbt->normal_state = new_state;
361
362 switch (jbt->state) {
363 case JBT_STATE_DEEP_STANDBY:
364 switch (new_state) {
365 case JBT_STATE_DEEP_STANDBY:
366 rc = 0;
367 break;
368 case JBT_STATE_SLEEP:
369 rc = standby_to_sleep(jbt);
370 break;
371 case JBT_STATE_NORMAL:
372 /* first transition into sleep */
373 rc = standby_to_sleep(jbt);
374 /* then transition into normal */
375 rc |= sleep_to_normal(jbt);
376 break;
377 case JBT_STATE_QVGA_NORMAL:
378 /* first transition into sleep */
379 rc = standby_to_sleep(jbt);
380 /* then transition into normal */
381 rc |= sleep_to_normal(jbt);
382 break;
383 }
384 break;
385 case JBT_STATE_SLEEP:
386 switch (new_state) {
387 case JBT_STATE_SLEEP:
388 rc = 0;
389 break;
390 case JBT_STATE_DEEP_STANDBY:
391 rc = sleep_to_standby(jbt);
392 break;
393 case JBT_STATE_NORMAL:
394 case JBT_STATE_QVGA_NORMAL:
395 rc = sleep_to_normal(jbt);
396 break;
397 }
398 break;
399 case JBT_STATE_NORMAL:
400 switch (new_state) {
401 case JBT_STATE_NORMAL:
402 rc = 0;
403 break;
404 case JBT_STATE_DEEP_STANDBY:
405 /* first transition into sleep */
406 rc = normal_to_sleep(jbt);
407 /* then transition into deep standby */
408 rc |= sleep_to_standby(jbt);
409 break;
410 case JBT_STATE_SLEEP:
411 rc = normal_to_sleep(jbt);
412 break;
413 case JBT_STATE_QVGA_NORMAL:
414 /* first transition into sleep */
415 rc = normal_to_sleep(jbt);
416 /* second transition into deep standby */
417 rc |= sleep_to_standby(jbt);
418 /* third transition into sleep */
419 rc |= standby_to_sleep(jbt);
420 /* fourth transition into normal */
421 rc |= sleep_to_normal(jbt);
422 break;
423 }
424 break;
425 case JBT_STATE_QVGA_NORMAL:
426 switch (new_state) {
427 case JBT_STATE_QVGA_NORMAL:
428 rc = 0;
429 break;
430 case JBT_STATE_DEEP_STANDBY:
431 /* first transition into sleep */
432 rc = normal_to_sleep(jbt);
433 /* then transition into deep standby */
434 rc |= sleep_to_standby(jbt);
435 break;
436 case JBT_STATE_SLEEP:
437 rc = normal_to_sleep(jbt);
438 break;
439 case JBT_STATE_NORMAL:
440 /* first transition into sleep */
441 rc = normal_to_sleep(jbt);
442 /* second transition into deep standby */
443 rc |= sleep_to_standby(jbt);
444 /* third transition into sleep */
445 rc |= standby_to_sleep(jbt);
446 /* fourth transition into normal */
447 rc |= sleep_to_normal(jbt);
448 break;
449 }
450 break;
451 }
452
453 if (rc == 0)
454 jbt->state = new_state;
455 else
456 dev_err(&jbt->spi_dev->dev, "Failed enter state '%s')\n",
457 jbt_state_names[new_state]);
458
459 mutex_unlock(&jbt->lock);
460
461 return rc;
462 }
463 EXPORT_SYMBOL_GPL(jbt6k74_enter_state);
464
465 static ssize_t state_read(struct device *dev, struct device_attribute *attr,
466 char *buf)
467 {
468 struct jbt_info *jbt = dev_get_drvdata(dev);
469
470 if (jbt->state >= ARRAY_SIZE(jbt_state_names))
471 return -EIO;
472
473 return sprintf(buf, "%s\n", jbt_state_names[jbt->state]);
474 }
475
476 static ssize_t state_write(struct device *dev, struct device_attribute *attr,
477 const char *buf, size_t count)
478 {
479 struct jbt_info *jbt = dev_get_drvdata(dev);
480 int i, rc;
481
482 for (i = 0; i < ARRAY_SIZE(jbt_state_names); i++) {
483 if (!strncmp(buf, jbt_state_names[i],
484 strlen(jbt_state_names[i]))) {
485 rc = jbt6k74_enter_state(jbt, i);
486 if (rc)
487 return rc;
488 return count;
489 }
490 }
491
492 return -EINVAL;
493 }
494
495 static DEVICE_ATTR(state, 0644, state_read, state_write);
496
497 static int reg_by_string(const char *name)
498 {
499 if (!strcmp(name, "gamma_fine1"))
500 return JBT_REG_GAMMA1_FINE_1;
501 else if (!strcmp(name, "gamma_fine2"))
502 return JBT_REG_GAMMA1_FINE_2;
503 else if (!strcmp(name, "gamma_inclination"))
504 return JBT_REG_GAMMA1_INCLINATION;
505 else
506 return JBT_REG_GAMMA1_BLUE_OFFSET;
507 }
508
509 static ssize_t gamma_read(struct device *dev, struct device_attribute *attr,
510 char *buf)
511 {
512 struct jbt_info *jbt = dev_get_drvdata(dev);
513 int reg = reg_by_string(attr->attr.name);
514 u16 val;
515
516 mutex_lock(&jbt->lock);
517 val = jbt->reg_cache[reg];
518 mutex_unlock(&jbt->lock);
519
520 return sprintf(buf, "0x%04x\n", val);
521 }
522
523 static ssize_t gamma_write(struct device *dev, struct device_attribute *attr,
524 const char *buf, size_t count)
525 {
526 struct jbt_info *jbt = dev_get_drvdata(dev);
527 int reg = reg_by_string(attr->attr.name);
528 unsigned long val = simple_strtoul(buf, NULL, 10);
529
530 dev_info(dev, "writing gama %lu\n", val & 0xff);
531
532 mutex_lock(&jbt->lock);
533 jbt_reg_write(jbt, reg, val & 0xff);
534 mutex_unlock(&jbt->lock);
535
536 return count;
537 }
538
539 static ssize_t reset_write(struct device *dev, struct device_attribute *attr,
540 const char *buf, size_t count)
541 {
542 int rc;
543 struct jbt_info *jbt = dev_get_drvdata(dev);
544 struct jbt6k74_platform_data *pdata = jbt->spi_dev->dev.platform_data;
545
546 dev_info(dev, "reset\n");
547
548 mutex_lock(&jbt->lock);
549
550 jbt->state = JBT_STATE_DEEP_STANDBY;
551
552 /* hard reset the jbt6k74 */
553 (pdata->reset)(0, 0);
554 mdelay(1);
555 (pdata->reset)(0, 1);
556 mdelay(120);
557
558 rc = jbt_reg_write_nodata(jbt, 0x01);
559 if (rc < 0)
560 dev_err(&jbt->spi_dev->dev, "cannot soft reset\n");
561 mdelay(120);
562
563 mutex_unlock(&jbt->lock);
564
565 jbt6k74_enter_state(jbt, jbt->normal_state);
566
567 return count;
568 }
569
570 static DEVICE_ATTR(gamma_fine1, 0644, gamma_read, gamma_write);
571 static DEVICE_ATTR(gamma_fine2, 0644, gamma_read, gamma_write);
572 static DEVICE_ATTR(gamma_inclination, 0644, gamma_read, gamma_write);
573 static DEVICE_ATTR(gamma_blue_offset, 0644, gamma_read, gamma_write);
574 static DEVICE_ATTR(reset, 0600, NULL, reset_write);
575
576 static struct attribute *jbt_sysfs_entries[] = {
577 &dev_attr_state.attr,
578 &dev_attr_gamma_fine1.attr,
579 &dev_attr_gamma_fine2.attr,
580 &dev_attr_gamma_inclination.attr,
581 &dev_attr_gamma_blue_offset.attr,
582 &dev_attr_reset.attr,
583 NULL,
584 };
585
586 static struct attribute_group jbt_attr_group = {
587 .name = NULL,
588 .attrs = jbt_sysfs_entries,
589 };
590
591 static int fb_notifier_callback(struct notifier_block *self,
592 unsigned long event, void *data)
593 {
594 struct jbt_info *jbt;
595 struct fb_event *evdata = data;
596 int fb_blank;
597
598 jbt = container_of(self, struct jbt_info, fb_notif);
599
600 dev_dbg(&jbt->spi_dev->dev, "event=%lu\n", event);
601
602 if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
603 return 0;
604
605 fb_blank = *(int *)evdata->data;
606 switch (fb_blank) {
607 case FB_BLANK_UNBLANK:
608 dev_dbg(&jbt->spi_dev->dev, "unblank\n");
609 jbt6k74_enter_state(jbt, jbt->normal_state);
610 break;
611 case FB_BLANK_NORMAL:
612 dev_dbg(&jbt->spi_dev->dev, "blank\n");
613 break;
614 case FB_BLANK_VSYNC_SUSPEND:
615 dev_dbg(&jbt->spi_dev->dev, "vsync suspend\n");
616 break;
617 case FB_BLANK_HSYNC_SUSPEND:
618 dev_dbg(&jbt->spi_dev->dev, "hsync suspend\n");
619 break;
620 case FB_BLANK_POWERDOWN:
621 dev_dbg(&jbt->spi_dev->dev, "powerdown\n");
622 jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
623 break;
624 }
625
626 return 0;
627 }
628
629 /* linux device model infrastructure */
630
631 static int __devinit jbt_probe(struct spi_device *spi)
632 {
633 int rc;
634 struct jbt_info *jbt;
635 struct jbt6k74_platform_data *pdata = spi->dev.platform_data;
636
637 /* the controller doesn't have a MISO pin; we can't do detection */
638
639 spi->mode = SPI_CPOL | SPI_CPHA;
640 spi->bits_per_word = 9;
641
642 rc = spi_setup(spi);
643 if (rc < 0) {
644 dev_err(&spi->dev,
645 "error during spi_setup of jbt6k74 driver\n");
646 return rc;
647 }
648
649 jbt = kzalloc(sizeof(*jbt), GFP_KERNEL);
650 if (!jbt)
651 return -ENOMEM;
652
653 jbt->spi_dev = spi;
654 jbt->normal_state = JBT_STATE_NORMAL;
655 jbt->state = JBT_STATE_DEEP_STANDBY;
656 jbt->last_sleep = current_kernel_time();
657 mutex_init(&jbt->lock);
658
659 dev_set_drvdata(&spi->dev, jbt);
660
661 rc = jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
662 if (rc < 0) {
663 dev_err(&spi->dev, "cannot enter NORMAL state\n");
664 goto err_free_drvdata;
665 }
666
667 rc = sysfs_create_group(&spi->dev.kobj, &jbt_attr_group);
668 if (rc < 0) {
669 dev_err(&spi->dev, "cannot create sysfs group\n");
670 goto err_standby;
671 }
672
673 jbt->fb_notif.notifier_call = fb_notifier_callback;
674 rc = fb_register_client(&jbt->fb_notif);
675 if (rc < 0) {
676 dev_err(&spi->dev, "cannot register notifier\n");
677 goto err_sysfs;
678 }
679
680 if (pdata->probe_completed)
681 (pdata->probe_completed)(&spi->dev);
682
683 return 0;
684
685 err_sysfs:
686 sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
687 err_standby:
688 jbt6k74_enter_state(jbt, JBT_STATE_DEEP_STANDBY);
689 err_free_drvdata:
690 dev_set_drvdata(&spi->dev, NULL);
691 kfree(jbt);
692
693 return rc;
694 }
695
696 static int __devexit jbt_remove(struct spi_device *spi)
697 {
698 struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
699
700 /* We don't want to switch off the display in case the user
701 * accidentially onloads the module (whose use count normally is 0) */
702 jbt6k74_enter_state(jbt, jbt->normal_state);
703
704 fb_unregister_client(&jbt->fb_notif);
705 sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
706 dev_set_drvdata(&spi->dev, NULL);
707 kfree(jbt);
708
709 return 0;
710 }
711
712 #ifdef CONFIG_PM
713 static int jbt_suspend(struct spi_device *spi, pm_message_t state)
714 {
715 struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
716
717 jbt6k74_enter_state(jbt, JBT_STATE_DEEP_STANDBY);
718
719 dev_info(&spi->dev, "suspended\n");
720
721 return 0;
722 }
723
724 int jbt6k74_resume(struct spi_device *spi)
725 {
726 struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
727 struct jbt6k74_platform_data *pdata = spi->dev.platform_data;
728
729 jbt6k74_enter_state(jbt, jbt->normal_state);
730
731 if (pdata->resuming)
732 (pdata->resuming)(0);
733
734 dev_info(&spi->dev, "resumed\n");
735
736 return 0;
737 }
738 EXPORT_SYMBOL_GPL(jbt6k74_resume);
739
740 #else
741 #define jbt_suspend NULL
742 #define jbt6k74_resume NULL
743 #endif
744
745 static struct spi_driver jbt6k74_driver = {
746 .driver = {
747 .name = "jbt6k74",
748 .owner = THIS_MODULE,
749 },
750
751 .probe = jbt_probe,
752 .remove = __devexit_p(jbt_remove),
753 .suspend = jbt_suspend,
754 .resume = jbt6k74_resume,
755 };
756
757 static int __init jbt_init(void)
758 {
759 return spi_register_driver(&jbt6k74_driver);
760 }
761
762 static void __exit jbt_exit(void)
763 {
764 spi_unregister_driver(&jbt6k74_driver);
765 }
766
767 MODULE_DESCRIPTION("SPI driver for tpo JBT6K74-AS LCM control interface");
768 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
769 MODULE_LICENSE("GPL");
770
771 module_init(jbt_init);
772 module_exit(jbt_exit);