3d31f27118f35326f054177c5c210e7f9a383733
[openwrt/svn-archive/archive.git] / target / linux / s3c24xx / patches-2.6.30 / 010-s3c-dma.patch
1 --- a/arch/arm/mach-s3c2410/include/mach/dma.h
2 +++ b/arch/arm/mach-s3c2410/include/mach/dma.h
3 @@ -3,7 +3,7 @@
4 * Copyright (C) 2003,2004,2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 - * Samsung S3C241XX DMA support
8 + * Samsung S3C24XX DMA support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 @@ -13,8 +13,8 @@
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
15
16 +#include <plat/dma.h>
17 #include <linux/sysdev.h>
18 -#include <mach/hardware.h>
19
20 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
21
22 @@ -55,9 +55,9 @@ enum dma_ch {
23
24 /* we have 4 dma channels */
25 #ifndef CONFIG_CPU_S3C2443
26 -#define S3C2410_DMA_CHANNELS (4)
27 +#define S3C_DMA_CHANNELS (4)
28 #else
29 -#define S3C2410_DMA_CHANNELS (6)
30 +#define S3C_DMA_CHANNELS (6)
31 #endif
32
33 /* types */
34 @@ -68,7 +68,6 @@ enum s3c2410_dma_state {
35 S3C2410_DMA_PAUSED
36 };
37
38 -
39 /* enum s3c2410_dma_loadst
40 *
41 * This represents the state of the DMA engine, wrt to the loaded / running
42 @@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
43 S3C2410_DMALOAD_1LOADED_1RUNNING,
44 };
45
46 -enum s3c2410_dma_buffresult {
47 - S3C2410_RES_OK,
48 - S3C2410_RES_ERR,
49 - S3C2410_RES_ABORT
50 -};
51 -
52 -enum s3c2410_dmasrc {
53 - S3C2410_DMASRC_HW, /* source is memory */
54 - S3C2410_DMASRC_MEM /* source is hardware */
55 -};
56 -
57 -/* enum s3c2410_chan_op
58 - *
59 - * operation codes passed to the DMA code by the user, and also used
60 - * to inform the current channel owner of any changes to the system state
61 -*/
62 -
63 -enum s3c2410_chan_op {
64 - S3C2410_DMAOP_START,
65 - S3C2410_DMAOP_STOP,
66 - S3C2410_DMAOP_PAUSE,
67 - S3C2410_DMAOP_RESUME,
68 - S3C2410_DMAOP_FLUSH,
69 - S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
70 - S3C2410_DMAOP_STARTED, /* indicate channel started */
71 -};
72
73 /* flags */
74
75 @@ -137,19 +110,18 @@ enum s3c2410_chan_op {
76 * waiting for reloads */
77 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
78
79 +#define S3C2410_DMAF_CIRCULAR (0x00) /* circular enqueue not supp. */
80 +
81 /* dma buffer */
82
83 -struct s3c2410_dma_client {
84 - char *name;
85 -};
86 +struct s3c2410_dma_buf;
87
88 -/* s3c2410_dma_buf_s
89 +/* s3c2410_dma_buf
90 *
91 * internally used buffer structure to describe a queued or running
92 * buffer.
93 */
94
95 -struct s3c2410_dma_buf;
96 struct s3c2410_dma_buf {
97 struct s3c2410_dma_buf *next;
98 int magic; /* magic */
99 @@ -161,20 +133,6 @@ struct s3c2410_dma_buf {
100
101 /* [1] is this updated for both recv/send modes? */
102
103 -struct s3c2410_dma_chan;
104 -
105 -/* s3c2410_dma_cbfn_t
106 - *
107 - * buffer callback routine type
108 -*/
109 -
110 -typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
111 - void *buf, int size,
112 - enum s3c2410_dma_buffresult result);
113 -
114 -typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
115 - enum s3c2410_chan_op );
116 -
117 struct s3c2410_dma_stats {
118 unsigned long loads;
119 unsigned long timeout_longest;
120 @@ -206,10 +164,10 @@ struct s3c2410_dma_chan {
121
122 /* channel configuration */
123 enum s3c2410_dmasrc source;
124 + enum dma_ch req_ch;
125 unsigned long dev_addr;
126 unsigned long load_timeout;
127 unsigned int flags; /* channel flags */
128 - unsigned int hw_cfg; /* last hw config */
129
130 struct s3c24xx_dma_map *map; /* channel hw maps */
131
132 @@ -236,213 +194,12 @@ struct s3c2410_dma_chan {
133 struct sys_device dev;
134 };
135
136 -/* the currently allocated channel information */
137 -extern struct s3c2410_dma_chan s3c2410_chans[];
138 -
139 -/* note, we don't really use dma_device_t at the moment */
140 typedef unsigned long dma_device_t;
141
142 -/* functions --------------------------------------------------------------- */
143 -
144 -/* s3c2410_dma_request
145 - *
146 - * request a dma channel exclusivley
147 -*/
148 -
149 -extern int s3c2410_dma_request(unsigned int channel,
150 - struct s3c2410_dma_client *, void *dev);
151 -
152 -
153 -/* s3c2410_dma_ctrl
154 - *
155 - * change the state of the dma channel
156 -*/
157 -
158 -extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
159 -
160 -/* s3c2410_dma_setflags
161 - *
162 - * set the channel's flags to a given state
163 -*/
164 -
165 -extern int s3c2410_dma_setflags(unsigned int channel,
166 - unsigned int flags);
167 -
168 -/* s3c2410_dma_free
169 - *
170 - * free the dma channel (will also abort any outstanding operations)
171 -*/
172 -
173 -extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
174 -
175 -/* s3c2410_dma_enqueue
176 - *
177 - * place the given buffer onto the queue of operations for the channel.
178 - * The buffer must be allocated from dma coherent memory, or the Dcache/WB
179 - * drained before the buffer is given to the DMA system.
180 -*/
181 -
182 -extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
183 - dma_addr_t data, int size);
184 -
185 -/* s3c2410_dma_config
186 - *
187 - * configure the dma channel
188 -*/
189 -
190 -extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
191 -
192 -/* s3c2410_dma_devconfig
193 - *
194 - * configure the device we're talking to
195 -*/
196 -
197 -extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
198 - int hwcfg, unsigned long devaddr);
199 -
200 -/* s3c2410_dma_getposition
201 - *
202 - * get the position that the dma transfer is currently at
203 -*/
204 -
205 -extern int s3c2410_dma_getposition(unsigned int channel,
206 - dma_addr_t *src, dma_addr_t *dest);
207 -
208 -extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
209 -extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
210 -
211 -/* DMA Register definitions */
212 -
213 -#define S3C2410_DMA_DISRC (0x00)
214 -#define S3C2410_DMA_DISRCC (0x04)
215 -#define S3C2410_DMA_DIDST (0x08)
216 -#define S3C2410_DMA_DIDSTC (0x0C)
217 -#define S3C2410_DMA_DCON (0x10)
218 -#define S3C2410_DMA_DSTAT (0x14)
219 -#define S3C2410_DMA_DCSRC (0x18)
220 -#define S3C2410_DMA_DCDST (0x1C)
221 -#define S3C2410_DMA_DMASKTRIG (0x20)
222 -#define S3C2412_DMA_DMAREQSEL (0x24)
223 -#define S3C2443_DMA_DMAREQSEL (0x24)
224 -
225 -#define S3C2410_DISRCC_INC (1<<0)
226 -#define S3C2410_DISRCC_APB (1<<1)
227 -
228 -#define S3C2410_DMASKTRIG_STOP (1<<2)
229 -#define S3C2410_DMASKTRIG_ON (1<<1)
230 -#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
231 -
232 -#define S3C2410_DCON_DEMAND (0<<31)
233 -#define S3C2410_DCON_HANDSHAKE (1<<31)
234 -#define S3C2410_DCON_SYNC_PCLK (0<<30)
235 -#define S3C2410_DCON_SYNC_HCLK (1<<30)
236 -
237 -#define S3C2410_DCON_INTREQ (1<<29)
238 -
239 -#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
240 -#define S3C2410_DCON_CH0_UART0 (1<<24)
241 -#define S3C2410_DCON_CH0_SDI (2<<24)
242 -#define S3C2410_DCON_CH0_TIMER (3<<24)
243 -#define S3C2410_DCON_CH0_USBEP1 (4<<24)
244 -
245 -#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
246 -#define S3C2410_DCON_CH1_UART1 (1<<24)
247 -#define S3C2410_DCON_CH1_I2SSDI (2<<24)
248 -#define S3C2410_DCON_CH1_SPI (3<<24)
249 -#define S3C2410_DCON_CH1_USBEP2 (4<<24)
250 -
251 -#define S3C2410_DCON_CH2_I2SSDO (0<<24)
252 -#define S3C2410_DCON_CH2_I2SSDI (1<<24)
253 -#define S3C2410_DCON_CH2_SDI (2<<24)
254 -#define S3C2410_DCON_CH2_TIMER (3<<24)
255 -#define S3C2410_DCON_CH2_USBEP3 (4<<24)
256 -
257 -#define S3C2410_DCON_CH3_UART2 (0<<24)
258 -#define S3C2410_DCON_CH3_SDI (1<<24)
259 -#define S3C2410_DCON_CH3_SPI (2<<24)
260 -#define S3C2410_DCON_CH3_TIMER (3<<24)
261 -#define S3C2410_DCON_CH3_USBEP4 (4<<24)
262 -
263 -#define S3C2410_DCON_SRCSHIFT (24)
264 -#define S3C2410_DCON_SRCMASK (7<<24)
265 -
266 -#define S3C2410_DCON_BYTE (0<<20)
267 -#define S3C2410_DCON_HALFWORD (1<<20)
268 -#define S3C2410_DCON_WORD (2<<20)
269 -
270 -#define S3C2410_DCON_AUTORELOAD (0<<22)
271 -#define S3C2410_DCON_NORELOAD (1<<22)
272 -#define S3C2410_DCON_HWTRIG (1<<23)
273 -
274 -#ifdef CONFIG_CPU_S3C2440
275 -#define S3C2440_DIDSTC_CHKINT (1<<2)
276 -
277 -#define S3C2440_DCON_CH0_I2SSDO (5<<24)
278 -#define S3C2440_DCON_CH0_PCMIN (6<<24)
279 -
280 -#define S3C2440_DCON_CH1_PCMOUT (5<<24)
281 -#define S3C2440_DCON_CH1_SDI (6<<24)
282 -
283 -#define S3C2440_DCON_CH2_PCMIN (5<<24)
284 -#define S3C2440_DCON_CH2_MICIN (6<<24)
285 -
286 -#define S3C2440_DCON_CH3_MICIN (5<<24)
287 -#define S3C2440_DCON_CH3_PCMOUT (6<<24)
288 -#endif
289 -
290 -#ifdef CONFIG_CPU_S3C2412
291 -
292 -#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
293 -
294 -#define S3C2412_DMAREQSEL_HW (1)
295 -
296 -#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
297 -#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
298 -#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
299 -#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
300 -#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
301 -#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
302 -#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
303 -#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
304 -#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
305 -#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
306 -#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
307 -#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
308 -#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
309 -#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
310 -#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
311 -#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
312 -#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
313 -#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
314 -#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
315 -#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
316 -
317 -#endif
318 -
319 -#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
320 -
321 -#define S3C2443_DMAREQSEL_HW (1)
322
323 -#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
324 -#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
325 -#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
326 -#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
327 -#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
328 -#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
329 -#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
330 -#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
331 -#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
332 -#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
333 -#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
334 -#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
335 -#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
336 -#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
337 -#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
338 -#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
339 -#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
340 -#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
341 -#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
342 -#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
343 -#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
344 +static int s3c_dma_has_circular(void)
345 +{
346 + return 0;
347 +}
348
349 #endif /* __ASM_ARCH_DMA_H */
350 --- a/arch/arm/mach-s3c2442/Kconfig
351 +++ b/arch/arm/mach-s3c2442/Kconfig
352 @@ -11,6 +11,7 @@ config CPU_S3C2442
353 select S3C2410_CLOCK
354 select S3C2410_GPIO
355 select S3C2410_PM if PM
356 + select S3C2440_DMA if S3C2410_DMA
357 select CPU_S3C244X
358 select CPU_LLSERIAL_S3C2440
359 help
360 --- /dev/null
361 +++ b/arch/arm/plat-s3c/dma.c
362 @@ -0,0 +1,86 @@
363 +/* linux/arch/arm/plat-s3c/dma.c
364 + *
365 + * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
366 + * Ben Dooks <ben@simtec.co.uk>
367 + * http://armlinux.simtec.co.uk/
368 + *
369 + * S3C DMA core
370 + *
371 + * This program is free software; you can redistribute it and/or modify
372 + * it under the terms of the GNU General Public License version 2 as
373 + * published by the Free Software Foundation.
374 +*/
375 +
376 +struct s3c2410_dma_buf;
377 +
378 +#include <linux/kernel.h>
379 +#include <linux/module.h>
380 +#include <linux/errno.h>
381 +
382 +#include <mach/dma.h>
383 +#include <mach/irqs.h>
384 +
385 +#include <plat/dma-plat.h>
386 +
387 +/* dma channel state information */
388 +struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
389 +struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
390 +
391 +/* s3c_dma_lookup_channel
392 + *
393 + * change the dma channel number given into a real dma channel id
394 +*/
395 +
396 +struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
397 +{
398 + if (channel & DMACH_LOW_LEVEL)
399 + return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
400 + else
401 + return s3c_dma_chan_map[channel];
402 +}
403 +
404 +/* do we need to protect the settings of the fields from
405 + * irq?
406 +*/
407 +
408 +int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
409 +{
410 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
411 +
412 + if (chan == NULL)
413 + return -EINVAL;
414 +
415 + pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
416 +
417 + chan->op_fn = rtn;
418 +
419 + return 0;
420 +}
421 +EXPORT_SYMBOL(s3c2410_dma_set_opfn);
422 +
423 +int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
424 +{
425 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
426 +
427 + if (chan == NULL)
428 + return -EINVAL;
429 +
430 + pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
431 +
432 + chan->callback_fn = rtn;
433 +
434 + return 0;
435 +}
436 +EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
437 +
438 +int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
439 +{
440 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
441 +
442 + if (chan == NULL)
443 + return -EINVAL;
444 +
445 + chan->flags = flags;
446 + return 0;
447 +}
448 +EXPORT_SYMBOL(s3c2410_dma_setflags);
449 --- /dev/null
450 +++ b/arch/arm/plat-s3c/include/plat/dma-core.h
451 @@ -0,0 +1,22 @@
452 +/* arch/arm/plat-s3c/include/plat/dma.h
453 + *
454 + * Copyright 2008 Openmoko, Inc.
455 + * Copyright 2008 Simtec Electronics
456 + * Ben Dooks <ben@simtec.co.uk>
457 + * http://armlinux.simtec.co.uk/
458 + *
459 + * Samsung S3C DMA core support
460 + *
461 + * This program is free software; you can redistribute it and/or modify
462 + * it under the terms of the GNU General Public License version 2 as
463 + * published by the Free Software Foundation.
464 +*/
465 +
466 +extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
467 +
468 +extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
469 +
470 +/* the currently allocated channel information */
471 +extern struct s3c2410_dma_chan s3c2410_chans[];
472 +
473 +
474 --- /dev/null
475 +++ b/arch/arm/plat-s3c/include/plat/dma.h
476 @@ -0,0 +1,128 @@
477 +/* arch/arm/plat-s3c/include/plat/dma.h
478 + *
479 + * Copyright (C) 2003,2004,2006 Simtec Electronics
480 + * Ben Dooks <ben@simtec.co.uk>
481 + *
482 + * Samsung S3C DMA support
483 + *
484 + * This program is free software; you can redistribute it and/or modify
485 + * it under the terms of the GNU General Public License version 2 as
486 + * published by the Free Software Foundation.
487 +*/
488 +
489 +enum s3c2410_dma_buffresult {
490 + S3C2410_RES_OK,
491 + S3C2410_RES_ERR,
492 + S3C2410_RES_ABORT
493 +};
494 +
495 +enum s3c2410_dmasrc {
496 + S3C2410_DMASRC_HW, /* source is memory */
497 + S3C2410_DMASRC_MEM /* source is hardware */
498 +};
499 +
500 +/* enum s3c2410_chan_op
501 + *
502 + * operation codes passed to the DMA code by the user, and also used
503 + * to inform the current channel owner of any changes to the system state
504 +*/
505 +
506 +enum s3c2410_chan_op {
507 + S3C2410_DMAOP_START,
508 + S3C2410_DMAOP_STOP,
509 + S3C2410_DMAOP_PAUSE,
510 + S3C2410_DMAOP_RESUME,
511 + S3C2410_DMAOP_FLUSH,
512 + S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
513 + S3C2410_DMAOP_STARTED, /* indicate channel started */
514 +};
515 +
516 +struct s3c2410_dma_client {
517 + char *name;
518 +};
519 +
520 +struct s3c2410_dma_chan;
521 +
522 +/* s3c2410_dma_cbfn_t
523 + *
524 + * buffer callback routine type
525 +*/
526 +
527 +typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
528 + void *buf, int size,
529 + enum s3c2410_dma_buffresult result);
530 +
531 +typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
532 + enum s3c2410_chan_op );
533 +
534 +
535 +
536 +/* s3c2410_dma_request
537 + *
538 + * request a dma channel exclusivley
539 +*/
540 +
541 +extern int s3c2410_dma_request(unsigned int channel,
542 + struct s3c2410_dma_client *, void *dev);
543 +
544 +
545 +/* s3c2410_dma_ctrl
546 + *
547 + * change the state of the dma channel
548 +*/
549 +
550 +extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
551 +
552 +/* s3c2410_dma_setflags
553 + *
554 + * set the channel's flags to a given state
555 +*/
556 +
557 +extern int s3c2410_dma_setflags(unsigned int channel,
558 + unsigned int flags);
559 +
560 +/* s3c2410_dma_free
561 + *
562 + * free the dma channel (will also abort any outstanding operations)
563 +*/
564 +
565 +extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
566 +
567 +/* s3c2410_dma_enqueue
568 + *
569 + * place the given buffer onto the queue of operations for the channel.
570 + * The buffer must be allocated from dma coherent memory, or the Dcache/WB
571 + * drained before the buffer is given to the DMA system.
572 +*/
573 +
574 +extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
575 + dma_addr_t data, int size);
576 +
577 +
578 +/* s3c2410_dma_config
579 + *
580 + * configure the dma channel
581 +*/
582 +
583 +extern int s3c2410_dma_config(unsigned int channel, int xferunit);
584 +
585 +/* s3c2410_dma_devconfig
586 + *
587 + * configure the device we're talking to
588 +*/
589 +
590 +extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
591 + unsigned long devaddr);
592 +
593 +/* s3c2410_dma_getposition
594 + *
595 + * get the position that the dma transfer is currently at
596 +*/
597 +
598 +extern int s3c2410_dma_getposition(unsigned int channel,
599 + dma_addr_t *src, dma_addr_t *dest);
600 +
601 +extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
602 +extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
603 +
604 +
605 --- a/arch/arm/plat-s3c/Kconfig
606 +++ b/arch/arm/plat-s3c/Kconfig
607 @@ -150,6 +150,13 @@ config S3C_GPIO_CFG_S3C64XX
608 Internal configuration to enable S3C64XX style GPIO configuration
609 functions.
610
611 +# DMA
612 +
613 +config S3C_DMA
614 + bool
615 + help
616 + Internal configuration for S3C DMA core
617 +
618 # device definitions to compile in
619
620 config S3C_DEV_HSMMC
621 --- a/arch/arm/plat-s3c/Makefile
622 +++ b/arch/arm/plat-s3c/Makefile
623 @@ -18,6 +18,10 @@ obj-y += pwm-clock.o
624 obj-y += gpio.o
625 obj-y += gpio-config.o
626
627 +# DMA support
628 +
629 +obj-$(CONFIG_S3C_DMA) += dma.o
630 +
631 # PM support
632
633 obj-$(CONFIG_PM) += pm.o
634 @@ -31,3 +35,5 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmm
635 obj-y += dev-i2c0.o
636 obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
637 obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
638 +obj-$(CONFIG_S3C_DMA) += dma.o
639 +
640 --- a/arch/arm/plat-s3c24xx/dma.c
641 +++ b/arch/arm/plat-s3c24xx/dma.c
642 @@ -31,10 +31,11 @@
643 #include <asm/irq.h>
644 #include <mach/hardware.h>
645 #include <mach/dma.h>
646 -
647 #include <mach/map.h>
648
649 -#include <plat/dma.h>
650 +#include <plat/dma-core.h>
651 +#include <plat/regs-dma.h>
652 +#include <plat/dma-plat.h>
653
654 /* io map for dma */
655 static void __iomem *dma_base;
656 @@ -44,8 +45,6 @@ static int dma_channels;
657
658 static struct s3c24xx_dma_selection dma_sel;
659
660 -/* dma channel state information */
661 -struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
662
663 /* debugging functions */
664
665 @@ -135,21 +134,6 @@ dmadbg_showregs(const char *fname, int l
666 #define dbg_showchan(chan) do { } while(0)
667 #endif /* CONFIG_S3C2410_DMA_DEBUG */
668
669 -static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
670 -
671 -/* lookup_dma_channel
672 - *
673 - * change the dma channel number given into a real dma channel id
674 -*/
675 -
676 -static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
677 -{
678 - if (channel & DMACH_LOW_LEVEL)
679 - return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
680 - else
681 - return dma_chan_map[channel];
682 -}
683 -
684 /* s3c2410_dma_stats_timeout
685 *
686 * Update DMA stats from timeout info
687 @@ -214,8 +198,6 @@ s3c2410_dma_waitforload(struct s3c2410_d
688 return 0;
689 }
690
691 -
692 -
693 /* s3c2410_dma_loadbuffer
694 *
695 * load a buffer, and update the channel state
696 @@ -453,7 +435,7 @@ s3c2410_dma_canload(struct s3c2410_dma_c
697 int s3c2410_dma_enqueue(unsigned int channel, void *id,
698 dma_addr_t data, int size)
699 {
700 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
701 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
702 struct s3c2410_dma_buf *buf;
703 unsigned long flags;
704
705 @@ -804,7 +786,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
706
707 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
708 {
709 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
710 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
711 unsigned long flags;
712
713 if (chan == NULL)
714 @@ -836,7 +818,7 @@ int s3c2410_dma_free(unsigned int channe
715 chan->irq_claimed = 0;
716
717 if (!(channel & DMACH_LOW_LEVEL))
718 - dma_chan_map[channel] = NULL;
719 + s3c_dma_chan_map[channel] = NULL;
720
721 local_irq_restore(flags);
722
723 @@ -995,7 +977,7 @@ static int s3c2410_dma_started(struct s3
724 int
725 s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
726 {
727 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
728 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
729
730 if (chan == NULL)
731 return -EINVAL;
732 @@ -1038,14 +1020,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
733 /* s3c2410_dma_config
734 *
735 * xfersize: size of unit in bytes (1,2,4)
736 - * dcon: base value of the DCONx register
737 */
738
739 int s3c2410_dma_config(unsigned int channel,
740 - int xferunit,
741 - int dcon)
742 + int xferunit)
743 {
744 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
745 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
746 + unsigned int dcon;
747
748 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
749 __func__, channel, xferunit, dcon);
750 @@ -1055,10 +1036,33 @@ int s3c2410_dma_config(unsigned int chan
751
752 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
753
754 - dcon |= chan->dcon & dma_sel.dcon_mask;
755 + dcon = chan->dcon & dma_sel.dcon_mask;
756
757 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
758
759 + switch (chan->req_ch) {
760 + case DMACH_I2S_IN:
761 + case DMACH_I2S_OUT:
762 + case DMACH_PCM_IN:
763 + case DMACH_PCM_OUT:
764 + case DMACH_MIC_IN:
765 + default:
766 + dcon |= S3C2410_DCON_HANDSHAKE;
767 + dcon |= S3C2410_DCON_SYNC_PCLK;
768 + break;
769 +
770 + case DMACH_SDI:
771 + /* note, ensure if need HANDSHAKE or not */
772 + dcon |= S3C2410_DCON_SYNC_PCLK;
773 + break;
774 +
775 + case DMACH_XD0:
776 + case DMACH_XD1:
777 + dcon |= S3C2410_DCON_HANDSHAKE;
778 + dcon |= S3C2410_DCON_SYNC_HCLK;
779 + break;
780 + }
781 +
782 switch (xferunit) {
783 case 1:
784 dcon |= S3C2410_DCON_BYTE;
785 @@ -1089,10 +1093,10 @@ int s3c2410_dma_config(unsigned int chan
786 }
787
788 EXPORT_SYMBOL(s3c2410_dma_config);
789 -
790 +#if 0 /* moved to plat-s3c? */
791 int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
792 {
793 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
794 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
795
796 if (chan == NULL)
797 return -EINVAL;
798 @@ -1105,43 +1109,7 @@ int s3c2410_dma_setflags(unsigned int ch
799 }
800
801 EXPORT_SYMBOL(s3c2410_dma_setflags);
802 -
803 -
804 -/* do we need to protect the settings of the fields from
805 - * irq?
806 -*/
807 -
808 -int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
809 -{
810 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
811 -
812 - if (chan == NULL)
813 - return -EINVAL;
814 -
815 - pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
816 -
817 - chan->op_fn = rtn;
818 -
819 - return 0;
820 -}
821 -
822 -EXPORT_SYMBOL(s3c2410_dma_set_opfn);
823 -
824 -int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
825 -{
826 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
827 -
828 - if (chan == NULL)
829 - return -EINVAL;
830 -
831 - pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
832 -
833 - chan->callback_fn = rtn;
834 -
835 - return 0;
836 -}
837 -
838 -EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
839 +#endif
840
841 /* s3c2410_dma_devconfig
842 *
843 @@ -1150,29 +1118,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_f
844 * source: S3C2410_DMASRC_HW: source is hardware
845 * S3C2410_DMASRC_MEM: source is memory
846 *
847 - * hwcfg: the value for xxxSTCn register,
848 - * bit 0: 0=increment pointer, 1=leave pointer
849 - * bit 1: 0=source is AHB, 1=source is APB
850 - *
851 * devaddr: physical address of the source
852 */
853
854 int s3c2410_dma_devconfig(int channel,
855 enum s3c2410_dmasrc source,
856 - int hwcfg,
857 unsigned long devaddr)
858 {
859 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
860 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
861 + unsigned int hwcfg;
862
863 if (chan == NULL)
864 return -EINVAL;
865
866 - pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
867 - __func__, (int)source, hwcfg, devaddr);
868 + pr_debug("%s: source=%d, devaddr=%08lx\n",
869 + __func__, (int)source, devaddr);
870
871 chan->source = source;
872 chan->dev_addr = devaddr;
873 - chan->hw_cfg = hwcfg;
874 +
875 + switch (chan->req_ch) {
876 + case DMACH_XD0:
877 + case DMACH_XD1:
878 + hwcfg = 0; /* AHB */
879 + break;
880 +
881 + default:
882 + hwcfg = S3C2410_DISRCC_APB;
883 + }
884 +
885 + /* always assume our peripheral desintation is a fixed
886 + * address in memory. */
887 + hwcfg |= S3C2410_DISRCC_INC;
888
889 switch (source) {
890 case S3C2410_DMASRC_HW:
891 @@ -1219,7 +1196,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
892
893 int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
894 {
895 - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
896 + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
897
898 if (chan == NULL)
899 return -EINVAL;
900 @@ -1278,8 +1255,8 @@ static int s3c2410_dma_resume(struct sys
901
902 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
903
904 - s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
905 - s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
906 + s3c2410_dma_config(no, cp->xfer_unit);
907 + s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
908
909 /* re-select the dma source for this channel */
910
911 @@ -1476,7 +1453,8 @@ static struct s3c2410_dma_chan *s3c2410_
912 found:
913 dmach = &s3c2410_chans[ch];
914 dmach->map = ch_map;
915 - dma_chan_map[channel] = dmach;
916 + dmach->req_ch = channel;
917 + s3c_dma_chan_map[channel] = dmach;
918
919 /* select the channel */
920
921 --- a/arch/arm/plat-s3c24xx/include/plat/dma.h
922 +++ /dev/null
923 @@ -1,82 +0,0 @@
924 -/* linux/include/asm-arm/plat-s3c24xx/dma.h
925 - *
926 - * Copyright (C) 2006 Simtec Electronics
927 - * Ben Dooks <ben@simtec.co.uk>
928 - *
929 - * Samsung S3C24XX DMA support
930 - *
931 - * This program is free software; you can redistribute it and/or modify
932 - * it under the terms of the GNU General Public License version 2 as
933 - * published by the Free Software Foundation.
934 -*/
935 -
936 -extern struct sysdev_class dma_sysclass;
937 -extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
938 -
939 -#define DMA_CH_VALID (1<<31)
940 -#define DMA_CH_NEVER (1<<30)
941 -
942 -struct s3c24xx_dma_addr {
943 - unsigned long from;
944 - unsigned long to;
945 -};
946 -
947 -/* struct s3c24xx_dma_map
948 - *
949 - * this holds the mapping information for the channel selected
950 - * to be connected to the specified device
951 -*/
952 -
953 -struct s3c24xx_dma_map {
954 - const char *name;
955 - struct s3c24xx_dma_addr hw_addr;
956 -
957 - unsigned long channels[S3C2410_DMA_CHANNELS];
958 - unsigned long channels_rx[S3C2410_DMA_CHANNELS];
959 -};
960 -
961 -struct s3c24xx_dma_selection {
962 - struct s3c24xx_dma_map *map;
963 - unsigned long map_size;
964 - unsigned long dcon_mask;
965 -
966 - void (*select)(struct s3c2410_dma_chan *chan,
967 - struct s3c24xx_dma_map *map);
968 -
969 - void (*direction)(struct s3c2410_dma_chan *chan,
970 - struct s3c24xx_dma_map *map,
971 - enum s3c2410_dmasrc dir);
972 -};
973 -
974 -extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
975 -
976 -/* struct s3c24xx_dma_order_ch
977 - *
978 - * channel map for one of the `enum dma_ch` dma channels. the list
979 - * entry contains a set of low-level channel numbers, orred with
980 - * DMA_CH_VALID, which are checked in the order in the array.
981 -*/
982 -
983 -struct s3c24xx_dma_order_ch {
984 - unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
985 - unsigned int flags; /* flags */
986 -};
987 -
988 -/* struct s3c24xx_dma_order
989 - *
990 - * information provided by either the core or the board to give the
991 - * dma system a hint on how to allocate channels
992 -*/
993 -
994 -struct s3c24xx_dma_order {
995 - struct s3c24xx_dma_order_ch channels[DMACH_MAX];
996 -};
997 -
998 -extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
999 -
1000 -/* DMA init code, called from the cpu support code */
1001 -
1002 -extern int s3c2410_dma_init(void);
1003 -
1004 -extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1005 - unsigned int stride);
1006 --- /dev/null
1007 +++ b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
1008 @@ -0,0 +1,84 @@
1009 +/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
1010 + *
1011 + * Copyright (C) 2006 Simtec Electronics
1012 + * Ben Dooks <ben@simtec.co.uk>
1013 + *
1014 + * Samsung S3C24XX DMA support
1015 + *
1016 + * This program is free software; you can redistribute it and/or modify
1017 + * it under the terms of the GNU General Public License version 2 as
1018 + * published by the Free Software Foundation.
1019 +*/
1020 +
1021 +#include <plat/dma-core.h>
1022 +
1023 +extern struct sysdev_class dma_sysclass;
1024 +extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
1025 +
1026 +#define DMA_CH_VALID (1<<31)
1027 +#define DMA_CH_NEVER (1<<30)
1028 +
1029 +struct s3c24xx_dma_addr {
1030 + unsigned long from;
1031 + unsigned long to;
1032 +};
1033 +
1034 +/* struct s3c24xx_dma_map
1035 + *
1036 + * this holds the mapping information for the channel selected
1037 + * to be connected to the specified device
1038 +*/
1039 +
1040 +struct s3c24xx_dma_map {
1041 + const char *name;
1042 + struct s3c24xx_dma_addr hw_addr;
1043 +
1044 + unsigned long channels[S3C_DMA_CHANNELS];
1045 + unsigned long channels_rx[S3C_DMA_CHANNELS];
1046 +};
1047 +
1048 +struct s3c24xx_dma_selection {
1049 + struct s3c24xx_dma_map *map;
1050 + unsigned long map_size;
1051 + unsigned long dcon_mask;
1052 +
1053 + void (*select)(struct s3c2410_dma_chan *chan,
1054 + struct s3c24xx_dma_map *map);
1055 +
1056 + void (*direction)(struct s3c2410_dma_chan *chan,
1057 + struct s3c24xx_dma_map *map,
1058 + enum s3c2410_dmasrc dir);
1059 +};
1060 +
1061 +extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
1062 +
1063 +/* struct s3c24xx_dma_order_ch
1064 + *
1065 + * channel map for one of the `enum dma_ch` dma channels. the list
1066 + * entry contains a set of low-level channel numbers, orred with
1067 + * DMA_CH_VALID, which are checked in the order in the array.
1068 +*/
1069 +
1070 +struct s3c24xx_dma_order_ch {
1071 + unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
1072 + unsigned int flags; /* flags */
1073 +};
1074 +
1075 +/* struct s3c24xx_dma_order
1076 + *
1077 + * information provided by either the core or the board to give the
1078 + * dma system a hint on how to allocate channels
1079 +*/
1080 +
1081 +struct s3c24xx_dma_order {
1082 + struct s3c24xx_dma_order_ch channels[DMACH_MAX];
1083 +};
1084 +
1085 +extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
1086 +
1087 +/* DMA init code, called from the cpu support code */
1088 +
1089 +extern int s3c2410_dma_init(void);
1090 +
1091 +extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1092 + unsigned int stride);
1093 --- /dev/null
1094 +++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
1095 @@ -0,0 +1,145 @@
1096 +/* arch/arm/mach-s3c2410/include/mach/dma.h
1097 + *
1098 + * Copyright (C) 2003,2004,2006 Simtec Electronics
1099 + * Ben Dooks <ben@simtec.co.uk>
1100 + *
1101 + * Samsung S3C24XX DMA support
1102 + *
1103 + * This program is free software; you can redistribute it and/or modify
1104 + * it under the terms of the GNU General Public License version 2 as
1105 + * published by the Free Software Foundation.
1106 +*/
1107 +
1108 +/* DMA Register definitions */
1109 +
1110 +#define S3C2410_DMA_DISRC (0x00)
1111 +#define S3C2410_DMA_DISRCC (0x04)
1112 +#define S3C2410_DMA_DIDST (0x08)
1113 +#define S3C2410_DMA_DIDSTC (0x0C)
1114 +#define S3C2410_DMA_DCON (0x10)
1115 +#define S3C2410_DMA_DSTAT (0x14)
1116 +#define S3C2410_DMA_DCSRC (0x18)
1117 +#define S3C2410_DMA_DCDST (0x1C)
1118 +#define S3C2410_DMA_DMASKTRIG (0x20)
1119 +#define S3C2412_DMA_DMAREQSEL (0x24)
1120 +#define S3C2443_DMA_DMAREQSEL (0x24)
1121 +
1122 +#define S3C2410_DISRCC_INC (1<<0)
1123 +#define S3C2410_DISRCC_APB (1<<1)
1124 +
1125 +#define S3C2410_DMASKTRIG_STOP (1<<2)
1126 +#define S3C2410_DMASKTRIG_ON (1<<1)
1127 +#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
1128 +
1129 +#define S3C2410_DCON_DEMAND (0<<31)
1130 +#define S3C2410_DCON_HANDSHAKE (1<<31)
1131 +#define S3C2410_DCON_SYNC_PCLK (0<<30)
1132 +#define S3C2410_DCON_SYNC_HCLK (1<<30)
1133 +
1134 +#define S3C2410_DCON_INTREQ (1<<29)
1135 +
1136 +#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
1137 +#define S3C2410_DCON_CH0_UART0 (1<<24)
1138 +#define S3C2410_DCON_CH0_SDI (2<<24)
1139 +#define S3C2410_DCON_CH0_TIMER (3<<24)
1140 +#define S3C2410_DCON_CH0_USBEP1 (4<<24)
1141 +
1142 +#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
1143 +#define S3C2410_DCON_CH1_UART1 (1<<24)
1144 +#define S3C2410_DCON_CH1_I2SSDI (2<<24)
1145 +#define S3C2410_DCON_CH1_SPI (3<<24)
1146 +#define S3C2410_DCON_CH1_USBEP2 (4<<24)
1147 +
1148 +#define S3C2410_DCON_CH2_I2SSDO (0<<24)
1149 +#define S3C2410_DCON_CH2_I2SSDI (1<<24)
1150 +#define S3C2410_DCON_CH2_SDI (2<<24)
1151 +#define S3C2410_DCON_CH2_TIMER (3<<24)
1152 +#define S3C2410_DCON_CH2_USBEP3 (4<<24)
1153 +
1154 +#define S3C2410_DCON_CH3_UART2 (0<<24)
1155 +#define S3C2410_DCON_CH3_SDI (1<<24)
1156 +#define S3C2410_DCON_CH3_SPI (2<<24)
1157 +#define S3C2410_DCON_CH3_TIMER (3<<24)
1158 +#define S3C2410_DCON_CH3_USBEP4 (4<<24)
1159 +
1160 +#define S3C2410_DCON_SRCSHIFT (24)
1161 +#define S3C2410_DCON_SRCMASK (7<<24)
1162 +
1163 +#define S3C2410_DCON_BYTE (0<<20)
1164 +#define S3C2410_DCON_HALFWORD (1<<20)
1165 +#define S3C2410_DCON_WORD (2<<20)
1166 +
1167 +#define S3C2410_DCON_AUTORELOAD (0<<22)
1168 +#define S3C2410_DCON_NORELOAD (1<<22)
1169 +#define S3C2410_DCON_HWTRIG (1<<23)
1170 +
1171 +#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1172 +#define S3C2440_DIDSTC_CHKINT (1<<2)
1173 +
1174 +#define S3C2440_DCON_CH0_I2SSDO (5<<24)
1175 +#define S3C2440_DCON_CH0_PCMIN (6<<24)
1176 +
1177 +#define S3C2440_DCON_CH1_PCMOUT (5<<24)
1178 +#define S3C2440_DCON_CH1_SDI (6<<24)
1179 +
1180 +#define S3C2440_DCON_CH2_PCMIN (5<<24)
1181 +#define S3C2440_DCON_CH2_MICIN (6<<24)
1182 +
1183 +#define S3C2440_DCON_CH3_MICIN (5<<24)
1184 +#define S3C2440_DCON_CH3_PCMOUT (6<<24)
1185 +#endif
1186 +
1187 +#ifdef CONFIG_CPU_S3C2412
1188 +
1189 +#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
1190 +
1191 +#define S3C2412_DMAREQSEL_HW (1)
1192 +
1193 +#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
1194 +#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
1195 +#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
1196 +#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
1197 +#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
1198 +#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
1199 +#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
1200 +#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
1201 +#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
1202 +#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
1203 +#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
1204 +#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
1205 +#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
1206 +#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
1207 +#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
1208 +#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
1209 +#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
1210 +#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
1211 +#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
1212 +#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
1213 +
1214 +#endif
1215 +
1216 +#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
1217 +
1218 +#define S3C2443_DMAREQSEL_HW (1)
1219 +
1220 +#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
1221 +#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
1222 +#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
1223 +#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
1224 +#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
1225 +#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
1226 +#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
1227 +#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
1228 +#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
1229 +#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
1230 +#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
1231 +#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
1232 +#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
1233 +#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
1234 +#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
1235 +#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
1236 +#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
1237 +#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
1238 +#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
1239 +#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
1240 +#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
1241 --- a/arch/arm/plat-s3c24xx/Kconfig
1242 +++ b/arch/arm/plat-s3c24xx/Kconfig
1243 @@ -71,6 +71,7 @@ config PM_SIMTEC
1244 config S3C2410_DMA
1245 bool "S3C2410 DMA support"
1246 depends on ARCH_S3C2410
1247 + select S3C_DMA
1248 help
1249 S3C2410 DMA support. This is needed for drivers like sound which
1250 use the S3C2410's DMA system to move data to and from the
1251 --- a/arch/arm/mach-s3c2410/dma.c
1252 +++ b/arch/arm/mach-s3c2410/dma.c
1253 @@ -17,14 +17,16 @@
1254 #include <linux/sysdev.h>
1255 #include <linux/serial_core.h>
1256
1257 +#include <mach/map.h>
1258 #include <mach/dma.h>
1259
1260 #include <plat/cpu.h>
1261 -#include <plat/dma.h>
1262 +#include <plat/dma-plat.h>
1263
1264 #include <plat/regs-serial.h>
1265 #include <mach/regs-gpio.h>
1266 #include <plat/regs-ac97.h>
1267 +#include <plat/regs-dma.h>
1268 #include <mach/regs-mem.h>
1269 #include <mach/regs-lcd.h>
1270 #include <mach/regs-sdi.h>
1271 --- a/arch/arm/mach-s3c2440/dma.c
1272 +++ b/arch/arm/mach-s3c2440/dma.c
1273 @@ -17,14 +17,16 @@
1274 #include <linux/sysdev.h>
1275 #include <linux/serial_core.h>
1276
1277 +#include <mach/map.h>
1278 #include <mach/dma.h>
1279
1280 -#include <plat/dma.h>
1281 +#include <plat/dma-plat.h>
1282 #include <plat/cpu.h>
1283
1284 #include <plat/regs-serial.h>
1285 #include <mach/regs-gpio.h>
1286 #include <plat/regs-ac97.h>
1287 +#include <plat/regs-dma.h>
1288 #include <mach/regs-mem.h>
1289 #include <mach/regs-lcd.h>
1290 #include <mach/regs-sdi.h>