target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch

   1 From 95c1fe603fbea0fd01d98262bd5ff7d5442a86db Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Mon, 24 Feb 2014 17:29:06 +0100
   4 Subject: [PATCH] ARM: sun6i: dt: Fix mod0 compatible
   5
   6 The module 0 clock compatibles were changed between the time the patch was sent
   7 and it was merged. Update the compatibles.
   8
   9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  10 ---
  11  arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++----
  12  1 file changed, 4 insertions(+), 4 deletions(-)
  13
  14 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
  15 index af6f87c..42f310a 100644
  16 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  17 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  18 @@ -200,7 +200,7 @@
  19
  20                 spi0_clk: clk@01c200a0 {
  21                         #clock-cells = <0>;
  22 -                       compatible = "allwinner,sun4i-mod0-clk";
  23 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
  24                         reg = <0x01c200a0 0x4>;
  25                         clocks = <&osc24M>, <&pll6>;
  26                         clock-output-names = "spi0";
  27 @@ -208,7 +208,7 @@
  28
  29                 spi1_clk: clk@01c200a4 {
  30                         #clock-cells = <0>;
  31 -                       compatible = "allwinner,sun4i-mod0-clk";
  32 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
  33                         reg = <0x01c200a4 0x4>;
  34                         clocks = <&osc24M>, <&pll6>;
  35                         clock-output-names = "spi1";
  36 @@ -216,7 +216,7 @@
  37
  38                 spi2_clk: clk@01c200a8 {
  39                         #clock-cells = <0>;
  40 -                       compatible = "allwinner,sun4i-mod0-clk";
  41 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
  42                         reg = <0x01c200a8 0x4>;
  43                         clocks = <&osc24M>, <&pll6>;
  44                         clock-output-names = "spi2";
  45 @@ -224,7 +224,7 @@
  46
  47                 spi3_clk: clk@01c200ac {
  48                         #clock-cells = <0>;
  49 -                       compatible = "allwinner,sun4i-mod0-clk";
  50 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
  51                         reg = <0x01c200ac 0x4>;
  52                         clocks = <&osc24M>, <&pll6>;
  53                         clock-output-names = "spi3";
  54 --
  55 2.0.3
  56