target/linux/sunxi/patches-3.14/184-clk-sunxi-add-pll6-on-a31.patch

   1 From c225f78660cd61914f25dd00499c7ae71d1d6919 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 5 Feb 2014 14:05:03 +0100
   4 Subject: [PATCH] clk: sunxi: Add support for PLL6 on the A31
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The A31 has a slightly different PLL6 clock. Add support for this new clock in
  10 our driver.
  11
  12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  14 ---
  15  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
  16  drivers/clk/sunxi/clk-sunxi.c                     | 45 +++++++++++++++++++++++
  17  2 files changed, 46 insertions(+)
  18
  19 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
  20 index ca2b692..c37c764 100644
  21 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  22 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  23 @@ -11,6 +11,7 @@ Required properties:
  24         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  25         "allwinner,sun4i-pll5-clk" - for the PLL5 clock
  26         "allwinner,sun4i-pll6-clk" - for the PLL6 clock
  27 +       "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
  28         "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
  29         "allwinner,sun4i-axi-clk" - for the AXI clock
  30         "allwinner,sun4i-axi-gates-clk" - for the AXI gates
  31 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  32 index a779c31..d4cf297 100644
  33 --- a/drivers/clk/sunxi/clk-sunxi.c
  34 +++ b/drivers/clk/sunxi/clk-sunxi.c
  35 @@ -252,7 +252,38 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
  36         *n = DIV_ROUND_UP(div, (*k+1));
  37  }
  38
  39 +/**
  40 + * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
  41 + * PLL6 rate is calculated as follows
  42 + * rate = parent_rate * n * (k + 1) / 2
  43 + * parent_rate is always 24Mhz
  44 + */
  45 +
  46 +static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
  47 +                                      u8 *n, u8 *k, u8 *m, u8 *p)
  48 +{
  49 +       u8 div;
  50 +
  51 +       /*
  52 +        * We always have 24MHz / 2, so we can just say that our
  53 +        * parent clock is 12MHz.
  54 +        */
  55 +       parent_rate = parent_rate / 2;
  56 +
  57 +       /* Normalize value to a parent_rate multiple (24M / 2) */
  58 +       div = *freq / parent_rate;
  59 +       *freq = parent_rate * div;
  60 +
  61 +       /* we were called to round the frequency, we can now return */
  62 +       if (n == NULL)
  63 +               return;
  64 +
  65 +       *k = div / 32;
  66 +       if (*k > 3)
  67 +               *k = 3;
  68
  69 +       *n = DIV_ROUND_UP(div, (*k+1));
  70 +}
  71
  72  /**
  73   * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  74 @@ -420,6 +451,13 @@ static struct clk_factors_config sun4i_pll5_config = {
  75         .kwidth = 2,
  76  };
  77
  78 +static struct clk_factors_config sun6i_a31_pll6_config = {
  79 +       .nshift = 8,
  80 +       .nwidth = 5,
  81 +       .kshift = 4,
  82 +       .kwidth = 2,
  83 +};
  84 +
  85  static struct clk_factors_config sun4i_apb1_config = {
  86         .mshift = 0,
  87         .mwidth = 5,
  88 @@ -469,6 +507,12 @@ static const struct factors_data sun4i_pll6_data __initconst = {
  89         .name = "pll6",
  90  };
  91
  92 +static const struct factors_data sun6i_a31_pll6_data __initconst = {
  93 +       .enable = 31,
  94 +       .table = &sun6i_a31_pll6_config,
  95 +       .getter = sun6i_a31_get_pll6_factors,
  96 +};
  97 +
  98  static const struct factors_data sun4i_apb1_data __initconst = {
  99         .table = &sun4i_apb1_config,
 100         .getter = sun4i_get_apb1_factors,
 101 @@ -1069,6 +1113,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 102  static const struct of_device_id clk_factors_match[] __initconst = {
 103         {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
 104         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 105 +       {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 106         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 107         {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
 108         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 109 --
 110 2.0.3
 111