kernel: update 3.18 to 3.18.14
[openwrt/svn-archive/archive.git] / target / linux / sunxi / patches-3.18 / 150-pwm-add-sunxi-driver.patch
1 --- a/drivers/pwm/Kconfig
2 +++ b/drivers/pwm/Kconfig
3 @@ -263,6 +263,15 @@ config PWM_STI
4 To compile this driver as a module, choose M here: the module
5 will be called pwm-sti.
6
7 +config PWM_SUN4I
8 + tristate "Allwinner sun4i PWM support"
9 + depends on ARCH_SUNXI || COMPILE_TEST
10 + help
11 + Generic PWM framework driver for Allwinner sun4i and sun7i SoCs.
12 +
13 + To compile this driver as a module, choose M here: the module
14 + will be called pwm-sun4i.
15 +
16 config PWM_TEGRA
17 tristate "NVIDIA Tegra PWM support"
18 depends on ARCH_TEGRA
19 --- a/drivers/pwm/Makefile
20 +++ b/drivers/pwm/Makefile
21 @@ -24,6 +24,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockch
22 obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
23 obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
24 obj-$(CONFIG_PWM_STI) += pwm-sti.o
25 +obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
26 obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
27 obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
28 obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
29 --- /dev/null
30 +++ b/drivers/pwm/pwm-sun4i.c
31 @@ -0,0 +1,371 @@
32 +/*
33 + * Driver for Allwinner sun4i Pulse Width Modulation Controller
34 + *
35 + * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
36 + *
37 + * Licensed under GPLv2.
38 + */
39 +
40 +#include <linux/bitops.h>
41 +#include <linux/clk.h>
42 +#include <linux/err.h>
43 +#include <linux/io.h>
44 +#include <linux/module.h>
45 +#include <linux/mutex.h>
46 +#include <linux/of.h>
47 +#include <linux/of_device.h>
48 +#include <linux/platform_device.h>
49 +#include <linux/pwm.h>
50 +#include <linux/slab.h>
51 +#include <linux/time.h>
52 +
53 +#define PWM_CTRL_REG 0x0
54 +
55 +#define PWM_CH_PRD_BASE 0x4
56 +#define PWM_CH_PRD_OFFSET 0x4
57 +#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
58 +
59 +#define PWMCH_OFFSET 15
60 +#define PWM_PRESCAL_MASK GENMASK(3, 0)
61 +#define PWM_PRESCAL_OFF 0
62 +#define PWM_EN BIT(4)
63 +#define PWM_ACT_STATE BIT(5)
64 +#define PWM_CLK_GATING BIT(6)
65 +#define PWM_MODE BIT(7)
66 +#define PWM_PULSE BIT(8)
67 +#define PWM_BYPASS BIT(9)
68 +
69 +#define PWM_RDY_BASE 28
70 +#define PWM_RDY_OFFSET 1
71 +#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
72 +
73 +#define PWM_PRD(prd) (((prd) - 1) << 16)
74 +#define PWM_PRD_MASK GENMASK(15, 0)
75 +
76 +#define PWM_DTY_MASK GENMASK(15, 0)
77 +
78 +#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
79 +
80 +static const u32 prescaler_table[] = {
81 + 120,
82 + 180,
83 + 240,
84 + 360,
85 + 480,
86 + 0,
87 + 0,
88 + 0,
89 + 12000,
90 + 24000,
91 + 36000,
92 + 48000,
93 + 72000,
94 + 0,
95 + 0,
96 + 0, /* Actually 1 but tested separately */
97 +};
98 +
99 +struct sun4i_pwm_data {
100 + bool has_prescaler_bypass;
101 + bool has_rdy;
102 +};
103 +
104 +struct sun4i_pwm_chip {
105 + struct pwm_chip chip;
106 + struct clk *clk;
107 + void __iomem *base;
108 + struct mutex ctrl_lock;
109 + const struct sun4i_pwm_data *data;
110 +};
111 +
112 +static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
113 +{
114 + return container_of(chip, struct sun4i_pwm_chip, chip);
115 +}
116 +
117 +static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
118 + unsigned long offset)
119 +{
120 + return readl(chip->base + offset);
121 +}
122 +
123 +static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
124 + u32 val, unsigned long offset)
125 +{
126 + writel(val, chip->base + offset);
127 +}
128 +
129 +static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
130 + int duty_ns, int period_ns)
131 +{
132 + struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
133 + u32 clk_rate, prd, dty, val, clk_gate;
134 + u64 div = 0;
135 + unsigned int prescaler = 0;
136 + int err;
137 +
138 + clk_rate = clk_get_rate(sun4i_pwm->clk);
139 +
140 + if (sun4i_pwm->data->has_prescaler_bypass) {
141 + /* First, test without any prescaler when available */
142 + prescaler = PWM_PRESCAL_MASK;
143 + /*
144 + * When not using any prescaler, the clock period in nanoseconds
145 + * is not an integer so round it half up instead of
146 + * truncating to get less surprising values.
147 + */
148 + div = clk_rate * (u64)period_ns + NSEC_PER_SEC/2;
149 + do_div(div, NSEC_PER_SEC);
150 + if (div - 1 > PWM_PRD_MASK)
151 + prescaler = 0;
152 + }
153 +
154 + if (prescaler == 0) {
155 + /* Go up from the first divider */
156 + for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
157 + if (!prescaler_table[prescaler])
158 + continue;
159 + div = clk_rate / prescaler_table[prescaler];
160 + div = div * (u64)period_ns;
161 + do_div(div, NSEC_PER_SEC);
162 + if (div - 1 <= PWM_PRD_MASK)
163 + break;
164 + }
165 +
166 + if (div - 1 > PWM_PRD_MASK) {
167 + dev_err(chip->dev, "period exceeds the maximum value\n");
168 + return -EINVAL;
169 + }
170 + }
171 +
172 + prd = div;
173 + div *= duty_ns;
174 + do_div(div, period_ns);
175 + dty = div;
176 +
177 + err = clk_prepare_enable(sun4i_pwm->clk);
178 + if (err) {
179 + dev_err(chip->dev, "failed to enable PWM clock\n");
180 + return err;
181 + }
182 +
183 + mutex_lock(&sun4i_pwm->ctrl_lock);
184 + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
185 +
186 + if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
187 + mutex_unlock(&sun4i_pwm->ctrl_lock);
188 + clk_disable_unprepare(sun4i_pwm->clk);
189 + return -EBUSY;
190 + }
191 +
192 + clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
193 + if (clk_gate) {
194 + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
195 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
196 + }
197 +
198 + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
199 + val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
200 + val |= BIT_CH(prescaler, pwm->hwpwm);
201 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
202 +
203 + val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);
204 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
205 +
206 + if (clk_gate) {
207 + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
208 + val |= clk_gate;
209 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
210 + }
211 +
212 + mutex_unlock(&sun4i_pwm->ctrl_lock);
213 + clk_disable_unprepare(sun4i_pwm->clk);
214 +
215 + return 0;
216 +}
217 +
218 +static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
219 + enum pwm_polarity polarity)
220 +{
221 + struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
222 + u32 val;
223 + int ret;
224 +
225 + ret = clk_prepare_enable(sun4i_pwm->clk);
226 + if (ret) {
227 + dev_err(chip->dev, "failed to enable PWM clock\n");
228 + return ret;
229 + }
230 +
231 + mutex_lock(&sun4i_pwm->ctrl_lock);
232 + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
233 +
234 + if (polarity != PWM_POLARITY_NORMAL)
235 + val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
236 + else
237 + val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
238 +
239 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
240 +
241 + mutex_unlock(&sun4i_pwm->ctrl_lock);
242 + clk_disable_unprepare(sun4i_pwm->clk);
243 +
244 + return 0;
245 +}
246 +
247 +static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
248 +{
249 + struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
250 + u32 val;
251 + int ret;
252 +
253 + ret = clk_prepare_enable(sun4i_pwm->clk);
254 + if (ret) {
255 + dev_err(chip->dev, "failed to enable PWM clock\n");
256 + return ret;
257 + }
258 +
259 + mutex_lock(&sun4i_pwm->ctrl_lock);
260 + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
261 + val |= BIT_CH(PWM_EN, pwm->hwpwm);
262 + val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
263 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
264 + mutex_unlock(&sun4i_pwm->ctrl_lock);
265 +
266 + return 0;
267 +}
268 +
269 +static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
270 +{
271 + struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
272 + u32 val;
273 +
274 + mutex_lock(&sun4i_pwm->ctrl_lock);
275 + val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
276 + val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
277 + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
278 + sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
279 + mutex_unlock(&sun4i_pwm->ctrl_lock);
280 +
281 + clk_disable_unprepare(sun4i_pwm->clk);
282 +}
283 +
284 +static const struct pwm_ops sun4i_pwm_ops = {
285 + .config = sun4i_pwm_config,
286 + .set_polarity = sun4i_pwm_set_polarity,
287 + .enable = sun4i_pwm_enable,
288 + .disable = sun4i_pwm_disable,
289 + .owner = THIS_MODULE,
290 +};
291 +
292 +static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
293 + .has_prescaler_bypass = false,
294 + .has_rdy = false,
295 +};
296 +
297 +static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
298 + .has_prescaler_bypass = true,
299 + .has_rdy = true,
300 +};
301 +
302 +static const struct of_device_id sun4i_pwm_dt_ids[] = {
303 + {
304 + .compatible = "allwinner,sun4i-a10-pwm",
305 + .data = &sun4i_pwm_data_a10,
306 + }, {
307 + .compatible = "allwinner,sun7i-a20-pwm",
308 + .data = &sun4i_pwm_data_a20,
309 + }, {
310 + /* sentinel */
311 + },
312 +};
313 +MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
314 +
315 +static int sun4i_pwm_probe(struct platform_device *pdev)
316 +{
317 + struct sun4i_pwm_chip *pwm;
318 + struct resource *res;
319 + u32 val;
320 + int i, ret;
321 + const struct of_device_id *match;
322 +
323 + match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev);
324 +
325 + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
326 + if (!pwm)
327 + return -ENOMEM;
328 +
329 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
330 + pwm->base = devm_ioremap_resource(&pdev->dev, res);
331 + if (IS_ERR(pwm->base))
332 + return PTR_ERR(pwm->base);
333 +
334 + pwm->clk = devm_clk_get(&pdev->dev, NULL);
335 + if (IS_ERR(pwm->clk))
336 + return PTR_ERR(pwm->clk);
337 +
338 + pwm->chip.dev = &pdev->dev;
339 + pwm->chip.ops = &sun4i_pwm_ops;
340 + pwm->chip.base = -1;
341 + pwm->chip.npwm = 2;
342 + pwm->chip.can_sleep = true;
343 + pwm->chip.of_xlate = of_pwm_xlate_with_flags;
344 + pwm->chip.of_pwm_n_cells = 3;
345 + pwm->data = match->data;
346 +
347 + mutex_init(&pwm->ctrl_lock);
348 +
349 + ret = pwmchip_add(&pwm->chip);
350 + if (ret < 0) {
351 + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
352 + goto error;
353 + }
354 +
355 + platform_set_drvdata(pdev, pwm);
356 +
357 + ret = clk_prepare_enable(pwm->clk);
358 + if (ret) {
359 + dev_err(&pdev->dev, "failed to enable PWM clock\n");
360 + goto clk_error;
361 + }
362 +
363 + val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
364 + for (i = 0; i < pwm->chip.npwm; i++) {
365 + if (!(val & BIT_CH(PWM_ACT_STATE, i)))
366 + pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED;
367 + }
368 + clk_disable_unprepare(pwm->clk);
369 +
370 + return 0;
371 +
372 +clk_error:
373 + pwmchip_remove(&pwm->chip);
374 +
375 +error:
376 + mutex_destroy(&pwm->ctrl_lock);
377 + return ret;
378 +}
379 +
380 +static int sun4i_pwm_remove(struct platform_device *pdev)
381 +{
382 + struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
383 +
384 + mutex_destroy(&pwm->ctrl_lock);
385 +
386 + return pwmchip_remove(&pwm->chip);
387 +}
388 +
389 +static struct platform_driver sun4i_pwm_driver = {
390 + .driver = {
391 + .name = "sun4i-pwm",
392 + .of_match_table = sun4i_pwm_dt_ids,
393 + },
394 + .probe = sun4i_pwm_probe,
395 + .remove = sun4i_pwm_remove,
396 +};
397 +module_platform_driver(sun4i_pwm_driver);
398 +
399 +MODULE_ALIAS("platform:sun4i-pwm");
400 +MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
401 +MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
402 +MODULE_LICENSE("GPL v2");