kernel: update kernel 4.1 to version 4.1.11
[openwrt/svn-archive/archive.git] / target / linux / sunxi / patches-4.1 / 128-1-mtd-nand-store-timing-in-nand_chip.patch
1 --- a/drivers/mtd/nand/nand_base.c
2 +++ b/drivers/mtd/nand/nand_base.c
3 @@ -4249,6 +4249,8 @@ static inline bool is_full_id_nand(struc
4 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
5 struct nand_flash_dev *type, const u8 *id_data, int *busw)
6 {
7 + int mode;
8 +
9 if (!strncmp(type->id, id_data, type->id_len)) {
10 mtd->writesize = type->pagesize;
11 mtd->erasesize = type->erasesize;
12 @@ -4259,8 +4261,9 @@ static bool find_full_id_nand(struct mtd
13 chip->options |= type->options;
14 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
15 chip->ecc_step_ds = NAND_ECC_STEP(type);
16 - chip->onfi_timing_mode_default =
17 - type->onfi_timing_mode_default;
18 +
19 + mode = type->onfi_timing_mode_default;
20 + chip->sdr_timings = onfi_async_timing_mode_to_sdr_timings(mode);
21
22 *busw = type->options & NAND_BUSWIDTH_16;
23
24 --- a/drivers/mtd/nand/sunxi_nand.c
25 +++ b/drivers/mtd/nand/sunxi_nand.c
26 @@ -1425,7 +1425,7 @@ static int sunxi_nand_chip_init_timings(
27
28 mode = onfi_get_async_timing_mode(&chip->nand);
29 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
30 - mode = chip->nand.onfi_timing_mode_default;
31 + timings = chip->nand.sdr_timings;
32 } else {
33 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
34
35 @@ -1439,9 +1439,10 @@ static int sunxi_nand_chip_init_timings(
36 feature);
37 if (ret)
38 return ret;
39 +
40 + timings = onfi_async_timing_mode_to_sdr_timings(mode);
41 }
42
43 - timings = onfi_async_timing_mode_to_sdr_timings(mode);
44 if (IS_ERR(timings))
45 return PTR_ERR(timings);
46
47 --- a/include/linux/mtd/nand.h
48 +++ b/include/linux/mtd/nand.h
49 @@ -612,6 +612,55 @@ struct nand_buffers {
50 uint8_t *databuf;
51 };
52
53 +/*
54 + * struct nand_sdr_timings - SDR NAND chip timings
55 + *
56 + * This struct defines the timing requirements of a SDR NAND chip.
57 + * These informations can be found in every NAND datasheets and the timings
58 + * meaning are described in the ONFI specifications:
59 + * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
60 + * Parameters)
61 + *
62 + * All these timings are expressed in picoseconds.
63 + */
64 +
65 +struct nand_sdr_timings {
66 + u32 tALH_min;
67 + u32 tADL_min;
68 + u32 tALS_min;
69 + u32 tAR_min;
70 + u32 tCEA_max;
71 + u32 tCEH_min;
72 + u32 tCH_min;
73 + u32 tCHZ_max;
74 + u32 tCLH_min;
75 + u32 tCLR_min;
76 + u32 tCLS_min;
77 + u32 tCOH_min;
78 + u32 tCS_min;
79 + u32 tDH_min;
80 + u32 tDS_min;
81 + u32 tFEAT_max;
82 + u32 tIR_min;
83 + u32 tITC_max;
84 + u32 tRC_min;
85 + u32 tREA_max;
86 + u32 tREH_min;
87 + u32 tRHOH_min;
88 + u32 tRHW_min;
89 + u32 tRHZ_max;
90 + u32 tRLOH_min;
91 + u32 tRP_min;
92 + u32 tRR_min;
93 + u64 tRST_max;
94 + u32 tWB_max;
95 + u32 tWC_min;
96 + u32 tWH_min;
97 + u32 tWHR_min;
98 + u32 tWP_min;
99 + u32 tWW_min;
100 +};
101 +
102 /**
103 * struct nand_chip - NAND Private Flash Chip Data
104 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
105 @@ -676,11 +725,7 @@ struct nand_buffers {
106 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
107 * also from the datasheet. It is the recommended ECC step
108 * size, if known; if unknown, set to zero.
109 - * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
110 - * either deduced from the datasheet if the NAND
111 - * chip is not ONFI compliant or set to 0 if it is
112 - * (an ONFI chip is always configured in mode 0
113 - * after a NAND reset)
114 + * @sdr_timings [INTERN] Pointer to default timings for SDR NAND.
115 * @numchips: [INTERN] number of physical chips
116 * @chipsize: [INTERN] the size of one chip for multichip arrays
117 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
118 @@ -769,7 +814,7 @@ struct nand_chip {
119 uint8_t bits_per_cell;
120 uint16_t ecc_strength_ds;
121 uint16_t ecc_step_ds;
122 - int onfi_timing_mode_default;
123 + const struct nand_sdr_timings *sdr_timings;
124 int badblockpos;
125 int badblockbits;
126
127 @@ -1156,55 +1201,6 @@ struct ofnandpart_data {
128 int ofnandpart_parse(struct mtd_info *master,
129 const struct ofnandpart_data *data);
130
131 -/*
132 - * struct nand_sdr_timings - SDR NAND chip timings
133 - *
134 - * This struct defines the timing requirements of a SDR NAND chip.
135 - * These informations can be found in every NAND datasheets and the timings
136 - * meaning are described in the ONFI specifications:
137 - * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
138 - * Parameters)
139 - *
140 - * All these timings are expressed in picoseconds.
141 - */
142 -
143 -struct nand_sdr_timings {
144 - u32 tALH_min;
145 - u32 tADL_min;
146 - u32 tALS_min;
147 - u32 tAR_min;
148 - u32 tCEA_max;
149 - u32 tCEH_min;
150 - u32 tCH_min;
151 - u32 tCHZ_max;
152 - u32 tCLH_min;
153 - u32 tCLR_min;
154 - u32 tCLS_min;
155 - u32 tCOH_min;
156 - u32 tCS_min;
157 - u32 tDH_min;
158 - u32 tDS_min;
159 - u32 tFEAT_max;
160 - u32 tIR_min;
161 - u32 tITC_max;
162 - u32 tRC_min;
163 - u32 tREA_max;
164 - u32 tREH_min;
165 - u32 tRHOH_min;
166 - u32 tRHW_min;
167 - u32 tRHZ_max;
168 - u32 tRLOH_min;
169 - u32 tRP_min;
170 - u32 tRR_min;
171 - u64 tRST_max;
172 - u32 tWB_max;
173 - u32 tWC_min;
174 - u32 tWH_min;
175 - u32 tWHR_min;
176 - u32 tWP_min;
177 - u32 tWW_min;
178 -};
179 -
180 /* get timing characteristics from ONFI timing mode. */
181 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
182 #endif /* __LINUX_MTD_NAND_H */