2 * linux/include/asm-mips/mach-jz4740/regs.h
4 * Ingenic's JZ4740 common include.
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
8 * Author: <yliu@ingenic.cn>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #ifndef __JZ4740_REGS_H__
16 #define __JZ4740_REGS_H__
18 #if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
19 #define REG8(addr) (addr)
20 #define REG16(addr) (addr)
21 #define REG32(addr) (addr)
23 #define REG8(addr) *((volatile unsigned char *)(addr))
24 #define REG16(addr) *((volatile unsigned short *)(addr))
25 #define REG32(addr) *((volatile unsigned int *)(addr))
29 * Define the module base addresses
31 #define CPM_BASE 0xB0000000
32 #define INTC_BASE 0xB0001000
33 #define TCU_BASE 0xB0002000
34 #define WDT_BASE 0xB0002000
35 #define RTC_BASE 0xB0003000
36 #define GPIO_BASE 0xB0010000
37 #define AIC_BASE 0xB0020000
38 #define ICDC_BASE 0xB0020000
39 #define MSC_BASE 0xB0021000
40 #define UART0_BASE 0xB0030000
41 #define UART1_BASE 0xB0031000
42 #define I2C_BASE 0xB0042000
43 #define SSI_BASE 0xB0043000
44 #define SADC_BASE 0xB0070000
45 #define EMC_BASE 0xB3010000
46 #define DMAC_BASE 0xB3020000
47 #define UHC_BASE 0xB3030000
48 #define UDC_BASE 0xB3040000
49 #define LCD_BASE 0xB3050000
50 #define SLCD_BASE 0xB3050000
51 #define CIM_BASE 0xB3060000
52 #define IPU_BASE 0xB3080000
53 #define ETH_BASE 0xB3100000
55 /*************************************************************************
56 * CPM (Clock reset and Power control Management)
57 *************************************************************************/
58 #define CPM_CPCCR (CPM_BASE+0x00)
59 #define CPM_CPPCR (CPM_BASE+0x10)
60 #define CPM_I2SCDR (CPM_BASE+0x60)
61 #define CPM_LPCDR (CPM_BASE+0x64)
62 #define CPM_MSCCDR (CPM_BASE+0x68)
63 #define CPM_UHCCDR (CPM_BASE+0x6C)
64 #define CPM_SSICDR (CPM_BASE+0x74)
66 #define CPM_LCR (CPM_BASE+0x04)
67 #define CPM_CLKGR (CPM_BASE+0x20)
68 #define CPM_SCR (CPM_BASE+0x24)
70 #define CPM_HCR (CPM_BASE+0x30)
71 #define CPM_HWFCR (CPM_BASE+0x34)
72 #define CPM_HRCR (CPM_BASE+0x38)
73 #define CPM_HWCR (CPM_BASE+0x3c)
74 #define CPM_HWSR (CPM_BASE+0x40)
75 #define CPM_HSPR (CPM_BASE+0x44)
77 #define CPM_RSR (CPM_BASE+0x08)
79 #define REG_CPM_CPCCR REG32(CPM_CPCCR)
80 #define REG_CPM_CPPCR REG32(CPM_CPPCR)
81 #define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
82 #define REG_CPM_LPCDR REG32(CPM_LPCDR)
83 #define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
84 #define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
85 #define REG_CPM_SSICDR REG32(CPM_SSICDR)
87 #define REG_CPM_LCR REG32(CPM_LCR)
88 #define REG_CPM_CLKGR REG32(CPM_CLKGR)
89 #define REG_CPM_SCR REG32(CPM_SCR)
90 #define REG_CPM_HCR REG32(CPM_HCR)
91 #define REG_CPM_HWFCR REG32(CPM_HWFCR)
92 #define REG_CPM_HRCR REG32(CPM_HRCR)
93 #define REG_CPM_HWCR REG32(CPM_HWCR)
94 #define REG_CPM_HWSR REG32(CPM_HWSR)
95 #define REG_CPM_HSPR REG32(CPM_HSPR)
97 #define REG_CPM_RSR REG32(CPM_RSR)
99 /* Clock Control Register */
100 #define CPM_CPCCR_I2CS (1 << 31)
101 #define CPM_CPCCR_CLKOEN (1 << 30)
102 #define CPM_CPCCR_UCS (1 << 29)
103 #define CPM_CPCCR_UDIV_BIT 23
104 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
105 #define CPM_CPCCR_CE (1 << 22)
106 #define CPM_CPCCR_PCS (1 << 21)
107 #define CPM_CPCCR_LDIV_BIT 16
108 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
109 #define CPM_CPCCR_MDIV_BIT 12
110 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
111 #define CPM_CPCCR_PDIV_BIT 8
112 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
113 #define CPM_CPCCR_HDIV_BIT 4
114 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
115 #define CPM_CPCCR_CDIV_BIT 0
116 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
118 /* I2S Clock Divider Register */
119 #define CPM_I2SCDR_I2SDIV_BIT 0
120 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
122 /* LCD Pixel Clock Divider Register */
123 #define CPM_LPCDR_PIXDIV_BIT 0
124 #define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
126 /* MSC Clock Divider Register */
127 #define CPM_MSCCDR_MSCDIV_BIT 0
128 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
130 /* UHC Clock Divider Register */
131 #define CPM_UHCCDR_UHCDIV_BIT 0
132 #define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
134 /* SSI Clock Divider Register */
135 #define CPM_SSICDR_SCS (1<<31) /* SSI clock source selection, 0:EXCLK, 1: PLL */
136 #define CPM_SSICDR_SSIDIV_BIT 0
137 #define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
139 /* PLL Control Register */
140 #define CPM_CPPCR_PLLM_BIT 23
141 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
142 #define CPM_CPPCR_PLLN_BIT 18
143 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
144 #define CPM_CPPCR_PLLOD_BIT 16
145 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
146 #define CPM_CPPCR_PLLS (1 << 10)
147 #define CPM_CPPCR_PLLBP (1 << 9)
148 #define CPM_CPPCR_PLLEN (1 << 8)
149 #define CPM_CPPCR_PLLST_BIT 0
150 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
152 /* Low Power Control Register */
153 #define CPM_LCR_DOZE_DUTY_BIT 3
154 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
155 #define CPM_LCR_DOZE_ON (1 << 2)
156 #define CPM_LCR_LPM_BIT 0
157 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
158 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
159 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
161 /* Clock Gate Register */
162 #define CPM_CLKGR_UART1 (1 << 15)
163 #define CPM_CLKGR_UHC (1 << 14)
164 #define CPM_CLKGR_IPU (1 << 13)
165 #define CPM_CLKGR_DMAC (1 << 12)
166 #define CPM_CLKGR_UDC (1 << 11)
167 #define CPM_CLKGR_LCD (1 << 10)
168 #define CPM_CLKGR_CIM (1 << 9)
169 #define CPM_CLKGR_SADC (1 << 8)
170 #define CPM_CLKGR_MSC (1 << 7)
171 #define CPM_CLKGR_AIC1 (1 << 6)
172 #define CPM_CLKGR_AIC2 (1 << 5)
173 #define CPM_CLKGR_SSI (1 << 4)
174 #define CPM_CLKGR_I2C (1 << 3)
175 #define CPM_CLKGR_RTC (1 << 2)
176 #define CPM_CLKGR_TCU (1 << 1)
177 #define CPM_CLKGR_UART0 (1 << 0)
179 /* Sleep Control Register */
180 #define CPM_SCR_O1ST_BIT 8
181 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
182 #define CPM_SCR_USBPHY_ENABLE (1 << 6)
183 #define CPM_SCR_OSC_ENABLE (1 << 4)
185 /* Hibernate Control Register */
186 #define CPM_HCR_PD (1 << 0)
188 /* Wakeup Filter Counter Register in Hibernate Mode */
189 #define CPM_HWFCR_TIME_BIT 0
190 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
192 /* Reset Counter Register in Hibernate Mode */
193 #define CPM_HRCR_TIME_BIT 0
194 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
196 /* Wakeup Control Register in Hibernate Mode */
197 #define CPM_HWCR_WLE_LOW (0 << 2)
198 #define CPM_HWCR_WLE_HIGH (1 << 2)
199 #define CPM_HWCR_PIN_WAKEUP (1 << 1)
200 #define CPM_HWCR_RTC_WAKEUP (1 << 0)
202 /* Wakeup Status Register in Hibernate Mode */
203 #define CPM_HWSR_WSR_PIN (1 << 1)
204 #define CPM_HWSR_WSR_RTC (1 << 0)
206 /* Reset Status Register */
207 #define CPM_RSR_HR (1 << 2)
208 #define CPM_RSR_WR (1 << 1)
209 #define CPM_RSR_PR (1 << 0)
211 /*************************************************************************
213 *************************************************************************/
215 #define IRDA_BASE UART0_BASE
216 #define UART_BASE UART0_BASE
217 #define UART_OFF 0x1000
219 /* Register Offset */
220 #define OFF_RDR (0x00) /* R 8b H'xx */
221 #define OFF_TDR (0x00) /* W 8b H'xx */
222 #define OFF_DLLR (0x00) /* RW 8b H'00 */
223 #define OFF_DLHR (0x04) /* RW 8b H'00 */
224 #define OFF_IER (0x04) /* RW 8b H'00 */
225 #define OFF_ISR (0x08) /* R 8b H'01 */
226 #define OFF_FCR (0x08) /* W 8b H'00 */
227 #define OFF_LCR (0x0C) /* RW 8b H'00 */
228 #define OFF_MCR (0x10) /* RW 8b H'00 */
229 #define OFF_LSR (0x14) /* R 8b H'00 */
230 #define OFF_MSR (0x18) /* R 8b H'00 */
231 #define OFF_SPR (0x1C) /* RW 8b H'00 */
232 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
233 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
234 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
236 /* Register Address */
237 #define UART0_RDR (UART0_BASE + OFF_RDR)
238 #define UART0_TDR (UART0_BASE + OFF_TDR)
239 #define UART0_DLLR (UART0_BASE + OFF_DLLR)
240 #define UART0_DLHR (UART0_BASE + OFF_DLHR)
241 #define UART0_IER (UART0_BASE + OFF_IER)
242 #define UART0_ISR (UART0_BASE + OFF_ISR)
243 #define UART0_FCR (UART0_BASE + OFF_FCR)
244 #define UART0_LCR (UART0_BASE + OFF_LCR)
245 #define UART0_MCR (UART0_BASE + OFF_MCR)
246 #define UART0_LSR (UART0_BASE + OFF_LSR)
247 #define UART0_MSR (UART0_BASE + OFF_MSR)
248 #define UART0_SPR (UART0_BASE + OFF_SPR)
249 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
250 #define UART0_UMR (UART0_BASE + OFF_UMR)
251 #define UART0_UACR (UART0_BASE + OFF_UACR)
254 * Define macros for UARTIER
255 * UART Interrupt Enable Register
257 #define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
258 #define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
259 #define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
260 #define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
261 #define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
264 * Define macros for UARTISR
265 * UART Interrupt Status Register
267 #define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
268 #define UARTISR_IID (7 << 1) /* Source of Interrupt */
269 #define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
270 #define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
271 #define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
272 #define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
273 #define UARTISR_IID_RTO (6 << 1) /* Receive timeout */
274 #define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
275 #define UARTISR_FFMS_NO_FIFO (0 << 6)
276 #define UARTISR_FFMS_FIFO_MODE (3 << 6)
279 * Define macros for UARTFCR
280 * UART FIFO Control Register
282 #define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
283 #define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
284 #define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
285 #define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
286 #define UARTFCR_UUE (1 << 4) /* 0: disable UART */
287 #define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
288 #define UARTFCR_RTRG_1 (0 << 6)
289 #define UARTFCR_RTRG_4 (1 << 6)
290 #define UARTFCR_RTRG_8 (2 << 6)
291 #define UARTFCR_RTRG_15 (3 << 6)
294 * Define macros for UARTLCR
295 * UART Line Control Register
297 #define UARTLCR_WLEN (3 << 0) /* word length */
298 #define UARTLCR_WLEN_5 (0 << 0)
299 #define UARTLCR_WLEN_6 (1 << 0)
300 #define UARTLCR_WLEN_7 (2 << 0)
301 #define UARTLCR_WLEN_8 (3 << 0)
302 #define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
303 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
304 #define UARTLCR_STOP1 (0 << 2)
305 #define UARTLCR_STOP2 (1 << 2)
306 #define UARTLCR_PE (1 << 3) /* 0: parity disable */
307 #define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
308 #define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
309 #define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
310 #define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
313 * Define macros for UARTLSR
314 * UART Line Status Register
316 #define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
317 #define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
318 #define UARTLSR_PER (1 << 2) /* 0: no parity error */
319 #define UARTLSR_FER (1 << 3) /* 0; no framing error */
320 #define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
321 #define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
322 #define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
323 #define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
326 * Define macros for UARTMCR
327 * UART Modem Control Register
329 #define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */
330 #define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
331 #define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
334 * Define macros for UARTMSR
335 * UART Modem Status Register
337 #define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */
338 #define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
341 * Define macros for SIRCR
342 * Slow IrDA Control Register
344 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */
345 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */
346 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
347 1: 0 pulse width is 1.6us for 115.2Kbps */
348 #define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
349 #define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
352 /*************************************************************************
353 * EMC (External Memory Controller)
354 *************************************************************************/
355 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
356 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
357 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
358 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
359 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
360 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
361 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
362 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
363 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
364 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
366 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
367 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
368 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
369 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
370 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
371 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
372 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
373 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
374 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
375 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
376 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
377 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
379 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
380 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
381 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
382 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
383 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
384 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
387 #define REG_EMC_SMCR0 REG32(EMC_SMCR0)
388 #define REG_EMC_SMCR1 REG32(EMC_SMCR1)
389 #define REG_EMC_SMCR2 REG32(EMC_SMCR2)
390 #define REG_EMC_SMCR3 REG32(EMC_SMCR3)
391 #define REG_EMC_SMCR4 REG32(EMC_SMCR4)
392 #define REG_EMC_SACR0 REG32(EMC_SACR0)
393 #define REG_EMC_SACR1 REG32(EMC_SACR1)
394 #define REG_EMC_SACR2 REG32(EMC_SACR2)
395 #define REG_EMC_SACR3 REG32(EMC_SACR3)
396 #define REG_EMC_SACR4 REG32(EMC_SACR4)
398 #define REG_EMC_NFCSR REG32(EMC_NFCSR)
399 #define REG_EMC_NFECR REG32(EMC_NFECR)
400 #define REG_EMC_NFECC REG32(EMC_NFECC)
401 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
402 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
403 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
404 #define REG_EMC_NFINTS REG32(EMC_NFINTS)
405 #define REG_EMC_NFINTE REG32(EMC_NFINTE)
406 #define REG_EMC_NFERR0 REG32(EMC_NFERR0)
407 #define REG_EMC_NFERR1 REG32(EMC_NFERR1)
408 #define REG_EMC_NFERR2 REG32(EMC_NFERR2)
409 #define REG_EMC_NFERR3 REG32(EMC_NFERR3)
411 #define REG_EMC_DMCR REG32(EMC_DMCR)
412 #define REG_EMC_RTCSR REG16(EMC_RTCSR)
413 #define REG_EMC_RTCNT REG16(EMC_RTCNT)
414 #define REG_EMC_RTCOR REG16(EMC_RTCOR)
415 #define REG_EMC_DMAR0 REG32(EMC_DMAR0)
417 /* Static Memory Control Register */
418 #define EMC_SMCR_STRV_BIT 24
419 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
420 #define EMC_SMCR_TAW_BIT 20
421 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
422 #define EMC_SMCR_TBP_BIT 16
423 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
424 #define EMC_SMCR_TAH_BIT 12
425 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
426 #define EMC_SMCR_TAS_BIT 8
427 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
428 #define EMC_SMCR_BW_BIT 6
429 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
430 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
431 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
432 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
433 #define EMC_SMCR_BCM (1 << 3)
434 #define EMC_SMCR_BL_BIT 1
435 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
436 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
437 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
438 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
439 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
440 #define EMC_SMCR_SMT (1 << 0)
442 /* Static Memory Bank Addr Config Reg */
443 #define EMC_SACR_BASE_BIT 8
444 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
445 #define EMC_SACR_MASK_BIT 0
446 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
448 /* NAND Flash Control/Status Register */
449 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
450 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
451 #define EMC_NFCSR_NFCE3 (1 << 5)
452 #define EMC_NFCSR_NFE3 (1 << 4)
453 #define EMC_NFCSR_NFCE2 (1 << 3)
454 #define EMC_NFCSR_NFE2 (1 << 2)
455 #define EMC_NFCSR_NFCE1 (1 << 1)
456 #define EMC_NFCSR_NFE1 (1 << 0)
458 /* NAND Flash ECC Control Register */
459 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
460 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
461 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
462 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
463 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
464 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
465 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
467 /* NAND Flash ECC Data Register */
468 #define EMC_NFECC_ECC2_BIT 16
469 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
470 #define EMC_NFECC_ECC1_BIT 8
471 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
472 #define EMC_NFECC_ECC0_BIT 0
473 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
475 /* NAND Flash Interrupt Status Register */
476 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
477 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
478 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
479 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
480 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
481 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
482 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
484 /* NAND Flash Interrupt Enable Register */
485 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
486 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
487 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
488 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
489 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
491 /* NAND Flash RS Error Report Register */
492 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
493 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
494 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
495 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
498 /* DRAM Control Register */
499 #define EMC_DMCR_BW_BIT 31
500 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
501 #define EMC_DMCR_CA_BIT 26
502 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
503 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
504 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
505 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
506 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
507 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
508 #define EMC_DMCR_RMODE (1 << 25)
509 #define EMC_DMCR_RFSH (1 << 24)
510 #define EMC_DMCR_MRSET (1 << 23)
511 #define EMC_DMCR_RA_BIT 20
512 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
513 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
514 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
515 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
516 #define EMC_DMCR_BA_BIT 19
517 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
518 #define EMC_DMCR_PDM (1 << 18)
519 #define EMC_DMCR_EPIN (1 << 17)
520 #define EMC_DMCR_TRAS_BIT 13
521 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
522 #define EMC_DMCR_RCD_BIT 11
523 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
524 #define EMC_DMCR_TPC_BIT 8
525 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
526 #define EMC_DMCR_TRWL_BIT 5
527 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
528 #define EMC_DMCR_TRC_BIT 2
529 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
530 #define EMC_DMCR_TCL_BIT 0
531 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
533 /* Refresh Time Control/Status Register */
534 #define EMC_RTCSR_CMF (1 << 7)
535 #define EMC_RTCSR_CKS_BIT 0
536 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
537 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
538 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
539 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
540 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
541 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
542 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
543 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
544 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
546 /* SDRAM Bank Address Configuration Register */
547 #define EMC_DMAR_BASE_BIT 8
548 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
549 #define EMC_DMAR_MASK_BIT 0
550 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
552 /* Mode Register of SDRAM bank 0 */
553 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
554 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */
555 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
556 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
557 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
558 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
559 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
560 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
561 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
562 #define EMC_SDMR_BT_BIT 3 /* Burst Type */
563 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
564 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
565 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
566 #define EMC_SDMR_BL_BIT 0 /* Burst Length */
567 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
568 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
569 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
570 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
571 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
573 #define EMC_SDMR_CAS2_16BIT \
574 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
575 #define EMC_SDMR_CAS2_32BIT \
576 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
577 #define EMC_SDMR_CAS3_16BIT \
578 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
579 #define EMC_SDMR_CAS3_32BIT \
580 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
582 /*************************************************************************
583 * WDT (WatchDog Timer)
584 *************************************************************************/
585 #define WDT_TDR (WDT_BASE + 0x00)
586 #define WDT_TCER (WDT_BASE + 0x04)
587 #define WDT_TCNT (WDT_BASE + 0x08)
588 #define WDT_TCSR (WDT_BASE + 0x0C)
590 #define REG_WDT_TDR REG16(WDT_TDR)
591 #define REG_WDT_TCER REG8(WDT_TCER)
592 #define REG_WDT_TCNT REG16(WDT_TCNT)
593 #define REG_WDT_TCSR REG16(WDT_TCSR)
595 // Register definition
596 #define WDT_TCSR_PRESCALE_BIT 3
597 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
598 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
599 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
600 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
601 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
602 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
603 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
604 #define WDT_TCSR_EXT_EN (1 << 2)
605 #define WDT_TCSR_RTC_EN (1 << 1)
606 #define WDT_TCSR_PCK_EN (1 << 0)
608 #define WDT_TCER_TCEN (1 << 0)
610 /*************************************************************************
612 *************************************************************************/
613 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
614 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
615 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
616 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
618 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
619 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
620 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
621 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
622 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
623 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
625 #define REG_RTC_RCR REG32(RTC_RCR)
626 #define REG_RTC_RSR REG32(RTC_RSR)
627 #define REG_RTC_RSAR REG32(RTC_RSAR)
628 #define REG_RTC_RGR REG32(RTC_RGR)
629 #define REG_RTC_HCR REG32(RTC_HCR)
630 #define REG_RTC_HWFCR REG32(RTC_HWFCR)
631 #define REG_RTC_HRCR REG32(RTC_HRCR)
632 #define REG_RTC_HWCR REG32(RTC_HWCR)
633 #define REG_RTC_HWRSR REG32(RTC_HWRSR)
634 #define REG_RTC_HSPR REG32(RTC_HSPR)
636 /* RTC Control Register */
637 #define RTC_RCR_WRDY_BIT 7
638 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
639 #define RTC_RCR_1HZ_BIT 6
640 #define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */
641 #define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */
642 #define RTC_RCR_AF_BIT 4
643 #define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */
644 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
645 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */
646 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
648 /* RTC Regulator Register */
649 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
650 #define RTC_RGR_ADJC_BIT 16
651 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
652 #define RTC_RGR_NC1HZ_BIT 0
653 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
655 /* Hibernate Control Register */
656 #define RTC_HCR_PD (1 << 0) /* Power Down */
658 /* Hibernate Wakeup Filter Counter Register */
659 #define RTC_HWFCR_BIT 5
660 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
662 /* Hibernate Reset Counter Register */
663 #define RTC_HRCR_BIT 5
664 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
666 /* Hibernate Wakeup Control Register */
667 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
669 /* Hibernate Wakeup Status Register */
670 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
671 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
672 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
673 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
675 #endif /* __JZ4740_REGS_H__ */
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