target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c

   1 /*
   2  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *      JZ4740 platform timer support
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the  GNU General Public License along
  11  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/time.h>
  19 #include <linux/clockchips.h>
  20 #include <linux/clk.h>
  21
  22 #include <asm/mach-jz4740/irq.h>
  23 #include <asm/mach-jz4740/jz4740.h>
  24 #include <asm/time.h>
  25
  26 #define JZ_REG_TIMER_STOP               0x1C
  27 #define JZ_REG_TIMER_STOP_SET           0x2C
  28 #define JZ_REG_TIMER_STOP_CLEAR         0x3C
  29 #define JZ_REG_TIMER_ENABLE             0x10
  30 #define JZ_REG_TIMER_ENABLE_SET         0x14
  31 #define JZ_REG_TIMER_ENABLE_CLEAR       0x18
  32 #define JZ_REG_TIMER_FLAG               0x20
  33 #define JZ_REG_TIMER_FLAG_SET           0x24
  34 #define JZ_REG_TIMER_FLAG_CLEAR         0x28
  35 #define JZ_REG_TIMER_MASK               0x30
  36 #define JZ_REG_TIMER_MASK_SET           0x34
  37 #define JZ_REG_TIMER_MASK_CLEAR         0x38
  38
  39 #define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
  40 #define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
  41 #define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
  42 #define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
  43
  44 #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
  45 #define JZ_TIMER_IRQ_FULL(x) BIT(x)
  46
  47 #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW    BIT(8)
  48 #define JZ_TIMER_CTRL_PWM_ENABLE        BIT(7)
  49 #define JZ_TIMER_CTRL_PRESCALE_MASK     0x1c
  50 #define JZ_TIMER_CTRL_PRESCALE_OFFSET   0x3
  51 #define JZ_TIMER_CTRL_PRESCALE_1        (0 << 3)
  52 #define JZ_TIMER_CTRL_PRESCALE_4        (1 << 3)
  53 #define JZ_TIMER_CTRL_PRESCALE_16       (2 << 3)
  54 #define JZ_TIMER_CTRL_PRESCALE_64       (3 << 3)
  55 #define JZ_TIMER_CTRL_PRESCALE_256      (4 << 3)
  56 #define JZ_TIMER_CTRL_PRESCALE_1024     (5 << 3)
  57
  58 #define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
  59 #define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
  60 #define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
  61
  62 static void __iomem *jz4740_timer_base;
  63 static uint16_t jz4740_jiffies_per_tick;
  64
  65 void jz4740_timer_enable_watchdog(void)
  66 {
  67         writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
  68 }
  69
  70 void jz4740_timer_disable_watchdog(void)
  71 {
  72         writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
  73 }
  74
  75 static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
  76 {
  77         writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
  78 }
  79
  80 static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
  81 {
  82         writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
  83 }
  84
  85 static void jz4740_init_timer(void)
  86 {
  87         uint16_t val = 0;
  88         val |= JZ_TIMER_CTRL_PRESCALE_16;
  89         val |= JZ_TIMER_CTRL_SRC_EXT;
  90
  91         writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
  92         writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
  93         writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
  94         writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
  95 }
  96
  97 static void jz4740_timer_enable(unsigned int timer)
  98 {
  99         writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
 100         writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
 101 }
 102
 103 static void jz4740_timer_disable(unsigned int timer)
 104 {
 105         writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
 106         writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
 107 }
 108
 109 static void jz4740_timer_irq_full_enable(unsigned int timer)
 110 {
 111         writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 112         writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
 113 }
 114
 115 static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
 116 {
 117         return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
 118         JZ_TIMER_IRQ_FULL(timer));
 119 }
 120
 121 static void jz4740_timer_irq_full_disable(unsigned int timer)
 122 {
 123         writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
 124 }
 125
 126 static void jz4740_timer_irq_half_enable(unsigned int timer)
 127 {
 128         writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 129         writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
 130 }
 131
 132 static void jz4740_timer_irq_half_disable(unsigned int timer)
 133 {
 134         writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
 135 }
 136
 137 static cycle_t jz4740_clocksource_read(struct clocksource *cs)
 138 {
 139     uint16_t val;
 140         val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
 141         return val;
 142 }
 143
 144 static struct clocksource jz4740_clocksource = {
 145         .name = "jz4740-timer",
 146         .rating = 200,
 147         .read = jz4740_clocksource_read,
 148         .mask = CLOCKSOURCE_MASK(16),
 149         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 150 };
 151
 152 static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
 153 {
 154         struct clock_event_device *cd = devid;
 155
 156         writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 157
 158         if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
 159                 jz4740_timer_disable(0);
 160                 cd->event_handler(cd);
 161          } else {
 162                 cd->event_handler(cd);
 163         }
 164
 165     return IRQ_HANDLED;
 166 }
 167
 168 static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
 169                                        struct clock_event_device *cd)
 170 {
 171         switch(mode) {
 172         case CLOCK_EVT_MODE_PERIODIC:
 173                 writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
 174                 writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
 175         case CLOCK_EVT_MODE_RESUME:
 176                 jz4740_timer_irq_full_enable(0);
 177                 jz4740_timer_enable(0);
 178                 break;
 179         case CLOCK_EVT_MODE_ONESHOT:
 180         case CLOCK_EVT_MODE_SHUTDOWN:
 181                 jz4740_timer_disable(0);
 182                 break;
 183         default:
 184                 break;
 185         }
 186 }
 187
 188 static int jz4740_clockevent_set_next(unsigned long evt, struct
 189 clock_event_device *cd)
 190 {
 191         writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
 192         writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
 193         jz4740_timer_enable(0);
 194
 195         return 0;
 196 }
 197
 198 static struct clock_event_device jz4740_clockevent = {
 199         .name = "jz4740-timer",
 200         .features = CLOCK_EVT_FEAT_PERIODIC,
 201         .set_next_event = jz4740_clockevent_set_next,
 202         .set_mode = jz4740_clockevent_set_mode,
 203         .rating = 200,
 204     .irq = JZ_IRQ_TCU0,
 205 };
 206
 207 static struct irqaction jz_irqaction = {
 208         .handler        = jz4740_clockevent_irq,
 209         .flags          = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
 210         .name           = "jz4740-timerirq",
 211     .dev_id      = &jz4740_clockevent,
 212 };
 213
 214
 215 void __init plat_time_init(void)
 216 {
 217     int ret;
 218         uint32_t clk_rate;
 219         struct clk *ext_clk;
 220
 221         jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
 222
 223         if (!jz4740_timer_base) {
 224             printk(KERN_ERR "Failed to ioremap timer registers");
 225             return;
 226         }
 227
 228         /*ext_clk = clk_get(NULL, "ext");
 229         clk_rate = clk_get_rate(ext_clk) >> 4;
 230         clk_put(ext_clk);*/
 231
 232
 233         clk_rate = JZ_EXTAL >> 4;
 234
 235     jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
 236
 237         clockevent_set_clock(&jz4740_clockevent, clk_rate);
 238         jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
 239         jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
 240         jz4740_clockevent.cpumask = cpumask_of(0);
 241
 242         clockevents_register_device(&jz4740_clockevent);
 243
 244         clocksource_set_clock(&jz4740_clocksource, clk_rate);
 245         ret = clocksource_register(&jz4740_clocksource);
 246
 247         if (ret)
 248             printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
 249
 250         setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
 251
 252         jz4740_init_timer();
 253         writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
 254     jz4740_timer_irq_half_disable(0);
 255     jz4740_timer_irq_full_enable(0);
 256         jz4740_timer_enable(0);
 257
 258     jz4740_timer_irq_half_disable(1);
 259     jz4740_timer_irq_full_disable(1);
 260
 261         jz4740_timer_enable(1);
 262 }