target/linux/xburst/files-2.6.32/drivers/misc/jz4740-adc.c

   1 /*
   2  * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
   3  *              JZ4720/JZ4740 SoC ADC driver
   4  *
   5  * This program is free software; you can redistribute   it and/or modify it
   6  * under  the terms of   the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the   License, or (at your
   8  * option) any later version.
   9  *
  10  * You should have received a copy of the  GNU General Public License along
  11  * with this program; if not, write  to the Free Software Foundation, Inc.,
  12  * 675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  * This driver is meant to synchronize access to the adc core for the battery
  15  * and touchscreen driver. Thus these drivers should use the adc driver as a
  16  * parent.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/jz4740-adc.h>
  25
  26 #define JZ_REG_ADC_ENABLE       0x00
  27 #define JZ_REG_ADC_CFG          0x04
  28 #define JZ_REG_ADC_CTRL         0x08
  29 #define JZ_REG_ADC_STATUS       0x0C
  30 #define JZ_REG_ADC_SAME         0x10
  31 #define JZ_REG_ADC_WAIT         0x14
  32 #define JZ_REG_ADC_TOUCH        0x18
  33 #define JZ_REG_ADC_BATTERY      0x1C
  34 #define JZ_REG_ADC_ADCIN        0x20
  35
  36 #define JZ_ADC_ENABLE_TOUCH             BIT(2)
  37 #define JZ_ADC_ENABLE_BATTERY           BIT(1)
  38 #define JZ_ADC_ENABLE_ADCIN             BIT(0)
  39
  40 #define JZ_ADC_CFG_SPZZ                 BIT(31)
  41 #define JZ_ADC_CFG_EX_IN                BIT(30)
  42 #define JZ_ADC_CFG_DNUM_MASK            (0x7 << 16)
  43 #define JZ_ADC_CFG_DMA_ENABLE           BIT(15)
  44 #define JZ_ADC_CFG_XYZ_MASK             (0x2 << 13)
  45 #define JZ_ADC_CFG_SAMPLE_NUM_MASK      (0x7 << 10)
  46 #define JZ_ADC_CFG_CLKDIV               (0xf << 5)
  47 #define JZ_ADC_CFG_BAT_MB               BIT(4)
  48
  49 #define JZ_ADC_CFG_DNUM_OFFSET          16
  50 #define JZ_ADC_CFG_XYZ_OFFSET           13
  51 #define JZ_ADC_CFG_SAMPLE_NUM_OFFSET    10
  52 #define JZ_ADC_CFG_CLKDIV_OFFSET        5
  53
  54 #define JZ_ADC_IRQ_PENDOWN              BIT(4)
  55 #define JZ_ADC_IRQ_PENUP                BIT(3)
  56 #define JZ_ADC_IRQ_TOUCH                BIT(2)
  57 #define JZ_ADC_IRQ_BATTERY              BIT(1)
  58 #define JZ_ADC_IRQ_ADCIN                BIT(0)
  59
  60 #define JZ_ADC_TOUCH_TYPE1              BIT(31)
  61 #define JZ_ADC_TOUCH_DATA1_MASK         0xfff
  62 #define JZ_ADC_TOUCH_TYPE0              BIT(15)
  63 #define JZ_ADC_TOUCH_DATA0_MASK         0xfff
  64
  65 #define JZ_ADC_BATTERY_MASK             0xfff
  66
  67 #define JZ_ADC_ADCIN_MASK               0xfff
  68
  69 struct jz4740_adc {
  70         struct resource *mem;
  71         void __iomem *base;
  72
  73         int irq;
  74
  75         struct completion bat_completion;
  76         struct completion adc_completion;
  77
  78         spinlock_t lock;
  79 };
  80
  81 static irqreturn_t jz4740_adc_irq(int irq, void *data)
  82 {
  83         struct jz4740_adc *adc = data;
  84         uint8_t status;
  85
  86         status = readb(adc->base + JZ_REG_ADC_STATUS);
  87
  88         if (status & JZ_ADC_IRQ_BATTERY)
  89                 complete(&adc->bat_completion);
  90         if (status & JZ_ADC_IRQ_ADCIN)
  91                 complete(&adc->adc_completion);
  92
  93         writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
  94
  95         return IRQ_HANDLED;
  96 }
  97
  98 static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
  99 {
 100         unsigned long flags;
 101         uint8_t val;
 102
 103         spin_lock_irqsave(&adc->lock, flags);
 104
 105         val = readb(adc->base + JZ_REG_ADC_CTRL);
 106         val &= ~irq;
 107         writeb(val, adc->base + JZ_REG_ADC_CTRL);
 108
 109         spin_unlock_irqrestore(&adc->lock, flags);
 110 }
 111
 112 static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
 113 {
 114         unsigned long flags;
 115         uint8_t val;
 116
 117         spin_lock_irqsave(&adc->lock, flags);
 118
 119         val = readb(adc->base + JZ_REG_ADC_CTRL);
 120         val |= irq;
 121         writeb(val, adc->base + JZ_REG_ADC_CTRL);
 122
 123         spin_unlock_irqrestore(&adc->lock, flags);
 124 }
 125
 126 static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
 127 {
 128         unsigned long flags;
 129         uint8_t val;
 130
 131         spin_lock_irqsave(&adc->lock, flags);
 132
 133         val = readb(adc->base + JZ_REG_ADC_ENABLE);
 134         val |= engine;
 135         writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 136
 137         spin_unlock_irqrestore(&adc->lock, flags);
 138 }
 139
 140 static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
 141 {
 142         unsigned long flags;
 143         uint8_t val;
 144
 145         spin_lock_irqsave(&adc->lock, flags);
 146
 147         val = readb(adc->base + JZ_REG_ADC_ENABLE);
 148         val &= ~engine;
 149         writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 150
 151         spin_unlock_irqrestore(&adc->lock, flags);
 152 }
 153
 154 static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
 155 uint32_t val)
 156 {
 157         unsigned long flags;
 158         uint32_t cfg;
 159
 160         spin_lock_irqsave(&adc->lock, flags);
 161
 162         cfg = readl(adc->base + JZ_REG_ADC_CFG);
 163
 164         cfg &= ~mask;
 165         cfg |= val;
 166
 167         writel(cfg, adc->base + JZ_REG_ADC_CFG);
 168
 169         spin_unlock_irqrestore(&adc->lock, flags);
 170 }
 171
 172 long jz4740_adc_read_battery_voltage(struct device *dev,
 173                                                 enum jz_adc_battery_scale scale)
 174 {
 175         struct jz4740_adc *adc = dev_get_drvdata(dev);
 176         unsigned long t;
 177         long long voltage;
 178         uint16_t val;
 179
 180         if (!adc)
 181                 return -ENODEV;
 182
 183         if (scale == JZ_ADC_BATTERY_SCALE_2V5)
 184                 jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
 185         else
 186                 jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
 187
 188         jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
 189         jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
 190
 191         t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
 192                                                         HZ);
 193
 194         jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
 195
 196         if (t <= 0) {
 197                 jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
 198                 return t ? t : -ETIMEDOUT;
 199         }
 200
 201         val = readw(adc->base + JZ_REG_ADC_BATTERY);
 202
 203         if (scale == JZ_ADC_BATTERY_SCALE_2V5)
 204                 voltage = (((long long)val) * 2500000LL) >> 12LL;
 205         else
 206                 voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
 207
 208         return voltage;
 209 }
 210 EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
 211
 212 static ssize_t jz4740_adc_read_adcin(struct device *dev,
 213                                         struct device_attribute *dev_attr,
 214                                         char *buf)
 215 {
 216         struct jz4740_adc *adc = dev_get_drvdata(dev);
 217         unsigned long t;
 218         uint16_t val;
 219
 220         jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
 221         jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
 222
 223         t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
 224                                                         HZ);
 225
 226         jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
 227
 228         if (t <= 0) {
 229                 jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
 230                 return t ? t : -ETIMEDOUT;
 231         }
 232
 233         val = readw(adc->base + JZ_REG_ADC_ADCIN);
 234
 235         return sprintf(buf, "%d\n", val);
 236 }
 237
 238 static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
 239
 240 static int __devinit jz4740_adc_probe(struct platform_device *pdev)
 241 {
 242         int ret;
 243         struct jz4740_adc *adc;
 244
 245         adc = kmalloc(sizeof(*adc), GFP_KERNEL);
 246
 247         adc->irq = platform_get_irq(pdev, 0);
 248
 249         if (adc->irq < 0) {
 250                 ret = adc->irq;
 251                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 252                 goto err_free;
 253         }
 254
 255         adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 256
 257         if (!adc->mem) {
 258                 ret = -ENOENT;
 259                 dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
 260                 goto err_free;
 261         }
 262
 263         adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
 264                                         pdev->name);
 265
 266         if (!adc->mem) {
 267                 ret = -EBUSY;
 268                 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 269                 goto err_free;
 270         }
 271
 272         adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
 273
 274         if (!adc->base) {
 275                 ret = -EBUSY;
 276                 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 277                 goto err_release_mem_region;
 278         }
 279
 280
 281         init_completion(&adc->bat_completion);
 282         init_completion(&adc->adc_completion);
 283
 284         spin_lock_init(&adc->lock);
 285
 286         platform_set_drvdata(pdev, adc);
 287
 288         ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
 289
 290         if (ret) {
 291                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
 292                 goto err_iounmap;
 293         }
 294
 295         ret = device_create_file(&pdev->dev, &dev_attr_adcin);
 296         if (ret) {
 297                 dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
 298                 goto err_free_irq;
 299         }
 300
 301         writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
 302         writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
 303
 304         return 0;
 305
 306 err_free_irq:
 307         free_irq(adc->irq, adc);
 308 err_iounmap:
 309         platform_set_drvdata(pdev, NULL);
 310         iounmap(adc->base);
 311 err_release_mem_region:
 312         release_mem_region(adc->mem->start, resource_size(adc->mem));
 313 err_free:
 314         kfree(adc);
 315
 316         return ret;
 317 }
 318
 319 static int __devexit jz4740_adc_remove(struct platform_device *pdev)
 320 {
 321         struct jz4740_adc *adc = platform_get_drvdata(pdev);
 322
 323         device_remove_file(&pdev->dev, &dev_attr_adcin);
 324
 325         free_irq(adc->irq, adc);
 326
 327         iounmap(adc->base);
 328         release_mem_region(adc->mem->start, resource_size(adc->mem));
 329
 330         platform_set_drvdata(pdev, NULL);
 331
 332         kfree(adc);
 333
 334         return 0;
 335 }
 336
 337 struct platform_driver jz4740_adc_driver = {
 338         .probe  = jz4740_adc_probe,
 339         .remove = jz4740_adc_remove,
 340         .driver = {
 341                 .name = "jz4740-adc",
 342                 .owner = THIS_MODULE,
 343         },
 344 };
 345
 346 static int __init jz4740_adc_init(void)
 347 {
 348         return platform_driver_register(&jz4740_adc_driver);
 349 }
 350 module_init(jz4740_adc_init);
 351
 352 static void __exit jz4740_adc_exit(void)
 353 {
 354         platform_driver_unregister(&jz4740_adc_driver);
 355 }
 356 module_exit(jz4740_adc_exit);
 357
 358 MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
 359 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 360 MODULE_LICENSE("GPL");
 361 MODULE_ALIAS("platform:jz4740-adc");
 362 MODULE_ALIAS("platform:jz4720-adc");