edd995e1516fd247dca3a10405d3cbe53e83372f
[openwrt/svn-archive/archive.git] / target / linux / xburst / files-2.6.32 / sound / soc / jz4740 / jz4740-i2s.c
1 /*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/delay.h>
23
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30
31 #include "jz4740-i2s.h"
32 #include "jz4740-pcm.h"
33
34 #define JZ_REG_AIC_CONF 0x00
35 #define JZ_REG_AIC_CTRL 0x04
36 #define JZ_REG_AIC_I2S_FMT 0x10
37 #define JZ_REG_AIC_FIFO_STATUS 0x14
38 #define JZ_REG_AIC_I2S_STATUS 0x1c
39 #define JZ_REG_AIC_CLK_DIV 0x30
40 #define JZ_REG_AIC_FIFO 0x34
41
42 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
43 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
44 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
45 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
46 #define JZ_AIC_CONF_I2S BIT(4)
47 #define JZ_AIC_CONF_RESET BIT(3)
48 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
49 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
50 #define JZ_AIC_CONF_ENABLE BIT(0)
51
52 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
53 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
54
55 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
56 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
57 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
58 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
59 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
60 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
61 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
62 #define JZ_AIC_CTRL_FLUSH BIT(8)
63 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
64 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
65 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
66 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
67 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
68 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
69 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
70
71 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
72 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
73
74 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
75 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
76 #define JZ_AIC_I2S_FMT_MSB BIT(0)
77
78 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
79
80 #define JZ_AIC_CLK_DIV_MASK 0xf
81
82 struct jz4740_i2s {
83 struct resource *mem;
84 void __iomem *base;
85 dma_addr_t phys_base;
86
87 struct clk *clk_aic;
88 struct clk *clk_i2s;
89
90 struct jz4740_pcm_config pcm_config;
91 };
92
93 static struct jz4740_dma_config jz4740_i2s_dma_playback_config = {
94 .src_width = JZ4740_DMA_WIDTH_16BIT,
95 .dst_width = JZ4740_DMA_WIDTH_32BIT,
96 .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
97 .request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT,
98 .flags = JZ4740_DMA_SRC_AUTOINC,
99 .mode = JZ4740_DMA_MODE_SINGLE,
100 };
101
102 static struct jz4740_dma_config jz4740_i2s_dma_capture_config = {
103 .src_width = JZ4740_DMA_WIDTH_32BIT,
104 .dst_width = JZ4740_DMA_WIDTH_16BIT,
105 .transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
106 .request_type = JZ4740_DMA_TYPE_AIC_RECEIVE,
107 .flags = JZ4740_DMA_DST_AUTOINC,
108 .mode = JZ4740_DMA_MODE_SINGLE,
109 };
110
111
112 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, unsigned int reg)
113 {
114 return readl(i2s->base + reg);
115 }
116
117 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, unsigned
118 int reg, uint32_t value)
119 {
120 writel(value, i2s->base + reg);
121 }
122
123 static inline struct jz4740_i2s *jz4740_dai_to_i2s(struct snd_soc_dai *dai)
124 {
125 return dai->private_data;
126 }
127
128 static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct
129 snd_soc_dai *dai)
130 {
131 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
132 uint32_t conf, ctrl;
133
134 if (dai->active)
135 return 0;
136
137 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
138 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
139
140 conf |= JZ_AIC_CONF_ENABLE;
141 ctrl |= JZ_AIC_CTRL_FLUSH;
142
143
144 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
145 clk_enable(i2s->clk_i2s);
146 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
147
148 return 0;
149 }
150
151 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct
152 snd_soc_dai *dai)
153 {
154 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
155 uint32_t conf;
156
157 if (!dai->active)
158 return;
159
160 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
161 conf &= ~JZ_AIC_CONF_ENABLE;
162 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
163
164 clk_disable(i2s->clk_i2s);
165 }
166
167
168 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
169 struct snd_soc_dai *dai)
170 {
171 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
172 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
173
174 uint32_t ctrl;
175 uint32_t mask;
176
177 if (playback) {
178 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK |
179 JZ_AIC_CTRL_ENABLE_TX_DMA;
180 } else {
181 mask = JZ_AIC_CTRL_ENABLE_CAPTURE |
182 JZ_AIC_CTRL_ENABLE_RX_DMA;
183 }
184
185 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
186
187 switch (cmd) {
188 case SNDRV_PCM_TRIGGER_START:
189 case SNDRV_PCM_TRIGGER_RESUME:
190 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
191 ctrl |= mask;
192 break;
193 case SNDRV_PCM_TRIGGER_STOP:
194 case SNDRV_PCM_TRIGGER_SUSPEND:
195 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
196 ctrl &= ~mask;
197 break;
198 default:
199 return -EINVAL;
200 }
201
202 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
203
204 return 0;
205 }
206
207
208 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai,
209 unsigned int fmt)
210 {
211 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
212
213 uint32_t format = 0;
214 uint32_t conf;
215
216 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
217
218 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
219
220 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
221 case SND_SOC_DAIFMT_CBS_CFS:
222 conf |= JZ_AIC_CONF_BIT_CLK_MASTER |
223 JZ_AIC_CONF_SYNC_CLK_MASTER;
224 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
225 break;
226 case SND_SOC_DAIFMT_CBM_CFS:
227 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
228 break;
229 case SND_SOC_DAIFMT_CBS_CFM:
230 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
231 break;
232 case SND_SOC_DAIFMT_CBM_CFM:
233 break;
234 default:
235 return -EINVAL;
236 }
237
238 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
239 case SND_SOC_DAIFMT_MSB:
240 format |= JZ_AIC_I2S_FMT_MSB;
241 break;
242 case SND_SOC_DAIFMT_I2S:
243 break;
244 default:
245 return -EINVAL;
246 }
247
248 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
249 case SND_SOC_DAIFMT_NB_NF:
250 break;
251 default:
252 return -EINVAL;
253 }
254
255 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
256 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
257
258 return 0;
259 }
260
261 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
262 struct snd_pcm_hw_params *params,
263 struct snd_soc_dai *dai)
264 {
265 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
266 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
267 int sample_size;
268 enum jz4740_dma_width dma_width;
269 uint32_t ctrl;
270
271 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
272
273 switch (params_format(params)) {
274 case SNDRV_PCM_FORMAT_S8:
275 sample_size = 0;
276 dma_width = JZ4740_DMA_WIDTH_8BIT;
277 break;
278 case SNDRV_PCM_FORMAT_S16:
279 sample_size = 1;
280 dma_width = JZ4740_DMA_WIDTH_16BIT;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 if (playback) {
287 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
288 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
289 } else {
290 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
291 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
292 }
293
294 switch (params_channels(params)) {
295 case 2:
296 break;
297 case 1:
298 if (playback) {
299 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
300 break;
301 }
302 default:
303 return -EINVAL;
304 }
305
306 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
307
308 /* This is quite ugly, but apperently it's offical method for passing dma
309 * config to the pcm module */
310 if (playback) {
311 jz4740_i2s_dma_playback_config.src_width = dma_width;
312 i2s->pcm_config.dma_config = &jz4740_i2s_dma_playback_config;
313 } else {
314 jz4740_i2s_dma_capture_config.dst_width = dma_width;
315 i2s->pcm_config.dma_config = &jz4740_i2s_dma_capture_config;
316 }
317 i2s->pcm_config.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
318
319 dai->dma_data = &i2s->pcm_config;
320
321 return 0;
322 }
323
324 static int jz4740_i2s_set_clkdiv(struct snd_soc_dai *dai,
325 int div_id, int div)
326 {
327 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
328
329 switch (div_id) {
330 case JZ4740_I2S_BIT_CLK:
331 if (div & 1 || div > 16)
332 return -EINVAL;
333 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div - 1);
334 break;
335 default:
336 return -EINVAL;
337 }
338
339 return 0;
340 }
341
342 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
343 unsigned int freq, int dir)
344 {
345 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
346 int ret = 0;
347 struct clk *parent;
348
349 switch (clk_id) {
350 case JZ4740_I2S_CLKSRC_EXT:
351 parent = clk_get(NULL, "ext");
352 clk_set_parent(i2s->clk_i2s, parent);
353 break;
354 case JZ4740_I2S_CLKSRC_PLL:
355 parent = clk_get(NULL, "pll half");
356 clk_set_parent(i2s->clk_i2s, parent);
357 ret = clk_set_rate(i2s->clk_i2s, freq);
358 break;
359 default:
360 return -EINVAL;
361 }
362 clk_put(parent);
363
364 return ret;
365 }
366
367 static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
368 {
369 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
370 uint32_t conf;
371
372 if (dai->active) {
373 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
374 conf &= ~JZ_AIC_CONF_ENABLE;
375 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
376
377 clk_disable(i2s->clk_i2s);
378 }
379
380 clk_disable(i2s->clk_aic);
381
382 return 0;
383 }
384
385 static int jz4740_i2s_resume(struct snd_soc_dai *dai)
386 {
387 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
388 uint32_t conf;
389
390 clk_enable(i2s->clk_aic);
391
392 if (dai->active) {
393 clk_enable(i2s->clk_i2s);
394
395 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
396 conf |= JZ_AIC_CONF_ENABLE;
397 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
398
399 }
400
401 return 0;
402 }
403
404
405 static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
406 {
407 struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
408 uint32_t conf;
409
410 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
411 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
412 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
413 JZ_AIC_CONF_I2S |
414 JZ_AIC_CONF_INTERNAL_CODEC;
415
416 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
417 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
418
419 return 0;
420 }
421
422
423 static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
424 .startup = jz4740_i2s_startup,
425 .shutdown = jz4740_i2s_shutdown,
426 .trigger = jz4740_i2s_trigger,
427 .hw_params = jz4740_i2s_hw_params,
428 .set_fmt = jz4740_i2s_set_fmt,
429 .set_clkdiv = jz4740_i2s_set_clkdiv,
430 .set_sysclk = jz4740_i2s_set_sysclk,
431 };
432
433 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
434 SNDRV_PCM_FMTBIT_S16_LE)
435
436 struct snd_soc_dai jz4740_i2s_dai = {
437 .name = "jz4740-i2s",
438 .probe = jz4740_i2s_probe,
439 .playback = {
440 .channels_min = 1,
441 .channels_max = 2,
442 .rates = SNDRV_PCM_RATE_8000_44100,
443 .formats = JZ4740_I2S_FMTS,
444 },
445 .capture = {
446 .channels_min = 2,
447 .channels_max = 2,
448 .rates = SNDRV_PCM_RATE_8000_44100,
449 .formats = JZ4740_I2S_FMTS,
450 },
451 .symmetric_rates = 1,
452 .ops = &jz4740_i2s_dai_ops,
453 .suspend = jz4740_i2s_suspend,
454 .resume = jz4740_i2s_resume,
455 };
456
457 static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
458 {
459 struct jz4740_i2s *i2s;
460 int ret;
461
462 i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
463
464 if (!i2s)
465 return -ENOMEM;
466
467 i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
468
469 if (!i2s->mem) {
470 ret = -ENOENT;
471 goto err_free;
472 }
473
474 i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
475 pdev->name);
476
477 if (!i2s->mem) {
478 ret = -EBUSY;
479 goto err_free;
480 }
481
482 i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
483
484 if (!i2s->base) {
485 ret = -EBUSY;
486 goto err_release_mem_region;
487 }
488
489 i2s->phys_base = i2s->mem->start;
490
491 jz4740_i2s_dai.private_data = i2s;
492
493 ret = snd_soc_register_dai(&jz4740_i2s_dai);
494
495 i2s->clk_aic = clk_get(&pdev->dev, "aic");
496
497 if (IS_ERR(i2s->clk_aic)) {
498 ret = PTR_ERR(i2s->clk_aic);
499 goto err_iounmap;
500 }
501
502
503 i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
504
505 if (IS_ERR(i2s->clk_i2s)) {
506 ret = PTR_ERR(i2s->clk_i2s);
507 goto err_iounmap;
508 }
509
510 clk_enable(i2s->clk_aic);
511
512 platform_set_drvdata(pdev, i2s);
513
514 return 0;
515
516 err_iounmap:
517 iounmap(i2s->base);
518 err_release_mem_region:
519 release_mem_region(i2s->mem->start, resource_size(i2s->mem));
520 err_free:
521 kfree(i2s);
522
523 return ret;
524 }
525
526 static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
527 {
528 struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
529
530 snd_soc_unregister_dai(&jz4740_i2s_dai);
531
532 clk_disable(i2s->clk_aic);
533 clk_put(i2s->clk_i2s);
534 clk_put(i2s->clk_aic);
535
536 iounmap(i2s->base);
537 release_mem_region(i2s->mem->start, resource_size(i2s->mem));
538
539 platform_set_drvdata(pdev, NULL);
540 kfree(i2s);
541
542 return 0;
543 }
544
545 static struct platform_driver jz4740_i2s_driver = {
546 .probe = jz4740_i2s_dev_probe,
547 .remove = __devexit_p(jz4740_i2s_dev_remove),
548 .driver = {
549 .name = "jz4740-i2s",
550 .owner = THIS_MODULE,
551 },
552 };
553
554 static int __init jz4740_i2s_init(void)
555 {
556 return platform_driver_register(&jz4740_i2s_driver);
557 }
558 module_init(jz4740_i2s_init);
559
560 static void __exit jz4740_i2s_exit(void)
561 {
562 platform_driver_unregister(&jz4740_i2s_driver);
563 }
564 module_exit(jz4740_i2s_exit);
565
566 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
567 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
568 MODULE_LICENSE("GPL");
569 MODULE_ALIAS("platform:jz4740-i2s");